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Fanout optimization

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This commit is contained in:
Alex Forencich 2019-06-28 17:24:37 -07:00
parent 209cb7d41d
commit 4afbd71f1f
2 changed files with 14 additions and 14 deletions
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12
rtl/pcie_us_axi_dma_rd.v
View File

@ -488,7 +488,7 @@ always @* begin
tlp_cmd_last_next = req_op_count_next == 0;
tlp_cmd_valid_next = 1'b1;
if (req_op_count_next > 0) begin
if (req_op_count_next != 0) begin
req_state_next = REQ_STATE_START;
end else begin
s_axis_read_desc_ready_next = 1'b0;
@ -527,7 +527,7 @@ always @* begin
tlp_cmd_last_next = req_op_count_next == 0;
tlp_cmd_valid_next = 1'b1;
if (req_op_count_next > 0) begin
if (req_op_count_next != 0) begin
req_state_next = REQ_STATE_START;
end else begin
s_axis_read_desc_ready_next = 1'b0;
@ -862,7 +862,7 @@ always @* begin
axi_addr_next = axi_addr_reg + tr_count_next;
op_count_next = op_count_reg - tr_count_next;
input_active_next = input_cycle_count_next > 0;
input_active_next = input_cycle_count_next != 0;
input_cycle_count_next = input_cycle_count_next - 1;
s_axis_rc_tready_next = m_axi_wready_int_early && input_active_next && bubble_cycle_reg && (!last_cycle_next || op_count_next == 0 || !m_axi_awvalid || m_axi_awready);
tlp_state_next = TLP_STATE_TRANSFER;
@ -889,13 +889,13 @@ always @* begin
if (input_active_reg && !(first_cycle_reg && !bubble_cycle_reg)) begin
input_cycle_count_next = input_cycle_count_reg - 1;
input_active_next = input_cycle_count_reg > 0;
input_active_next = input_cycle_count_reg != 0;
end
output_cycle_count_next = output_cycle_count_reg - 1;
last_cycle_next = output_cycle_count_next == 0;
if (last_cycle_reg) begin
if (last_cycle_offset_reg > 0 && op_count_reg == 0) begin
if (last_cycle_offset_reg != 0 && op_count_reg == 0) begin
m_axi_wstrb_int = m_axi_wstrb_int & {AXI_STRB_WIDTH{1'b1}} >> (AXI_STRB_WIDTH-last_cycle_offset_reg);
end
m_axi_wlast_int = 1'b1;
@ -906,7 +906,7 @@ always @* begin
// current transfer not finished yet
s_axis_rc_tready_next = m_axi_wready_int_early && input_active_next && (!last_cycle_next || op_count_reg == 0 || !m_axi_awvalid || m_axi_awready);
tlp_state_next = TLP_STATE_TRANSFER;
end else if (op_count_reg > 0) begin
end else if (op_count_reg != 0) begin
// current transfer done, but operation not finished yet
if (op_count_reg <= AXI_MAX_BURST_SIZE-axi_addr_reg[1:0]) begin
// packet smaller than max burst size

16
rtl/pcie_us_axi_dma_wr.v
View File

@ -386,9 +386,9 @@ always @* begin
axi_addr_next = axi_addr_reg + tr_count_next;
tlp_count_next = tlp_count_reg - tr_count_next;
if (tlp_count_next > 0) begin
if (tlp_count_next != 0) begin
axi_state_next = AXI_STATE_REQ;
end else if (op_count_next > 0) begin
end else if (op_count_next != 0) begin
axi_state_next = AXI_STATE_START;
end else begin
s_axis_write_desc_ready_next = !tlp_cmd_valid_reg && enable;
@ -511,7 +511,7 @@ always @* begin
if (bubble_cycle_reg) begin
if (input_active_reg) begin
input_cycle_count_next = input_cycle_count_reg - 1;
input_active_next = input_cycle_count_reg > 0;
input_active_next = input_cycle_count_reg != 0;
end
bubble_cycle_next = 1'b0;
m_axi_rready_next = m_axis_rq_tready_int_early && input_active_next;
@ -520,7 +520,7 @@ always @* begin
dword_count_next = dword_count_reg - 4;
if (input_active_reg) begin
input_cycle_count_next = input_cycle_count_reg - 1;
input_active_next = input_cycle_count_reg > 0;
input_active_next = input_cycle_count_reg != 0;
end
output_cycle_count_next = output_cycle_count_reg - 1;
last_cycle_next = output_cycle_count_next == 0;
@ -585,7 +585,7 @@ always @* begin
transfer_in_save = 1'b1;
if (input_active_reg) begin
input_cycle_count_next = input_cycle_count_reg - 1;
input_active_next = input_cycle_count_reg > 0;
input_active_next = input_cycle_count_reg != 0;
end
bubble_cycle_next = 1'b0;
m_axi_rready_next = m_axis_rq_tready_int_early && input_active_next;
@ -621,7 +621,7 @@ always @* begin
transfer_in_save = 1'b1;
if (input_active_reg) begin
input_cycle_count_next = input_cycle_count_reg - 1;
input_active_next = input_cycle_count_reg > 0;
input_active_next = input_cycle_count_reg != 0;
end
bubble_cycle_next = 1'b0;
m_axi_rready_next = m_axis_rq_tready_int_early && input_active_next;
@ -641,7 +641,7 @@ always @* begin
if (bubble_cycle_reg) begin
if (input_active_reg) begin
input_cycle_count_next = input_cycle_count_reg - 1;
input_active_next = input_cycle_count_reg > 0;
input_active_next = input_cycle_count_reg != 0;
end
bubble_cycle_next = 1'b0;
m_axi_rready_next = m_axis_rq_tready_int_early && input_active_next;
@ -650,7 +650,7 @@ always @* begin
dword_count_next = dword_count_reg - AXI_STRB_WIDTH/4;
if (input_active_reg) begin
input_cycle_count_next = input_cycle_count_reg - 1;
input_active_next = input_cycle_count_reg > 0;
input_active_next = input_cycle_count_reg != 0;
end
output_cycle_count_next = output_cycle_count_reg - 1;
last_cycle_next = output_cycle_count_next == 0;