From 4b25e6e9c9bffb61a7b91d633f8c02d6ca0bccac Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 17 Jan 2020 10:27:56 -0800 Subject: [PATCH] Update readme --- README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/README.md b/README.md index 19a746854..121af18eb 100644 --- a/README.md +++ b/README.md @@ -32,6 +32,7 @@ devices. Designs are included for the following FPGA boards: * Exablaze ExaNIC X25 (Xilinx Kintex Ultrascale Plus XCKU3P) * Xilinx VCU108 (Xilinx Virtex Ultrascale XCVU095) * Xilinx VCU118 (Xilinx Virtex Ultrascale Plus XCVU9P) +* Xilinx VCU1525 (Xilinx Virtex Ultrascale Plus XCVU9P) For operation at 10G and 25G, Corundum uses the open source 10G/25G MAC and PHY modules from the verilog-ethernet repository, no extra licenses are