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Add mqnic core logic for Intel P-Tile
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
parent
b50c389b4a
commit
4b6a96d5ee
986
fpga/common/rtl/mqnic_core_pcie_ptile.v
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986
fpga/common/rtl/mqnic_core_pcie_ptile.v
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/*
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Copyright 2022, The Regents of the University of California.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
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IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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The views and conclusions contained in the software and documentation are those
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of the authors and should not be interpreted as representing official policies,
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either expressed or implied, of The Regents of the University of California.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* mqnic core logic - Intel P-Tile wrapper
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*/
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module mqnic_core_pcie_ptile #
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(
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// FW and board IDs
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parameter FPGA_ID = 32'hDEADBEEF,
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parameter FW_ID = 32'h00000000,
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parameter FW_VER = 32'h00_00_01_00,
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parameter BOARD_ID = 32'h1234_0000,
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parameter BOARD_VER = 32'h01_00_00_00,
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parameter BUILD_DATE = 32'd602976000,
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parameter GIT_HASH = 32'hdce357bf,
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parameter RELEASE_INFO = 32'h00000000,
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// Structural configuration
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parameter IF_COUNT = 1,
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parameter PORTS_PER_IF = 1,
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parameter SCHED_PER_IF = PORTS_PER_IF,
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parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF,
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// PTP configuration
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parameter PTP_CLK_PERIOD_NS_NUM = 4,
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parameter PTP_CLK_PERIOD_NS_DENOM = 1,
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parameter PTP_TS_WIDTH = 96,
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parameter PTP_CLOCK_PIPELINE = 0,
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parameter PTP_CLOCK_CDC_PIPELINE = 0,
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parameter PTP_USE_SAMPLE_CLOCK = 0,
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parameter PTP_SEPARATE_TX_CLOCK = 0,
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parameter PTP_SEPARATE_RX_CLOCK = 0,
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parameter PTP_PORT_CDC_PIPELINE = 0,
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parameter PTP_PEROUT_ENABLE = 0,
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parameter PTP_PEROUT_COUNT = 1,
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// Queue manager configuration
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parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
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parameter TX_QUEUE_OP_TABLE_SIZE = 32,
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parameter RX_QUEUE_OP_TABLE_SIZE = 32,
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parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE,
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parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE,
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parameter EVENT_QUEUE_INDEX_WIDTH = 5,
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parameter TX_QUEUE_INDEX_WIDTH = 13,
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parameter RX_QUEUE_INDEX_WIDTH = 8,
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parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
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parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
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parameter EVENT_QUEUE_PIPELINE = 3,
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parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0),
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parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0),
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parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
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parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
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// TX and RX engine configuration
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parameter TX_DESC_TABLE_SIZE = 32,
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parameter RX_DESC_TABLE_SIZE = 32,
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// Scheduler configuration
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parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
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parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
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parameter TDMA_INDEX_WIDTH = 6,
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// Interface configuration
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parameter PTP_TS_ENABLE = 1,
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parameter TX_CPL_ENABLE = PTP_TS_ENABLE,
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parameter TX_CPL_FIFO_DEPTH = 32,
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parameter TX_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE)+1,
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parameter TX_CHECKSUM_ENABLE = 1,
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parameter RX_RSS_ENABLE = 1,
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parameter RX_HASH_ENABLE = 1,
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parameter RX_CHECKSUM_ENABLE = 1,
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parameter TX_FIFO_DEPTH = 32768,
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parameter RX_FIFO_DEPTH = 32768,
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parameter MAX_TX_SIZE = 9214,
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parameter MAX_RX_SIZE = 9214,
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parameter TX_RAM_SIZE = 32768,
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parameter RX_RAM_SIZE = 32768,
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// Application block configuration
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parameter APP_ID = 32'h00000000,
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parameter APP_ENABLE = 0,
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parameter APP_CTRL_ENABLE = 1,
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parameter APP_DMA_ENABLE = 1,
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parameter APP_AXIS_DIRECT_ENABLE = 1,
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parameter APP_AXIS_SYNC_ENABLE = 1,
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parameter APP_AXIS_IF_ENABLE = 1,
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parameter APP_STAT_ENABLE = 1,
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parameter APP_GPIO_IN_WIDTH = 32,
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parameter APP_GPIO_OUT_WIDTH = 32,
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// DMA interface configuration
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parameter DMA_IMM_ENABLE = 0,
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parameter DMA_IMM_WIDTH = 32,
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parameter DMA_LEN_WIDTH = 16,
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parameter DMA_TAG_WIDTH = 16,
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parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
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parameter RAM_PIPELINE = 2,
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// PCIe interface configuration
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parameter SEG_COUNT = 1,
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parameter SEG_DATA_WIDTH = 256,
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parameter SEG_EMPTY_WIDTH = $clog2(SEG_DATA_WIDTH/32),
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parameter SEG_HDR_WIDTH = 128,
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parameter SEG_PRFX_WIDTH = 32,
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parameter TX_SEQ_NUM_WIDTH = 6,
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parameter TX_SEQ_NUM_ENABLE = 1,
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parameter PF_COUNT = 1,
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parameter VF_COUNT = 0,
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parameter F_COUNT = PF_COUNT+VF_COUNT,
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parameter PCIE_TAG_COUNT = 256,
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parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
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parameter PCIE_DMA_READ_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
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parameter PCIE_DMA_READ_TX_FC_ENABLE = 1,
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parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 2**TX_SEQ_NUM_WIDTH,
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parameter PCIE_DMA_WRITE_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
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parameter PCIE_DMA_WRITE_TX_FC_ENABLE = 1,
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// Interrupt configuration
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parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
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// AXI lite interface configuration (control)
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parameter AXIL_CTRL_DATA_WIDTH = 32,
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parameter AXIL_CTRL_ADDR_WIDTH = 24,
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parameter AXIL_CTRL_STRB_WIDTH = (AXIL_CTRL_DATA_WIDTH/8),
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parameter AXIL_IF_CTRL_ADDR_WIDTH = AXIL_CTRL_ADDR_WIDTH-$clog2(IF_COUNT),
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parameter AXIL_CSR_ADDR_WIDTH = AXIL_IF_CTRL_ADDR_WIDTH-5-$clog2((PORTS_PER_IF+3)/8),
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parameter AXIL_CSR_PASSTHROUGH_ENABLE = 0,
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parameter RB_NEXT_PTR = 0,
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// AXI lite interface configuration (application control)
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parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH,
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parameter AXIL_APP_CTRL_ADDR_WIDTH = 24,
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// Ethernet interface configuration
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parameter AXIS_ETH_DATA_WIDTH = 512,
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parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8,
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parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH,
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parameter AXIS_ETH_IF_DATA_WIDTH = AXIS_ETH_SYNC_DATA_WIDTH*2**$clog2(PORTS_PER_IF),
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parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1,
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parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
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parameter AXIS_ETH_RX_USE_READY = 0,
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parameter AXIS_ETH_TX_PIPELINE = 0,
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parameter AXIS_ETH_TX_FIFO_PIPELINE = 2,
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parameter AXIS_ETH_TX_TS_PIPELINE = 0,
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parameter AXIS_ETH_RX_PIPELINE = 0,
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parameter AXIS_ETH_RX_FIFO_PIPELINE = 2,
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// Statistics counter subsystem
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parameter STAT_ENABLE = 1,
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parameter STAT_DMA_ENABLE = 1,
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parameter STAT_PCIE_ENABLE = 1,
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parameter STAT_INC_WIDTH = 24,
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parameter STAT_ID_WIDTH = 12
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)
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(
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input wire clk,
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input wire rst,
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/*
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* P-Tile RX AVST interface
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*/
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input wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] rx_st_data,
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input wire [SEG_COUNT*SEG_EMPTY_WIDTH-1:0] rx_st_empty,
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input wire [SEG_COUNT-1:0] rx_st_sop,
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input wire [SEG_COUNT-1:0] rx_st_eop,
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input wire [SEG_COUNT-1:0] rx_st_valid,
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output wire rx_st_ready,
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input wire [SEG_COUNT*SEG_HDR_WIDTH-1:0] rx_st_hdr,
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input wire [SEG_COUNT*SEG_PRFX_WIDTH-1:0] rx_st_tlp_prfx,
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input wire [SEG_COUNT-1:0] rx_st_vf_active,
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input wire [SEG_COUNT*3-1:0] rx_st_func_num,
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input wire [SEG_COUNT*11-1:0] rx_st_vf_num,
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input wire [SEG_COUNT*3-1:0] rx_st_bar_range,
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input wire [SEG_COUNT-1:0] rx_st_tlp_abort,
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/*
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* P-Tile TX AVST interface
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*/
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output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] tx_st_data,
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output wire [SEG_COUNT-1:0] tx_st_sop,
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output wire [SEG_COUNT-1:0] tx_st_eop,
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output wire [SEG_COUNT-1:0] tx_st_valid,
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input wire tx_st_ready,
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output wire [SEG_COUNT-1:0] tx_st_err,
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output wire [SEG_COUNT*SEG_HDR_WIDTH-1:0] tx_st_hdr,
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output wire [SEG_COUNT*SEG_PRFX_WIDTH-1:0] tx_st_tlp_prfx,
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/*
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* P-Tile RX flow control
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*/
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output wire [11:0] rx_buffer_limit,
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output wire [1:0] rx_buffer_limit_tdm_idx,
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/*
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* P-Tile TX flow control
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*/
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input wire [15:0] tx_cdts_limit,
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input wire [2:0] tx_cdts_limit_tdm_idx,
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/*
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* P-Tile configuration interface
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*/
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input wire [15:0] tl_cfg_ctl,
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input wire [4:0] tl_cfg_add,
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input wire [2:0] tl_cfg_func,
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/*
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* AXI-Lite master interface (passthrough for NIC control and status)
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*/
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output wire [AXIL_CSR_ADDR_WIDTH-1:0] m_axil_csr_awaddr,
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output wire [2:0] m_axil_csr_awprot,
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output wire m_axil_csr_awvalid,
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input wire m_axil_csr_awready,
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output wire [AXIL_CTRL_DATA_WIDTH-1:0] m_axil_csr_wdata,
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output wire [AXIL_CTRL_STRB_WIDTH-1:0] m_axil_csr_wstrb,
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output wire m_axil_csr_wvalid,
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input wire m_axil_csr_wready,
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input wire [1:0] m_axil_csr_bresp,
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input wire m_axil_csr_bvalid,
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output wire m_axil_csr_bready,
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output wire [AXIL_CSR_ADDR_WIDTH-1:0] m_axil_csr_araddr,
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output wire [2:0] m_axil_csr_arprot,
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output wire m_axil_csr_arvalid,
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input wire m_axil_csr_arready,
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input wire [AXIL_CTRL_DATA_WIDTH-1:0] m_axil_csr_rdata,
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input wire [1:0] m_axil_csr_rresp,
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input wire m_axil_csr_rvalid,
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output wire m_axil_csr_rready,
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/*
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* Control register interface
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*/
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output wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_wr_addr,
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output wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_wr_data,
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output wire [AXIL_CTRL_STRB_WIDTH-1:0] ctrl_reg_wr_strb,
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output wire ctrl_reg_wr_en,
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input wire ctrl_reg_wr_wait,
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input wire ctrl_reg_wr_ack,
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output wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_rd_addr,
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output wire ctrl_reg_rd_en,
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input wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data,
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input wire ctrl_reg_rd_wait,
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input wire ctrl_reg_rd_ack,
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/*
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* PTP clock
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*/
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input wire ptp_clk,
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input wire ptp_rst,
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input wire ptp_sample_clk,
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output wire ptp_pps,
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output wire ptp_pps_str,
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output wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
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output wire ptp_ts_step,
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output wire ptp_sync_pps,
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output wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96,
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output wire ptp_sync_ts_step,
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output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked,
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output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error,
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output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse,
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/*
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* Ethernet
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*/
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input wire [PORT_COUNT-1:0] eth_tx_clk,
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input wire [PORT_COUNT-1:0] eth_tx_rst,
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input wire [PORT_COUNT-1:0] eth_tx_ptp_clk,
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input wire [PORT_COUNT-1:0] eth_tx_ptp_rst,
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output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96,
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output wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step,
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output wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] m_axis_eth_tx_tdata,
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output wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] m_axis_eth_tx_tkeep,
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output wire [PORT_COUNT-1:0] m_axis_eth_tx_tvalid,
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input wire [PORT_COUNT-1:0] m_axis_eth_tx_tready,
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output wire [PORT_COUNT-1:0] m_axis_eth_tx_tlast,
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output wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] m_axis_eth_tx_tuser,
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input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] s_axis_eth_tx_cpl_ts,
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input wire [PORT_COUNT*TX_TAG_WIDTH-1:0] s_axis_eth_tx_cpl_tag,
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input wire [PORT_COUNT-1:0] s_axis_eth_tx_cpl_valid,
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output wire [PORT_COUNT-1:0] s_axis_eth_tx_cpl_ready,
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input wire [PORT_COUNT-1:0] eth_tx_status,
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input wire [PORT_COUNT-1:0] eth_rx_clk,
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input wire [PORT_COUNT-1:0] eth_rx_rst,
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input wire [PORT_COUNT-1:0] eth_rx_ptp_clk,
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input wire [PORT_COUNT-1:0] eth_rx_ptp_rst,
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output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96,
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output wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step,
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input wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] s_axis_eth_rx_tdata,
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input wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] s_axis_eth_rx_tkeep,
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input wire [PORT_COUNT-1:0] s_axis_eth_rx_tvalid,
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output wire [PORT_COUNT-1:0] s_axis_eth_rx_tready,
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input wire [PORT_COUNT-1:0] s_axis_eth_rx_tlast,
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input wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] s_axis_eth_rx_tuser,
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input wire [PORT_COUNT-1:0] eth_rx_status,
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/*
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* Statistics increment input
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*/
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input wire [STAT_INC_WIDTH-1:0] s_axis_stat_tdata,
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input wire [STAT_ID_WIDTH-1:0] s_axis_stat_tid,
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input wire s_axis_stat_tvalid,
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output wire s_axis_stat_tready,
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/*
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* GPIO
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*/
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input wire [APP_GPIO_IN_WIDTH-1:0] app_gpio_in,
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output wire [APP_GPIO_OUT_WIDTH-1:0] app_gpio_out,
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/*
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* JTAG
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*/
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input wire app_jtag_tdi,
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output wire app_jtag_tdo,
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input wire app_jtag_tms,
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input wire app_jtag_tck
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);
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parameter TLP_DATA_WIDTH = SEG_COUNT*SEG_DATA_WIDTH;
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parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32;
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parameter TLP_HDR_WIDTH = 128;
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parameter TLP_SEG_COUNT = 1;
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parameter TX_SEQ_NUM_COUNT = SEG_COUNT;
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wire [TLP_DATA_WIDTH-1:0] pcie_rx_req_tlp_data;
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wire [TLP_STRB_WIDTH-1:0] pcie_rx_req_tlp_strb;
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wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr;
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wire [TLP_SEG_COUNT*3-1:0] pcie_rx_req_tlp_bar_id;
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wire [TLP_SEG_COUNT*8-1:0] pcie_rx_req_tlp_func_num;
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wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_valid;
|
||||
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_sop;
|
||||
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_eop;
|
||||
wire pcie_rx_req_tlp_ready;
|
||||
|
||||
wire [TLP_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data;
|
||||
wire [TLP_STRB_WIDTH-1:0] pcie_rx_cpl_tlp_strb;
|
||||
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr;
|
||||
wire [TLP_SEG_COUNT*4-1:0] pcie_rx_cpl_tlp_error;
|
||||
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_valid;
|
||||
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_sop;
|
||||
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_eop;
|
||||
wire pcie_rx_cpl_tlp_ready;
|
||||
|
||||
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr;
|
||||
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_rd_req_tlp_seq;
|
||||
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_valid;
|
||||
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_sop;
|
||||
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_eop;
|
||||
wire pcie_tx_rd_req_tlp_ready;
|
||||
|
||||
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_rd_req_tx_seq_num;
|
||||
wire [TX_SEQ_NUM_COUNT-1:0] pcie_rd_req_tx_seq_num_valid;
|
||||
|
||||
wire [TLP_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data;
|
||||
wire [TLP_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb;
|
||||
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr;
|
||||
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_wr_req_tlp_seq;
|
||||
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_valid;
|
||||
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_sop;
|
||||
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_eop;
|
||||
wire pcie_tx_wr_req_tlp_ready;
|
||||
|
||||
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_wr_req_tx_seq_num;
|
||||
wire [TX_SEQ_NUM_COUNT-1:0] pcie_wr_req_tx_seq_num_valid;
|
||||
|
||||
wire [TLP_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data;
|
||||
wire [TLP_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb;
|
||||
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr;
|
||||
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_valid;
|
||||
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop;
|
||||
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop;
|
||||
wire pcie_tx_cpl_tlp_ready;
|
||||
|
||||
wire [31:0] pcie_tx_msix_wr_req_tlp_data;
|
||||
wire pcie_tx_msix_wr_req_tlp_strb;
|
||||
wire [TLP_HDR_WIDTH-1:0] pcie_tx_msix_wr_req_tlp_hdr;
|
||||
wire pcie_tx_msix_wr_req_tlp_valid;
|
||||
wire pcie_tx_msix_wr_req_tlp_sop;
|
||||
wire pcie_tx_msix_wr_req_tlp_eop;
|
||||
wire pcie_tx_msix_wr_req_tlp_ready;
|
||||
|
||||
wire [7:0] pcie_tx_fc_ph_av;
|
||||
wire [11:0] pcie_tx_fc_pd_av;
|
||||
wire [7:0] pcie_tx_fc_nph_av;
|
||||
|
||||
wire [F_COUNT-1:0] ext_tag_enable;
|
||||
wire [7:0] bus_num;
|
||||
wire [F_COUNT*3-1:0] max_read_request_size;
|
||||
wire [F_COUNT*3-1:0] max_payload_size;
|
||||
wire [F_COUNT-1:0] msix_enable;
|
||||
wire [F_COUNT-1:0] msix_mask;
|
||||
|
||||
pcie_ptile_if #(
|
||||
.SEG_COUNT(SEG_COUNT),
|
||||
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
|
||||
.SEG_EMPTY_WIDTH(SEG_EMPTY_WIDTH),
|
||||
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
|
||||
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
|
||||
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
|
||||
.TLP_SEG_COUNT(TLP_SEG_COUNT),
|
||||
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
|
||||
.PF_COUNT(1),
|
||||
.VF_COUNT(0),
|
||||
.F_COUNT(PF_COUNT+VF_COUNT),
|
||||
.IO_BAR_INDEX(5)
|
||||
)
|
||||
pcie_ptile_if_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* P-Tile RX AVST interface
|
||||
*/
|
||||
.rx_st_data(rx_st_data),
|
||||
.rx_st_empty(rx_st_empty),
|
||||
.rx_st_sop(rx_st_sop),
|
||||
.rx_st_eop(rx_st_eop),
|
||||
.rx_st_valid(rx_st_valid),
|
||||
.rx_st_ready(rx_st_ready),
|
||||
.rx_st_hdr(rx_st_hdr),
|
||||
.rx_st_tlp_prfx(rx_st_tlp_prfx),
|
||||
.rx_st_vf_active(rx_st_vf_active),
|
||||
.rx_st_func_num(rx_st_func_num),
|
||||
.rx_st_vf_num(rx_st_vf_num),
|
||||
.rx_st_bar_range(rx_st_bar_range),
|
||||
.rx_st_tlp_abort(rx_st_tlp_abort),
|
||||
|
||||
/*
|
||||
* P-Tile TX AVST interface
|
||||
*/
|
||||
.tx_st_data(tx_st_data),
|
||||
.tx_st_sop(tx_st_sop),
|
||||
.tx_st_eop(tx_st_eop),
|
||||
.tx_st_valid(tx_st_valid),
|
||||
.tx_st_ready(tx_st_ready),
|
||||
.tx_st_err(tx_st_err),
|
||||
.tx_st_hdr(tx_st_hdr),
|
||||
.tx_st_tlp_prfx(tx_st_tlp_prfx),
|
||||
|
||||
/*
|
||||
* P-Tile RX flow control
|
||||
*/
|
||||
.rx_buffer_limit(rx_buffer_limit),
|
||||
.rx_buffer_limit_tdm_idx(rx_buffer_limit_tdm_idx),
|
||||
|
||||
/*
|
||||
* P-Tile TX flow control
|
||||
*/
|
||||
.tx_cdts_limit(tx_cdts_limit),
|
||||
.tx_cdts_limit_tdm_idx(tx_cdts_limit_tdm_idx),
|
||||
|
||||
/*
|
||||
* P-Tile configuration interface
|
||||
*/
|
||||
.tl_cfg_ctl(tl_cfg_ctl),
|
||||
.tl_cfg_add(tl_cfg_add),
|
||||
.tl_cfg_func(tl_cfg_func),
|
||||
|
||||
/*
|
||||
* TLP output (request to BAR)
|
||||
*/
|
||||
.rx_req_tlp_data(pcie_rx_req_tlp_data),
|
||||
.rx_req_tlp_strb(pcie_rx_req_tlp_strb),
|
||||
.rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
|
||||
.rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
|
||||
.rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
|
||||
.rx_req_tlp_valid(pcie_rx_req_tlp_valid),
|
||||
.rx_req_tlp_sop(pcie_rx_req_tlp_sop),
|
||||
.rx_req_tlp_eop(pcie_rx_req_tlp_eop),
|
||||
.rx_req_tlp_ready(pcie_rx_req_tlp_ready),
|
||||
|
||||
/*
|
||||
* TLP output (completion to DMA)
|
||||
*/
|
||||
.rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
|
||||
.rx_cpl_tlp_strb(pcie_rx_cpl_tlp_strb),
|
||||
.rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
|
||||
.rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
|
||||
.rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
|
||||
.rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
|
||||
.rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
|
||||
.rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
|
||||
|
||||
/*
|
||||
* TLP input (read request from DMA)
|
||||
*/
|
||||
.tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
|
||||
.tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
|
||||
.tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
|
||||
.tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
|
||||
.tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
|
||||
.tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
|
||||
|
||||
/*
|
||||
* Transmit sequence number output (DMA read request)
|
||||
*/
|
||||
.m_axis_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
|
||||
.m_axis_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
|
||||
|
||||
/*
|
||||
* TLP input (write request from DMA)
|
||||
*/
|
||||
.tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
|
||||
.tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
|
||||
.tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
|
||||
.tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
|
||||
.tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
|
||||
.tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
|
||||
.tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
|
||||
.tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
|
||||
|
||||
/*
|
||||
* Transmit sequence number output (DMA write request)
|
||||
*/
|
||||
.m_axis_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
|
||||
.m_axis_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
|
||||
|
||||
/*
|
||||
* TLP input (completion from BAR)
|
||||
*/
|
||||
.tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
|
||||
.tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
|
||||
.tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
|
||||
.tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
|
||||
.tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
|
||||
.tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
|
||||
.tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
|
||||
|
||||
/*
|
||||
* TLP input (write request from MSI)
|
||||
*/
|
||||
.tx_msi_wr_req_tlp_data(pcie_tx_msix_wr_req_tlp_data),
|
||||
.tx_msi_wr_req_tlp_strb(pcie_tx_msix_wr_req_tlp_strb),
|
||||
.tx_msi_wr_req_tlp_hdr(pcie_tx_msix_wr_req_tlp_hdr),
|
||||
.tx_msi_wr_req_tlp_valid(pcie_tx_msix_wr_req_tlp_valid),
|
||||
.tx_msi_wr_req_tlp_sop(pcie_tx_msix_wr_req_tlp_sop),
|
||||
.tx_msi_wr_req_tlp_eop(pcie_tx_msix_wr_req_tlp_eop),
|
||||
.tx_msi_wr_req_tlp_ready(pcie_tx_msix_wr_req_tlp_ready),
|
||||
|
||||
/*
|
||||
* Flow control
|
||||
*/
|
||||
.tx_fc_ph_av(pcie_tx_fc_ph_av),
|
||||
.tx_fc_pd_av(pcie_tx_fc_pd_av),
|
||||
.tx_fc_nph_av(pcie_tx_fc_nph_av),
|
||||
.tx_fc_npd_av(),
|
||||
.tx_fc_cplh_av(),
|
||||
.tx_fc_cpld_av(),
|
||||
|
||||
/*
|
||||
* Configuration outputs
|
||||
*/
|
||||
.ext_tag_enable(ext_tag_enable),
|
||||
.bus_num(bus_num),
|
||||
.max_read_request_size(max_read_request_size),
|
||||
.max_payload_size(max_payload_size),
|
||||
.msix_enable(msix_enable),
|
||||
.msix_mask(msix_mask)
|
||||
);
|
||||
|
||||
mqnic_core_pcie #(
|
||||
// FW and board IDs
|
||||
.FPGA_ID(FPGA_ID),
|
||||
.FW_ID(FW_ID),
|
||||
.FW_VER(FW_VER),
|
||||
.BOARD_ID(BOARD_ID),
|
||||
.BOARD_VER(BOARD_VER),
|
||||
.BUILD_DATE(BUILD_DATE),
|
||||
.GIT_HASH(GIT_HASH),
|
||||
.RELEASE_INFO(RELEASE_INFO),
|
||||
|
||||
// Structural configuration
|
||||
.IF_COUNT(IF_COUNT),
|
||||
.PORTS_PER_IF(PORTS_PER_IF),
|
||||
.SCHED_PER_IF(SCHED_PER_IF),
|
||||
|
||||
.PORT_COUNT(PORT_COUNT),
|
||||
|
||||
// PTP configuration
|
||||
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
|
||||
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
|
||||
.PTP_TS_WIDTH(PTP_TS_WIDTH),
|
||||
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
|
||||
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
|
||||
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
|
||||
.PTP_SEPARATE_TX_CLOCK(PTP_SEPARATE_TX_CLOCK),
|
||||
.PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
|
||||
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
|
||||
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
|
||||
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
|
||||
|
||||
// Queue manager configuration
|
||||
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
|
||||
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
|
||||
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
|
||||
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
|
||||
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
|
||||
.EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH),
|
||||
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
|
||||
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
|
||||
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
|
||||
.RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
|
||||
.EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE),
|
||||
.TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE),
|
||||
.RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE),
|
||||
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
|
||||
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
|
||||
|
||||
// TX and RX engine configuration
|
||||
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
|
||||
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
|
||||
|
||||
// Scheduler configuration
|
||||
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
|
||||
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
|
||||
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
|
||||
|
||||
// Interface configuration
|
||||
.PTP_TS_ENABLE(PTP_TS_ENABLE),
|
||||
.TX_CPL_ENABLE(TX_CPL_ENABLE),
|
||||
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
|
||||
.TX_TAG_WIDTH(TX_TAG_WIDTH),
|
||||
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
|
||||
.RX_RSS_ENABLE(RX_RSS_ENABLE),
|
||||
.RX_HASH_ENABLE(RX_HASH_ENABLE),
|
||||
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
|
||||
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
|
||||
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
|
||||
.MAX_TX_SIZE(MAX_TX_SIZE),
|
||||
.MAX_RX_SIZE(MAX_RX_SIZE),
|
||||
.TX_RAM_SIZE(TX_RAM_SIZE),
|
||||
.RX_RAM_SIZE(RX_RAM_SIZE),
|
||||
|
||||
// Application block configuration
|
||||
.APP_ID(APP_ID),
|
||||
.APP_ENABLE(APP_ENABLE),
|
||||
.APP_CTRL_ENABLE(APP_CTRL_ENABLE),
|
||||
.APP_DMA_ENABLE(APP_DMA_ENABLE),
|
||||
.APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE),
|
||||
.APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE),
|
||||
.APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE),
|
||||
.APP_STAT_ENABLE(APP_STAT_ENABLE),
|
||||
|
||||
// DMA interface configuration
|
||||
.DMA_IMM_ENABLE(DMA_IMM_ENABLE),
|
||||
.DMA_IMM_WIDTH(DMA_IMM_WIDTH),
|
||||
.DMA_LEN_WIDTH(DMA_LEN_WIDTH),
|
||||
.DMA_TAG_WIDTH(DMA_TAG_WIDTH),
|
||||
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
|
||||
.RAM_PIPELINE(RAM_PIPELINE),
|
||||
|
||||
// PCIe interface configuration
|
||||
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
|
||||
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
|
||||
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
|
||||
.TLP_SEG_COUNT(TLP_SEG_COUNT),
|
||||
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
|
||||
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
|
||||
.TX_SEQ_NUM_ENABLE(1),
|
||||
.PF_COUNT(PF_COUNT),
|
||||
.VF_COUNT(VF_COUNT),
|
||||
.F_COUNT(F_COUNT),
|
||||
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
|
||||
.PCIE_DMA_READ_OP_TABLE_SIZE(PCIE_DMA_READ_OP_TABLE_SIZE),
|
||||
.PCIE_DMA_READ_TX_LIMIT(PCIE_DMA_READ_TX_LIMIT),
|
||||
.PCIE_DMA_READ_TX_FC_ENABLE(0),
|
||||
.PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE),
|
||||
.PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT),
|
||||
.PCIE_DMA_WRITE_TX_FC_ENABLE(0),
|
||||
.TLP_FORCE_64_BIT_ADDR(0),
|
||||
.CHECK_BUS_NUMBER(1),
|
||||
|
||||
// Interrupt configuration
|
||||
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH),
|
||||
|
||||
// AXI lite interface configuration (control)
|
||||
.AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
|
||||
.AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH),
|
||||
.AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH),
|
||||
.AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH),
|
||||
.AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH),
|
||||
.AXIL_CSR_PASSTHROUGH_ENABLE(AXIL_CSR_PASSTHROUGH_ENABLE),
|
||||
.RB_NEXT_PTR(RB_NEXT_PTR),
|
||||
|
||||
// AXI lite interface configuration (application control)
|
||||
.AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH),
|
||||
.AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH),
|
||||
|
||||
// Ethernet interface configuration
|
||||
.AXIS_DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
|
||||
.AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
|
||||
.AXIS_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH),
|
||||
.AXIS_IF_DATA_WIDTH(AXIS_ETH_IF_DATA_WIDTH),
|
||||
.AXIS_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
|
||||
.AXIS_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH),
|
||||
.AXIS_RX_USE_READY(AXIS_ETH_RX_USE_READY),
|
||||
.AXIS_TX_PIPELINE(AXIS_ETH_TX_PIPELINE),
|
||||
.AXIS_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE),
|
||||
.AXIS_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE),
|
||||
.AXIS_RX_PIPELINE(AXIS_ETH_RX_PIPELINE),
|
||||
.AXIS_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE),
|
||||
|
||||
// Statistics counter subsystem
|
||||
.STAT_ENABLE(STAT_ENABLE),
|
||||
.STAT_DMA_ENABLE(STAT_DMA_ENABLE),
|
||||
.STAT_PCIE_ENABLE(STAT_PCIE_ENABLE),
|
||||
.STAT_INC_WIDTH(STAT_INC_WIDTH),
|
||||
.STAT_ID_WIDTH(STAT_ID_WIDTH)
|
||||
)
|
||||
core_pcie_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* TLP input (request to BAR)
|
||||
*/
|
||||
.pcie_rx_req_tlp_data(pcie_rx_req_tlp_data),
|
||||
.pcie_rx_req_tlp_strb(pcie_rx_req_tlp_strb),
|
||||
.pcie_rx_req_tlp_hdr(pcie_rx_req_tlp_hdr),
|
||||
.pcie_rx_req_tlp_bar_id(pcie_rx_req_tlp_bar_id),
|
||||
.pcie_rx_req_tlp_func_num(pcie_rx_req_tlp_func_num),
|
||||
.pcie_rx_req_tlp_valid(pcie_rx_req_tlp_valid),
|
||||
.pcie_rx_req_tlp_sop(pcie_rx_req_tlp_sop),
|
||||
.pcie_rx_req_tlp_eop(pcie_rx_req_tlp_eop),
|
||||
.pcie_rx_req_tlp_ready(pcie_rx_req_tlp_ready),
|
||||
|
||||
/*
|
||||
* TLP input (completion to DMA)
|
||||
*/
|
||||
.pcie_rx_cpl_tlp_data(pcie_rx_cpl_tlp_data),
|
||||
.pcie_rx_cpl_tlp_strb(pcie_rx_cpl_tlp_strb),
|
||||
.pcie_rx_cpl_tlp_hdr(pcie_rx_cpl_tlp_hdr),
|
||||
.pcie_rx_cpl_tlp_error(pcie_rx_cpl_tlp_error),
|
||||
.pcie_rx_cpl_tlp_valid(pcie_rx_cpl_tlp_valid),
|
||||
.pcie_rx_cpl_tlp_sop(pcie_rx_cpl_tlp_sop),
|
||||
.pcie_rx_cpl_tlp_eop(pcie_rx_cpl_tlp_eop),
|
||||
.pcie_rx_cpl_tlp_ready(pcie_rx_cpl_tlp_ready),
|
||||
|
||||
/*
|
||||
* TLP output (read request from DMA)
|
||||
*/
|
||||
.pcie_tx_rd_req_tlp_hdr(pcie_tx_rd_req_tlp_hdr),
|
||||
.pcie_tx_rd_req_tlp_seq(pcie_tx_rd_req_tlp_seq),
|
||||
.pcie_tx_rd_req_tlp_valid(pcie_tx_rd_req_tlp_valid),
|
||||
.pcie_tx_rd_req_tlp_sop(pcie_tx_rd_req_tlp_sop),
|
||||
.pcie_tx_rd_req_tlp_eop(pcie_tx_rd_req_tlp_eop),
|
||||
.pcie_tx_rd_req_tlp_ready(pcie_tx_rd_req_tlp_ready),
|
||||
|
||||
/*
|
||||
* Transmit sequence number input (DMA read request)
|
||||
*/
|
||||
.s_axis_pcie_rd_req_tx_seq_num(pcie_rd_req_tx_seq_num),
|
||||
.s_axis_pcie_rd_req_tx_seq_num_valid(pcie_rd_req_tx_seq_num_valid),
|
||||
|
||||
/*
|
||||
* TLP output (write request from DMA)
|
||||
*/
|
||||
.pcie_tx_wr_req_tlp_data(pcie_tx_wr_req_tlp_data),
|
||||
.pcie_tx_wr_req_tlp_strb(pcie_tx_wr_req_tlp_strb),
|
||||
.pcie_tx_wr_req_tlp_hdr(pcie_tx_wr_req_tlp_hdr),
|
||||
.pcie_tx_wr_req_tlp_seq(pcie_tx_wr_req_tlp_seq),
|
||||
.pcie_tx_wr_req_tlp_valid(pcie_tx_wr_req_tlp_valid),
|
||||
.pcie_tx_wr_req_tlp_sop(pcie_tx_wr_req_tlp_sop),
|
||||
.pcie_tx_wr_req_tlp_eop(pcie_tx_wr_req_tlp_eop),
|
||||
.pcie_tx_wr_req_tlp_ready(pcie_tx_wr_req_tlp_ready),
|
||||
|
||||
/*
|
||||
* Transmit sequence number input (DMA write request)
|
||||
*/
|
||||
.s_axis_pcie_wr_req_tx_seq_num(pcie_wr_req_tx_seq_num),
|
||||
.s_axis_pcie_wr_req_tx_seq_num_valid(pcie_wr_req_tx_seq_num_valid),
|
||||
|
||||
/*
|
||||
* TLP output (completion from BAR)
|
||||
*/
|
||||
.pcie_tx_cpl_tlp_data(pcie_tx_cpl_tlp_data),
|
||||
.pcie_tx_cpl_tlp_strb(pcie_tx_cpl_tlp_strb),
|
||||
.pcie_tx_cpl_tlp_hdr(pcie_tx_cpl_tlp_hdr),
|
||||
.pcie_tx_cpl_tlp_valid(pcie_tx_cpl_tlp_valid),
|
||||
.pcie_tx_cpl_tlp_sop(pcie_tx_cpl_tlp_sop),
|
||||
.pcie_tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop),
|
||||
.pcie_tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready),
|
||||
|
||||
/*
|
||||
* TLP output (MSI-X write request)
|
||||
*/
|
||||
.pcie_tx_msix_wr_req_tlp_data(pcie_tx_msix_wr_req_tlp_data),
|
||||
.pcie_tx_msix_wr_req_tlp_strb(pcie_tx_msix_wr_req_tlp_strb),
|
||||
.pcie_tx_msix_wr_req_tlp_hdr(pcie_tx_msix_wr_req_tlp_hdr),
|
||||
.pcie_tx_msix_wr_req_tlp_valid(pcie_tx_msix_wr_req_tlp_valid),
|
||||
.pcie_tx_msix_wr_req_tlp_sop(pcie_tx_msix_wr_req_tlp_sop),
|
||||
.pcie_tx_msix_wr_req_tlp_eop(pcie_tx_msix_wr_req_tlp_eop),
|
||||
.pcie_tx_msix_wr_req_tlp_ready(pcie_tx_msix_wr_req_tlp_ready),
|
||||
|
||||
/*
|
||||
* Flow control credits
|
||||
*/
|
||||
.pcie_tx_fc_ph_av(pcie_tx_fc_ph_av),
|
||||
.pcie_tx_fc_pd_av(pcie_tx_fc_pd_av),
|
||||
.pcie_tx_fc_nph_av(pcie_tx_fc_nph_av),
|
||||
|
||||
/*
|
||||
* Configuration inputs
|
||||
*/
|
||||
.bus_num(bus_num),
|
||||
.ext_tag_enable(ext_tag_enable),
|
||||
.max_read_request_size(max_read_request_size),
|
||||
.max_payload_size(max_payload_size),
|
||||
.msix_enable(msix_enable),
|
||||
.msix_mask(msix_mask),
|
||||
|
||||
/*
|
||||
* PCIe error outputs
|
||||
*/
|
||||
.pcie_error_cor(),
|
||||
.pcie_error_uncor(),
|
||||
|
||||
/*
|
||||
* AXI-Lite master interface (passthrough for NIC control and status)
|
||||
*/
|
||||
.m_axil_csr_awaddr(m_axil_csr_awaddr),
|
||||
.m_axil_csr_awprot(m_axil_csr_awprot),
|
||||
.m_axil_csr_awvalid(m_axil_csr_awvalid),
|
||||
.m_axil_csr_awready(m_axil_csr_awready),
|
||||
.m_axil_csr_wdata(m_axil_csr_wdata),
|
||||
.m_axil_csr_wstrb(m_axil_csr_wstrb),
|
||||
.m_axil_csr_wvalid(m_axil_csr_wvalid),
|
||||
.m_axil_csr_wready(m_axil_csr_wready),
|
||||
.m_axil_csr_bresp(m_axil_csr_bresp),
|
||||
.m_axil_csr_bvalid(m_axil_csr_bvalid),
|
||||
.m_axil_csr_bready(m_axil_csr_bready),
|
||||
.m_axil_csr_araddr(m_axil_csr_araddr),
|
||||
.m_axil_csr_arprot(m_axil_csr_arprot),
|
||||
.m_axil_csr_arvalid(m_axil_csr_arvalid),
|
||||
.m_axil_csr_arready(m_axil_csr_arready),
|
||||
.m_axil_csr_rdata(m_axil_csr_rdata),
|
||||
.m_axil_csr_rresp(m_axil_csr_rresp),
|
||||
.m_axil_csr_rvalid(m_axil_csr_rvalid),
|
||||
.m_axil_csr_rready(m_axil_csr_rready),
|
||||
|
||||
/*
|
||||
* Control register interface
|
||||
*/
|
||||
.ctrl_reg_wr_addr(ctrl_reg_wr_addr),
|
||||
.ctrl_reg_wr_data(ctrl_reg_wr_data),
|
||||
.ctrl_reg_wr_strb(ctrl_reg_wr_strb),
|
||||
.ctrl_reg_wr_en(ctrl_reg_wr_en),
|
||||
.ctrl_reg_wr_wait(ctrl_reg_wr_wait),
|
||||
.ctrl_reg_wr_ack(ctrl_reg_wr_ack),
|
||||
.ctrl_reg_rd_addr(ctrl_reg_rd_addr),
|
||||
.ctrl_reg_rd_en(ctrl_reg_rd_en),
|
||||
.ctrl_reg_rd_data(ctrl_reg_rd_data),
|
||||
.ctrl_reg_rd_wait(ctrl_reg_rd_wait),
|
||||
.ctrl_reg_rd_ack(ctrl_reg_rd_ack),
|
||||
|
||||
/*
|
||||
* PTP clock
|
||||
*/
|
||||
.ptp_clk(ptp_clk),
|
||||
.ptp_rst(ptp_rst),
|
||||
.ptp_sample_clk(ptp_sample_clk),
|
||||
.ptp_pps(ptp_pps),
|
||||
.ptp_pps_str(ptp_pps_str),
|
||||
.ptp_ts_96(ptp_ts_96),
|
||||
.ptp_ts_step(ptp_ts_step),
|
||||
.ptp_sync_pps(ptp_sync_pps),
|
||||
.ptp_sync_ts_96(ptp_sync_ts_96),
|
||||
.ptp_sync_ts_step(ptp_sync_ts_step),
|
||||
.ptp_perout_locked(ptp_perout_locked),
|
||||
.ptp_perout_error(ptp_perout_error),
|
||||
.ptp_perout_pulse(ptp_perout_pulse),
|
||||
|
||||
/*
|
||||
* Ethernet
|
||||
*/
|
||||
.tx_clk(eth_tx_clk),
|
||||
.tx_rst(eth_tx_rst),
|
||||
|
||||
.tx_ptp_clk(eth_tx_ptp_clk),
|
||||
.tx_ptp_rst(eth_tx_ptp_rst),
|
||||
.tx_ptp_ts_96(eth_tx_ptp_ts_96),
|
||||
.tx_ptp_ts_step(eth_tx_ptp_ts_step),
|
||||
|
||||
.m_axis_tx_tdata(m_axis_eth_tx_tdata),
|
||||
.m_axis_tx_tkeep(m_axis_eth_tx_tkeep),
|
||||
.m_axis_tx_tvalid(m_axis_eth_tx_tvalid),
|
||||
.m_axis_tx_tready(m_axis_eth_tx_tready),
|
||||
.m_axis_tx_tlast(m_axis_eth_tx_tlast),
|
||||
.m_axis_tx_tuser(m_axis_eth_tx_tuser),
|
||||
|
||||
.s_axis_tx_cpl_ts(s_axis_eth_tx_cpl_ts),
|
||||
.s_axis_tx_cpl_tag(s_axis_eth_tx_cpl_tag),
|
||||
.s_axis_tx_cpl_valid(s_axis_eth_tx_cpl_valid),
|
||||
.s_axis_tx_cpl_ready(s_axis_eth_tx_cpl_ready),
|
||||
|
||||
.tx_status(eth_tx_status),
|
||||
|
||||
.rx_clk(eth_rx_clk),
|
||||
.rx_rst(eth_rx_rst),
|
||||
|
||||
.rx_ptp_clk(eth_rx_ptp_clk),
|
||||
.rx_ptp_rst(eth_rx_ptp_rst),
|
||||
.rx_ptp_ts_96(eth_rx_ptp_ts_96),
|
||||
.rx_ptp_ts_step(eth_rx_ptp_ts_step),
|
||||
|
||||
.s_axis_rx_tdata(s_axis_eth_rx_tdata),
|
||||
.s_axis_rx_tkeep(s_axis_eth_rx_tkeep),
|
||||
.s_axis_rx_tvalid(s_axis_eth_rx_tvalid),
|
||||
.s_axis_rx_tready(s_axis_eth_rx_tready),
|
||||
.s_axis_rx_tlast(s_axis_eth_rx_tlast),
|
||||
.s_axis_rx_tuser(s_axis_eth_rx_tuser),
|
||||
|
||||
.rx_status(eth_rx_status),
|
||||
|
||||
/*
|
||||
* Statistics input
|
||||
*/
|
||||
.s_axis_stat_tdata(s_axis_stat_tdata),
|
||||
.s_axis_stat_tid(s_axis_stat_tid),
|
||||
.s_axis_stat_tvalid(s_axis_stat_tvalid),
|
||||
.s_axis_stat_tready(s_axis_stat_tready),
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
.app_gpio_in(app_gpio_in),
|
||||
.app_gpio_out(app_gpio_out),
|
||||
|
||||
/*
|
||||
* JTAG
|
||||
*/
|
||||
.app_jtag_tdi(app_jtag_tdi),
|
||||
.app_jtag_tdo(app_jtag_tdo),
|
||||
.app_jtag_tms(app_jtag_tms),
|
||||
.app_jtag_tck(app_jtag_tck)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
477
fpga/common/tb/mqnic_core_pcie_ptile/Makefile
Normal file
477
fpga/common/tb/mqnic_core_pcie_ptile/Makefile
Normal file
@ -0,0 +1,477 @@
|
||||
# Copyright 2022, The Regents of the University of California.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright notice,
|
||||
# this list of conditions and the following disclaimer.
|
||||
#
|
||||
# 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
# this list of conditions and the following disclaimer in the documentation
|
||||
# and/or other materials provided with the distribution.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
# OF SUCH DAMAGE.
|
||||
#
|
||||
# The views and conclusions contained in the software and documentation are those
|
||||
# of the authors and should not be interpreted as representing official policies,
|
||||
# either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= icarus
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
DUT = mqnic_core_pcie_ptile
|
||||
TOPLEVEL = $(DUT)
|
||||
MODULE = test_$(DUT)
|
||||
VERILOG_SOURCES += ../../rtl/$(DUT).v
|
||||
VERILOG_SOURCES += ../../rtl/mqnic_core_pcie.v
|
||||
VERILOG_SOURCES += ../../rtl/mqnic_core.v
|
||||
VERILOG_SOURCES += ../../rtl/mqnic_interface.v
|
||||
VERILOG_SOURCES += ../../rtl/mqnic_interface_tx.v
|
||||
VERILOG_SOURCES += ../../rtl/mqnic_interface_rx.v
|
||||
VERILOG_SOURCES += ../../rtl/mqnic_port.v
|
||||
VERILOG_SOURCES += ../../rtl/mqnic_port_tx.v
|
||||
VERILOG_SOURCES += ../../rtl/mqnic_port_rx.v
|
||||
VERILOG_SOURCES += ../../rtl/mqnic_egress.v
|
||||
VERILOG_SOURCES += ../../rtl/mqnic_ingress.v
|
||||
VERILOG_SOURCES += ../../rtl/mqnic_l2_egress.v
|
||||
VERILOG_SOURCES += ../../rtl/mqnic_l2_ingress.v
|
||||
VERILOG_SOURCES += ../../rtl/mqnic_rx_queue_map.v
|
||||
VERILOG_SOURCES += ../../rtl/mqnic_ptp.v
|
||||
VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v
|
||||
VERILOG_SOURCES += ../../rtl/mqnic_ptp_perout.v
|
||||
VERILOG_SOURCES += ../../rtl/cpl_write.v
|
||||
VERILOG_SOURCES += ../../rtl/cpl_op_mux.v
|
||||
VERILOG_SOURCES += ../../rtl/desc_fetch.v
|
||||
VERILOG_SOURCES += ../../rtl/desc_op_mux.v
|
||||
VERILOG_SOURCES += ../../rtl/event_mux.v
|
||||
VERILOG_SOURCES += ../../rtl/queue_manager.v
|
||||
VERILOG_SOURCES += ../../rtl/cpl_queue_manager.v
|
||||
VERILOG_SOURCES += ../../rtl/tx_fifo.v
|
||||
VERILOG_SOURCES += ../../rtl/rx_fifo.v
|
||||
VERILOG_SOURCES += ../../rtl/tx_req_mux.v
|
||||
VERILOG_SOURCES += ../../rtl/tx_engine.v
|
||||
VERILOG_SOURCES += ../../rtl/rx_engine.v
|
||||
VERILOG_SOURCES += ../../rtl/tx_checksum.v
|
||||
VERILOG_SOURCES += ../../rtl/rx_hash.v
|
||||
VERILOG_SOURCES += ../../rtl/rx_checksum.v
|
||||
VERILOG_SOURCES += ../../rtl/stats_counter.v
|
||||
VERILOG_SOURCES += ../../rtl/stats_collect.v
|
||||
VERILOG_SOURCES += ../../rtl/stats_pcie_if.v
|
||||
VERILOG_SOURCES += ../../rtl/stats_pcie_tlp.v
|
||||
VERILOG_SOURCES += ../../rtl/stats_dma_if_pcie.v
|
||||
VERILOG_SOURCES += ../../rtl/stats_dma_latency.v
|
||||
VERILOG_SOURCES += ../../rtl/mqnic_tx_scheduler_block_rr.v
|
||||
VERILOG_SOURCES += ../../rtl/tx_scheduler_rr.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_rd.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_wr.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_rd.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_wr.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_rd.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_wr.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/arbiter.v
|
||||
VERILOG_SOURCES += ../../lib/axi/rtl/priority_encoder.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_desc_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_rd.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_wr.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_sink.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_source.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_ptile_if.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_ptile_if_rx.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_ptile_if_tx.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_ptile_cfg.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
# module parameters
|
||||
|
||||
# Structural configuration
|
||||
export PARAM_IF_COUNT ?= 1
|
||||
export PARAM_PORTS_PER_IF ?= 1
|
||||
export PARAM_SCHED_PER_IF ?= $(PARAM_PORTS_PER_IF)
|
||||
|
||||
# PTP configuration
|
||||
export PARAM_PTP_CLK_PERIOD_NS_NUM = 32
|
||||
export PARAM_PTP_CLK_PERIOD_NS_DENOM = 5
|
||||
export PARAM_PTP_CLOCK_PIPELINE ?= 0
|
||||
export PARAM_PTP_CLOCK_CDC_PIPELINE ?= 0
|
||||
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 1
|
||||
export PARAM_PTP_SEPARATE_TX_CLOCK ?= 0
|
||||
export PARAM_PTP_SEPARATE_RX_CLOCK ?= 0
|
||||
export PARAM_PTP_PORT_CDC_PIPELINE ?= 0
|
||||
export PARAM_PTP_PEROUT_ENABLE ?= 0
|
||||
export PARAM_PTP_PEROUT_COUNT ?= 1
|
||||
|
||||
# Queue manager configuration
|
||||
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE ?= 32
|
||||
export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
|
||||
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
|
||||
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
|
||||
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
|
||||
export PARAM_EVENT_QUEUE_INDEX_WIDTH ?= 6
|
||||
export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13
|
||||
export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8
|
||||
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH)
|
||||
export PARAM_RX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_RX_QUEUE_INDEX_WIDTH)
|
||||
export PARAM_EVENT_QUEUE_PIPELINE ?= 3
|
||||
export PARAM_TX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))")
|
||||
export PARAM_RX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))")
|
||||
export PARAM_TX_CPL_QUEUE_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
|
||||
export PARAM_RX_CPL_QUEUE_PIPELINE ?= $(PARAM_RX_QUEUE_PIPELINE)
|
||||
|
||||
# TX and RX engine configuration
|
||||
export PARAM_TX_DESC_TABLE_SIZE ?= 32
|
||||
export PARAM_RX_DESC_TABLE_SIZE ?= 32
|
||||
|
||||
# Scheduler configuration
|
||||
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE ?= $(PARAM_TX_DESC_TABLE_SIZE)
|
||||
export PARAM_TX_SCHEDULER_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
|
||||
export PARAM_TDMA_INDEX_WIDTH ?= 6
|
||||
|
||||
# Interface configuration
|
||||
export PARAM_PTP_TS_ENABLE ?= 1
|
||||
export PARAM_TX_CPL_ENABLE ?= $(PARAM_PTP_TS_ENABLE)
|
||||
export PARAM_TX_CPL_FIFO_DEPTH ?= 32
|
||||
export PARAM_TX_TAG_WIDTH ?= 16
|
||||
export PARAM_TX_CHECKSUM_ENABLE ?= 1
|
||||
export PARAM_RX_RSS_ENABLE ?= 1
|
||||
export PARAM_RX_HASH_ENABLE ?= 1
|
||||
export PARAM_RX_CHECKSUM_ENABLE ?= 1
|
||||
export PARAM_TX_FIFO_DEPTH ?= 32768
|
||||
export PARAM_RX_FIFO_DEPTH ?= 131072
|
||||
export PARAM_MAX_TX_SIZE ?= 9214
|
||||
export PARAM_MAX_RX_SIZE ?= 9214
|
||||
export PARAM_TX_RAM_SIZE ?= 131072
|
||||
export PARAM_RX_RAM_SIZE ?= 131072
|
||||
|
||||
# Application block configuration
|
||||
export PARAM_APP_ID ?= $(shell echo $$((0x00000000)) )
|
||||
export PARAM_APP_ENABLE ?= 0
|
||||
export PARAM_APP_CTRL_ENABLE ?= 1
|
||||
export PARAM_APP_DMA_ENABLE ?= 1
|
||||
export PARAM_APP_AXIS_DIRECT_ENABLE ?= 1
|
||||
export PARAM_APP_AXIS_SYNC_ENABLE ?= 1
|
||||
export PARAM_APP_AXIS_IF_ENABLE ?= 1
|
||||
export PARAM_APP_STAT_ENABLE ?= 1
|
||||
|
||||
# DMA interface configuration
|
||||
export PARAM_DMA_IMM_ENABLE ?= 0
|
||||
export PARAM_DMA_IMM_WIDTH ?= 32
|
||||
export PARAM_DMA_LEN_WIDTH ?= 16
|
||||
export PARAM_DMA_TAG_WIDTH ?= 16
|
||||
export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
|
||||
export PARAM_RAM_PIPELINE ?= 2
|
||||
|
||||
# PCIe interface configuration
|
||||
export PARAM_SEG_COUNT ?= 2
|
||||
export PARAM_SEG_DATA_WIDTH ?= 256
|
||||
export PARAM_SEG_EMPTY_WIDTH ?= $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" )
|
||||
export PARAM_SEG_HDR_WIDTH ?= 128
|
||||
export PARAM_SEG_PRFX_WIDTH ?= 32
|
||||
export PARAM_TX_SEQ_NUM_WIDTH ?= 6
|
||||
export PARAM_TX_SEQ_NUM_ENABLE ?= 1
|
||||
export PARAM_PF_COUNT ?= 1
|
||||
export PARAM_VF_COUNT ?= 0
|
||||
export PARAM_PCIE_TAG_COUNT ?= 256
|
||||
export PARAM_PCIE_DMA_READ_OP_TABLE_SIZE ?= $(PARAM_PCIE_TAG_COUNT)
|
||||
export PARAM_PCIE_DMA_READ_TX_LIMIT ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
|
||||
export PARAM_PCIE_DMA_READ_TX_FC_ENABLE ?= 1
|
||||
export PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
|
||||
export PARAM_PCIE_DMA_WRITE_TX_LIMIT ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH) ))" )
|
||||
export PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE ?= 1
|
||||
|
||||
# Interrupt configuration
|
||||
export PARAM_IRQ_INDEX_WIDTH ?= $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
|
||||
|
||||
# AXI lite interface configuration (control)
|
||||
export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32
|
||||
export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24
|
||||
export PARAM_AXIL_CSR_PASSTHROUGH_ENABLE ?= 0
|
||||
|
||||
# AXI lite interface configuration (application control)
|
||||
export PARAM_AXIL_APP_CTRL_DATA_WIDTH ?= $(PARAM_AXIL_CTRL_DATA_WIDTH)
|
||||
export PARAM_AXIL_APP_CTRL_ADDR_WIDTH ?= 24
|
||||
|
||||
# Ethernet interface configuration
|
||||
export PARAM_AXIS_ETH_DATA_WIDTH ?= 512
|
||||
export PARAM_AXIS_ETH_SYNC_DATA_WIDTH ?= $(PARAM_AXIS_ETH_DATA_WIDTH)
|
||||
export PARAM_AXIS_ETH_RX_USE_READY ?= 0
|
||||
export PARAM_AXIS_ETH_TX_PIPELINE ?= 0
|
||||
export PARAM_AXIS_ETH_TX_FIFO_PIPELINE ?= 2
|
||||
export PARAM_AXIS_ETH_TX_TS_PIPELINE ?= 0
|
||||
export PARAM_AXIS_ETH_RX_PIPELINE ?= 0
|
||||
export PARAM_AXIS_ETH_RX_FIFO_PIPELINE ?= 2
|
||||
|
||||
# Statistics counter subsystem
|
||||
export PARAM_STAT_ENABLE ?= 1
|
||||
export PARAM_STAT_DMA_ENABLE ?= 1
|
||||
export PARAM_STAT_PCIE_ENABLE ?= 1
|
||||
export PARAM_STAT_INC_WIDTH ?= 24
|
||||
export PARAM_STAT_ID_WIDTH ?= 12
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).SCHED_PER_IF=$(PARAM_SCHED_PER_IF)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_TX_CLOCK=$(PARAM_PTP_SEPARATE_TX_CLOCK)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_COUNT=$(PARAM_PTP_PEROUT_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).EVENT_QUEUE_OP_TABLE_SIZE=$(PARAM_EVENT_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).EVENT_QUEUE_INDEX_WIDTH=$(PARAM_EVENT_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_INDEX_WIDTH=$(PARAM_TX_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_INDEX_WIDTH=$(PARAM_RX_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_TX_CPL_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_RX_CPL_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).EVENT_QUEUE_PIPELINE=$(PARAM_EVENT_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_PIPELINE=$(PARAM_TX_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_PIPELINE=$(PARAM_RX_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_PIPELINE=$(PARAM_TX_CPL_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_PIPELINE=$(PARAM_RX_CPL_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_DESC_TABLE_SIZE=$(PARAM_TX_DESC_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_DESC_TABLE_SIZE=$(PARAM_RX_DESC_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_OP_TABLE_SIZE=$(PARAM_TX_SCHEDULER_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_ENABLE=$(PARAM_TX_CPL_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).MAX_TX_SIZE=$(PARAM_MAX_TX_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).MAX_RX_SIZE=$(PARAM_MAX_RX_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_RAM_SIZE=$(PARAM_TX_RAM_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RX_RAM_SIZE=$(PARAM_RX_RAM_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_ID=$(PARAM_APP_ID)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_ENABLE=$(PARAM_APP_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_CTRL_ENABLE=$(PARAM_APP_CTRL_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_DMA_ENABLE=$(PARAM_APP_DMA_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_DIRECT_ENABLE=$(PARAM_APP_AXIS_DIRECT_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).DMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).SEG_COUNT=$(PARAM_SEG_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).SEG_DATA_WIDTH=$(PARAM_SEG_DATA_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).SEG_EMPTY_WIDTH=$(PARAM_SEG_EMPTY_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).SEG_HDR_WIDTH=$(PARAM_SEG_HDR_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).SEG_PRFX_WIDTH=$(PARAM_SEG_PRFX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_SEQ_NUM_WIDTH=$(PARAM_TX_SEQ_NUM_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).TX_SEQ_NUM_ENABLE=$(PARAM_TX_SEQ_NUM_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PF_COUNT=$(PARAM_PF_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).VF_COUNT=$(PARAM_VF_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_READ_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_READ_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_READ_TX_LIMIT=$(PARAM_PCIE_DMA_READ_TX_LIMIT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_READ_TX_FC_ENABLE=$(PARAM_PCIE_DMA_READ_TX_FC_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).IRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CSR_PASSTHROUGH_ENABLE=$(PARAM_AXIL_CSR_PASSTHROUGH_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_ADDR_WIDTH=$(PARAM_AXIL_APP_CTRL_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_DATA_WIDTH=$(PARAM_AXIS_ETH_DATA_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_SYNC_DATA_WIDTH=$(PARAM_AXIS_ETH_SYNC_DATA_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_RX_USE_READY=$(PARAM_AXIS_ETH_RX_USE_READY)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_PIPELINE=$(PARAM_AXIS_ETH_TX_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_TX_FIFO_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_TX_TS_PIPELINE=$(PARAM_AXIS_ETH_TX_TS_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_RX_PIPELINE=$(PARAM_AXIS_ETH_RX_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_ETH_RX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_RX_FIFO_PIPELINE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_ENABLE=$(PARAM_STAT_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_DMA_ENABLE=$(PARAM_STAT_DMA_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_PCIE_ENABLE=$(PARAM_STAT_PCIE_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_INC_WIDTH=$(PARAM_STAT_INC_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).STAT_ID_WIDTH=$(PARAM_STAT_ID_WIDTH)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
VERILOG_SOURCES += iverilog_dump.v
|
||||
COMPILE_ARGS += -s iverilog_dump
|
||||
endif
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
|
||||
|
||||
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
|
||||
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
|
||||
COMPILE_ARGS += -GSCHED_PER_IF=$(PARAM_SCHED_PER_IF)
|
||||
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_NUM=$(PARAM_PTP_CLK_PERIOD_NS_NUM)
|
||||
COMPILE_ARGS += -GPTP_CLK_PERIOD_NS_DENOM=$(PARAM_PTP_CLK_PERIOD_NS_DENOM)
|
||||
COMPILE_ARGS += -GPTP_CLOCK_PIPELINE=$(PARAM_PTP_CLOCK_PIPELINE)
|
||||
COMPILE_ARGS += -GPTP_CLOCK_CDC_PIPELINE=$(PARAM_PTP_CLOCK_CDC_PIPELINE)
|
||||
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
|
||||
COMPILE_ARGS += -GPTP_SEPARATE_TX_CLOCK=$(PARAM_PTP_SEPARATE_TX_CLOCK)
|
||||
COMPILE_ARGS += -GPTP_SEPARATE_RX_CLOCK=$(PARAM_PTP_SEPARATE_RX_CLOCK)
|
||||
COMPILE_ARGS += -GPTP_PORT_CDC_PIPELINE=$(PARAM_PTP_PORT_CDC_PIPELINE)
|
||||
COMPILE_ARGS += -GPTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
|
||||
COMPILE_ARGS += -GPTP_PEROUT_COUNT=$(PARAM_PTP_PEROUT_COUNT)
|
||||
COMPILE_ARGS += -GEVENT_QUEUE_OP_TABLE_SIZE=$(PARAM_EVENT_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GTX_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GRX_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GTX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GRX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GEVENT_QUEUE_INDEX_WIDTH=$(PARAM_EVENT_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GTX_QUEUE_INDEX_WIDTH=$(PARAM_TX_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GRX_QUEUE_INDEX_WIDTH=$(PARAM_RX_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GTX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_TX_CPL_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GRX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_RX_CPL_QUEUE_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GEVENT_QUEUE_PIPELINE=$(PARAM_EVENT_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GTX_QUEUE_PIPELINE=$(PARAM_TX_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GRX_QUEUE_PIPELINE=$(PARAM_RX_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GTX_CPL_QUEUE_PIPELINE=$(PARAM_TX_CPL_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GRX_CPL_QUEUE_PIPELINE=$(PARAM_RX_CPL_QUEUE_PIPELINE)
|
||||
COMPILE_ARGS += -GTX_DESC_TABLE_SIZE=$(PARAM_TX_DESC_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GRX_DESC_TABLE_SIZE=$(PARAM_RX_DESC_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GTX_SCHEDULER_OP_TABLE_SIZE=$(PARAM_TX_SCHEDULER_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GTX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
|
||||
COMPILE_ARGS += -GTDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
|
||||
COMPILE_ARGS += -GTX_CPL_ENABLE=$(PARAM_TX_CPL_ENABLE)
|
||||
COMPILE_ARGS += -GTX_CPL_FIFO_DEPTH=$(PARAM_TX_CPL_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -GTX_TAG_WIDTH=$(PARAM_TX_TAG_WIDTH)
|
||||
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
|
||||
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
|
||||
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
|
||||
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
|
||||
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -GRX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH)
|
||||
COMPILE_ARGS += -GMAX_TX_SIZE=$(PARAM_MAX_TX_SIZE)
|
||||
COMPILE_ARGS += -GMAX_RX_SIZE=$(PARAM_MAX_RX_SIZE)
|
||||
COMPILE_ARGS += -GTX_RAM_SIZE=$(PARAM_TX_RAM_SIZE)
|
||||
COMPILE_ARGS += -GRX_RAM_SIZE=$(PARAM_RX_RAM_SIZE)
|
||||
COMPILE_ARGS += -GAPP_ID=$(PARAM_APP_ID)
|
||||
COMPILE_ARGS += -GAPP_ENABLE=$(PARAM_APP_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_CTRL_ENABLE=$(PARAM_APP_CTRL_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_DMA_ENABLE=$(PARAM_APP_DMA_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_AXIS_DIRECT_ENABLE=$(PARAM_APP_AXIS_DIRECT_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
|
||||
COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
|
||||
COMPILE_ARGS += -GDMA_IMM_ENABLE=$(PARAM_DMA_IMM_ENABLE)
|
||||
COMPILE_ARGS += -GDMA_IMM_WIDTH=$(PARAM_DMA_IMM_WIDTH)
|
||||
COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
|
||||
COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
|
||||
COMPILE_ARGS += -GRAM_ADDR_WIDTH=$(PARAM_RAM_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE)
|
||||
COMPILE_ARGS += -GSEG_COUNT=$(PARAM_SEG_COUNT)
|
||||
COMPILE_ARGS += -GSEG_DATA_WIDTH=$(PARAM_SEG_DATA_WIDTH)
|
||||
COMPILE_ARGS += -GSEG_EMPTY_WIDTH=$(PARAM_SEG_EMPTY_WIDTH)
|
||||
COMPILE_ARGS += -GSEG_HDR_WIDTH=$(PARAM_SEG_HDR_WIDTH)
|
||||
COMPILE_ARGS += -GSEG_PRFX_WIDTH=$(PARAM_SEG_PRFX_WIDTH)
|
||||
COMPILE_ARGS += -GTX_SEQ_NUM_WIDTH=$(PARAM_TX_SEQ_NUM_WIDTH)
|
||||
COMPILE_ARGS += -GTX_SEQ_NUM_ENABLE=$(PARAM_TX_SEQ_NUM_ENABLE)
|
||||
COMPILE_ARGS += -GPF_COUNT=$(PARAM_PF_COUNT)
|
||||
COMPILE_ARGS += -GVF_COUNT=$(PARAM_VF_COUNT)
|
||||
COMPILE_ARGS += -GPCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -GPCIE_DMA_READ_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_READ_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GPCIE_DMA_READ_TX_LIMIT=$(PARAM_PCIE_DMA_READ_TX_LIMIT)
|
||||
COMPILE_ARGS += -GPCIE_DMA_READ_TX_FC_ENABLE=$(PARAM_PCIE_DMA_READ_TX_FC_ENABLE)
|
||||
COMPILE_ARGS += -GPCIE_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_PCIE_DMA_WRITE_OP_TABLE_SIZE)
|
||||
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_LIMIT=$(PARAM_PCIE_DMA_WRITE_TX_LIMIT)
|
||||
COMPILE_ARGS += -GPCIE_DMA_WRITE_TX_FC_ENABLE=$(PARAM_PCIE_DMA_WRITE_TX_FC_ENABLE)
|
||||
COMPILE_ARGS += -GIRQ_INDEX_WIDTH=$(PARAM_IRQ_INDEX_WIDTH)
|
||||
COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
|
||||
COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -GAXIL_CSR_PASSTHROUGH_ENABLE=$(PARAM_AXIL_CSR_PASSTHROUGH_ENABLE)
|
||||
COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)
|
||||
COMPILE_ARGS += -GAXIL_APP_CTRL_ADDR_WIDTH=$(PARAM_AXIL_APP_CTRL_ADDR_WIDTH)
|
||||
COMPILE_ARGS += -GAXIS_ETH_DATA_WIDTH=$(PARAM_AXIS_ETH_DATA_WIDTH)
|
||||
COMPILE_ARGS += -GAXIS_ETH_SYNC_DATA_WIDTH=$(PARAM_AXIS_ETH_SYNC_DATA_WIDTH)
|
||||
COMPILE_ARGS += -GAXIS_ETH_RX_USE_READY=$(PARAM_AXIS_ETH_RX_USE_READY)
|
||||
COMPILE_ARGS += -GAXIS_ETH_TX_PIPELINE=$(PARAM_AXIS_ETH_TX_PIPELINE)
|
||||
COMPILE_ARGS += -GAXIS_ETH_TX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_TX_FIFO_PIPELINE)
|
||||
COMPILE_ARGS += -GAXIS_ETH_TX_TS_PIPELINE=$(PARAM_AXIS_ETH_TX_TS_PIPELINE)
|
||||
COMPILE_ARGS += -GAXIS_ETH_RX_PIPELINE=$(PARAM_AXIS_ETH_RX_PIPELINE)
|
||||
COMPILE_ARGS += -GAXIS_ETH_RX_FIFO_PIPELINE=$(PARAM_AXIS_ETH_RX_FIFO_PIPELINE)
|
||||
COMPILE_ARGS += -GSTAT_ENABLE=$(PARAM_STAT_ENABLE)
|
||||
COMPILE_ARGS += -GSTAT_DMA_ENABLE=$(PARAM_STAT_DMA_ENABLE)
|
||||
COMPILE_ARGS += -GSTAT_PCIE_ENABLE=$(PARAM_STAT_PCIE_ENABLE)
|
||||
COMPILE_ARGS += -GSTAT_INC_WIDTH=$(PARAM_STAT_INC_WIDTH)
|
||||
COMPILE_ARGS += -GSTAT_ID_WIDTH=$(PARAM_STAT_ID_WIDTH)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
|
||||
iverilog_dump.v:
|
||||
echo 'module iverilog_dump();' > $@
|
||||
echo 'initial begin' >> $@
|
||||
echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@
|
||||
echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@
|
||||
echo 'end' >> $@
|
||||
echo 'endmodule' >> $@
|
||||
|
||||
clean::
|
||||
@rm -rf iverilog_dump.v
|
||||
@rm -rf dump.fst $(TOPLEVEL).fst
|
||||
1
fpga/common/tb/mqnic_core_pcie_ptile/mqnic.py
Symbolic link
1
fpga/common/tb/mqnic_core_pcie_ptile/mqnic.py
Symbolic link
@ -0,0 +1 @@
|
||||
../mqnic.py
|
||||
@ -0,0 +1,902 @@
|
||||
"""
|
||||
|
||||
Copyright 2022, The Regents of the University of California.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
|
||||
The views and conclusions contained in the software and documentation are those
|
||||
of the authors and should not be interpreted as representing official policies,
|
||||
either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
"""
|
||||
|
||||
import logging
|
||||
import os
|
||||
import sys
|
||||
|
||||
import scapy.utils
|
||||
from scapy.layers.l2 import Ether
|
||||
from scapy.layers.inet import IP, UDP
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.log import SimLog
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge, FallingEdge, Timer
|
||||
|
||||
from cocotbext.axi import AxiStreamBus
|
||||
from cocotbext.eth import EthMac
|
||||
from cocotbext.pcie.core import RootComplex
|
||||
from cocotbext.pcie.intel.ptile import PTilePcieDevice, PTileRxBus, PTileTxBus
|
||||
|
||||
try:
|
||||
import mqnic
|
||||
except ImportError:
|
||||
# attempt import from current directory
|
||||
sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
|
||||
try:
|
||||
import mqnic
|
||||
finally:
|
||||
del sys.path[0]
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut, msix_count=32):
|
||||
self.dut = dut
|
||||
|
||||
self.log = SimLog("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
# PCIe
|
||||
self.rc = RootComplex()
|
||||
|
||||
self.rc.max_payload_size = 0x1 # 256 bytes
|
||||
self.rc.max_read_request_size = 0x2 # 512 bytes
|
||||
|
||||
self.dev = PTilePcieDevice(
|
||||
# configuration options
|
||||
pcie_generation=3,
|
||||
# pcie_link_width=2,
|
||||
# pld_clk_frequency=250e6,
|
||||
pf_count=1,
|
||||
max_payload_size=512,
|
||||
enable_extended_tag=True,
|
||||
|
||||
pf0_msi_enable=False,
|
||||
pf0_msi_count=1,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=True,
|
||||
pf0_msix_table_size=msix_count-1,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_table_offset=0x00010000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00018000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
pf2_msix_enable=False,
|
||||
pf2_msix_table_size=0,
|
||||
pf2_msix_table_bir=0,
|
||||
pf2_msix_table_offset=0x00000000,
|
||||
pf2_msix_pba_bir=0,
|
||||
pf2_msix_pba_offset=0x00000000,
|
||||
pf3_msix_enable=False,
|
||||
pf3_msix_table_size=0,
|
||||
pf3_msix_table_bir=0,
|
||||
pf3_msix_table_offset=0x00000000,
|
||||
pf3_msix_pba_bir=0,
|
||||
pf3_msix_pba_offset=0x00000000,
|
||||
|
||||
# signals
|
||||
# Clock and reset
|
||||
reset_status=dut.rst,
|
||||
# reset_status_n=dut.reset_status_n,
|
||||
coreclkout_hip=dut.clk,
|
||||
# refclk0=dut.refclk0,
|
||||
# refclk1=dut.refclk1,
|
||||
# pin_perst_n=dut.pin_perst_n,
|
||||
|
||||
# RX interface
|
||||
rx_bus=PTileRxBus.from_prefix(dut, "rx_st"),
|
||||
# rx_par_err=dut.rx_par_err,
|
||||
|
||||
# TX interface
|
||||
tx_bus=PTileTxBus.from_prefix(dut, "tx_st"),
|
||||
# tx_par_err=dut.tx_par_err,
|
||||
|
||||
# RX flow control
|
||||
rx_buffer_limit=dut.rx_buffer_limit,
|
||||
rx_buffer_limit_tdm_idx=dut.rx_buffer_limit_tdm_idx,
|
||||
|
||||
# TX flow control
|
||||
tx_cdts_limit=dut.tx_cdts_limit,
|
||||
tx_cdts_limit_tdm_idx=dut.tx_cdts_limit_tdm_idx,
|
||||
|
||||
# Power management and hard IP status interface
|
||||
# link_up=dut.link_up,
|
||||
# dl_up=dut.dl_up,
|
||||
# surprise_down_err=dut.surprise_down_err,
|
||||
# ltssm_state=dut.ltssm_state,
|
||||
# pm_state=dut.pm_state,
|
||||
# pm_dstate=dut.pm_dstate,
|
||||
# apps_pm_xmt_pme=dut.apps_pm_xmt_pme,
|
||||
# app_req_retry_en=dut.app_req_retry_en,
|
||||
|
||||
# Interrupt interface
|
||||
# app_int=dut.app_int,
|
||||
# msi_pnd_func=dut.msi_pnd_func,
|
||||
# msi_pnd_byte=dut.msi_pnd_byte,
|
||||
# msi_pnd_addr=dut.msi_pnd_addr,
|
||||
|
||||
# Error interface
|
||||
# serr_out=dut.serr_out,
|
||||
# hip_enter_err_mode=dut.hip_enter_err_mode,
|
||||
# app_err_valid=dut.app_err_valid,
|
||||
# app_err_hdr=dut.app_err_hdr,
|
||||
# app_err_info=dut.app_err_info,
|
||||
# app_err_func_num=dut.app_err_func_num,
|
||||
|
||||
# Completion timeout interface
|
||||
# cpl_timeout=dut.cpl_timeout,
|
||||
# cpl_timeout_avmm_clk=dut.cpl_timeout_avmm_clk,
|
||||
# cpl_timeout_avmm_address=dut.cpl_timeout_avmm_address,
|
||||
# cpl_timeout_avmm_read=dut.cpl_timeout_avmm_read,
|
||||
# cpl_timeout_avmm_readdata=dut.cpl_timeout_avmm_readdata,
|
||||
# cpl_timeout_avmm_readdatavalid=dut.cpl_timeout_avmm_readdatavalid,
|
||||
# cpl_timeout_avmm_write=dut.cpl_timeout_avmm_write,
|
||||
# cpl_timeout_avmm_writedata=dut.cpl_timeout_avmm_writedata,
|
||||
# cpl_timeout_avmm_waitrequest=dut.cpl_timeout_avmm_waitrequest,
|
||||
|
||||
# Configuration output
|
||||
tl_cfg_func=dut.tl_cfg_func,
|
||||
tl_cfg_add=dut.tl_cfg_add,
|
||||
tl_cfg_ctl=dut.tl_cfg_ctl,
|
||||
# dl_timer_update=dut.dl_timer_update,
|
||||
|
||||
# Configuration intercept interface
|
||||
# cii_req=dut.cii_req,
|
||||
# cii_hdr_poisoned=dut.cii_hdr_poisoned,
|
||||
# cii_hdr_first_be=dut.cii_hdr_first_be,
|
||||
# cii_func_num=dut.cii_func_num,
|
||||
# cii_wr_vf_active=dut.cii_wr_vf_active,
|
||||
# cii_vf_num=dut.cii_vf_num,
|
||||
# cii_wr=dut.cii_wr,
|
||||
# cii_addr=dut.cii_addr,
|
||||
# cii_dout=dut.cii_dout,
|
||||
# cii_override_en=dut.cii_override_en,
|
||||
# cii_override_din=dut.cii_override_din,
|
||||
# cii_halt=dut.cii_halt,
|
||||
|
||||
# Hard IP reconfiguration interface
|
||||
# hip_reconfig_clk=dut.hip_reconfig_clk,
|
||||
# hip_reconfig_address=dut.hip_reconfig_address,
|
||||
# hip_reconfig_read=dut.hip_reconfig_read,
|
||||
# hip_reconfig_readdata=dut.hip_reconfig_readdata,
|
||||
# hip_reconfig_readdatavalid=dut.hip_reconfig_readdatavalid,
|
||||
# hip_reconfig_write=dut.hip_reconfig_write,
|
||||
# hip_reconfig_writedata=dut.hip_reconfig_writedata,
|
||||
# hip_reconfig_waitrequest=dut.hip_reconfig_waitrequest,
|
||||
|
||||
# Page request service
|
||||
# prs_event_valid=dut.prs_event_valid,
|
||||
# prs_event_func=dut.prs_event_func,
|
||||
# prs_event=dut.prs_event,
|
||||
|
||||
# SR-IOV (VF error)
|
||||
# vf_err_ur_posted_s0=dut.vf_err_ur_posted_s0,
|
||||
# vf_err_ur_posted_s1=dut.vf_err_ur_posted_s1,
|
||||
# vf_err_ur_posted_s2=dut.vf_err_ur_posted_s2,
|
||||
# vf_err_ur_posted_s3=dut.vf_err_ur_posted_s3,
|
||||
# vf_err_func_num_s0=dut.vf_err_func_num_s0,
|
||||
# vf_err_func_num_s1=dut.vf_err_func_num_s1,
|
||||
# vf_err_func_num_s2=dut.vf_err_func_num_s2,
|
||||
# vf_err_func_num_s3=dut.vf_err_func_num_s3,
|
||||
# vf_err_ca_postedreq_s0=dut.vf_err_ca_postedreq_s0,
|
||||
# vf_err_ca_postedreq_s1=dut.vf_err_ca_postedreq_s1,
|
||||
# vf_err_ca_postedreq_s2=dut.vf_err_ca_postedreq_s2,
|
||||
# vf_err_ca_postedreq_s3=dut.vf_err_ca_postedreq_s3,
|
||||
# vf_err_vf_num_s0=dut.vf_err_vf_num_s0,
|
||||
# vf_err_vf_num_s1=dut.vf_err_vf_num_s1,
|
||||
# vf_err_vf_num_s2=dut.vf_err_vf_num_s2,
|
||||
# vf_err_vf_num_s3=dut.vf_err_vf_num_s3,
|
||||
# vf_err_poisonedwrreq_s0=dut.vf_err_poisonedwrreq_s0,
|
||||
# vf_err_poisonedwrreq_s1=dut.vf_err_poisonedwrreq_s1,
|
||||
# vf_err_poisonedwrreq_s2=dut.vf_err_poisonedwrreq_s2,
|
||||
# vf_err_poisonedwrreq_s3=dut.vf_err_poisonedwrreq_s3,
|
||||
# vf_err_poisonedcompl_s0=dut.vf_err_poisonedcompl_s0,
|
||||
# vf_err_poisonedcompl_s1=dut.vf_err_poisonedcompl_s1,
|
||||
# vf_err_poisonedcompl_s2=dut.vf_err_poisonedcompl_s2,
|
||||
# vf_err_poisonedcompl_s3=dut.vf_err_poisonedcompl_s3,
|
||||
# user_vfnonfatalmsg_func_num=dut.user_vfnonfatalmsg_func_num,
|
||||
# user_vfnonfatalmsg_vfnum=dut.user_vfnonfatalmsg_vfnum,
|
||||
# user_sent_vfnonfatalmsg=dut.user_sent_vfnonfatalmsg,
|
||||
# vf_err_overflow=dut.vf_err_overflow,
|
||||
|
||||
# FLR
|
||||
# flr_rcvd_pf=dut.flr_rcvd_pf,
|
||||
# flr_rcvd_vf=dut.flr_rcvd_vf,
|
||||
# flr_rcvd_pf_num=dut.flr_rcvd_pf_num,
|
||||
# flr_rcvd_vf_num=dut.flr_rcvd_vf_num,
|
||||
# flr_completed_pf=dut.flr_completed_pf,
|
||||
# flr_completed_vf=dut.flr_completed_vf,
|
||||
# flr_completed_pf_num=dut.flr_completed_pf_num,
|
||||
# flr_completed_vf_num=dut.flr_completed_vf_num,
|
||||
|
||||
# VirtIO
|
||||
# virtio_pcicfg_vfaccess=dut.virtio_pcicfg_vfaccess,
|
||||
# virtio_pcicfg_vfnum=dut.virtio_pcicfg_vfnum,
|
||||
# virtio_pcicfg_pfnum=dut.virtio_pcicfg_pfnum,
|
||||
# virtio_pcicfg_bar=dut.virtio_pcicfg_bar,
|
||||
# virtio_pcicfg_length=dut.virtio_pcicfg_length,
|
||||
# virtio_pcicfg_baroffset=dut.virtio_pcicfg_baroffset,
|
||||
# virtio_pcicfg_cfgdata=dut.virtio_pcicfg_cfgdata,
|
||||
# virtio_pcicfg_cfgwr=dut.virtio_pcicfg_cfgwr,
|
||||
# virtio_pcicfg_cfgrd=dut.virtio_pcicfg_cfgrd,
|
||||
# virtio_pcicfg_appvfnum=dut.virtio_pcicfg_appvfnum,
|
||||
# virtio_pcicfg_apppfnum=dut.virtio_pcicfg_apppfnum,
|
||||
# virtio_pcicfg_rdack=dut.virtio_pcicfg_rdack,
|
||||
# virtio_pcicfg_rdbe=dut.virtio_pcicfg_rdbe,
|
||||
# virtio_pcicfg_data=dut.virtio_pcicfg_data,
|
||||
)
|
||||
|
||||
# self.dev.log.setLevel(logging.DEBUG)
|
||||
|
||||
self.rc.make_port().connect(self.dev)
|
||||
|
||||
self.driver = mqnic.Driver()
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
|
||||
if hasattr(dut.core_pcie_inst, 'pcie_app_ctrl'):
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
|
||||
|
||||
# Ethernet
|
||||
self.port_mac = []
|
||||
|
||||
eth_int_if_width = len(dut.core_pcie_inst.core_inst.m_axis_tx_tdata) / len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)
|
||||
eth_clock_period = 6.4
|
||||
eth_speed = 10e9
|
||||
|
||||
if eth_int_if_width == 64:
|
||||
# 10G
|
||||
eth_clock_period = 6.4
|
||||
eth_speed = 10e9
|
||||
elif eth_int_if_width == 128:
|
||||
# 25G
|
||||
eth_clock_period = 2.56
|
||||
eth_speed = 25e9
|
||||
elif eth_int_if_width == 512:
|
||||
# 100G
|
||||
eth_clock_period = 3.102
|
||||
eth_speed = 100e9
|
||||
|
||||
for iface in dut.core_pcie_inst.core_inst.iface:
|
||||
for k in range(len(iface.port)):
|
||||
cocotb.start_soon(Clock(iface.port[k].port_rx_clk, eth_clock_period, units="ns").start())
|
||||
cocotb.start_soon(Clock(iface.port[k].port_tx_clk, eth_clock_period, units="ns").start())
|
||||
|
||||
iface.port[k].port_rx_rst.setimmediatevalue(0)
|
||||
iface.port[k].port_tx_rst.setimmediatevalue(0)
|
||||
|
||||
mac = EthMac(
|
||||
tx_clk=iface.port[k].port_tx_clk,
|
||||
tx_rst=iface.port[k].port_tx_rst,
|
||||
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_tx_inst, "m_axis_tx"),
|
||||
tx_ptp_time=iface.port[k].port_tx_ptp_ts_96,
|
||||
tx_ptp_ts=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_ts,
|
||||
tx_ptp_ts_tag=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_tag,
|
||||
tx_ptp_ts_valid=iface.interface_inst.port[k].port_inst.port_tx_inst.s_axis_tx_cpl_valid,
|
||||
rx_clk=iface.port[k].port_rx_clk,
|
||||
rx_rst=iface.port[k].port_rx_rst,
|
||||
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_inst.port_rx_inst, "s_axis_rx"),
|
||||
rx_ptp_time=iface.port[k].port_rx_ptp_ts_96,
|
||||
ifg=12, speed=eth_speed
|
||||
)
|
||||
|
||||
self.port_mac.append(mac)
|
||||
|
||||
dut.eth_tx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1)
|
||||
dut.eth_rx_status.setimmediatevalue(2**len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)-1)
|
||||
|
||||
dut.ctrl_reg_wr_wait.setimmediatevalue(0)
|
||||
dut.ctrl_reg_wr_ack.setimmediatevalue(0)
|
||||
dut.ctrl_reg_rd_data.setimmediatevalue(0)
|
||||
dut.ctrl_reg_rd_wait.setimmediatevalue(0)
|
||||
dut.ctrl_reg_rd_ack.setimmediatevalue(0)
|
||||
|
||||
cocotb.start_soon(Clock(dut.ptp_clk, 6.4, units="ns").start())
|
||||
dut.ptp_rst.setimmediatevalue(0)
|
||||
cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start())
|
||||
|
||||
dut.s_axis_stat_tdata.setimmediatevalue(0)
|
||||
dut.s_axis_stat_tid.setimmediatevalue(0)
|
||||
dut.s_axis_stat_tvalid.setimmediatevalue(0)
|
||||
|
||||
self.loopback_enable = False
|
||||
cocotb.start_soon(self._run_loopback())
|
||||
|
||||
async def init(self):
|
||||
|
||||
for mac in self.port_mac:
|
||||
mac.rx.reset.setimmediatevalue(0)
|
||||
mac.tx.reset.setimmediatevalue(0)
|
||||
|
||||
self.dut.ptp_rst.setimmediatevalue(0)
|
||||
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
for mac in self.port_mac:
|
||||
mac.rx.reset.setimmediatevalue(1)
|
||||
mac.tx.reset.setimmediatevalue(1)
|
||||
|
||||
self.dut.ptp_rst.setimmediatevalue(1)
|
||||
|
||||
await FallingEdge(self.dut.rst)
|
||||
await Timer(100, 'ns')
|
||||
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
for mac in self.port_mac:
|
||||
mac.rx.reset.setimmediatevalue(0)
|
||||
mac.tx.reset.setimmediatevalue(0)
|
||||
|
||||
self.dut.ptp_rst.setimmediatevalue(0)
|
||||
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
if self.loopback_enable:
|
||||
for mac in self.port_mac:
|
||||
if not mac.tx.empty():
|
||||
await mac.rx.send(await mac.tx.recv())
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def run_test_nic(dut):
|
||||
|
||||
tb = TB(dut, msix_count=2**len(dut.core_pcie_inst.irq_index))
|
||||
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver")
|
||||
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
for interface in tb.driver.interfaces:
|
||||
await interface.open()
|
||||
|
||||
# enable queues
|
||||
tb.log.info("Enable queues")
|
||||
for interface in tb.driver.interfaces:
|
||||
await interface.sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
|
||||
for k in range(interface.tx_queue_count):
|
||||
await interface.sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
|
||||
|
||||
# wait for all writes to complete
|
||||
await tb.driver.hw_regs.read_dword(0)
|
||||
tb.log.info("Init complete")
|
||||
|
||||
tb.log.info("Send and receive single packet")
|
||||
|
||||
for interface in tb.driver.interfaces:
|
||||
data = bytearray([x % 256 for x in range(1024)])
|
||||
|
||||
await interface.start_xmit(data, 0)
|
||||
|
||||
pkt = await tb.port_mac[interface.index*interface.port_count].tx.recv()
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
|
||||
await tb.port_mac[interface.index*interface.port_count].rx.send(pkt)
|
||||
|
||||
pkt = await interface.recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
|
||||
tb.log.info("RX and TX checksum tests")
|
||||
|
||||
payload = bytes([x % 256 for x in range(256)])
|
||||
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
|
||||
ip = IP(src='192.168.1.100', dst='192.168.1.101')
|
||||
udp = UDP(sport=1, dport=2)
|
||||
test_pkt = eth / ip / udp / payload
|
||||
|
||||
test_pkt2 = test_pkt.copy()
|
||||
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
|
||||
|
||||
pkt = await tb.port_mac[0].tx.recv()
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
|
||||
await tb.port_mac[0].rx.send(pkt)
|
||||
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
assert Ether(pkt.data).build() == test_pkt.build()
|
||||
|
||||
tb.log.info("Queue mapping offset test")
|
||||
|
||||
data = bytearray([x % 256 for x in range(1024)])
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
for k in range(4):
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, k)
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(data, 0)
|
||||
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
assert pkt.queue == k
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(0, 0)
|
||||
|
||||
tb.log.info("Queue mapping RSS mask test")
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
queues = set()
|
||||
|
||||
for k in range(64):
|
||||
payload = bytes([x % 256 for x in range(256)])
|
||||
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
|
||||
ip = IP(src='192.168.1.100', dst='192.168.1.101')
|
||||
udp = UDP(sport=1, dport=k+0)
|
||||
test_pkt = eth / ip / udp / payload
|
||||
|
||||
test_pkt2 = test_pkt.copy()
|
||||
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
|
||||
|
||||
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
|
||||
|
||||
for k in range(64):
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
|
||||
queues.add(pkt.queue)
|
||||
|
||||
assert len(queues) == 4
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
|
||||
|
||||
tb.log.info("Multiple small packets")
|
||||
|
||||
count = 64
|
||||
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
for p in pkts:
|
||||
await tb.driver.interfaces[0].start_xmit(p, 0)
|
||||
|
||||
for k in range(count):
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.data == pkts[k]
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
tb.log.info("Multiple large packets")
|
||||
|
||||
count = 64
|
||||
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
for p in pkts:
|
||||
await tb.driver.interfaces[0].start_xmit(p, 0)
|
||||
|
||||
for k in range(count):
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.data == pkts[k]
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
tb.log.info("Jumbo frames")
|
||||
|
||||
count = 64
|
||||
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(9014)]) for k in range(count)]
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
for p in pkts:
|
||||
await tb.driver.interfaces[0].start_xmit(p, 0)
|
||||
|
||||
for k in range(count):
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.data == pkts[k]
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
if len(tb.driver.interfaces) > 1:
|
||||
tb.log.info("All interfaces")
|
||||
|
||||
count = 64
|
||||
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
for k, p in enumerate(pkts):
|
||||
await tb.driver.interfaces[k % len(tb.driver.interfaces)].start_xmit(p, 0)
|
||||
|
||||
for k in range(count):
|
||||
pkt = await tb.driver.interfaces[k % len(tb.driver.interfaces)].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
assert pkt.data == pkts[k]
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
if len(tb.driver.interfaces[0].sched_blocks) > 1:
|
||||
tb.log.info("All interface 0 scheduler blocks")
|
||||
|
||||
for block in tb.driver.interfaces[0].sched_blocks:
|
||||
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, block.index)
|
||||
for k in range(block.interface.tx_queue_count):
|
||||
if k % len(tb.driver.interfaces[0].sched_blocks) == block.index:
|
||||
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
|
||||
else:
|
||||
await block.schedulers[0].hw_regs.write_dword(4*k, 0x00000000)
|
||||
|
||||
count = 64
|
||||
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
queues = set()
|
||||
|
||||
for k, p in enumerate(pkts):
|
||||
await tb.driver.interfaces[0].start_xmit(p, k % len(tb.driver.interfaces[0].sched_blocks))
|
||||
|
||||
for k in range(count):
|
||||
pkt = await tb.driver.interfaces[0].recv()
|
||||
|
||||
tb.log.info("Packet: %s", pkt)
|
||||
# assert pkt.data == pkts[k]
|
||||
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
|
||||
|
||||
queues.add(pkt.queue)
|
||||
|
||||
assert len(queues) == len(tb.driver.interfaces[0].sched_blocks)
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
for block in tb.driver.interfaces[0].sched_blocks[1:]:
|
||||
await block.schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000000)
|
||||
await tb.driver.interfaces[0].set_rx_queue_map_offset(block.index, 0)
|
||||
|
||||
tb.log.info("Read statistics counters")
|
||||
|
||||
await Timer(2000, 'ns')
|
||||
|
||||
lst = []
|
||||
|
||||
for k in range(64):
|
||||
lst.append(await tb.driver.hw_regs.read_dword(0x020000+k*8))
|
||||
|
||||
print(lst)
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib'))
|
||||
axi_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axi', 'rtl'))
|
||||
axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl'))
|
||||
eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl'))
|
||||
pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl'))
|
||||
|
||||
|
||||
@pytest.mark.parametrize(("if_count", "ports_per_if", "pcie_data_width",
|
||||
"axis_eth_data_width", "axis_eth_sync_data_width", "ptp_ts_enable"), [
|
||||
(1, 1, 256, 64, 64, 1),
|
||||
(1, 1, 256, 64, 64, 0),
|
||||
(2, 1, 256, 64, 64, 1),
|
||||
(1, 2, 256, 64, 64, 1),
|
||||
(1, 1, 256, 64, 128, 1),
|
||||
(1, 1, 512, 64, 64, 1),
|
||||
(1, 1, 512, 64, 128, 1),
|
||||
(1, 1, 512, 512, 512, 1),
|
||||
])
|
||||
def test_mqnic_core_pcie_ptile(request, if_count, ports_per_if, pcie_data_width,
|
||||
axis_eth_data_width, axis_eth_sync_data_width, ptp_ts_enable):
|
||||
dut = "mqnic_core_pcie_ptile"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = dut
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(rtl_dir, f"{dut}.v"),
|
||||
os.path.join(rtl_dir, "mqnic_core.v"),
|
||||
os.path.join(rtl_dir, "mqnic_core_pcie.v"),
|
||||
os.path.join(rtl_dir, "mqnic_interface.v"),
|
||||
os.path.join(rtl_dir, "mqnic_interface_tx.v"),
|
||||
os.path.join(rtl_dir, "mqnic_interface_rx.v"),
|
||||
os.path.join(rtl_dir, "mqnic_port.v"),
|
||||
os.path.join(rtl_dir, "mqnic_port_tx.v"),
|
||||
os.path.join(rtl_dir, "mqnic_port_rx.v"),
|
||||
os.path.join(rtl_dir, "mqnic_egress.v"),
|
||||
os.path.join(rtl_dir, "mqnic_ingress.v"),
|
||||
os.path.join(rtl_dir, "mqnic_l2_egress.v"),
|
||||
os.path.join(rtl_dir, "mqnic_l2_ingress.v"),
|
||||
os.path.join(rtl_dir, "mqnic_rx_queue_map.v"),
|
||||
os.path.join(rtl_dir, "mqnic_ptp.v"),
|
||||
os.path.join(rtl_dir, "mqnic_ptp_clock.v"),
|
||||
os.path.join(rtl_dir, "mqnic_ptp_perout.v"),
|
||||
os.path.join(rtl_dir, "cpl_write.v"),
|
||||
os.path.join(rtl_dir, "cpl_op_mux.v"),
|
||||
os.path.join(rtl_dir, "desc_fetch.v"),
|
||||
os.path.join(rtl_dir, "desc_op_mux.v"),
|
||||
os.path.join(rtl_dir, "event_mux.v"),
|
||||
os.path.join(rtl_dir, "queue_manager.v"),
|
||||
os.path.join(rtl_dir, "cpl_queue_manager.v"),
|
||||
os.path.join(rtl_dir, "tx_fifo.v"),
|
||||
os.path.join(rtl_dir, "rx_fifo.v"),
|
||||
os.path.join(rtl_dir, "tx_req_mux.v"),
|
||||
os.path.join(rtl_dir, "tx_engine.v"),
|
||||
os.path.join(rtl_dir, "rx_engine.v"),
|
||||
os.path.join(rtl_dir, "tx_checksum.v"),
|
||||
os.path.join(rtl_dir, "rx_hash.v"),
|
||||
os.path.join(rtl_dir, "rx_checksum.v"),
|
||||
os.path.join(rtl_dir, "stats_counter.v"),
|
||||
os.path.join(rtl_dir, "stats_collect.v"),
|
||||
os.path.join(rtl_dir, "stats_pcie_if.v"),
|
||||
os.path.join(rtl_dir, "stats_pcie_tlp.v"),
|
||||
os.path.join(rtl_dir, "stats_dma_if_pcie.v"),
|
||||
os.path.join(rtl_dir, "stats_dma_latency.v"),
|
||||
os.path.join(rtl_dir, "mqnic_tx_scheduler_block_rr.v"),
|
||||
os.path.join(rtl_dir, "tx_scheduler_rr.v"),
|
||||
os.path.join(eth_rtl_dir, "ptp_clock.v"),
|
||||
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
|
||||
os.path.join(eth_rtl_dir, "ptp_perout.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_crossbar.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_crossbar_rd.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_crossbar_wr.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_reg_if.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_reg_if_rd.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_reg_if_wr.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_register_rd.v"),
|
||||
os.path.join(axi_rtl_dir, "axil_register_wr.v"),
|
||||
os.path.join(axi_rtl_dir, "arbiter.v"),
|
||||
os.path.join(axi_rtl_dir, "priority_encoder.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_adapter.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_demux.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_fifo.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_register.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_desc_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_ram_demux_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_ram_demux_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_psdpram.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_client_axis_sink.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_client_axis_source.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_ptile_if.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_ptile_if_rx.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_ptile_if_tx.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_ptile_cfg.v"),
|
||||
os.path.join(pcie_rtl_dir, "pulse_merge.v"),
|
||||
]
|
||||
|
||||
parameters = {}
|
||||
|
||||
# Structural configuration
|
||||
parameters['IF_COUNT'] = if_count
|
||||
parameters['PORTS_PER_IF'] = ports_per_if
|
||||
parameters['SCHED_PER_IF'] = ports_per_if
|
||||
|
||||
# PTP configuration
|
||||
parameters['PTP_CLK_PERIOD_NS_NUM'] = 32
|
||||
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 5
|
||||
parameters['PTP_CLOCK_PIPELINE'] = 0
|
||||
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
|
||||
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
|
||||
parameters['PTP_SEPARATE_TX_CLOCK'] = 0
|
||||
parameters['PTP_SEPARATE_RX_CLOCK'] = 0
|
||||
parameters['PTP_PORT_CDC_PIPELINE'] = 0
|
||||
parameters['PTP_PEROUT_ENABLE'] = 0
|
||||
parameters['PTP_PEROUT_COUNT'] = 1
|
||||
|
||||
# Queue manager configuration
|
||||
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
|
||||
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
|
||||
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
|
||||
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
|
||||
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
|
||||
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6
|
||||
parameters['TX_QUEUE_INDEX_WIDTH'] = 13
|
||||
parameters['RX_QUEUE_INDEX_WIDTH'] = 8
|
||||
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
|
||||
parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH']
|
||||
parameters['EVENT_QUEUE_PIPELINE'] = 3
|
||||
parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0)
|
||||
parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0)
|
||||
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
|
||||
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
|
||||
|
||||
# TX and RX engine configuration
|
||||
parameters['TX_DESC_TABLE_SIZE'] = 32
|
||||
parameters['RX_DESC_TABLE_SIZE'] = 32
|
||||
|
||||
# Scheduler configuration
|
||||
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
|
||||
parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
|
||||
parameters['TDMA_INDEX_WIDTH'] = 6
|
||||
|
||||
# Interface configuration
|
||||
parameters['PTP_TS_ENABLE'] = ptp_ts_enable
|
||||
parameters['TX_CPL_ENABLE'] = parameters['PTP_TS_ENABLE']
|
||||
parameters['TX_CPL_FIFO_DEPTH'] = 32
|
||||
parameters['TX_TAG_WIDTH'] = 16
|
||||
parameters['TX_CHECKSUM_ENABLE'] = 1
|
||||
parameters['RX_RSS_ENABLE'] = 1
|
||||
parameters['RX_HASH_ENABLE'] = 1
|
||||
parameters['RX_CHECKSUM_ENABLE'] = 1
|
||||
parameters['TX_FIFO_DEPTH'] = 32768
|
||||
parameters['RX_FIFO_DEPTH'] = 131072
|
||||
parameters['MAX_TX_SIZE'] = 9214
|
||||
parameters['MAX_RX_SIZE'] = 9214
|
||||
parameters['TX_RAM_SIZE'] = 131072
|
||||
parameters['RX_RAM_SIZE'] = 131072
|
||||
|
||||
# Application block configuration
|
||||
parameters['APP_ID'] = 0x00000000
|
||||
parameters['APP_ENABLE'] = 0
|
||||
parameters['APP_CTRL_ENABLE'] = 1
|
||||
parameters['APP_DMA_ENABLE'] = 1
|
||||
parameters['APP_AXIS_DIRECT_ENABLE'] = 1
|
||||
parameters['APP_AXIS_SYNC_ENABLE'] = 1
|
||||
parameters['APP_AXIS_IF_ENABLE'] = 1
|
||||
parameters['APP_STAT_ENABLE'] = 1
|
||||
|
||||
# DMA interface configuration
|
||||
parameters['DMA_IMM_ENABLE'] = 0
|
||||
parameters['DMA_IMM_WIDTH'] = 32
|
||||
parameters['DMA_LEN_WIDTH'] = 16
|
||||
parameters['DMA_TAG_WIDTH'] = 16
|
||||
parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
|
||||
parameters['RAM_PIPELINE'] = 2
|
||||
|
||||
# PCIe interface configuration
|
||||
parameters['SEG_COUNT'] = 2 if pcie_data_width == 512 else 1
|
||||
parameters['SEG_DATA_WIDTH'] = pcie_data_width // parameters['SEG_COUNT']
|
||||
parameters['SEG_EMPTY_WIDTH'] = ((parameters['SEG_DATA_WIDTH'] // 32) - 1).bit_length()
|
||||
parameters['SEG_HDR_WIDTH'] = 128
|
||||
parameters['SEG_PRFX_WIDTH'] = 32
|
||||
parameters['TX_SEQ_NUM_WIDTH'] = 6
|
||||
parameters['TX_SEQ_NUM_ENABLE'] = 1
|
||||
parameters['PF_COUNT'] = 1
|
||||
parameters['VF_COUNT'] = 0
|
||||
parameters['PCIE_TAG_COUNT'] = 256
|
||||
parameters['PCIE_DMA_READ_OP_TABLE_SIZE'] = parameters['PCIE_TAG_COUNT']
|
||||
parameters['PCIE_DMA_READ_TX_LIMIT'] = 2**parameters['TX_SEQ_NUM_WIDTH']
|
||||
parameters['PCIE_DMA_READ_TX_FC_ENABLE'] = 1
|
||||
parameters['PCIE_DMA_WRITE_OP_TABLE_SIZE'] = 2**parameters['TX_SEQ_NUM_WIDTH']
|
||||
parameters['PCIE_DMA_WRITE_TX_LIMIT'] = 2**parameters['TX_SEQ_NUM_WIDTH']
|
||||
parameters['PCIE_DMA_WRITE_TX_FC_ENABLE'] = 1
|
||||
|
||||
# Interrupt configuration
|
||||
parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH']
|
||||
|
||||
# AXI lite interface configuration (control)
|
||||
parameters['AXIL_CTRL_DATA_WIDTH'] = 32
|
||||
parameters['AXIL_CTRL_ADDR_WIDTH'] = 24
|
||||
parameters['AXIL_CSR_PASSTHROUGH_ENABLE'] = 0
|
||||
|
||||
# AXI lite interface configuration (application control)
|
||||
parameters['AXIL_APP_CTRL_DATA_WIDTH'] = parameters['AXIL_CTRL_DATA_WIDTH']
|
||||
parameters['AXIL_APP_CTRL_ADDR_WIDTH'] = 24
|
||||
|
||||
# Ethernet interface configuration
|
||||
parameters['AXIS_ETH_DATA_WIDTH'] = axis_eth_data_width
|
||||
parameters['AXIS_ETH_SYNC_DATA_WIDTH'] = axis_eth_sync_data_width
|
||||
parameters['AXIS_ETH_RX_USE_READY'] = 0
|
||||
parameters['AXIS_ETH_TX_PIPELINE'] = 0
|
||||
parameters['AXIS_ETH_TX_FIFO_PIPELINE'] = 2
|
||||
parameters['AXIS_ETH_TX_TS_PIPELINE'] = 0
|
||||
parameters['AXIS_ETH_RX_PIPELINE'] = 0
|
||||
parameters['AXIS_ETH_RX_FIFO_PIPELINE'] = 2
|
||||
|
||||
# Statistics counter subsystem
|
||||
parameters['STAT_ENABLE'] = 1
|
||||
parameters['STAT_DMA_ENABLE'] = 1
|
||||
parameters['STAT_PCIE_ENABLE'] = 1
|
||||
parameters['STAT_INC_WIDTH'] = 24
|
||||
parameters['STAT_ID_WIDTH'] = 12
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
Loading…
x
Reference in New Issue
Block a user