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mirror of https://github.com/corundum/corundum.git synced 2025-01-30 08:32:52 +08:00

fpga/mqnic: Enable statistics counters on all targets

Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-12-06 13:06:39 -08:00
parent e8aaadd102
commit 4b7d51133f
16 changed files with 16 additions and 16 deletions

View File

@ -172,7 +172,7 @@ dict set params AXIS_ETH_RX_PIPELINE "0"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
# Statistics counter subsystem
dict set params STAT_ENABLE "0"
dict set params STAT_ENABLE "1"
dict set params STAT_DMA_ENABLE "1"
dict set params STAT_PCIE_ENABLE "1"
dict set params STAT_INC_WIDTH "24"

View File

@ -172,7 +172,7 @@ dict set params AXIS_ETH_RX_PIPELINE "0"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
# Statistics counter subsystem
dict set params STAT_ENABLE "0"
dict set params STAT_ENABLE "1"
dict set params STAT_DMA_ENABLE "1"
dict set params STAT_PCIE_ENABLE "1"
dict set params STAT_INC_WIDTH "24"

View File

@ -174,7 +174,7 @@ dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
dict set params MAC_RSFEC "0"
# Statistics counter subsystem
dict set params STAT_ENABLE "0"
dict set params STAT_ENABLE "1"
dict set params STAT_DMA_ENABLE "1"
dict set params STAT_PCIE_ENABLE "1"
dict set params STAT_INC_WIDTH "24"

View File

@ -174,7 +174,7 @@ dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
dict set params MAC_RSFEC "0"
# Statistics counter subsystem
dict set params STAT_ENABLE "0"
dict set params STAT_ENABLE "1"
dict set params STAT_DMA_ENABLE "1"
dict set params STAT_PCIE_ENABLE "1"
dict set params STAT_INC_WIDTH "24"

View File

@ -174,7 +174,7 @@ dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
dict set params MAC_RSFEC "1"
# Statistics counter subsystem
dict set params STAT_ENABLE "0"
dict set params STAT_ENABLE "1"
dict set params STAT_DMA_ENABLE "1"
dict set params STAT_PCIE_ENABLE "1"
dict set params STAT_INC_WIDTH "24"

View File

@ -174,7 +174,7 @@ dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
dict set params MAC_RSFEC "1"
# Statistics counter subsystem
dict set params STAT_ENABLE "0"
dict set params STAT_ENABLE "1"
dict set params STAT_DMA_ENABLE "1"
dict set params STAT_PCIE_ENABLE "1"
dict set params STAT_INC_WIDTH "24"

View File

@ -182,7 +182,7 @@ dict set params AXIS_ETH_RX_PIPELINE "0"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
# Statistics counter subsystem
dict set params STAT_ENABLE "0"
dict set params STAT_ENABLE "1"
dict set params STAT_DMA_ENABLE "1"
dict set params STAT_PCIE_ENABLE "1"
dict set params STAT_INC_WIDTH "24"

View File

@ -182,7 +182,7 @@ dict set params AXIS_ETH_RX_PIPELINE "0"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
# Statistics counter subsystem
dict set params STAT_ENABLE "0"
dict set params STAT_ENABLE "1"
dict set params STAT_DMA_ENABLE "1"
dict set params STAT_PCIE_ENABLE "1"
dict set params STAT_INC_WIDTH "24"

View File

@ -173,7 +173,7 @@ dict set params AXIS_ETH_RX_PIPELINE "0"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
# Statistics counter subsystem
dict set params STAT_ENABLE "0"
dict set params STAT_ENABLE "1"
dict set params STAT_DMA_ENABLE "1"
dict set params STAT_PCIE_ENABLE "1"
dict set params STAT_INC_WIDTH "24"

View File

@ -173,7 +173,7 @@ dict set params AXIS_ETH_RX_PIPELINE "0"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
# Statistics counter subsystem
dict set params STAT_ENABLE "0"
dict set params STAT_ENABLE "1"
dict set params STAT_DMA_ENABLE "1"
dict set params STAT_PCIE_ENABLE "1"
dict set params STAT_INC_WIDTH "24"

View File

@ -174,7 +174,7 @@ dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
dict set params MAC_RSFEC "1"
# Statistics counter subsystem
dict set params STAT_ENABLE "0"
dict set params STAT_ENABLE "1"
dict set params STAT_DMA_ENABLE "1"
dict set params STAT_PCIE_ENABLE "1"
dict set params STAT_INC_WIDTH "24"

View File

@ -174,7 +174,7 @@ dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
dict set params MAC_RSFEC "0"
# Statistics counter subsystem
dict set params STAT_ENABLE "0"
dict set params STAT_ENABLE "1"
dict set params STAT_DMA_ENABLE "1"
dict set params STAT_PCIE_ENABLE "1"
dict set params STAT_INC_WIDTH "24"

View File

@ -178,7 +178,7 @@ dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
dict set params ETH_XCVR_GXT "0"
# Statistics counter subsystem
dict set params STAT_ENABLE "0"
dict set params STAT_ENABLE "1"
dict set params STAT_DMA_ENABLE "1"
dict set params STAT_PCIE_ENABLE "1"
dict set params STAT_INC_WIDTH "24"

View File

@ -176,7 +176,7 @@ dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
dict set params ETH_XCVR_GXT "0"
# Statistics counter subsystem
dict set params STAT_ENABLE "0"
dict set params STAT_ENABLE "1"
dict set params STAT_DMA_ENABLE "1"
dict set params STAT_PCIE_ENABLE "1"
dict set params STAT_INC_WIDTH "24"

View File

@ -178,7 +178,7 @@ dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
dict set params ETH_XCVR_GXT "1"
# Statistics counter subsystem
dict set params STAT_ENABLE "0"
dict set params STAT_ENABLE "1"
dict set params STAT_DMA_ENABLE "1"
dict set params STAT_PCIE_ENABLE "1"
dict set params STAT_INC_WIDTH "24"

View File

@ -176,7 +176,7 @@ dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
dict set params ETH_XCVR_GXT "1"
# Statistics counter subsystem
dict set params STAT_ENABLE "0"
dict set params STAT_ENABLE "1"
dict set params STAT_DMA_ENABLE "1"
dict set params STAT_PCIE_ENABLE "1"
dict set params STAT_INC_WIDTH "24"