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fpga/mqnic: Enable statistics counters on all targets
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
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e8aaadd102
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@ -172,7 +172,7 @@ dict set params AXIS_ETH_RX_PIPELINE "0"
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dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
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# Statistics counter subsystem
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dict set params STAT_ENABLE "0"
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dict set params STAT_ENABLE "1"
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dict set params STAT_DMA_ENABLE "1"
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dict set params STAT_PCIE_ENABLE "1"
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dict set params STAT_INC_WIDTH "24"
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@ -172,7 +172,7 @@ dict set params AXIS_ETH_RX_PIPELINE "0"
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dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
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# Statistics counter subsystem
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dict set params STAT_ENABLE "0"
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dict set params STAT_ENABLE "1"
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dict set params STAT_DMA_ENABLE "1"
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dict set params STAT_PCIE_ENABLE "1"
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dict set params STAT_INC_WIDTH "24"
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@ -174,7 +174,7 @@ dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
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dict set params MAC_RSFEC "0"
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# Statistics counter subsystem
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dict set params STAT_ENABLE "0"
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dict set params STAT_ENABLE "1"
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dict set params STAT_DMA_ENABLE "1"
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dict set params STAT_PCIE_ENABLE "1"
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dict set params STAT_INC_WIDTH "24"
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@ -174,7 +174,7 @@ dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
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dict set params MAC_RSFEC "0"
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# Statistics counter subsystem
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dict set params STAT_ENABLE "0"
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dict set params STAT_ENABLE "1"
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dict set params STAT_DMA_ENABLE "1"
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dict set params STAT_PCIE_ENABLE "1"
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dict set params STAT_INC_WIDTH "24"
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@ -174,7 +174,7 @@ dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
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dict set params MAC_RSFEC "1"
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# Statistics counter subsystem
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dict set params STAT_ENABLE "0"
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dict set params STAT_ENABLE "1"
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dict set params STAT_DMA_ENABLE "1"
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dict set params STAT_PCIE_ENABLE "1"
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dict set params STAT_INC_WIDTH "24"
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@ -174,7 +174,7 @@ dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
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dict set params MAC_RSFEC "1"
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# Statistics counter subsystem
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dict set params STAT_ENABLE "0"
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dict set params STAT_ENABLE "1"
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dict set params STAT_DMA_ENABLE "1"
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dict set params STAT_PCIE_ENABLE "1"
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dict set params STAT_INC_WIDTH "24"
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@ -182,7 +182,7 @@ dict set params AXIS_ETH_RX_PIPELINE "0"
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dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
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# Statistics counter subsystem
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dict set params STAT_ENABLE "0"
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dict set params STAT_ENABLE "1"
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dict set params STAT_DMA_ENABLE "1"
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dict set params STAT_PCIE_ENABLE "1"
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dict set params STAT_INC_WIDTH "24"
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@ -182,7 +182,7 @@ dict set params AXIS_ETH_RX_PIPELINE "0"
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dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
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# Statistics counter subsystem
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dict set params STAT_ENABLE "0"
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dict set params STAT_ENABLE "1"
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dict set params STAT_DMA_ENABLE "1"
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dict set params STAT_PCIE_ENABLE "1"
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dict set params STAT_INC_WIDTH "24"
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@ -173,7 +173,7 @@ dict set params AXIS_ETH_RX_PIPELINE "0"
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dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
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# Statistics counter subsystem
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dict set params STAT_ENABLE "0"
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dict set params STAT_ENABLE "1"
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dict set params STAT_DMA_ENABLE "1"
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dict set params STAT_PCIE_ENABLE "1"
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dict set params STAT_INC_WIDTH "24"
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@ -173,7 +173,7 @@ dict set params AXIS_ETH_RX_PIPELINE "0"
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dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
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# Statistics counter subsystem
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dict set params STAT_ENABLE "0"
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dict set params STAT_ENABLE "1"
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dict set params STAT_DMA_ENABLE "1"
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dict set params STAT_PCIE_ENABLE "1"
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dict set params STAT_INC_WIDTH "24"
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@ -174,7 +174,7 @@ dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
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dict set params MAC_RSFEC "1"
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# Statistics counter subsystem
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dict set params STAT_ENABLE "0"
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dict set params STAT_ENABLE "1"
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dict set params STAT_DMA_ENABLE "1"
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dict set params STAT_PCIE_ENABLE "1"
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dict set params STAT_INC_WIDTH "24"
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@ -174,7 +174,7 @@ dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
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dict set params MAC_RSFEC "0"
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# Statistics counter subsystem
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dict set params STAT_ENABLE "0"
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dict set params STAT_ENABLE "1"
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dict set params STAT_DMA_ENABLE "1"
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dict set params STAT_PCIE_ENABLE "1"
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dict set params STAT_INC_WIDTH "24"
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@ -178,7 +178,7 @@ dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
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dict set params ETH_XCVR_GXT "0"
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# Statistics counter subsystem
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dict set params STAT_ENABLE "0"
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dict set params STAT_ENABLE "1"
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dict set params STAT_DMA_ENABLE "1"
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dict set params STAT_PCIE_ENABLE "1"
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dict set params STAT_INC_WIDTH "24"
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@ -176,7 +176,7 @@ dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
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dict set params ETH_XCVR_GXT "0"
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# Statistics counter subsystem
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dict set params STAT_ENABLE "0"
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dict set params STAT_ENABLE "1"
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dict set params STAT_DMA_ENABLE "1"
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dict set params STAT_PCIE_ENABLE "1"
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dict set params STAT_INC_WIDTH "24"
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@ -178,7 +178,7 @@ dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
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dict set params ETH_XCVR_GXT "1"
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# Statistics counter subsystem
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dict set params STAT_ENABLE "0"
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dict set params STAT_ENABLE "1"
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dict set params STAT_DMA_ENABLE "1"
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dict set params STAT_PCIE_ENABLE "1"
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dict set params STAT_INC_WIDTH "24"
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@ -176,7 +176,7 @@ dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
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dict set params ETH_XCVR_GXT "1"
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# Statistics counter subsystem
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dict set params STAT_ENABLE "0"
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dict set params STAT_ENABLE "1"
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dict set params STAT_DMA_ENABLE "1"
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dict set params STAT_PCIE_ENABLE "1"
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dict set params STAT_INC_WIDTH "24"
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