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Add statistics outputs to AXI DMA IF modules

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This commit is contained in:
Alex Forencich 2022-03-31 17:56:05 -07:00
parent dd7cc63d55
commit 4bbd187567
3 changed files with 306 additions and 5 deletions
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74
rtl/dma_if_axi.v
View File

@ -169,7 +169,39 @@ module dma_if_axi #
* Configuration
*/
input wire read_enable,
input wire write_enable
input wire write_enable,
/*
* Statistics
*/
output wire [$clog2(READ_OP_TABLE_SIZE)-1:0] stat_rd_op_start_tag,
output wire [LEN_WIDTH-1:0] stat_rd_op_start_len,
output wire stat_rd_op_start_valid,
output wire [$clog2(READ_OP_TABLE_SIZE)-1:0] stat_rd_op_finish_tag,
output wire [3:0] stat_rd_op_finish_status,
output wire stat_rd_op_finish_valid,
output wire [$clog2(READ_OP_TABLE_SIZE)-1:0] stat_rd_req_start_tag,
output wire [12:0] stat_rd_req_start_len,
output wire stat_rd_req_start_valid,
output wire [$clog2(READ_OP_TABLE_SIZE)-1:0] stat_rd_req_finish_tag,
output wire [3:0] stat_rd_req_finish_status,
output wire stat_rd_req_finish_valid,
output wire stat_rd_op_table_full,
output wire stat_rd_tx_stall,
output wire [$clog2(WRITE_OP_TABLE_SIZE)-1:0] stat_wr_op_start_tag,
output wire [LEN_WIDTH-1:0] stat_wr_op_start_len,
output wire stat_wr_op_start_valid,
output wire [$clog2(WRITE_OP_TABLE_SIZE)-1:0] stat_wr_op_finish_tag,
output wire [3:0] stat_wr_op_finish_status,
output wire stat_wr_op_finish_valid,
output wire [$clog2(WRITE_OP_TABLE_SIZE)-1:0] stat_wr_req_start_tag,
output wire [12:0] stat_wr_req_start_len,
output wire stat_wr_req_start_valid,
output wire [$clog2(WRITE_OP_TABLE_SIZE)-1:0] stat_wr_req_finish_tag,
output wire [3:0] stat_wr_req_finish_status,
output wire stat_wr_req_finish_valid,
output wire stat_wr_op_table_full,
output wire stat_wr_tx_stall
);
dma_if_axi_rd #(
@ -245,7 +277,25 @@ dma_if_axi_rd_inst (
/*
* Configuration
*/
.enable(read_enable)
.enable(read_enable),
/*
* Statistics
*/
.stat_rd_op_start_tag(stat_rd_op_start_tag),
.stat_rd_op_start_len(stat_rd_op_start_len),
.stat_rd_op_start_valid(stat_rd_op_start_valid),
.stat_rd_op_finish_tag(stat_rd_op_finish_tag),
.stat_rd_op_finish_status(stat_rd_op_finish_status),
.stat_rd_op_finish_valid(stat_rd_op_finish_valid),
.stat_rd_req_start_tag(stat_rd_req_start_tag),
.stat_rd_req_start_len(stat_rd_req_start_len),
.stat_rd_req_start_valid(stat_rd_req_start_valid),
.stat_rd_req_finish_tag(stat_rd_req_finish_tag),
.stat_rd_req_finish_status(stat_rd_req_finish_status),
.stat_rd_req_finish_valid(stat_rd_req_finish_valid),
.stat_rd_op_table_full(stat_rd_op_table_full),
.stat_rd_tx_stall(stat_rd_tx_stall)
);
dma_if_axi_wr #(
@ -324,7 +374,25 @@ dma_if_axi_wr_inst (
/*
* Configuration
*/
.enable(write_enable)
.enable(write_enable),
/*
* Statistics
*/
.stat_wr_op_start_tag(stat_wr_op_start_tag),
.stat_wr_op_start_len(stat_wr_op_start_len),
.stat_wr_op_start_valid(stat_wr_op_start_valid),
.stat_wr_op_finish_tag(stat_wr_op_finish_tag),
.stat_wr_op_finish_status(stat_wr_op_finish_status),
.stat_wr_op_finish_valid(stat_wr_op_finish_valid),
.stat_wr_req_start_tag(stat_wr_req_start_tag),
.stat_wr_req_start_len(stat_wr_req_start_len),
.stat_wr_req_start_valid(stat_wr_req_start_valid),
.stat_wr_req_finish_tag(stat_wr_req_finish_tag),
.stat_wr_req_finish_status(stat_wr_req_finish_status),
.stat_wr_req_finish_valid(stat_wr_req_finish_valid),
.stat_wr_op_table_full(stat_wr_op_table_full),
.stat_wr_tx_stall(stat_wr_tx_stall)
);
endmodule

117
rtl/dma_if_axi_rd.v
View File

@ -120,7 +120,25 @@ module dma_if_axi_rd #
/*
* Configuration
*/
input wire enable
input wire enable,
/*
* Statistics
*/
output wire [$clog2(OP_TABLE_SIZE)-1:0] stat_rd_op_start_tag,
output wire [LEN_WIDTH-1:0] stat_rd_op_start_len,
output wire stat_rd_op_start_valid,
output wire [$clog2(OP_TABLE_SIZE)-1:0] stat_rd_op_finish_tag,
output wire [3:0] stat_rd_op_finish_status,
output wire stat_rd_op_finish_valid,
output wire [$clog2(OP_TABLE_SIZE)-1:0] stat_rd_req_start_tag,
output wire [12:0] stat_rd_req_start_len,
output wire stat_rd_req_start_valid,
output wire [$clog2(OP_TABLE_SIZE)-1:0] stat_rd_req_finish_tag,
output wire [3:0] stat_rd_req_finish_status,
output wire stat_rd_req_finish_valid,
output wire stat_rd_op_table_full,
output wire stat_rd_tx_stall
);
parameter RAM_WORD_WIDTH = RAM_SEG_BE_WIDTH;
@ -287,6 +305,21 @@ reg [TAG_WIDTH-1:0] m_axis_read_desc_status_tag_reg = {TAG_WIDTH{1'b0}}, m_axis_
reg [3:0] m_axis_read_desc_status_error_reg = 4'd0, m_axis_read_desc_status_error_next;
reg m_axis_read_desc_status_valid_reg = 1'b0, m_axis_read_desc_status_valid_next;
reg [OP_TAG_WIDTH-1:0] stat_rd_op_start_tag_reg = 0, stat_rd_op_start_tag_next;
reg [LEN_WIDTH-1:0] stat_rd_op_start_len_reg = 0, stat_rd_op_start_len_next;
reg stat_rd_op_start_valid_reg = 1'b0, stat_rd_op_start_valid_next;
reg [OP_TAG_WIDTH-1:0] stat_rd_op_finish_tag_reg = 0, stat_rd_op_finish_tag_next;
reg [3:0] stat_rd_op_finish_status_reg = 4'd0, stat_rd_op_finish_status_next;
reg stat_rd_op_finish_valid_reg = 1'b0, stat_rd_op_finish_valid_next;
reg [OP_TAG_WIDTH-1:0] stat_rd_req_start_tag_reg = 0, stat_rd_req_start_tag_next;
reg [12:0] stat_rd_req_start_len_reg = 13'd0, stat_rd_req_start_len_next;
reg stat_rd_req_start_valid_reg = 1'b0, stat_rd_req_start_valid_next;
reg [OP_TAG_WIDTH-1:0] stat_rd_req_finish_tag_reg = 0, stat_rd_req_finish_tag_next;
reg [3:0] stat_rd_req_finish_status_reg = 4'd0, stat_rd_req_finish_status_next;
reg stat_rd_req_finish_valid_reg = 1'b0, stat_rd_req_finish_valid_next;
reg stat_rd_op_table_full_reg = 1'b0, stat_rd_op_table_full_next;
reg stat_rd_tx_stall_reg = 1'b0, stat_rd_tx_stall_next;
// internal datapath
reg [RAM_SEG_COUNT*RAM_SEL_WIDTH-1:0] ram_wr_cmd_sel_int;
reg [RAM_SEG_COUNT*RAM_SEG_BE_WIDTH-1:0] ram_wr_cmd_be_int;
@ -315,6 +348,21 @@ assign m_axis_read_desc_status_tag = m_axis_read_desc_status_tag_reg;
assign m_axis_read_desc_status_error = m_axis_read_desc_status_error_reg;
assign m_axis_read_desc_status_valid = m_axis_read_desc_status_valid_reg;
assign stat_rd_op_start_tag = stat_rd_op_start_tag_reg;
assign stat_rd_op_start_len = stat_rd_op_start_len_reg;
assign stat_rd_op_start_valid = stat_rd_op_start_valid_reg;
assign stat_rd_op_finish_tag = stat_rd_op_finish_tag_reg;
assign stat_rd_op_finish_status = stat_rd_op_finish_status_reg;
assign stat_rd_op_finish_valid = stat_rd_op_finish_valid_reg;
assign stat_rd_req_start_tag = stat_rd_req_start_tag_reg;
assign stat_rd_req_start_len = stat_rd_req_start_len_reg;
assign stat_rd_req_start_valid = stat_rd_req_start_valid_reg;
assign stat_rd_req_finish_tag = stat_rd_req_finish_tag_reg;
assign stat_rd_req_finish_status = stat_rd_req_finish_status_reg;
assign stat_rd_req_finish_valid = stat_rd_req_finish_valid_reg;
assign stat_rd_op_table_full = stat_rd_op_table_full_reg;
assign stat_rd_tx_stall = stat_rd_tx_stall_reg;
// operation tag management
reg [OP_TAG_WIDTH+1-1:0] op_table_start_ptr_reg = 0;
reg [AXI_ADDR_WIDTH-1:0] op_table_start_axi_addr;
@ -386,6 +434,15 @@ always @* begin
s_axis_read_desc_ready_next = 1'b0;
stat_rd_op_start_tag_next = stat_rd_op_start_tag_reg;
stat_rd_op_start_len_next = stat_rd_op_start_len_reg;
stat_rd_op_start_valid_next = 1'b0;
stat_rd_req_start_tag_next = stat_rd_req_start_tag_reg;
stat_rd_req_start_len_next = stat_rd_req_start_len_reg;
stat_rd_req_start_valid_next = 1'b0;
stat_rd_op_table_full_next = !(!op_table_active[op_table_start_ptr_reg[OP_TAG_WIDTH-1:0]] && ($unsigned(op_table_start_ptr_reg - op_table_finish_ptr_reg) < 2**OP_TAG_WIDTH));
stat_rd_tx_stall_next = m_axi_arvalid_reg && !m_axi_arready;
req_axi_addr_next = req_axi_addr_reg;
req_ram_sel_next = req_ram_sel_reg;
req_ram_addr_next = req_ram_addr_reg;
@ -449,6 +506,11 @@ always @* begin
if (s_axis_read_desc_ready && s_axis_read_desc_valid) begin
s_axis_read_desc_ready_next = 1'b0;
stat_rd_op_start_tag_next = stat_rd_op_start_tag_reg+1;
stat_rd_op_start_len_next = s_axis_read_desc_len;
stat_rd_op_start_valid_next = 1'b1;
req_state_next = REQ_STATE_START;
end else begin
req_state_next = REQ_STATE_IDLE;
@ -470,6 +532,10 @@ always @* begin
op_table_start_last = req_op_count_reg == req_tr_count_next;
op_table_start_en = 1'b1;
stat_rd_req_start_tag_next = op_table_start_ptr_reg[OP_TAG_WIDTH-1:0];
stat_rd_req_start_len_next = req_zero_len_reg ? 0 : req_tr_count_reg;
stat_rd_req_start_valid_next = 1'b1;
m_axi_arid_next = op_table_start_ptr_reg[OP_TAG_WIDTH-1:0];
m_axi_araddr_next = req_axi_addr_reg;
m_axi_arlen_next = op_table_start_cycle_count;
@ -513,6 +579,13 @@ always @* begin
m_axi_rready_next = 1'b0;
stat_rd_op_finish_tag_next = stat_rd_op_finish_tag_reg;
stat_rd_op_finish_status_next = stat_rd_op_finish_status_reg;
stat_rd_op_finish_valid_next = 1'b0;
stat_rd_req_finish_tag_next = stat_rd_req_finish_tag_reg;
stat_rd_req_finish_status_next = stat_rd_req_finish_status_reg;
stat_rd_req_finish_valid_next = 1'b0;
ram_sel_next = ram_sel_reg;
addr_next = addr_reg;
addr_delay_next = addr_delay_reg;
@ -624,12 +697,17 @@ always @* begin
status_fifo_error_next = DMA_ERROR_AXI_RD_DECERR;
end
stat_rd_req_finish_tag_next = op_tag_next;
stat_rd_req_finish_status_next = status_fifo_error_next;
stat_rd_req_finish_valid_next = 1'b0;
if (!USE_AXI_ID) begin
op_table_read_complete_en = 1'b1;
end
if (m_axi_rlast) begin
status_fifo_finish_next = 1'b1;
stat_rd_req_finish_valid_next = 1'b1;
axi_state_next = AXI_STATE_IDLE;
end else begin
axi_state_next = AXI_STATE_WRITE;
@ -685,8 +763,13 @@ always @* begin
status_fifo_error_next = DMA_ERROR_AXI_RD_DECERR;
end
stat_rd_req_finish_tag_next = op_tag_next;
stat_rd_req_finish_status_next = status_fifo_error_next;
stat_rd_req_finish_valid_next = 1'b0;
if (m_axi_rlast) begin
status_fifo_finish_next = 1'b1;
stat_rd_req_finish_valid_next = 1'b1;
axi_state_next = AXI_STATE_IDLE;
end else begin
axi_state_next = AXI_STATE_WRITE;
@ -762,6 +845,10 @@ always @* begin
m_axis_read_desc_status_tag_next = op_table_tag[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]];
m_axis_read_desc_status_valid_next = 1'b0;
stat_rd_op_finish_tag_next = stat_rd_op_finish_tag_reg;
stat_rd_op_finish_status_next = m_axis_read_desc_status_error_next;
stat_rd_op_finish_valid_next = 1'b0;
if (op_table_active[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]] && op_table_write_complete[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]] && op_table_finish_ptr_reg != op_table_start_ptr_reg) begin
op_table_finish_en = 1'b1;
@ -769,9 +856,13 @@ always @* begin
m_axis_read_desc_status_error_next = op_table_error_code[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]];
end
stat_rd_op_finish_status_next = m_axis_read_desc_status_error_next;
if (op_table_last[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]]) begin
m_axis_read_desc_status_tag_next = op_table_tag[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]];
m_axis_read_desc_status_valid_next = 1'b1;
stat_rd_op_finish_tag_next = stat_rd_op_finish_tag_reg + 1;
stat_rd_op_finish_valid_next = 1'b1;
end
end
end
@ -818,6 +909,21 @@ always @(posedge clk) begin
m_axis_read_desc_status_error_reg <= m_axis_read_desc_status_error_next;
m_axis_read_desc_status_valid_reg <= m_axis_read_desc_status_valid_next;
stat_rd_op_start_tag_reg <= stat_rd_op_start_tag_next;
stat_rd_op_start_len_reg <= stat_rd_op_start_len_next;
stat_rd_op_start_valid_reg <= stat_rd_op_start_valid_next;
stat_rd_op_finish_tag_reg <= stat_rd_op_finish_tag_next;
stat_rd_op_finish_status_reg <= stat_rd_op_finish_status_next;
stat_rd_op_finish_valid_reg <= stat_rd_op_finish_valid_next;
stat_rd_req_start_tag_reg <= stat_rd_req_start_tag_next;
stat_rd_req_start_len_reg <= stat_rd_req_start_len_next;
stat_rd_req_start_valid_reg <= stat_rd_req_start_valid_next;
stat_rd_req_finish_tag_reg <= stat_rd_req_finish_tag_next;
stat_rd_req_finish_status_reg <= stat_rd_req_finish_status_next;
stat_rd_req_finish_valid_reg <= stat_rd_req_finish_valid_next;
stat_rd_op_table_full_reg <= stat_rd_op_table_full_next;
stat_rd_tx_stall_reg <= stat_rd_tx_stall_next;
if (status_fifo_we) begin
status_fifo_op_tag[status_fifo_wr_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]] <= status_fifo_wr_op_tag;
status_fifo_mask[status_fifo_wr_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]] <= status_fifo_wr_mask;
@ -888,6 +994,15 @@ always @(posedge clk) begin
m_axis_read_desc_status_error_reg = 4'd0;
m_axis_read_desc_status_valid_reg <= 1'b0;
stat_rd_op_start_tag_reg <= 0;
stat_rd_op_start_valid_reg <= 1'b0;
stat_rd_op_finish_tag_reg <= 0;
stat_rd_op_finish_valid_reg <= 1'b0;
stat_rd_req_start_valid_reg <= 1'b0;
stat_rd_req_finish_valid_reg <= 1'b0;
stat_rd_op_table_full_reg <= 1'b0;
stat_rd_tx_stall_reg <= 1'b0;
status_fifo_wr_ptr_reg <= 0;
status_fifo_rd_ptr_reg <= 0;
status_fifo_we_reg <= 1'b0;

120
rtl/dma_if_axi_wr.v
View File

@ -123,7 +123,25 @@ module dma_if_axi_wr #
/*
* Configuration
*/
input wire enable
input wire enable,
/*
* Statistics
*/
output wire [$clog2(OP_TABLE_SIZE)-1:0] stat_wr_op_start_tag,
output wire [LEN_WIDTH-1:0] stat_wr_op_start_len,
output wire stat_wr_op_start_valid,
output wire [$clog2(OP_TABLE_SIZE)-1:0] stat_wr_op_finish_tag,
output wire [3:0] stat_wr_op_finish_status,
output wire stat_wr_op_finish_valid,
output wire [$clog2(OP_TABLE_SIZE)-1:0] stat_wr_req_start_tag,
output wire [12:0] stat_wr_req_start_len,
output wire stat_wr_req_start_valid,
output wire [$clog2(OP_TABLE_SIZE)-1:0] stat_wr_req_finish_tag,
output wire [3:0] stat_wr_req_finish_status,
output wire stat_wr_req_finish_valid,
output wire stat_wr_op_table_full,
output wire stat_wr_tx_stall
);
parameter RAM_WORD_WIDTH = RAM_SEG_BE_WIDTH;
@ -304,6 +322,21 @@ reg [RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] ram_rd_cmd_addr_reg = 0, ram_rd_cmd_a
reg [RAM_SEG_COUNT-1:0] ram_rd_cmd_valid_reg = 0, ram_rd_cmd_valid_next;
reg [RAM_SEG_COUNT-1:0] ram_rd_resp_ready_cmb;
reg [OP_TAG_WIDTH-1:0] stat_wr_op_start_tag_reg = 0, stat_wr_op_start_tag_next;
reg [LEN_WIDTH-1:0] stat_wr_op_start_len_reg = 0, stat_wr_op_start_len_next;
reg stat_wr_op_start_valid_reg = 1'b0, stat_wr_op_start_valid_next;
reg [OP_TAG_WIDTH-1:0] stat_wr_op_finish_tag_reg = 0, stat_wr_op_finish_tag_next;
reg [3:0] stat_wr_op_finish_status_reg = 0, stat_wr_op_finish_status_next;
reg stat_wr_op_finish_valid_reg = 1'b0, stat_wr_op_finish_valid_next;
reg [OP_TAG_WIDTH-1:0] stat_wr_req_start_tag_reg = 0, stat_wr_req_start_tag_next;
reg [12:0] stat_wr_req_start_len_reg = 13'd0, stat_wr_req_start_len_next;
reg stat_wr_req_start_valid_reg = 1'b0, stat_wr_req_start_valid_next;
reg [OP_TAG_WIDTH-1:0] stat_wr_req_finish_tag_reg = 0, stat_wr_req_finish_tag_next;
reg [3:0] stat_wr_req_finish_status_reg = 0, stat_wr_req_finish_status_next;
reg stat_wr_req_finish_valid_reg = 1'b0, stat_wr_req_finish_valid_next;
reg stat_wr_op_table_full_reg = 1'b0, stat_wr_op_table_full_next;
reg stat_wr_tx_stall_reg = 1'b0, stat_wr_tx_stall_next;
// internal datapath
reg [AXI_DATA_WIDTH-1:0] m_axi_wdata_int;
reg [AXI_STRB_WIDTH-1:0] m_axi_wstrb_int;
@ -333,6 +366,21 @@ assign ram_rd_cmd_addr = ram_rd_cmd_addr_reg;
assign ram_rd_cmd_valid = ram_rd_cmd_valid_reg;
assign ram_rd_resp_ready = ram_rd_resp_ready_cmb;
assign stat_wr_op_start_tag = stat_wr_op_start_tag_reg;
assign stat_wr_op_start_len = stat_wr_op_start_len_reg;
assign stat_wr_op_start_valid = stat_wr_op_start_valid_reg;
assign stat_wr_op_finish_tag = stat_wr_op_finish_tag_reg;
assign stat_wr_op_finish_status = stat_wr_op_finish_status_reg;
assign stat_wr_op_finish_valid = stat_wr_op_finish_valid_reg;
assign stat_wr_req_start_tag = stat_wr_req_start_tag_reg;
assign stat_wr_req_start_len = stat_wr_req_start_len_reg;
assign stat_wr_req_start_valid = stat_wr_req_start_valid_reg;
assign stat_wr_req_finish_tag = stat_wr_req_finish_tag_reg;
assign stat_wr_req_finish_status = stat_wr_req_finish_status_reg;
assign stat_wr_req_finish_valid = stat_wr_req_finish_valid_reg;
assign stat_wr_op_table_full = stat_wr_op_table_full_reg;
assign stat_wr_tx_stall = stat_wr_tx_stall_reg;
// operation tag management
reg [OP_TAG_WIDTH+1-1:0] op_table_start_ptr_reg = 0;
reg [AXI_ADDR_WIDTH-1:0] op_table_start_axi_addr;
@ -392,6 +440,15 @@ always @* begin
s_axis_write_desc_ready_next = 1'b0;
stat_wr_op_start_tag_next = stat_wr_op_start_tag_reg;
stat_wr_op_start_len_next = stat_wr_op_start_len_reg;
stat_wr_op_start_valid_next = 1'b0;
stat_wr_req_start_tag_next = stat_wr_req_start_tag_reg;
stat_wr_req_start_len_next = stat_wr_req_start_len_reg;
stat_wr_req_start_valid_next = 1'b0;
stat_wr_op_table_full_next = !(!op_table_active[op_table_start_ptr_reg[OP_TAG_WIDTH-1:0]] && ($unsigned(op_table_start_ptr_reg - op_table_finish_ptr_reg) < 2**OP_TAG_WIDTH));
stat_wr_tx_stall_next = (m_axi_awvalid && !m_axi_awready) || (m_axi_wvalid && !m_axi_wready);
tag_next = tag_reg;
req_axi_addr_next = req_axi_addr_reg;
ram_sel_next = ram_sel_reg;
@ -459,6 +516,11 @@ always @* begin
if (s_axis_write_desc_ready & s_axis_write_desc_valid) begin
s_axis_write_desc_ready_next = 1'b0;
stat_wr_op_start_tag_next = stat_wr_op_start_tag_reg+1;
stat_wr_op_start_len_next = s_axis_write_desc_len;
stat_wr_op_start_valid_next = 1'b1;
req_state_next = REQ_STATE_START;
end else begin
req_state_next = REQ_STATE_IDLE;
@ -488,6 +550,10 @@ always @* begin
op_table_start_last = op_count_reg == tr_word_count_next;
op_table_start_en = 1'b1;
stat_wr_req_start_tag_next = op_table_start_ptr_reg[OP_TAG_WIDTH-1:0];
stat_wr_req_start_len_next = zero_len_reg ? 0 : tr_word_count_next;
stat_wr_req_start_valid_next = 1'b1;
if (op_count_next <= AXI_MAX_BURST_SIZE - (req_axi_addr_next & OFFSET_MASK) || AXI_MAX_BURST_SIZE >= 4096) begin
// packet smaller than max burst size
if (((req_axi_addr_next & 12'hfff) + (op_count_next & 12'hfff)) >> 12 != 0 || op_count_next >> 12 != 0) begin
@ -679,6 +745,13 @@ always @* begin
ram_rd_resp_ready_cmb = {RAM_SEG_COUNT{1'b0}};
stat_wr_op_finish_tag_next = stat_wr_op_finish_tag_reg;
stat_wr_op_finish_status_next = stat_wr_op_finish_status_reg;
stat_wr_op_finish_valid_next = 1'b0;
stat_wr_req_finish_tag_next = stat_wr_req_finish_tag_reg;
stat_wr_req_finish_status_next = stat_wr_req_finish_status_reg;
stat_wr_req_finish_valid_next = 1'b0;
axi_addr_next = axi_addr_reg;
axi_len_next = axi_len_reg;
axi_zero_len_next = axi_zero_len_reg;
@ -813,12 +886,22 @@ always @* begin
end
m_axis_write_desc_status_valid_next = 1'b0;
stat_wr_req_finish_status_next = op_table_write_complete_error;
stat_wr_req_finish_valid_next = 1'b0;
stat_wr_op_finish_tag_next = stat_wr_op_finish_tag_reg;
stat_wr_op_finish_status_next = m_axis_write_desc_status_error_next;
stat_wr_op_finish_valid_next = 1'b0;
if (USE_AXI_ID) begin
// accept write completions
stat_wr_req_finish_tag_next = m_axi_bid;
m_axi_bready_next = 1'b1;
if (m_axi_bready && m_axi_bvalid) begin
op_table_write_complete_ptr = m_axi_bid;
op_table_write_complete_en = 1'b1;
stat_wr_req_finish_valid_next = 1'b1;
end
// commit operations in-order
@ -831,18 +914,25 @@ always @* begin
m_axis_write_desc_status_error_next = op_table_error_code[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]];
end
stat_wr_op_finish_status_next = m_axis_write_desc_status_error_next;
if (op_table_last[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]]) begin
m_axis_write_desc_status_tag_next = op_table_tag[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]];
m_axis_write_desc_status_valid_next = 1'b1;
stat_wr_op_finish_tag_next = stat_wr_op_finish_tag_reg + 1;
stat_wr_op_finish_valid_next = 1'b1;
end
end
end else begin
// accept write completions
op_table_finish_en = 1'b0;
stat_wr_req_finish_tag_next = op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0];
m_axi_bready_next = 1'b1;
if (m_axi_bready && m_axi_bvalid) begin
op_table_finish_en = 1'b1;
stat_wr_req_finish_valid_next = 1'b1;
if (m_axi_bresp == AXI_RESP_SLVERR) begin
m_axis_write_desc_status_error_next = DMA_ERROR_AXI_WR_SLVERR;
@ -850,9 +940,13 @@ always @* begin
m_axis_write_desc_status_error_next = DMA_ERROR_AXI_WR_DECERR;
end
stat_wr_op_finish_status_next = m_axis_write_desc_status_error_next;
if (op_table_last[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]]) begin
m_axis_write_desc_status_tag_next = op_table_tag[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]];
m_axis_write_desc_status_valid_next = 1'b1;
stat_wr_op_finish_tag_next = stat_wr_op_finish_tag_reg + 1;
stat_wr_op_finish_valid_next = 1'b1;
end
end
end
@ -917,6 +1011,21 @@ always @(posedge clk) begin
m_axis_write_desc_status_error_reg <= m_axis_write_desc_status_error_next;
m_axis_write_desc_status_valid_reg <= m_axis_write_desc_status_valid_next;
stat_wr_op_start_tag_reg <= stat_wr_op_start_tag_next;
stat_wr_op_start_len_reg <= stat_wr_op_start_len_next;
stat_wr_op_start_valid_reg <= stat_wr_op_start_valid_next;
stat_wr_op_finish_tag_reg <= stat_wr_op_finish_tag_next;
stat_wr_op_finish_status_reg <= stat_wr_op_finish_status_next;
stat_wr_op_finish_valid_reg <= stat_wr_op_finish_valid_next;
stat_wr_req_start_tag_reg <= stat_wr_req_start_tag_next;
stat_wr_req_start_len_reg <= stat_wr_req_start_len_next;
stat_wr_req_start_valid_reg <= stat_wr_req_start_valid_next;
stat_wr_req_finish_tag_reg <= stat_wr_req_finish_tag_next;
stat_wr_req_finish_status_reg <= stat_wr_req_finish_status_next;
stat_wr_req_finish_valid_reg <= stat_wr_req_finish_valid_next;
stat_wr_op_table_full_reg <= stat_wr_op_table_full_next;
stat_wr_tx_stall_reg <= stat_wr_tx_stall_next;
ram_rd_cmd_sel_reg <= ram_rd_cmd_sel_next;
ram_rd_cmd_addr_reg <= ram_rd_cmd_addr_next;
ram_rd_cmd_valid_reg <= ram_rd_cmd_valid_next;
@ -974,6 +1083,15 @@ always @(posedge clk) begin
m_axis_write_desc_status_error_reg <= 4'd0;
m_axis_write_desc_status_valid_reg <= 1'b0;
stat_wr_op_start_tag_reg <= 0;
stat_wr_op_start_valid_reg <= 1'b0;
stat_wr_op_finish_tag_reg <= 0;
stat_wr_op_finish_valid_reg <= 1'b0;
stat_wr_req_start_valid_reg <= 1'b0;
stat_wr_req_finish_valid_reg <= 1'b0;
stat_wr_op_table_full_reg <= 1'b0;
stat_wr_tx_stall_reg <= 1'b0;
ram_rd_cmd_valid_reg <= {RAM_SEG_COUNT{1'b0}};
mask_fifo_wr_ptr_reg <= 0;