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Improve status FIFO utilization

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-05-15 01:52:13 -07:00
parent 2d307a6d60
commit 4c82a8f465
3 changed files with 20 additions and 20 deletions
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10
rtl/dma_if_pcie_rd.v
View File

@ -391,7 +391,7 @@ reg status_fifo_mask_reg = 1'b0, status_fifo_mask_next;
reg status_fifo_finish_reg = 1'b0, status_fifo_finish_next;
reg [3:0] status_fifo_error_reg = 4'd0, status_fifo_error_next;
reg status_fifo_wr_en_reg = 1'b0, status_fifo_wr_en_next;
reg status_fifo_half_full_reg = 1'b0;
reg status_fifo_full_reg = 1'b0;
reg status_fifo_rd_en;
reg [OP_TAG_WIDTH-1:0] status_fifo_rd_op_tag_reg = 0;
reg [RAM_SEG_COUNT-1:0] status_fifo_rd_mask_reg = 0;
@ -928,7 +928,7 @@ always @* begin
case (tlp_state_reg)
TLP_STATE_IDLE: begin
// idle state, wait for completion
rx_cpl_tlp_ready_next = init_done_reg && &ram_wr_cmd_ready_int && !status_fifo_half_full_reg;
rx_cpl_tlp_ready_next = init_done_reg && &ram_wr_cmd_ready_int && !status_fifo_full_reg;
if (rx_cpl_tlp_ready && rx_cpl_tlp_valid && rx_cpl_tlp_sop) begin
op_dword_count_next = rx_cpl_tlp_hdr_length;
@ -1115,7 +1115,7 @@ always @* begin
end
TLP_STATE_WRITE: begin
// write state - generate write operations
rx_cpl_tlp_ready_next = init_done_reg && &ram_wr_cmd_ready_int && !status_fifo_half_full_reg;
rx_cpl_tlp_ready_next = init_done_reg && &ram_wr_cmd_ready_int && !status_fifo_full_reg;
if (rx_cpl_tlp_ready && rx_cpl_tlp_valid) begin
tlp_data_int_next = rx_cpl_tlp_data;
@ -1185,7 +1185,7 @@ always @* begin
if (rx_cpl_tlp_ready && rx_cpl_tlp_valid) begin
if (rx_cpl_tlp_eop) begin
rx_cpl_tlp_ready_next = init_done_reg && &ram_wr_cmd_ready_int && !status_fifo_half_full_reg;
rx_cpl_tlp_ready_next = init_done_reg && &ram_wr_cmd_ready_int && !status_fifo_full_reg;
tlp_state_next = TLP_STATE_IDLE;
end else begin
tlp_state_next = TLP_STATE_WAIT_END;
@ -1424,7 +1424,7 @@ always @(posedge clk) begin
status_fifo_rd_valid_reg <= status_fifo_rd_valid_next;
status_fifo_half_full_reg <= $unsigned(status_fifo_wr_ptr_reg - status_fifo_rd_ptr_reg) >= 2**(STATUS_FIFO_ADDR_WIDTH-1);
status_fifo_full_reg <= $unsigned(status_fifo_wr_ptr_reg - status_fifo_rd_ptr_reg) >= 2**STATUS_FIFO_ADDR_WIDTH-4;
active_tx_count_reg <= active_tx_count_next;
active_tx_count_av_reg <= active_tx_count_av_next;

14
rtl/dma_if_pcie_us_rd.v
View File

@ -409,7 +409,7 @@ reg status_fifo_mask_reg = 1'b0, status_fifo_mask_next;
reg status_fifo_finish_reg = 1'b0, status_fifo_finish_next;
reg [3:0] status_fifo_error_reg = 4'd0, status_fifo_error_next;
reg status_fifo_wr_en_reg = 1'b0, status_fifo_wr_en_next;
reg status_fifo_half_full_reg = 1'b0;
reg status_fifo_full_reg = 1'b0;
reg status_fifo_rd_en;
reg [OP_TAG_WIDTH-1:0] status_fifo_rd_op_tag_reg = 0;
reg [SEG_COUNT-1:0] status_fifo_rd_mask_reg = 0;
@ -906,7 +906,7 @@ always @* begin
TLP_STATE_IDLE: begin
// idle state, wait for completion
if (AXIS_PCIE_DATA_WIDTH > 64) begin
s_axis_rc_tready_next = init_done_reg && &ram_wr_cmd_ready_int && !status_fifo_half_full_reg;
s_axis_rc_tready_next = init_done_reg && &ram_wr_cmd_ready_int && !status_fifo_full_reg;
if (s_axis_rc_tready && s_axis_rc_tvalid) begin
// header fields
@ -1132,7 +1132,7 @@ always @* begin
s_axis_rc_tready_next = init_done_reg;
tlp_state_next = TLP_STATE_IDLE;
end else begin
s_axis_rc_tready_next = init_done_reg && &ram_wr_cmd_ready_int && !status_fifo_half_full_reg;
s_axis_rc_tready_next = init_done_reg && &ram_wr_cmd_ready_int && !status_fifo_full_reg;
tlp_state_next = TLP_STATE_HEADER;
end
end else begin
@ -1143,7 +1143,7 @@ always @* begin
end
TLP_STATE_HEADER: begin
// header state; process header (64 bit interface only)
s_axis_rc_tready_next = init_done_reg && &ram_wr_cmd_ready_int && !status_fifo_half_full_reg;
s_axis_rc_tready_next = init_done_reg && &ram_wr_cmd_ready_int && !status_fifo_full_reg;
if (s_axis_rc_tready && s_axis_rc_tvalid) begin
pcie_tag_next = s_axis_rc_tdata[7:0]; // tag
@ -1285,7 +1285,7 @@ always @* begin
end
TLP_STATE_WRITE: begin
// write state - generate write operations
s_axis_rc_tready_next = init_done_reg && &ram_wr_cmd_ready_int && !status_fifo_half_full_reg;
s_axis_rc_tready_next = init_done_reg && &ram_wr_cmd_ready_int && !status_fifo_full_reg;
if (s_axis_rc_tready && s_axis_rc_tvalid) begin
rc_tdata_int_next = s_axis_rc_tdata;
@ -1350,7 +1350,7 @@ always @* begin
if (s_axis_rc_tready & s_axis_rc_tvalid) begin
if (s_axis_rc_tlast) begin
if (AXIS_PCIE_DATA_WIDTH > 64) begin
s_axis_rc_tready_next = init_done_reg && &ram_wr_cmd_ready_int && !status_fifo_half_full_reg;
s_axis_rc_tready_next = init_done_reg && &ram_wr_cmd_ready_int && !status_fifo_full_reg;
end else begin
s_axis_rc_tready_next = init_done_reg;
end
@ -1538,7 +1538,7 @@ always @(posedge clk) begin
status_fifo_rd_valid_reg <= status_fifo_rd_valid_next;
status_fifo_half_full_reg <= $unsigned(status_fifo_wr_ptr_reg - status_fifo_rd_ptr_reg) >= 2**(STATUS_FIFO_ADDR_WIDTH-1);
status_fifo_full_reg <= $unsigned(status_fifo_wr_ptr_reg - status_fifo_rd_ptr_reg) >= 2**STATUS_FIFO_ADDR_WIDTH-4;
if (active_tx_count_reg < TX_LIMIT && inc_active_tx && !s_axis_rq_seq_num_valid_0 && !s_axis_rq_seq_num_valid_1) begin
// inc by 1

16
rtl/pcie_us_axi_dma_rd.v
View File

@ -413,7 +413,7 @@ reg status_fifo_skip_reg = 1'b0, status_fifo_skip_next;
reg status_fifo_finish_reg = 1'b0, status_fifo_finish_next;
reg [3:0] status_fifo_error_reg = 4'd0, status_fifo_error_next;
reg status_fifo_we_reg = 1'b0, status_fifo_we_next;
reg status_fifo_half_full_reg = 1'b0;
reg status_fifo_full_reg = 1'b0;
reg [OP_TAG_WIDTH-1:0] status_fifo_rd_op_tag_reg = 0, status_fifo_rd_op_tag_next;
reg status_fifo_rd_skip_reg = 1'b0, status_fifo_rd_skip_next;
reg status_fifo_rd_finish_reg = 1'b0, status_fifo_rd_finish_next;
@ -907,7 +907,7 @@ always @* begin
if (AXIS_PCIE_DATA_WIDTH > 64) begin
s_axis_rc_tready_next = 1'b0;
if (init_done_reg && s_axis_rc_tvalid && !status_fifo_half_full_reg) begin
if (init_done_reg && s_axis_rc_tvalid && !status_fifo_full_reg) begin
// header fields
lower_addr_next = s_axis_rc_tdata[11:0]; // lower address
error_code_next = s_axis_rc_tdata[15:12]; // error code
@ -1036,7 +1036,7 @@ always @* begin
tlp_state_next = TLP_STATE_IDLE;
end
end else begin
s_axis_rc_tready_next = init_done_reg && !status_fifo_half_full_reg;
s_axis_rc_tready_next = init_done_reg && !status_fifo_full_reg;
if (s_axis_rc_tready && s_axis_rc_tvalid) begin
// header fields
@ -1070,14 +1070,14 @@ always @* begin
end
if (s_axis_rc_tlast) begin
s_axis_rc_tready_next = init_done_reg && !status_fifo_half_full_reg;
s_axis_rc_tready_next = init_done_reg && !status_fifo_full_reg;
tlp_state_next = TLP_STATE_IDLE;
end else begin
s_axis_rc_tready_next = 1'b0;
tlp_state_next = TLP_STATE_HEADER;
end
end else begin
s_axis_rc_tready_next = init_done_reg && !status_fifo_half_full_reg;
s_axis_rc_tready_next = init_done_reg && !status_fifo_full_reg;
tlp_state_next = TLP_STATE_IDLE;
end
end
@ -1341,7 +1341,7 @@ always @* begin
if (AXIS_PCIE_DATA_WIDTH > 64) begin
s_axis_rc_tready_next = 1'b0;
end else begin
s_axis_rc_tready_next = init_done_reg && !status_fifo_half_full_reg;
s_axis_rc_tready_next = init_done_reg && !status_fifo_full_reg;
end
tlp_state_next = TLP_STATE_IDLE;
end
@ -1358,7 +1358,7 @@ always @* begin
if (AXIS_PCIE_DATA_WIDTH > 64) begin
s_axis_rc_tready_next = 1'b0;
end else begin
s_axis_rc_tready_next = init_done_reg && !status_fifo_half_full_reg;
s_axis_rc_tready_next = init_done_reg && !status_fifo_full_reg;
end
tlp_state_next = TLP_STATE_IDLE;
end else begin
@ -1571,7 +1571,7 @@ always @(posedge clk) begin
status_fifo_rd_error_reg <= status_fifo_rd_error_next;
status_fifo_rd_valid_reg <= status_fifo_rd_valid_next;
status_fifo_half_full_reg <= $unsigned(status_fifo_wr_ptr_reg - status_fifo_rd_ptr_reg) >= 2**(STATUS_FIFO_ADDR_WIDTH-1);
status_fifo_full_reg <= $unsigned(status_fifo_wr_ptr_reg - status_fifo_rd_ptr_reg) >= 2**STATUS_FIFO_ADDR_WIDTH-4;
if (inc_active_tx && !s_axis_rq_seq_num_valid_0 && !s_axis_rq_seq_num_valid_1) begin
// inc by 1