From 4d1180d74c902897ba2666b0308c2472fc21f40d Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sun, 16 Nov 2014 02:20:44 -0800 Subject: [PATCH] Reverse priority in arbitrated mux --- rtl/eth_arb_mux.py | 7 +++-- rtl/eth_arb_mux_4.v | 7 +++-- rtl/eth_arb_mux_64.py | 7 +++-- rtl/eth_arb_mux_64_4.v | 7 +++-- tb/test_eth_arb_mux_4.py | 58 ++++++++++++++++++------------------- tb/test_eth_arb_mux_64_4.py | 58 ++++++++++++++++++------------------- 6 files changed, 78 insertions(+), 66 deletions(-) diff --git a/rtl/eth_arb_mux.py b/rtl/eth_arb_mux.py index 918787607..998ff328b 100755 --- a/rtl/eth_arb_mux.py +++ b/rtl/eth_arb_mux.py @@ -102,7 +102,9 @@ THE SOFTWARE. module {{name}} # ( // arbitration type: "PRIORITY" or "ROUND_ROBIN" - parameter ARB_TYPE = "PRIORITY" + parameter ARB_TYPE = "PRIORITY", + // LSB priority: "LOW", "HIGH" + parameter LSB_PRIORITY = "HIGH" ) ( input wire clk, @@ -183,7 +185,8 @@ mux_inst ( arbiter #( .PORTS({{n}}), .TYPE(ARB_TYPE), - .BLOCK("ACKNOWLEDGE") + .BLOCK("ACKNOWLEDGE"), + .LSB_PRIORITY(LSB_PRIORITY) ) arb_inst ( .clk(clk), diff --git a/rtl/eth_arb_mux_4.v b/rtl/eth_arb_mux_4.v index 166f05f58..71e75e091 100644 --- a/rtl/eth_arb_mux_4.v +++ b/rtl/eth_arb_mux_4.v @@ -32,7 +32,9 @@ THE SOFTWARE. module eth_arb_mux_4 # ( // arbitration type: "PRIORITY" or "ROUND_ROBIN" - parameter ARB_TYPE = "PRIORITY" + parameter ARB_TYPE = "PRIORITY", + // LSB priority: "LOW", "HIGH" + parameter LSB_PRIORITY = "HIGH" ) ( input wire clk, @@ -178,7 +180,8 @@ mux_inst ( arbiter #( .PORTS(4), .TYPE(ARB_TYPE), - .BLOCK("ACKNOWLEDGE") + .BLOCK("ACKNOWLEDGE"), + .LSB_PRIORITY(LSB_PRIORITY) ) arb_inst ( .clk(clk), diff --git a/rtl/eth_arb_mux_64.py b/rtl/eth_arb_mux_64.py index cbc839fab..9c7b642f5 100755 --- a/rtl/eth_arb_mux_64.py +++ b/rtl/eth_arb_mux_64.py @@ -102,7 +102,9 @@ THE SOFTWARE. module {{name}} # ( // arbitration type: "PRIORITY" or "ROUND_ROBIN" - parameter ARB_TYPE = "PRIORITY" + parameter ARB_TYPE = "PRIORITY", + // LSB priority: "LOW", "HIGH" + parameter LSB_PRIORITY = "HIGH" ) ( input wire clk, @@ -187,7 +189,8 @@ mux_inst ( arbiter #( .PORTS({{n}}), .TYPE(ARB_TYPE), - .BLOCK("ACKNOWLEDGE") + .BLOCK("ACKNOWLEDGE"), + .LSB_PRIORITY(LSB_PRIORITY) ) arb_inst ( .clk(clk), diff --git a/rtl/eth_arb_mux_64_4.v b/rtl/eth_arb_mux_64_4.v index 4c2aa57fe..84a7ab1ff 100644 --- a/rtl/eth_arb_mux_64_4.v +++ b/rtl/eth_arb_mux_64_4.v @@ -32,7 +32,9 @@ THE SOFTWARE. module eth_arb_mux_64_4 # ( // arbitration type: "PRIORITY" or "ROUND_ROBIN" - parameter ARB_TYPE = "PRIORITY" + parameter ARB_TYPE = "PRIORITY", + // LSB priority: "LOW", "HIGH" + parameter LSB_PRIORITY = "HIGH" ) ( input wire clk, @@ -188,7 +190,8 @@ mux_inst ( arbiter #( .PORTS(4), .TYPE(ARB_TYPE), - .BLOCK("ACKNOWLEDGE") + .BLOCK("ACKNOWLEDGE"), + .LSB_PRIORITY(LSB_PRIORITY) ) arb_inst ( .clk(clk), diff --git a/tb/test_eth_arb_mux_4.py b/tb/test_eth_arb_mux_4.py index 84347fac0..d3c086ef0 100755 --- a/tb/test_eth_arb_mux_4.py +++ b/tb/test_eth_arb_mux_4.py @@ -508,13 +508,13 @@ def bench(): if not sink_queue.empty(): rx_frame = sink_queue.get() - assert rx_frame == test_frame2 + assert rx_frame == test_frame1 rx_frame = None if not sink_queue.empty(): rx_frame = sink_queue.get() - assert rx_frame == test_frame1 + assert rx_frame == test_frame2 yield delay(100) @@ -558,13 +558,13 @@ def bench(): if not sink_queue.empty(): rx_frame = sink_queue.get() - assert rx_frame == test_frame2 + assert rx_frame == test_frame1 rx_frame = None if not sink_queue.empty(): rx_frame = sink_queue.get() - assert rx_frame == test_frame1 + assert rx_frame == test_frame2 yield delay(100) @@ -603,13 +603,13 @@ def bench(): if not sink_queue.empty(): rx_frame = sink_queue.get() - assert rx_frame == test_frame2 + assert rx_frame == test_frame1 rx_frame = None if not sink_queue.empty(): rx_frame = sink_queue.get() - assert rx_frame == test_frame1 + assert rx_frame == test_frame2 yield delay(100) @@ -630,39 +630,21 @@ def bench(): source_1_queue.put(test_frame1) source_2_queue.put(test_frame2) - source_1_queue.put(test_frame1) - source_1_queue.put(test_frame1) - source_1_queue.put(test_frame1) - source_1_queue.put(test_frame1) + source_2_queue.put(test_frame2) + source_2_queue.put(test_frame2) + source_2_queue.put(test_frame2) + source_2_queue.put(test_frame2) yield clk.posedge yield delay(800) yield clk.posedge - source_2_queue.put(test_frame2) + source_1_queue.put(test_frame1) while input_0_eth_payload_tvalid or input_1_eth_payload_tvalid or input_2_eth_payload_tvalid or input_3_eth_payload_tvalid: yield clk.posedge yield clk.posedge yield clk.posedge - rx_frame = None - if not sink_queue.empty(): - rx_frame = sink_queue.get() - - assert rx_frame == test_frame2 - - rx_frame = None - if not sink_queue.empty(): - rx_frame = sink_queue.get() - - assert rx_frame == test_frame1 - - rx_frame = None - if not sink_queue.empty(): - rx_frame = sink_queue.get() - - assert rx_frame == test_frame1 - rx_frame = None if not sink_queue.empty(): rx_frame = sink_queue.get() @@ -675,12 +657,30 @@ def bench(): assert rx_frame == test_frame2 + rx_frame = None + if not sink_queue.empty(): + rx_frame = sink_queue.get() + + assert rx_frame == test_frame2 + + rx_frame = None + if not sink_queue.empty(): + rx_frame = sink_queue.get() + + assert rx_frame == test_frame2 + rx_frame = None if not sink_queue.empty(): rx_frame = sink_queue.get() assert rx_frame == test_frame1 + rx_frame = None + if not sink_queue.empty(): + rx_frame = sink_queue.get() + + assert rx_frame == test_frame2 + yield delay(100) raise StopSimulation diff --git a/tb/test_eth_arb_mux_64_4.py b/tb/test_eth_arb_mux_64_4.py index edf0ee619..699276ce1 100755 --- a/tb/test_eth_arb_mux_64_4.py +++ b/tb/test_eth_arb_mux_64_4.py @@ -533,13 +533,13 @@ def bench(): if not sink_queue.empty(): rx_frame = sink_queue.get() - assert rx_frame == test_frame2 + assert rx_frame == test_frame1 rx_frame = None if not sink_queue.empty(): rx_frame = sink_queue.get() - assert rx_frame == test_frame1 + assert rx_frame == test_frame2 yield delay(100) @@ -583,13 +583,13 @@ def bench(): if not sink_queue.empty(): rx_frame = sink_queue.get() - assert rx_frame == test_frame2 + assert rx_frame == test_frame1 rx_frame = None if not sink_queue.empty(): rx_frame = sink_queue.get() - assert rx_frame == test_frame1 + assert rx_frame == test_frame2 yield delay(100) @@ -628,13 +628,13 @@ def bench(): if not sink_queue.empty(): rx_frame = sink_queue.get() - assert rx_frame == test_frame2 + assert rx_frame == test_frame1 rx_frame = None if not sink_queue.empty(): rx_frame = sink_queue.get() - assert rx_frame == test_frame1 + assert rx_frame == test_frame2 yield delay(100) @@ -655,39 +655,21 @@ def bench(): source_1_queue.put(test_frame1) source_2_queue.put(test_frame2) - source_1_queue.put(test_frame1) - source_1_queue.put(test_frame1) - source_1_queue.put(test_frame1) - source_1_queue.put(test_frame1) + source_2_queue.put(test_frame2) + source_2_queue.put(test_frame2) + source_2_queue.put(test_frame2) + source_2_queue.put(test_frame2) yield clk.posedge yield delay(150) yield clk.posedge - source_2_queue.put(test_frame2) + source_1_queue.put(test_frame1) while input_0_eth_payload_tvalid or input_1_eth_payload_tvalid or input_2_eth_payload_tvalid or input_3_eth_payload_tvalid: yield clk.posedge yield clk.posedge yield clk.posedge - rx_frame = None - if not sink_queue.empty(): - rx_frame = sink_queue.get() - - assert rx_frame == test_frame2 - - rx_frame = None - if not sink_queue.empty(): - rx_frame = sink_queue.get() - - assert rx_frame == test_frame1 - - rx_frame = None - if not sink_queue.empty(): - rx_frame = sink_queue.get() - - assert rx_frame == test_frame1 - rx_frame = None if not sink_queue.empty(): rx_frame = sink_queue.get() @@ -700,12 +682,30 @@ def bench(): assert rx_frame == test_frame2 + rx_frame = None + if not sink_queue.empty(): + rx_frame = sink_queue.get() + + assert rx_frame == test_frame2 + + rx_frame = None + if not sink_queue.empty(): + rx_frame = sink_queue.get() + + assert rx_frame == test_frame2 + rx_frame = None if not sink_queue.empty(): rx_frame = sink_queue.get() assert rx_frame == test_frame1 + rx_frame = None + if not sink_queue.empty(): + rx_frame = sink_queue.get() + + assert rx_frame == test_frame2 + yield delay(100) raise StopSimulation