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Reverse priority in arbitrated mux

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This commit is contained in:
Alex Forencich 2014-11-16 02:20:44 -08:00
parent f1d075d974
commit 4d1180d74c
6 changed files with 78 additions and 66 deletions
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7
rtl/eth_arb_mux.py
View File

@ -102,7 +102,9 @@ THE SOFTWARE.
module {{name}} # module {{name}} #
( (
// arbitration type: "PRIORITY" or "ROUND_ROBIN" // arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter ARB_TYPE = "PRIORITY" parameter ARB_TYPE = "PRIORITY",
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "HIGH"
) )
( (
input wire clk, input wire clk,
@ -183,7 +185,8 @@ mux_inst (
arbiter #( arbiter #(
.PORTS({{n}}), .PORTS({{n}}),
.TYPE(ARB_TYPE), .TYPE(ARB_TYPE),
.BLOCK("ACKNOWLEDGE") .BLOCK("ACKNOWLEDGE"),
.LSB_PRIORITY(LSB_PRIORITY)
) )
arb_inst ( arb_inst (
.clk(clk), .clk(clk),

7
rtl/eth_arb_mux_4.v
View File

@ -32,7 +32,9 @@ THE SOFTWARE.
module eth_arb_mux_4 # module eth_arb_mux_4 #
( (
// arbitration type: "PRIORITY" or "ROUND_ROBIN" // arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter ARB_TYPE = "PRIORITY" parameter ARB_TYPE = "PRIORITY",
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "HIGH"
) )
( (
input wire clk, input wire clk,
@ -178,7 +180,8 @@ mux_inst (
arbiter #( arbiter #(
.PORTS(4), .PORTS(4),
.TYPE(ARB_TYPE), .TYPE(ARB_TYPE),
.BLOCK("ACKNOWLEDGE") .BLOCK("ACKNOWLEDGE"),
.LSB_PRIORITY(LSB_PRIORITY)
) )
arb_inst ( arb_inst (
.clk(clk), .clk(clk),

7
rtl/eth_arb_mux_64.py
View File

@ -102,7 +102,9 @@ THE SOFTWARE.
module {{name}} # module {{name}} #
( (
// arbitration type: "PRIORITY" or "ROUND_ROBIN" // arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter ARB_TYPE = "PRIORITY" parameter ARB_TYPE = "PRIORITY",
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "HIGH"
) )
( (
input wire clk, input wire clk,
@ -187,7 +189,8 @@ mux_inst (
arbiter #( arbiter #(
.PORTS({{n}}), .PORTS({{n}}),
.TYPE(ARB_TYPE), .TYPE(ARB_TYPE),
.BLOCK("ACKNOWLEDGE") .BLOCK("ACKNOWLEDGE"),
.LSB_PRIORITY(LSB_PRIORITY)
) )
arb_inst ( arb_inst (
.clk(clk), .clk(clk),

7
rtl/eth_arb_mux_64_4.v
View File

@ -32,7 +32,9 @@ THE SOFTWARE.
module eth_arb_mux_64_4 # module eth_arb_mux_64_4 #
( (
// arbitration type: "PRIORITY" or "ROUND_ROBIN" // arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter ARB_TYPE = "PRIORITY" parameter ARB_TYPE = "PRIORITY",
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "HIGH"
) )
( (
input wire clk, input wire clk,
@ -188,7 +190,8 @@ mux_inst (
arbiter #( arbiter #(
.PORTS(4), .PORTS(4),
.TYPE(ARB_TYPE), .TYPE(ARB_TYPE),
.BLOCK("ACKNOWLEDGE") .BLOCK("ACKNOWLEDGE"),
.LSB_PRIORITY(LSB_PRIORITY)
) )
arb_inst ( arb_inst (
.clk(clk), .clk(clk),

58
tb/test_eth_arb_mux_4.py
View File

@ -508,13 +508,13 @@ def bench():
if not sink_queue.empty(): if not sink_queue.empty():
rx_frame = sink_queue.get() rx_frame = sink_queue.get()
assert rx_frame == test_frame2 assert rx_frame == test_frame1
rx_frame = None rx_frame = None
if not sink_queue.empty(): if not sink_queue.empty():
rx_frame = sink_queue.get() rx_frame = sink_queue.get()
assert rx_frame == test_frame1 assert rx_frame == test_frame2
yield delay(100) yield delay(100)
@ -558,13 +558,13 @@ def bench():
if not sink_queue.empty(): if not sink_queue.empty():
rx_frame = sink_queue.get() rx_frame = sink_queue.get()
assert rx_frame == test_frame2 assert rx_frame == test_frame1
rx_frame = None rx_frame = None
if not sink_queue.empty(): if not sink_queue.empty():
rx_frame = sink_queue.get() rx_frame = sink_queue.get()
assert rx_frame == test_frame1 assert rx_frame == test_frame2
yield delay(100) yield delay(100)
@ -603,13 +603,13 @@ def bench():
if not sink_queue.empty(): if not sink_queue.empty():
rx_frame = sink_queue.get() rx_frame = sink_queue.get()
assert rx_frame == test_frame2 assert rx_frame == test_frame1
rx_frame = None rx_frame = None
if not sink_queue.empty(): if not sink_queue.empty():
rx_frame = sink_queue.get() rx_frame = sink_queue.get()
assert rx_frame == test_frame1 assert rx_frame == test_frame2
yield delay(100) yield delay(100)
@ -630,39 +630,21 @@ def bench():
source_1_queue.put(test_frame1) source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2) source_2_queue.put(test_frame2)
source_1_queue.put(test_frame1) source_2_queue.put(test_frame2)
source_1_queue.put(test_frame1) source_2_queue.put(test_frame2)
source_1_queue.put(test_frame1) source_2_queue.put(test_frame2)
source_1_queue.put(test_frame1) source_2_queue.put(test_frame2)
yield clk.posedge yield clk.posedge
yield delay(800) yield delay(800)
yield clk.posedge yield clk.posedge
source_2_queue.put(test_frame2) source_1_queue.put(test_frame1)
while input_0_eth_payload_tvalid or input_1_eth_payload_tvalid or input_2_eth_payload_tvalid or input_3_eth_payload_tvalid: while input_0_eth_payload_tvalid or input_1_eth_payload_tvalid or input_2_eth_payload_tvalid or input_3_eth_payload_tvalid:
yield clk.posedge yield clk.posedge
yield clk.posedge yield clk.posedge
yield clk.posedge yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None rx_frame = None
if not sink_queue.empty(): if not sink_queue.empty():
rx_frame = sink_queue.get() rx_frame = sink_queue.get()
@ -675,12 +657,30 @@ def bench():
assert rx_frame == test_frame2 assert rx_frame == test_frame2
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
rx_frame = None rx_frame = None
if not sink_queue.empty(): if not sink_queue.empty():
rx_frame = sink_queue.get() rx_frame = sink_queue.get()
assert rx_frame == test_frame1 assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
yield delay(100) yield delay(100)
raise StopSimulation raise StopSimulation

58
tb/test_eth_arb_mux_64_4.py
View File

@ -533,13 +533,13 @@ def bench():
if not sink_queue.empty(): if not sink_queue.empty():
rx_frame = sink_queue.get() rx_frame = sink_queue.get()
assert rx_frame == test_frame2 assert rx_frame == test_frame1
rx_frame = None rx_frame = None
if not sink_queue.empty(): if not sink_queue.empty():
rx_frame = sink_queue.get() rx_frame = sink_queue.get()
assert rx_frame == test_frame1 assert rx_frame == test_frame2
yield delay(100) yield delay(100)
@ -583,13 +583,13 @@ def bench():
if not sink_queue.empty(): if not sink_queue.empty():
rx_frame = sink_queue.get() rx_frame = sink_queue.get()
assert rx_frame == test_frame2 assert rx_frame == test_frame1
rx_frame = None rx_frame = None
if not sink_queue.empty(): if not sink_queue.empty():
rx_frame = sink_queue.get() rx_frame = sink_queue.get()
assert rx_frame == test_frame1 assert rx_frame == test_frame2
yield delay(100) yield delay(100)
@ -628,13 +628,13 @@ def bench():
if not sink_queue.empty(): if not sink_queue.empty():
rx_frame = sink_queue.get() rx_frame = sink_queue.get()
assert rx_frame == test_frame2 assert rx_frame == test_frame1
rx_frame = None rx_frame = None
if not sink_queue.empty(): if not sink_queue.empty():
rx_frame = sink_queue.get() rx_frame = sink_queue.get()
assert rx_frame == test_frame1 assert rx_frame == test_frame2
yield delay(100) yield delay(100)
@ -655,39 +655,21 @@ def bench():
source_1_queue.put(test_frame1) source_1_queue.put(test_frame1)
source_2_queue.put(test_frame2) source_2_queue.put(test_frame2)
source_1_queue.put(test_frame1) source_2_queue.put(test_frame2)
source_1_queue.put(test_frame1) source_2_queue.put(test_frame2)
source_1_queue.put(test_frame1) source_2_queue.put(test_frame2)
source_1_queue.put(test_frame1) source_2_queue.put(test_frame2)
yield clk.posedge yield clk.posedge
yield delay(150) yield delay(150)
yield clk.posedge yield clk.posedge
source_2_queue.put(test_frame2) source_1_queue.put(test_frame1)
while input_0_eth_payload_tvalid or input_1_eth_payload_tvalid or input_2_eth_payload_tvalid or input_3_eth_payload_tvalid: while input_0_eth_payload_tvalid or input_1_eth_payload_tvalid or input_2_eth_payload_tvalid or input_3_eth_payload_tvalid:
yield clk.posedge yield clk.posedge
yield clk.posedge yield clk.posedge
yield clk.posedge yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame1
rx_frame = None rx_frame = None
if not sink_queue.empty(): if not sink_queue.empty():
rx_frame = sink_queue.get() rx_frame = sink_queue.get()
@ -700,12 +682,30 @@ def bench():
assert rx_frame == test_frame2 assert rx_frame == test_frame2
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
rx_frame = None rx_frame = None
if not sink_queue.empty(): if not sink_queue.empty():
rx_frame = sink_queue.get() rx_frame = sink_queue.get()
assert rx_frame == test_frame1 assert rx_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame2
yield delay(100) yield delay(100)
raise StopSimulation raise StopSimulation