diff --git a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au200.v b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au200.v
index 2a9324bd5..ea959fa2d 100644
--- a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au200.v
+++ b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au200.v
@@ -1991,6 +1991,10 @@ fpga_core #(
     .QSFP_CNT(QSFP_CNT),
     .CH_CNT(QSFP_CNT*4),
     .CMS_ENABLE(CMS_ENABLE),
+    .FLASH_SEG_COUNT(2),
+    .FLASH_SEG_DEFAULT(1),
+    .FLASH_SEG_FALLBACK(0),
+    .FLASH_SEG0_SIZE(32'h01002000),
 
     // Structural configuration
     .IF_COUNT(IF_COUNT),
diff --git a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au280.v b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au280.v
index f5d21ac08..0f01f06b3 100644
--- a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au280.v
+++ b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au280.v
@@ -1789,6 +1789,10 @@ fpga_core #(
     .QSFP_CNT(QSFP_CNT),
     .CH_CNT(QSFP_CNT*4),
     .CMS_ENABLE(CMS_ENABLE),
+    .FLASH_SEG_COUNT(2),
+    .FLASH_SEG_DEFAULT(1),
+    .FLASH_SEG_FALLBACK(0),
+    .FLASH_SEG0_SIZE(32'h01002000),
 
     // Structural configuration
     .IF_COUNT(IF_COUNT),
diff --git a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au50.v b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au50.v
index 0f4a12a6b..f9744ce99 100644
--- a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au50.v
+++ b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au50.v
@@ -1288,6 +1288,10 @@ fpga_core #(
     .QSFP_CNT(QSFP_CNT),
     .CH_CNT(QSFP_CNT*4),
     .CMS_ENABLE(CMS_ENABLE),
+    .FLASH_SEG_COUNT(2),
+    .FLASH_SEG_DEFAULT(1),
+    .FLASH_SEG_FALLBACK(0),
+    .FLASH_SEG0_SIZE(32'h01002000),
 
     // Structural configuration
     .IF_COUNT(IF_COUNT),
diff --git a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au55.v b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au55.v
index b56e34898..a79f43128 100644
--- a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au55.v
+++ b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au55.v
@@ -1415,6 +1415,10 @@ fpga_core #(
     .QSFP_CNT(QSFP_CNT),
     .CH_CNT(QSFP_CNT*4),
     .CMS_ENABLE(CMS_ENABLE),
+    .FLASH_SEG_COUNT(2),
+    .FLASH_SEG_DEFAULT(1),
+    .FLASH_SEG_FALLBACK(0),
+    .FLASH_SEG0_SIZE(32'h01002000),
 
     // Structural configuration
     .IF_COUNT(IF_COUNT),
diff --git a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_core.v
index b4bcb2584..2139dcb2a 100644
--- a/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_core.v
+++ b/fpga/mqnic/Alveo/fpga_100g/rtl/fpga_core.v
@@ -28,6 +28,10 @@ module fpga_core #
     parameter QSFP_CNT = 2,
     parameter CH_CNT = QSFP_CNT*4,
     parameter CMS_ENABLE = 1,
+    parameter FLASH_SEG_COUNT = 2,
+    parameter FLASH_SEG_DEFAULT = 1,
+    parameter FLASH_SEG_FALLBACK = 0,
+    parameter FLASH_SEG0_SIZE = 32'h01002000,
 
     // Structural configuration
     parameter IF_COUNT = 2,
@@ -722,10 +726,10 @@ always @(posedge clk_250mhz) begin
             RBB+8'h28: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h40;       // SPI flash ctrl: Next header
             RBB+8'h2C: begin
                 // SPI flash ctrl: format
-                ctrl_reg_rd_data_reg[3:0]   <= 2;                   // configuration (two segments)
-                ctrl_reg_rd_data_reg[7:4]   <= 1;                   // default segment
-                ctrl_reg_rd_data_reg[11:8]  <= 0;                   // fallback segment
-                ctrl_reg_rd_data_reg[31:12] <= 32'h01002000 >> 12;  // first segment size (Alveo default)
+                ctrl_reg_rd_data_reg[3:0]   <= FLASH_SEG_COUNT;     // configuration
+                ctrl_reg_rd_data_reg[7:4]   <= FLASH_SEG_DEFAULT;   // default segment
+                ctrl_reg_rd_data_reg[11:8]  <= FLASH_SEG_FALLBACK;  // fallback segment
+                ctrl_reg_rd_data_reg[31:12] <= FLASH_SEG0_SIZE;     // first segment size
             end
             RBB+8'h30: begin
                 // SPI flash ctrl: control 0
diff --git a/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/test_fpga_core.v b/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/test_fpga_core.v
index a095dde1f..b89aa8fbc 100644
--- a/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/test_fpga_core.v
+++ b/fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/test_fpga_core.v
@@ -47,6 +47,10 @@ module test_fpga_core #
     parameter QSFP_CNT = 2,
     parameter CH_CNT = QSFP_CNT*4,
     parameter CMS_ENABLE = 1,
+    parameter FLASH_SEG_COUNT = 2,
+    parameter FLASH_SEG_DEFAULT = 1,
+    parameter FLASH_SEG_FALLBACK = 0,
+    parameter FLASH_SEG0_SIZE = 32'h01002000,
 
     // Structural configuration
     parameter IF_COUNT = 2,
@@ -635,6 +639,10 @@ fpga_core #(
     .QSFP_CNT(QSFP_CNT),
     .CH_CNT(CH_CNT),
     .CMS_ENABLE(CMS_ENABLE),
+    .FLASH_SEG_COUNT(2),
+    .FLASH_SEG_DEFAULT(1),
+    .FLASH_SEG_FALLBACK(0),
+    .FLASH_SEG0_SIZE(32'h01002000),
 
     // Structural configuration
     .IF_COUNT(IF_COUNT),
diff --git a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au200.v b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au200.v
index 31bca4850..3342746b4 100644
--- a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au200.v
+++ b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au200.v
@@ -2026,6 +2026,10 @@ fpga_core #(
     .CH_CNT(CH_CNT),
     .CMS_ENABLE(CMS_ENABLE),
     .TDMA_BER_ENABLE(TDMA_BER_ENABLE),
+    .FLASH_SEG_COUNT(2),
+    .FLASH_SEG_DEFAULT(1),
+    .FLASH_SEG_FALLBACK(0),
+    .FLASH_SEG0_SIZE(32'h01002000),
 
     // Structural configuration
     .IF_COUNT(IF_COUNT),
diff --git a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au280.v b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au280.v
index 0af7c171f..acf1c465d 100644
--- a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au280.v
+++ b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au280.v
@@ -1826,6 +1826,10 @@ fpga_core #(
     .QSFP_CNT(QSFP_CNT),
     .CH_CNT(CH_CNT),
     .TDMA_BER_ENABLE(TDMA_BER_ENABLE),
+    .FLASH_SEG_COUNT(2),
+    .FLASH_SEG_DEFAULT(1),
+    .FLASH_SEG_FALLBACK(0),
+    .FLASH_SEG0_SIZE(32'h01002000),
 
     // Structural configuration
     .IF_COUNT(IF_COUNT),
diff --git a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au50.v b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au50.v
index 4a7f6f304..9f832b5c7 100644
--- a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au50.v
+++ b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au50.v
@@ -1296,6 +1296,10 @@ fpga_core #(
     .QSFP_CNT(QSFP_CNT),
     .CH_CNT(CH_CNT),
     .TDMA_BER_ENABLE(TDMA_BER_ENABLE),
+    .FLASH_SEG_COUNT(2),
+    .FLASH_SEG_DEFAULT(1),
+    .FLASH_SEG_FALLBACK(0),
+    .FLASH_SEG0_SIZE(32'h01002000),
 
     // Structural configuration
     .IF_COUNT(IF_COUNT),
diff --git a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au55.v b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au55.v
index 40bac5810..f4296bb25 100644
--- a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au55.v
+++ b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au55.v
@@ -1453,6 +1453,10 @@ fpga_core #(
     .QSFP_CNT(QSFP_CNT),
     .CH_CNT(CH_CNT),
     .TDMA_BER_ENABLE(TDMA_BER_ENABLE),
+    .FLASH_SEG_COUNT(2),
+    .FLASH_SEG_DEFAULT(1),
+    .FLASH_SEG_FALLBACK(0),
+    .FLASH_SEG0_SIZE(32'h01002000),
 
     // Structural configuration
     .IF_COUNT(IF_COUNT),
diff --git a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_core.v
index 1ebb480cb..c11bdf06b 100644
--- a/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_core.v
+++ b/fpga/mqnic/Alveo/fpga_25g/rtl/fpga_core.v
@@ -29,6 +29,10 @@ module fpga_core #
     parameter CH_CNT = QSFP_CNT*4,
     parameter CMS_ENABLE = 1,
     parameter TDMA_BER_ENABLE = 0,
+    parameter FLASH_SEG_COUNT = 2,
+    parameter FLASH_SEG_DEFAULT = 1,
+    parameter FLASH_SEG_FALLBACK = 0,
+    parameter FLASH_SEG0_SIZE = 32'h01002000,
 
     // Structural configuration
     parameter IF_COUNT = 2,
@@ -723,10 +727,10 @@ always @(posedge clk_250mhz) begin
             RBB+8'h28: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h40;       // SPI flash ctrl: Next header
             RBB+8'h2C: begin
                 // SPI flash ctrl: format
-                ctrl_reg_rd_data_reg[3:0]   <= 2;                   // configuration (two segments)
-                ctrl_reg_rd_data_reg[7:4]   <= 1;                   // default segment
-                ctrl_reg_rd_data_reg[11:8]  <= 0;                   // fallback segment
-                ctrl_reg_rd_data_reg[31:12] <= 32'h01002000 >> 12;  // first segment size (Alveo default)
+                ctrl_reg_rd_data_reg[3:0]   <= FLASH_SEG_COUNT;     // configuration
+                ctrl_reg_rd_data_reg[7:4]   <= FLASH_SEG_DEFAULT;   // default segment
+                ctrl_reg_rd_data_reg[11:8]  <= FLASH_SEG_FALLBACK;  // fallback segment
+                ctrl_reg_rd_data_reg[31:12] <= FLASH_SEG0_SIZE;     // first segment size
             end
             RBB+8'h30: begin
                 // SPI flash ctrl: control 0
diff --git a/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.v b/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.v
index e8717db3c..5c3887e29 100644
--- a/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.v
+++ b/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.v
@@ -48,6 +48,10 @@ module test_fpga_core #
     parameter CH_CNT = QSFP_CNT*4,
     parameter CMS_ENABLE = 1,
     parameter TDMA_BER_ENABLE = 0,
+    parameter FLASH_SEG_COUNT = 2,
+    parameter FLASH_SEG_DEFAULT = 1,
+    parameter FLASH_SEG_FALLBACK = 0,
+    parameter FLASH_SEG0_SIZE = 32'h01002000,
 
     // Structural configuration
     parameter IF_COUNT = 2,
@@ -532,6 +536,10 @@ fpga_core #(
     .CH_CNT(CH_CNT),
     .CMS_ENABLE(CMS_ENABLE),
     .TDMA_BER_ENABLE(TDMA_BER_ENABLE),
+    .FLASH_SEG_COUNT(2),
+    .FLASH_SEG_DEFAULT(1),
+    .FLASH_SEG_FALLBACK(0),
+    .FLASH_SEG0_SIZE(32'h01002000),
 
     // Structural configuration
     .IF_COUNT(IF_COUNT),