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fpga/mqnic/Alveo: Add parameters for flash config

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-11-13 12:39:20 -08:00
parent b2f853cae7
commit 4f60691485
12 changed files with 64 additions and 8 deletions
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4
fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au200.v
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@ -1991,6 +1991,10 @@ fpga_core #(
.QSFP_CNT(QSFP_CNT), .QSFP_CNT(QSFP_CNT),
.CH_CNT(QSFP_CNT*4), .CH_CNT(QSFP_CNT*4),
.CMS_ENABLE(CMS_ENABLE), .CMS_ENABLE(CMS_ENABLE),
.FLASH_SEG_COUNT(2),
.FLASH_SEG_DEFAULT(1),
.FLASH_SEG_FALLBACK(0),
.FLASH_SEG0_SIZE(32'h01002000),
// Structural configuration // Structural configuration
.IF_COUNT(IF_COUNT), .IF_COUNT(IF_COUNT),

4
fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au280.v
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@ -1789,6 +1789,10 @@ fpga_core #(
.QSFP_CNT(QSFP_CNT), .QSFP_CNT(QSFP_CNT),
.CH_CNT(QSFP_CNT*4), .CH_CNT(QSFP_CNT*4),
.CMS_ENABLE(CMS_ENABLE), .CMS_ENABLE(CMS_ENABLE),
.FLASH_SEG_COUNT(2),
.FLASH_SEG_DEFAULT(1),
.FLASH_SEG_FALLBACK(0),
.FLASH_SEG0_SIZE(32'h01002000),
// Structural configuration // Structural configuration
.IF_COUNT(IF_COUNT), .IF_COUNT(IF_COUNT),

4
fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au50.v
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@ -1288,6 +1288,10 @@ fpga_core #(
.QSFP_CNT(QSFP_CNT), .QSFP_CNT(QSFP_CNT),
.CH_CNT(QSFP_CNT*4), .CH_CNT(QSFP_CNT*4),
.CMS_ENABLE(CMS_ENABLE), .CMS_ENABLE(CMS_ENABLE),
.FLASH_SEG_COUNT(2),
.FLASH_SEG_DEFAULT(1),
.FLASH_SEG_FALLBACK(0),
.FLASH_SEG0_SIZE(32'h01002000),
// Structural configuration // Structural configuration
.IF_COUNT(IF_COUNT), .IF_COUNT(IF_COUNT),

4
fpga/mqnic/Alveo/fpga_100g/rtl/fpga_au55.v
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@ -1415,6 +1415,10 @@ fpga_core #(
.QSFP_CNT(QSFP_CNT), .QSFP_CNT(QSFP_CNT),
.CH_CNT(QSFP_CNT*4), .CH_CNT(QSFP_CNT*4),
.CMS_ENABLE(CMS_ENABLE), .CMS_ENABLE(CMS_ENABLE),
.FLASH_SEG_COUNT(2),
.FLASH_SEG_DEFAULT(1),
.FLASH_SEG_FALLBACK(0),
.FLASH_SEG0_SIZE(32'h01002000),
// Structural configuration // Structural configuration
.IF_COUNT(IF_COUNT), .IF_COUNT(IF_COUNT),

12
fpga/mqnic/Alveo/fpga_100g/rtl/fpga_core.v
View File

@ -28,6 +28,10 @@ module fpga_core #
parameter QSFP_CNT = 2, parameter QSFP_CNT = 2,
parameter CH_CNT = QSFP_CNT*4, parameter CH_CNT = QSFP_CNT*4,
parameter CMS_ENABLE = 1, parameter CMS_ENABLE = 1,
parameter FLASH_SEG_COUNT = 2,
parameter FLASH_SEG_DEFAULT = 1,
parameter FLASH_SEG_FALLBACK = 0,
parameter FLASH_SEG0_SIZE = 32'h01002000,
// Structural configuration // Structural configuration
parameter IF_COUNT = 2, parameter IF_COUNT = 2,
@ -722,10 +726,10 @@ always @(posedge clk_250mhz) begin
RBB+8'h28: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h40; // SPI flash ctrl: Next header RBB+8'h28: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h40; // SPI flash ctrl: Next header
RBB+8'h2C: begin RBB+8'h2C: begin
// SPI flash ctrl: format // SPI flash ctrl: format
ctrl_reg_rd_data_reg[3:0] <= 2; // configuration (two segments) ctrl_reg_rd_data_reg[3:0] <= FLASH_SEG_COUNT; // configuration
ctrl_reg_rd_data_reg[7:4] <= 1; // default segment ctrl_reg_rd_data_reg[7:4] <= FLASH_SEG_DEFAULT; // default segment
ctrl_reg_rd_data_reg[11:8] <= 0; // fallback segment ctrl_reg_rd_data_reg[11:8] <= FLASH_SEG_FALLBACK; // fallback segment
ctrl_reg_rd_data_reg[31:12] <= 32'h01002000 >> 12; // first segment size (Alveo default) ctrl_reg_rd_data_reg[31:12] <= FLASH_SEG0_SIZE; // first segment size
end end
RBB+8'h30: begin RBB+8'h30: begin
// SPI flash ctrl: control 0 // SPI flash ctrl: control 0

8
fpga/mqnic/Alveo/fpga_100g/tb/fpga_core/test_fpga_core.v
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@ -47,6 +47,10 @@ module test_fpga_core #
parameter QSFP_CNT = 2, parameter QSFP_CNT = 2,
parameter CH_CNT = QSFP_CNT*4, parameter CH_CNT = QSFP_CNT*4,
parameter CMS_ENABLE = 1, parameter CMS_ENABLE = 1,
parameter FLASH_SEG_COUNT = 2,
parameter FLASH_SEG_DEFAULT = 1,
parameter FLASH_SEG_FALLBACK = 0,
parameter FLASH_SEG0_SIZE = 32'h01002000,
// Structural configuration // Structural configuration
parameter IF_COUNT = 2, parameter IF_COUNT = 2,
@ -635,6 +639,10 @@ fpga_core #(
.QSFP_CNT(QSFP_CNT), .QSFP_CNT(QSFP_CNT),
.CH_CNT(CH_CNT), .CH_CNT(CH_CNT),
.CMS_ENABLE(CMS_ENABLE), .CMS_ENABLE(CMS_ENABLE),
.FLASH_SEG_COUNT(2),
.FLASH_SEG_DEFAULT(1),
.FLASH_SEG_FALLBACK(0),
.FLASH_SEG0_SIZE(32'h01002000),
// Structural configuration // Structural configuration
.IF_COUNT(IF_COUNT), .IF_COUNT(IF_COUNT),

4
fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au200.v
View File

@ -2026,6 +2026,10 @@ fpga_core #(
.CH_CNT(CH_CNT), .CH_CNT(CH_CNT),
.CMS_ENABLE(CMS_ENABLE), .CMS_ENABLE(CMS_ENABLE),
.TDMA_BER_ENABLE(TDMA_BER_ENABLE), .TDMA_BER_ENABLE(TDMA_BER_ENABLE),
.FLASH_SEG_COUNT(2),
.FLASH_SEG_DEFAULT(1),
.FLASH_SEG_FALLBACK(0),
.FLASH_SEG0_SIZE(32'h01002000),
// Structural configuration // Structural configuration
.IF_COUNT(IF_COUNT), .IF_COUNT(IF_COUNT),

4
fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au280.v
View File

@ -1826,6 +1826,10 @@ fpga_core #(
.QSFP_CNT(QSFP_CNT), .QSFP_CNT(QSFP_CNT),
.CH_CNT(CH_CNT), .CH_CNT(CH_CNT),
.TDMA_BER_ENABLE(TDMA_BER_ENABLE), .TDMA_BER_ENABLE(TDMA_BER_ENABLE),
.FLASH_SEG_COUNT(2),
.FLASH_SEG_DEFAULT(1),
.FLASH_SEG_FALLBACK(0),
.FLASH_SEG0_SIZE(32'h01002000),
// Structural configuration // Structural configuration
.IF_COUNT(IF_COUNT), .IF_COUNT(IF_COUNT),

4
fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au50.v
View File

@ -1296,6 +1296,10 @@ fpga_core #(
.QSFP_CNT(QSFP_CNT), .QSFP_CNT(QSFP_CNT),
.CH_CNT(CH_CNT), .CH_CNT(CH_CNT),
.TDMA_BER_ENABLE(TDMA_BER_ENABLE), .TDMA_BER_ENABLE(TDMA_BER_ENABLE),
.FLASH_SEG_COUNT(2),
.FLASH_SEG_DEFAULT(1),
.FLASH_SEG_FALLBACK(0),
.FLASH_SEG0_SIZE(32'h01002000),
// Structural configuration // Structural configuration
.IF_COUNT(IF_COUNT), .IF_COUNT(IF_COUNT),

4
fpga/mqnic/Alveo/fpga_25g/rtl/fpga_au55.v
View File

@ -1453,6 +1453,10 @@ fpga_core #(
.QSFP_CNT(QSFP_CNT), .QSFP_CNT(QSFP_CNT),
.CH_CNT(CH_CNT), .CH_CNT(CH_CNT),
.TDMA_BER_ENABLE(TDMA_BER_ENABLE), .TDMA_BER_ENABLE(TDMA_BER_ENABLE),
.FLASH_SEG_COUNT(2),
.FLASH_SEG_DEFAULT(1),
.FLASH_SEG_FALLBACK(0),
.FLASH_SEG0_SIZE(32'h01002000),
// Structural configuration // Structural configuration
.IF_COUNT(IF_COUNT), .IF_COUNT(IF_COUNT),

12
fpga/mqnic/Alveo/fpga_25g/rtl/fpga_core.v
View File

@ -29,6 +29,10 @@ module fpga_core #
parameter CH_CNT = QSFP_CNT*4, parameter CH_CNT = QSFP_CNT*4,
parameter CMS_ENABLE = 1, parameter CMS_ENABLE = 1,
parameter TDMA_BER_ENABLE = 0, parameter TDMA_BER_ENABLE = 0,
parameter FLASH_SEG_COUNT = 2,
parameter FLASH_SEG_DEFAULT = 1,
parameter FLASH_SEG_FALLBACK = 0,
parameter FLASH_SEG0_SIZE = 32'h01002000,
// Structural configuration // Structural configuration
parameter IF_COUNT = 2, parameter IF_COUNT = 2,
@ -723,10 +727,10 @@ always @(posedge clk_250mhz) begin
RBB+8'h28: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h40; // SPI flash ctrl: Next header RBB+8'h28: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h40; // SPI flash ctrl: Next header
RBB+8'h2C: begin RBB+8'h2C: begin
// SPI flash ctrl: format // SPI flash ctrl: format
ctrl_reg_rd_data_reg[3:0] <= 2; // configuration (two segments) ctrl_reg_rd_data_reg[3:0] <= FLASH_SEG_COUNT; // configuration
ctrl_reg_rd_data_reg[7:4] <= 1; // default segment ctrl_reg_rd_data_reg[7:4] <= FLASH_SEG_DEFAULT; // default segment
ctrl_reg_rd_data_reg[11:8] <= 0; // fallback segment ctrl_reg_rd_data_reg[11:8] <= FLASH_SEG_FALLBACK; // fallback segment
ctrl_reg_rd_data_reg[31:12] <= 32'h01002000 >> 12; // first segment size (Alveo default) ctrl_reg_rd_data_reg[31:12] <= FLASH_SEG0_SIZE; // first segment size
end end
RBB+8'h30: begin RBB+8'h30: begin
// SPI flash ctrl: control 0 // SPI flash ctrl: control 0

8
fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.v
View File

@ -48,6 +48,10 @@ module test_fpga_core #
parameter CH_CNT = QSFP_CNT*4, parameter CH_CNT = QSFP_CNT*4,
parameter CMS_ENABLE = 1, parameter CMS_ENABLE = 1,
parameter TDMA_BER_ENABLE = 0, parameter TDMA_BER_ENABLE = 0,
parameter FLASH_SEG_COUNT = 2,
parameter FLASH_SEG_DEFAULT = 1,
parameter FLASH_SEG_FALLBACK = 0,
parameter FLASH_SEG0_SIZE = 32'h01002000,
// Structural configuration // Structural configuration
parameter IF_COUNT = 2, parameter IF_COUNT = 2,
@ -532,6 +536,10 @@ fpga_core #(
.CH_CNT(CH_CNT), .CH_CNT(CH_CNT),
.CMS_ENABLE(CMS_ENABLE), .CMS_ENABLE(CMS_ENABLE),
.TDMA_BER_ENABLE(TDMA_BER_ENABLE), .TDMA_BER_ENABLE(TDMA_BER_ENABLE),
.FLASH_SEG_COUNT(2),
.FLASH_SEG_DEFAULT(1),
.FLASH_SEG_FALLBACK(0),
.FLASH_SEG0_SIZE(32'h01002000),
// Structural configuration // Structural configuration
.IF_COUNT(IF_COUNT), .IF_COUNT(IF_COUNT),