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fpga/mqnic/DK_DEV_AGF014EA: Add virtual I2C switch to control modsel pins

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-06-11 00:37:50 -07:00
parent a3e7cc4c77
commit 5099e4a3d5
16 changed files with 111 additions and 47 deletions
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2
docs/source/devicelist.rst
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@ -86,7 +86,7 @@ This section details PCIe form-factor targets, which interface with a separate h
DK-DEV-1SMX-H-A N :sup:`3` N :sup:`7` N
DK-DEV-1SMC-H-A N :sup:`3` N :sup:`7` N
DK-DEV-1SDX-P-A Y N :sup:`3` N :sup:`10`
DK-DEV-AGF014EA N :sup:`3` N :sup:`3` N
DK-DEV-AGF014EA Y N :sup:`3` N
DE10-Agilex Y N :sup:`7` N :sup:`10`
Alveo U50 N :sup:`4` Y Y
Alveo U200 Y Y Y

1
fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga/Makefile
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@ -56,6 +56,7 @@ SYN_FILES += rtl/common/tdma_scheduler.v
SYN_FILES += rtl/common/avst2axis.v
SYN_FILES += rtl/common/axis2avst.v
SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += rtl/common/i2c_single_reg.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v

1
fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_24AR0/Makefile
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@ -56,6 +56,7 @@ SYN_FILES += rtl/common/tdma_scheduler.v
SYN_FILES += rtl/common/avst2axis.v
SYN_FILES += rtl/common/axis2avst.v
SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += rtl/common/i2c_single_reg.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v

1
fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_app_dma_bench/Makefile
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@ -56,6 +56,7 @@ SYN_FILES += rtl/common/tdma_scheduler.v
SYN_FILES += rtl/common/avst2axis.v
SYN_FILES += rtl/common/axis2avst.v
SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += rtl/common/i2c_single_reg.v
SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
SYN_FILES += app/dma_bench/rtl/dma_bench.v
SYN_FILES += lib/eth/rtl/lfsr.v

1
fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_app_dma_bench_24AR0/Makefile
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@ -56,6 +56,7 @@ SYN_FILES += rtl/common/tdma_scheduler.v
SYN_FILES += rtl/common/avst2axis.v
SYN_FILES += rtl/common/axis2avst.v
SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += rtl/common/i2c_single_reg.v
SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
SYN_FILES += app/dma_bench/rtl/dma_bench.v
SYN_FILES += lib/eth/rtl/lfsr.v

65
fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga_core.v
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@ -434,22 +434,25 @@ reg ctrl_reg_wr_ack_reg = 1'b0;
reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}};
reg ctrl_reg_rd_ack_reg = 1'b0;
wire qsfpdd_i2c_select_scl_o;
wire qsfpdd_i2c_select_sda_o;
wire [7:0] qsfpdd_i2c_select;
wire qsfpdd_i2c_scl_i_int = qsfpdd_i2c_scl_i & qsfpdd_i2c_scl_o;
wire qsfpdd_i2c_sda_i_int = qsfpdd_i2c_sda_i & qsfpdd_i2c_sda_o;
reg fpga_i2c_scl_o_reg = 1'b1;
reg fpga_i2c_sda_o_reg = 1'b1;
reg qsfpdd0_reset_reg = 1'b0;
reg qsfpdd0_modsel_reg = 1'b0;
reg qsfpdd0_lpmode_reg = 1'b0;
reg qsfpdd1_reset_reg = 1'b0;
reg qsfpdd1_modsel_reg = 1'b0;
reg qsfpdd1_lpmode_reg = 1'b0;
reg qsfpdd_i2c_scl_o_reg = 1'b1;
reg qsfpdd_i2c_sda_o_reg = 1'b1;
// reg fpga_boot_reg = 1'b0;
assign ctrl_reg_wr_wait = 1'b0;
assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg;
assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg;
@ -457,24 +460,48 @@ assign ctrl_reg_rd_wait = 1'b0;
assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg;
assign fpga_i2c_scl_o = fpga_i2c_scl_o_reg;
assign fpga_i2c_scl_t = fpga_i2c_scl_o_reg;
assign fpga_i2c_scl_t = fpga_i2c_scl_o;
assign fpga_i2c_sda_o = fpga_i2c_sda_o_reg;
assign fpga_i2c_sda_t = fpga_i2c_sda_o_reg;
assign fpga_i2c_sda_t = fpga_i2c_sda_o;
assign qsfpdd0_lpmode = qsfpdd0_lpmode_reg;
assign qsfpdd0_modsel_l = !qsfpdd0_modsel_reg;
assign qsfpdd0_modsel_l = !qsfpdd_i2c_select[0];
assign qsfpdd0_reset_l = !qsfpdd0_reset_reg;
assign qsfpdd1_lpmode = qsfpdd1_lpmode_reg;
assign qsfpdd1_modsel_l = !qsfpdd1_modsel_reg;
assign qsfpdd1_modsel_l = !qsfpdd_i2c_select[1];
assign qsfpdd1_reset_l = !qsfpdd1_reset_reg;
assign qsfpdd_i2c_scl_o = qsfpdd_i2c_scl_o_reg;
assign qsfpdd_i2c_scl_t = qsfpdd_i2c_scl_o_reg;
assign qsfpdd_i2c_sda_o = qsfpdd_i2c_sda_o_reg;
assign qsfpdd_i2c_sda_t = qsfpdd_i2c_sda_o_reg;
assign qsfpdd_i2c_scl_o = qsfpdd_i2c_scl_o_reg & qsfpdd_i2c_select_scl_o;
assign qsfpdd_i2c_scl_t = qsfpdd_i2c_scl_o;
assign qsfpdd_i2c_sda_o = qsfpdd_i2c_sda_o_reg & qsfpdd_i2c_select_sda_o;
assign qsfpdd_i2c_sda_t = qsfpdd_i2c_sda_o;
// assign fpga_boot = fpga_boot_reg;
i2c_single_reg #(
.FILTER_LEN(4),
.DEV_ADDR(7'h74)
)
qsfpdd_i2c_select_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* I2C interface
*/
.scl_i(qsfpdd_i2c_scl_i_int),
.scl_o(qsfpdd_i2c_select_scl_o),
.scl_t(),
.sda_i(qsfpdd_i2c_sda_i_int),
.sda_o(qsfpdd_i2c_select_sda_o),
.sda_t(),
/*
* Data register
*/
.data_in(8'd0),
.data_latch(1'b0),
.data_out(qsfpdd_i2c_select)
);
always @(posedge clk_250mhz) begin
ctrl_reg_wr_ack_reg <= 1'b0;
@ -504,10 +531,6 @@ always @(posedge clk_250mhz) begin
if (ctrl_reg_wr_strb[1]) begin
qsfpdd_i2c_sda_o_reg <= ctrl_reg_wr_data[9];
end
if (ctrl_reg_wr_strb[2]) begin
qsfpdd0_modsel_reg <= ctrl_reg_wr_data[16];
qsfpdd1_modsel_reg <= ctrl_reg_wr_data[17];
end
end
// XCVR GPIO
RBB+8'h2C: begin
@ -546,12 +569,10 @@ always @(posedge clk_250mhz) begin
RBB+8'h18: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h20; // I2C ctrl: Next header
RBB+8'h1C: begin
// I2C ctrl: control
ctrl_reg_rd_data_reg[0] <= qsfpdd_i2c_scl_i;
ctrl_reg_rd_data_reg[0] <= qsfpdd_i2c_scl_i_int;
ctrl_reg_rd_data_reg[1] <= qsfpdd_i2c_scl_o_reg;
ctrl_reg_rd_data_reg[8] <= qsfpdd_i2c_sda_i;
ctrl_reg_rd_data_reg[8] <= qsfpdd_i2c_sda_i_int;
ctrl_reg_rd_data_reg[9] <= qsfpdd_i2c_sda_o_reg;
ctrl_reg_rd_data_reg[16] <= qsfpdd0_modsel_reg;
ctrl_reg_rd_data_reg[17] <= qsfpdd1_modsel_reg;
end
// XCVR GPIO
RBB+8'h20: ctrl_reg_rd_data_reg <= 32'h0000C101; // XCVR GPIO: Type
@ -580,11 +601,9 @@ always @(posedge clk_250mhz) begin
fpga_i2c_sda_o_reg <= 1'b1;
qsfpdd0_reset_reg <= 1'b0;
qsfpdd0_modsel_reg <= 1'b0;
qsfpdd0_lpmode_reg <= 1'b0;
qsfpdd1_reset_reg <= 1'b0;
qsfpdd1_modsel_reg <= 1'b0;
qsfpdd1_lpmode_reg <= 1'b0;
qsfpdd_i2c_scl_o_reg <= 1'b1;

1
fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/Makefile
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@ -84,6 +84,7 @@ VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v
VERILOG_SOURCES += ../../rtl/common/tdma_scheduler.v
VERILOG_SOURCES += ../../rtl/common/tdma_ber.v
VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v
VERILOG_SOURCES += ../../rtl/common/i2c_single_reg.v
VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v
VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v
VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v

1
fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.py
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@ -679,6 +679,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "tdma_scheduler.v"),
os.path.join(rtl_dir, "common", "tdma_ber.v"),
os.path.join(rtl_dir, "common", "tdma_ber_ch.v"),
os.path.join(rtl_dir, "common", "i2c_single_reg.v"),
os.path.join(eth_rtl_dir, "eth_mac_10g.v"),
os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"),
os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"),

1
fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga/Makefile
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@ -56,6 +56,7 @@ SYN_FILES += rtl/common/tdma_scheduler.v
SYN_FILES += rtl/common/avst2axis.v
SYN_FILES += rtl/common/axis2avst.v
SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += rtl/common/i2c_single_reg.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v

1
fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_10g/Makefile
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@ -56,6 +56,7 @@ SYN_FILES += rtl/common/tdma_scheduler.v
SYN_FILES += rtl/common/avst2axis.v
SYN_FILES += rtl/common/axis2avst.v
SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += rtl/common/i2c_single_reg.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v

1
fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_10g_24AR0/Makefile
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@ -56,6 +56,7 @@ SYN_FILES += rtl/common/tdma_scheduler.v
SYN_FILES += rtl/common/avst2axis.v
SYN_FILES += rtl/common/axis2avst.v
SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += rtl/common/i2c_single_reg.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v

1
fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/fpga_24AR0/Makefile
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@ -56,6 +56,7 @@ SYN_FILES += rtl/common/tdma_scheduler.v
SYN_FILES += rtl/common/avst2axis.v
SYN_FILES += rtl/common/axis2avst.v
SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += rtl/common/i2c_single_reg.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v

65
fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/rtl/fpga_core.v
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@ -868,22 +868,25 @@ reg ctrl_reg_wr_ack_reg = 1'b0;
reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}};
reg ctrl_reg_rd_ack_reg = 1'b0;
wire qsfpdd_i2c_select_scl_o;
wire qsfpdd_i2c_select_sda_o;
wire [7:0] qsfpdd_i2c_select;
wire qsfpdd_i2c_scl_i_int = qsfpdd_i2c_scl_i & qsfpdd_i2c_scl_o;
wire qsfpdd_i2c_sda_i_int = qsfpdd_i2c_sda_i & qsfpdd_i2c_sda_o;
reg fpga_i2c_scl_o_reg = 1'b1;
reg fpga_i2c_sda_o_reg = 1'b1;
reg qsfpdd0_reset_reg = 1'b0;
reg qsfpdd0_modsel_reg = 1'b0;
reg qsfpdd0_lpmode_reg = 1'b0;
reg qsfpdd1_reset_reg = 1'b0;
reg qsfpdd1_modsel_reg = 1'b0;
reg qsfpdd1_lpmode_reg = 1'b0;
reg qsfpdd_i2c_scl_o_reg = 1'b1;
reg qsfpdd_i2c_sda_o_reg = 1'b1;
// reg fpga_boot_reg = 1'b0;
assign ctrl_reg_wr_wait = 1'b0;
assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg;
assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg;
@ -891,24 +894,48 @@ assign ctrl_reg_rd_wait = 1'b0;
assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg;
assign fpga_i2c_scl_o = fpga_i2c_scl_o_reg;
assign fpga_i2c_scl_t = fpga_i2c_scl_o_reg;
assign fpga_i2c_scl_t = fpga_i2c_scl_o;
assign fpga_i2c_sda_o = fpga_i2c_sda_o_reg;
assign fpga_i2c_sda_t = fpga_i2c_sda_o_reg;
assign fpga_i2c_sda_t = fpga_i2c_sda_o;
assign qsfpdd0_lpmode = qsfpdd0_lpmode_reg;
assign qsfpdd0_modsel_l = !qsfpdd0_modsel_reg;
assign qsfpdd0_modsel_l = !qsfpdd_i2c_select[0];
assign qsfpdd0_reset_l = !qsfpdd0_reset_reg;
assign qsfpdd1_lpmode = qsfpdd1_lpmode_reg;
assign qsfpdd1_modsel_l = !qsfpdd1_modsel_reg;
assign qsfpdd1_modsel_l = !qsfpdd_i2c_select[1];
assign qsfpdd1_reset_l = !qsfpdd1_reset_reg;
assign qsfpdd_i2c_scl_o = qsfpdd_i2c_scl_o_reg;
assign qsfpdd_i2c_scl_t = qsfpdd_i2c_scl_o_reg;
assign qsfpdd_i2c_sda_o = qsfpdd_i2c_sda_o_reg;
assign qsfpdd_i2c_sda_t = qsfpdd_i2c_sda_o_reg;
assign qsfpdd_i2c_scl_o = qsfpdd_i2c_scl_o_reg & qsfpdd_i2c_select_scl_o;
assign qsfpdd_i2c_scl_t = qsfpdd_i2c_scl_o;
assign qsfpdd_i2c_sda_o = qsfpdd_i2c_sda_o_reg & qsfpdd_i2c_select_sda_o;
assign qsfpdd_i2c_sda_t = qsfpdd_i2c_sda_o;
// assign fpga_boot = fpga_boot_reg;
i2c_single_reg #(
.FILTER_LEN(4),
.DEV_ADDR(7'h74)
)
qsfpdd_i2c_select_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* I2C interface
*/
.scl_i(qsfpdd_i2c_scl_i_int),
.scl_o(qsfpdd_i2c_select_scl_o),
.scl_t(),
.sda_i(qsfpdd_i2c_sda_i_int),
.sda_o(qsfpdd_i2c_select_sda_o),
.sda_t(),
/*
* Data register
*/
.data_in(8'd0),
.data_latch(1'b0),
.data_out(qsfpdd_i2c_select)
);
always @(posedge clk_250mhz) begin
ctrl_reg_wr_ack_reg <= 1'b0;
@ -938,10 +965,6 @@ always @(posedge clk_250mhz) begin
if (ctrl_reg_wr_strb[1]) begin
qsfpdd_i2c_sda_o_reg <= ctrl_reg_wr_data[9];
end
if (ctrl_reg_wr_strb[2]) begin
qsfpdd0_modsel_reg <= ctrl_reg_wr_data[16];
qsfpdd1_modsel_reg <= ctrl_reg_wr_data[17];
end
end
// XCVR GPIO
RBB+8'h2C: begin
@ -980,12 +1003,10 @@ always @(posedge clk_250mhz) begin
RBB+8'h18: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h20; // I2C ctrl: Next header
RBB+8'h1C: begin
// I2C ctrl: control
ctrl_reg_rd_data_reg[0] <= qsfpdd_i2c_scl_i;
ctrl_reg_rd_data_reg[0] <= qsfpdd_i2c_scl_i_int;
ctrl_reg_rd_data_reg[1] <= qsfpdd_i2c_scl_o_reg;
ctrl_reg_rd_data_reg[8] <= qsfpdd_i2c_sda_i;
ctrl_reg_rd_data_reg[8] <= qsfpdd_i2c_sda_i_int;
ctrl_reg_rd_data_reg[9] <= qsfpdd_i2c_sda_o_reg;
ctrl_reg_rd_data_reg[16] <= qsfpdd0_modsel_reg;
ctrl_reg_rd_data_reg[17] <= qsfpdd1_modsel_reg;
end
// XCVR GPIO
RBB+8'h20: ctrl_reg_rd_data_reg <= 32'h0000C101; // XCVR GPIO: Type
@ -1014,11 +1035,9 @@ always @(posedge clk_250mhz) begin
fpga_i2c_sda_o_reg <= 1'b1;
qsfpdd0_reset_reg <= 1'b0;
qsfpdd0_modsel_reg <= 1'b0;
qsfpdd0_lpmode_reg <= 1'b0;
qsfpdd1_reset_reg <= 1'b0;
qsfpdd1_modsel_reg <= 1'b0;
qsfpdd1_lpmode_reg <= 1'b0;
qsfpdd_i2c_scl_o_reg <= 1'b1;

1
fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/tb/fpga_core/Makefile
View File

@ -84,6 +84,7 @@ VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v
VERILOG_SOURCES += ../../rtl/common/tdma_scheduler.v
VERILOG_SOURCES += ../../rtl/common/tdma_ber.v
VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v
VERILOG_SOURCES += ../../rtl/common/i2c_single_reg.v
VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v
VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v
VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v

1
fpga/mqnic/DK_DEV_AGF014EA/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -999,6 +999,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "tdma_scheduler.v"),
os.path.join(rtl_dir, "common", "tdma_ber.v"),
os.path.join(rtl_dir, "common", "tdma_ber_ch.v"),
os.path.join(rtl_dir, "common", "i2c_single_reg.v"),
os.path.join(eth_rtl_dir, "eth_mac_10g.v"),
os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"),
os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"),

14
modules/mqnic/mqnic_board.c
View File

@ -471,6 +471,20 @@ static int mqnic_generic_board_init(struct mqnic_dev *mqnic)
// U23 I2C EEPROM
mqnic->eeprom_i2c_client = create_i2c_client(adapter, "24c64", 0x50);
// I2C adapter
adapter = mqnic_i2c_adapter_create(mqnic, 1);
// Virtual I2C MUX
mux = create_i2c_client(adapter, "pca9543", 0x74);
// QSFPDD0
mqnic->mod_i2c_client[0] = create_i2c_client(get_i2c_mux_channel(mux, 0), "24c02", 0x50);
// QSFPDD1
mqnic->mod_i2c_client[1] = create_i2c_client(get_i2c_mux_channel(mux, 1), "24c02", 0x50);
mqnic->mod_i2c_client_count = 2;
break;
case MQNIC_BOARD_ID_DE10_AGILEX: