diff --git a/tb/test_axis_async_fifo.py b/tb/test_axis_async_fifo.py
index 68090aaa3..817887c1f 100755
--- a/tb/test_axis_async_fifo.py
+++ b/tb/test_axis_async_fifo.py
@@ -401,6 +401,90 @@ def bench():
 
         yield delay(100)
 
+        yield input_clk.posedge
+        print("test 8: initial sink pause")
+        current_test.next = 8
+
+        test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+        sink_pause.next = 0
+
+        yield output_axis_tlast.posedge
+        yield output_clk.posedge
+        yield output_clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame
+
+        yield delay(100)
+
+        yield input_clk.posedge
+        print("test 9: initial sink pause, input reset")
+        current_test.next = 9
+
+        test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+
+        input_rst.next = 1
+        yield input_clk.posedge
+        input_rst.next = 0
+
+        sink_pause.next = 0
+
+        yield delay(100)
+
+        yield output_clk.posedge
+        yield output_clk.posedge
+        yield output_clk.posedge
+
+        assert sink_queue.empty()
+
+        yield delay(100)
+
+        yield input_clk.posedge
+        print("test 10: initial sink pause, output reset")
+        current_test.next = 10
+
+        test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+
+        output_rst.next = 1
+        yield output_clk.posedge
+        output_rst.next = 0
+
+        sink_pause.next = 0
+
+        yield delay(100)
+
+        yield output_clk.posedge
+        yield output_clk.posedge
+        yield output_clk.posedge
+
+        assert sink_queue.empty()
+
+        yield delay(100)
+
         raise StopSimulation
 
     return dut, source, sink, input_clkgen, output_clkgen, check
diff --git a/tb/test_axis_async_fifo_64.py b/tb/test_axis_async_fifo_64.py
index 94be27207..e72c4ebcc 100755
--- a/tb/test_axis_async_fifo_64.py
+++ b/tb/test_axis_async_fifo_64.py
@@ -411,6 +411,90 @@ def bench():
 
         yield delay(100)
 
+        yield input_clk.posedge
+        print("test 8: initial sink pause")
+        current_test.next = 8
+
+        test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+        sink_pause.next = 0
+
+        yield output_axis_tlast.posedge
+        yield output_clk.posedge
+        yield output_clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame
+
+        yield delay(100)
+
+        yield input_clk.posedge
+        print("test 9: initial sink pause, input reset")
+        current_test.next = 9
+
+        test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+
+        input_rst.next = 1
+        yield input_clk.posedge
+        input_rst.next = 0
+
+        sink_pause.next = 0
+
+        yield delay(100)
+
+        yield output_clk.posedge
+        yield output_clk.posedge
+        yield output_clk.posedge
+
+        assert sink_queue.empty()
+
+        yield delay(100)
+
+        yield input_clk.posedge
+        print("test 10: initial sink pause, output reset")
+        current_test.next = 10
+
+        test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+
+        output_rst.next = 1
+        yield output_clk.posedge
+        output_rst.next = 0
+
+        sink_pause.next = 0
+
+        yield delay(100)
+
+        yield output_clk.posedge
+        yield output_clk.posedge
+        yield output_clk.posedge
+
+        assert sink_queue.empty()
+
+        yield delay(100)
+
         raise StopSimulation
 
     return dut, source, sink, input_clkgen, output_clkgen, check
diff --git a/tb/test_axis_async_frame_fifo.py b/tb/test_axis_async_frame_fifo.py
index 75c30747e..77b87f45b 100755
--- a/tb/test_axis_async_frame_fifo.py
+++ b/tb/test_axis_async_frame_fifo.py
@@ -510,6 +510,90 @@ def bench():
 
         yield delay(100)
 
+        yield input_clk.posedge
+        print("test 9: initial sink pause")
+        current_test.next = 9
+
+        test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+        sink_pause.next = 0
+
+        yield output_axis_tlast.posedge
+        yield output_clk.posedge
+        yield output_clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame
+
+        yield delay(100)
+
+        yield input_clk.posedge
+        print("test 10: initial sink pause, input reset")
+        current_test.next = 10
+
+        test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+
+        input_rst.next = 1
+        yield input_clk.posedge
+        input_rst.next = 0
+
+        sink_pause.next = 0
+
+        yield delay(100)
+
+        yield output_clk.posedge
+        yield output_clk.posedge
+        yield output_clk.posedge
+
+        assert sink_queue.empty()
+
+        yield delay(100)
+
+        yield input_clk.posedge
+        print("test 11: initial sink pause, output reset")
+        current_test.next = 11
+
+        test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+
+        output_rst.next = 1
+        yield output_clk.posedge
+        output_rst.next = 0
+
+        sink_pause.next = 0
+
+        yield delay(100)
+
+        yield output_clk.posedge
+        yield output_clk.posedge
+        yield output_clk.posedge
+
+        assert sink_queue.empty()
+
+        yield delay(100)
+
         raise StopSimulation
 
     return dut, monitor, source, sink, input_clkgen, output_clkgen, check
diff --git a/tb/test_axis_async_frame_fifo_64.py b/tb/test_axis_async_frame_fifo_64.py
index 5f0fb2b2c..5c5cb6ade 100755
--- a/tb/test_axis_async_frame_fifo_64.py
+++ b/tb/test_axis_async_frame_fifo_64.py
@@ -520,6 +520,90 @@ def bench():
 
         yield delay(100)
 
+        yield input_clk.posedge
+        print("test 9: initial sink pause")
+        current_test.next = 9
+
+        test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+        sink_pause.next = 0
+
+        yield output_axis_tlast.posedge
+        yield output_clk.posedge
+        yield output_clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame
+
+        yield delay(100)
+
+        yield input_clk.posedge
+        print("test 10: initial sink pause, input reset")
+        current_test.next = 10
+
+        test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+
+        input_rst.next = 1
+        yield input_clk.posedge
+        input_rst.next = 0
+
+        sink_pause.next = 0
+
+        yield delay(100)
+
+        yield output_clk.posedge
+        yield output_clk.posedge
+        yield output_clk.posedge
+
+        assert sink_queue.empty()
+
+        yield delay(100)
+
+        yield input_clk.posedge
+        print("test 11: initial sink pause, output reset")
+        current_test.next = 11
+
+        test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+        yield input_clk.posedge
+
+        output_rst.next = 1
+        yield output_clk.posedge
+        output_rst.next = 0
+
+        sink_pause.next = 0
+
+        yield delay(100)
+
+        yield output_clk.posedge
+        yield output_clk.posedge
+        yield output_clk.posedge
+
+        assert sink_queue.empty()
+
+        yield delay(100)
+
         raise StopSimulation
 
     return dut, monitor, source, sink, input_clkgen, output_clkgen, check
diff --git a/tb/test_axis_fifo.py b/tb/test_axis_fifo.py
index de7a2ba71..19382b3b5 100755
--- a/tb/test_axis_fifo.py
+++ b/tb/test_axis_fifo.py
@@ -385,6 +385,61 @@ def bench():
 
         yield delay(100)
 
+        yield clk.posedge
+        print("test 8: initial sink pause")
+        current_test.next = 8
+
+        test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+        sink_pause.next = 0
+
+        yield output_axis_tlast.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 9: initial sink pause, reset")
+        current_test.next = 9
+
+        test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rst.next = 1
+        yield clk.posedge
+        rst.next = 0
+
+        sink_pause.next = 0
+
+        yield delay(100)
+
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        assert sink_queue.empty()
+
+        yield delay(100)
+
         raise StopSimulation
 
     return dut, source, sink, clkgen, check
diff --git a/tb/test_axis_fifo_64.py b/tb/test_axis_fifo_64.py
index 320dd60a0..9ebbe3e50 100755
--- a/tb/test_axis_fifo_64.py
+++ b/tb/test_axis_fifo_64.py
@@ -395,6 +395,61 @@ def bench():
 
         yield delay(100)
 
+        yield clk.posedge
+        print("test 8: initial sink pause")
+        current_test.next = 8
+
+        test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+        sink_pause.next = 0
+
+        yield output_axis_tlast.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 9: initial sink pause, reset")
+        current_test.next = 9
+
+        test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rst.next = 1
+        yield clk.posedge
+        rst.next = 0
+
+        sink_pause.next = 0
+
+        yield delay(100)
+
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        assert sink_queue.empty()
+
+        yield delay(100)
+
         raise StopSimulation
 
     return dut, source, sink, clkgen, check
diff --git a/tb/test_axis_frame_fifo.py b/tb/test_axis_frame_fifo.py
index 84868e765..d01334821 100755
--- a/tb/test_axis_frame_fifo.py
+++ b/tb/test_axis_frame_fifo.py
@@ -490,6 +490,61 @@ def bench():
 
         yield delay(100)
 
+        yield clk.posedge
+        print("test 9: initial sink pause")
+        current_test.next = 9
+
+        test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+        sink_pause.next = 0
+
+        yield output_axis_tlast.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 10: initial sink pause, reset")
+        current_test.next = 10
+
+        test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rst.next = 1
+        yield clk.posedge
+        rst.next = 0
+
+        sink_pause.next = 0
+
+        yield delay(100)
+
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        assert sink_queue.empty()
+
+        yield delay(100)
+
         raise StopSimulation
 
     return dut, monitor, source, sink, clkgen, check
diff --git a/tb/test_axis_frame_fifo_64.py b/tb/test_axis_frame_fifo_64.py
index ed8524dcf..b37f483ac 100755
--- a/tb/test_axis_frame_fifo_64.py
+++ b/tb/test_axis_frame_fifo_64.py
@@ -505,6 +505,61 @@ def bench():
 
         yield delay(100)
 
+        yield clk.posedge
+        print("test 9: initial sink pause")
+        current_test.next = 9
+
+        test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+        sink_pause.next = 0
+
+        yield output_axis_tlast.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rx_frame = None
+        if not sink_queue.empty():
+            rx_frame = sink_queue.get()
+
+        assert rx_frame == test_frame
+
+        yield delay(100)
+
+        yield clk.posedge
+        print("test 10: initial sink pause, reset")
+        current_test.next = 10
+
+        test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
+
+        sink_pause.next = 1
+        source_queue.put(test_frame)
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        rst.next = 1
+        yield clk.posedge
+        rst.next = 0
+
+        sink_pause.next = 0
+
+        yield delay(100)
+
+        yield clk.posedge
+        yield clk.posedge
+        yield clk.posedge
+
+        assert sink_queue.empty()
+
+        yield delay(100)
+
         raise StopSimulation
 
     return dut, monitor, source, sink, clkgen, check