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Add FIFO reset tests

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This commit is contained in:
Alex Forencich 2015-07-09 11:13:25 -07:00
parent f387e4c300
commit 516c50d786
8 changed files with 556 additions and 0 deletions
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84
tb/test_axis_async_fifo.py
View File

@ -401,6 +401,90 @@ def bench():
yield delay(100) yield delay(100)
yield input_clk.posedge
print("test 8: initial sink pause")
current_test.next = 8
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
sink_pause.next = 1
source_queue.put(test_frame)
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
sink_pause.next = 0
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
yield delay(100)
yield input_clk.posedge
print("test 9: initial sink pause, input reset")
current_test.next = 9
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
sink_pause.next = 1
source_queue.put(test_frame)
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
input_rst.next = 1
yield input_clk.posedge
input_rst.next = 0
sink_pause.next = 0
yield delay(100)
yield output_clk.posedge
yield output_clk.posedge
yield output_clk.posedge
assert sink_queue.empty()
yield delay(100)
yield input_clk.posedge
print("test 10: initial sink pause, output reset")
current_test.next = 10
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
sink_pause.next = 1
source_queue.put(test_frame)
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
output_rst.next = 1
yield output_clk.posedge
output_rst.next = 0
sink_pause.next = 0
yield delay(100)
yield output_clk.posedge
yield output_clk.posedge
yield output_clk.posedge
assert sink_queue.empty()
yield delay(100)
raise StopSimulation raise StopSimulation
return dut, source, sink, input_clkgen, output_clkgen, check return dut, source, sink, input_clkgen, output_clkgen, check

84
tb/test_axis_async_fifo_64.py
View File

@ -411,6 +411,90 @@ def bench():
yield delay(100) yield delay(100)
yield input_clk.posedge
print("test 8: initial sink pause")
current_test.next = 8
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
sink_pause.next = 1
source_queue.put(test_frame)
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
sink_pause.next = 0
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
yield delay(100)
yield input_clk.posedge
print("test 9: initial sink pause, input reset")
current_test.next = 9
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
sink_pause.next = 1
source_queue.put(test_frame)
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
input_rst.next = 1
yield input_clk.posedge
input_rst.next = 0
sink_pause.next = 0
yield delay(100)
yield output_clk.posedge
yield output_clk.posedge
yield output_clk.posedge
assert sink_queue.empty()
yield delay(100)
yield input_clk.posedge
print("test 10: initial sink pause, output reset")
current_test.next = 10
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
sink_pause.next = 1
source_queue.put(test_frame)
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
output_rst.next = 1
yield output_clk.posedge
output_rst.next = 0
sink_pause.next = 0
yield delay(100)
yield output_clk.posedge
yield output_clk.posedge
yield output_clk.posedge
assert sink_queue.empty()
yield delay(100)
raise StopSimulation raise StopSimulation
return dut, source, sink, input_clkgen, output_clkgen, check return dut, source, sink, input_clkgen, output_clkgen, check

84
tb/test_axis_async_frame_fifo.py
View File

@ -510,6 +510,90 @@ def bench():
yield delay(100) yield delay(100)
yield input_clk.posedge
print("test 9: initial sink pause")
current_test.next = 9
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
sink_pause.next = 1
source_queue.put(test_frame)
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
sink_pause.next = 0
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
yield delay(100)
yield input_clk.posedge
print("test 10: initial sink pause, input reset")
current_test.next = 10
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
sink_pause.next = 1
source_queue.put(test_frame)
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
input_rst.next = 1
yield input_clk.posedge
input_rst.next = 0
sink_pause.next = 0
yield delay(100)
yield output_clk.posedge
yield output_clk.posedge
yield output_clk.posedge
assert sink_queue.empty()
yield delay(100)
yield input_clk.posedge
print("test 11: initial sink pause, output reset")
current_test.next = 11
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
sink_pause.next = 1
source_queue.put(test_frame)
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
output_rst.next = 1
yield output_clk.posedge
output_rst.next = 0
sink_pause.next = 0
yield delay(100)
yield output_clk.posedge
yield output_clk.posedge
yield output_clk.posedge
assert sink_queue.empty()
yield delay(100)
raise StopSimulation raise StopSimulation
return dut, monitor, source, sink, input_clkgen, output_clkgen, check return dut, monitor, source, sink, input_clkgen, output_clkgen, check

84
tb/test_axis_async_frame_fifo_64.py
View File

@ -520,6 +520,90 @@ def bench():
yield delay(100) yield delay(100)
yield input_clk.posedge
print("test 9: initial sink pause")
current_test.next = 9
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
sink_pause.next = 1
source_queue.put(test_frame)
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
sink_pause.next = 0
yield output_axis_tlast.posedge
yield output_clk.posedge
yield output_clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
yield delay(100)
yield input_clk.posedge
print("test 10: initial sink pause, input reset")
current_test.next = 10
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
sink_pause.next = 1
source_queue.put(test_frame)
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
input_rst.next = 1
yield input_clk.posedge
input_rst.next = 0
sink_pause.next = 0
yield delay(100)
yield output_clk.posedge
yield output_clk.posedge
yield output_clk.posedge
assert sink_queue.empty()
yield delay(100)
yield input_clk.posedge
print("test 11: initial sink pause, output reset")
current_test.next = 11
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
sink_pause.next = 1
source_queue.put(test_frame)
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
yield input_clk.posedge
output_rst.next = 1
yield output_clk.posedge
output_rst.next = 0
sink_pause.next = 0
yield delay(100)
yield output_clk.posedge
yield output_clk.posedge
yield output_clk.posedge
assert sink_queue.empty()
yield delay(100)
raise StopSimulation raise StopSimulation
return dut, monitor, source, sink, input_clkgen, output_clkgen, check return dut, monitor, source, sink, input_clkgen, output_clkgen, check

55
tb/test_axis_fifo.py
View File

@ -385,6 +385,61 @@ def bench():
yield delay(100) yield delay(100)
yield clk.posedge
print("test 8: initial sink pause")
current_test.next = 8
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
sink_pause.next = 1
source_queue.put(test_frame)
yield clk.posedge
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = 0
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 9: initial sink pause, reset")
current_test.next = 9
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
sink_pause.next = 1
source_queue.put(test_frame)
yield clk.posedge
yield clk.posedge
yield clk.posedge
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
sink_pause.next = 0
yield delay(100)
yield clk.posedge
yield clk.posedge
yield clk.posedge
assert sink_queue.empty()
yield delay(100)
raise StopSimulation raise StopSimulation
return dut, source, sink, clkgen, check return dut, source, sink, clkgen, check

55
tb/test_axis_fifo_64.py
View File

@ -395,6 +395,61 @@ def bench():
yield delay(100) yield delay(100)
yield clk.posedge
print("test 8: initial sink pause")
current_test.next = 8
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
sink_pause.next = 1
source_queue.put(test_frame)
yield clk.posedge
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = 0
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 9: initial sink pause, reset")
current_test.next = 9
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
sink_pause.next = 1
source_queue.put(test_frame)
yield clk.posedge
yield clk.posedge
yield clk.posedge
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
sink_pause.next = 0
yield delay(100)
yield clk.posedge
yield clk.posedge
yield clk.posedge
assert sink_queue.empty()
yield delay(100)
raise StopSimulation raise StopSimulation
return dut, source, sink, clkgen, check return dut, source, sink, clkgen, check

55
tb/test_axis_frame_fifo.py
View File

@ -490,6 +490,61 @@ def bench():
yield delay(100) yield delay(100)
yield clk.posedge
print("test 9: initial sink pause")
current_test.next = 9
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
sink_pause.next = 1
source_queue.put(test_frame)
yield clk.posedge
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = 0
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 10: initial sink pause, reset")
current_test.next = 10
test_frame = axis_ep.AXIStreamFrame(b'\x01\x02\x03')
sink_pause.next = 1
source_queue.put(test_frame)
yield clk.posedge
yield clk.posedge
yield clk.posedge
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
sink_pause.next = 0
yield delay(100)
yield clk.posedge
yield clk.posedge
yield clk.posedge
assert sink_queue.empty()
yield delay(100)
raise StopSimulation raise StopSimulation
return dut, monitor, source, sink, clkgen, check return dut, monitor, source, sink, clkgen, check

55
tb/test_axis_frame_fifo_64.py
View File

@ -505,6 +505,61 @@ def bench():
yield delay(100) yield delay(100)
yield clk.posedge
print("test 9: initial sink pause")
current_test.next = 9
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
sink_pause.next = 1
source_queue.put(test_frame)
yield clk.posedge
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_pause.next = 0
yield output_axis_tlast.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 10: initial sink pause, reset")
current_test.next = 10
test_frame = axis_ep.AXIStreamFrame(bytearray(range(24)))
sink_pause.next = 1
source_queue.put(test_frame)
yield clk.posedge
yield clk.posedge
yield clk.posedge
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
sink_pause.next = 0
yield delay(100)
yield clk.posedge
yield clk.posedge
yield clk.posedge
assert sink_queue.empty()
yield delay(100)
raise StopSimulation raise StopSimulation
return dut, monitor, source, sink, clkgen, check return dut, monitor, source, sink, clkgen, check