diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/led_sreg_driver.v b/fpga/common/rtl/led_sreg_driver.v similarity index 100% rename from fpga/mqnic/fb2CG/fpga_100g/rtl/led_sreg_driver.v rename to fpga/common/rtl/led_sreg_driver.v diff --git a/fpga/common/syn/vivado/led_sreg_driver.tcl b/fpga/common/syn/vivado/led_sreg_driver.tcl new file mode 100644 index 000000000..19dca3037 --- /dev/null +++ b/fpga/common/syn/vivado/led_sreg_driver.tcl @@ -0,0 +1,32 @@ +# Copyright (c) 2020 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Timing constraints for led_sreg_driver + +foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == led_sreg_driver || REF_NAME == led_sreg_driver)}] { + puts "Inserting timing constraints for led_sreg_driver instance $inst" + + set select_ffs [get_cells "$inst/led_sync_reg_1_reg[*] $inst/led_sync_reg_2_reg[*]"] + + if {[llength $select_ffs]} { + set_property ASYNC_REG TRUE $select_ffs + set_false_path -to [get_pins "$inst/led_sync_reg_1_reg[*]/D"] + } +} diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile index 64a351a3c..d0fb77f9e 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile @@ -8,7 +8,6 @@ FPGA_ARCH = kintexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/bmc_spi.v -SYN_FILES += rtl/led_sreg_driver.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v @@ -58,6 +57,7 @@ SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v SYN_FILES += rtl/common/tx_scheduler_rr.v SYN_FILES += rtl/common/cmac_pad.v SYN_FILES += rtl/common/mac_ts_insert.v +SYN_FILES += rtl/common/led_sreg_driver.v SYN_FILES += lib/eth/rtl/ptp_clock.v SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v SYN_FILES += lib/eth/rtl/ptp_perout.v @@ -115,7 +115,6 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v XDC_FILES = fpga.xdc XDC_FILES += placement.xdc XDC_FILES += boot.xdc -XDC_FILES += led.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl @@ -125,6 +124,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/cmac_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/cmac_gty_ch_wrapper.tcl +XDC_FILES += ../../../common/syn/vivado/led_sreg_driver.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile index 5bbe90f56..4fab920f2 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile @@ -8,7 +8,6 @@ FPGA_ARCH = kintexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/bmc_spi.v -SYN_FILES += rtl/led_sreg_driver.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v @@ -58,6 +57,7 @@ SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v SYN_FILES += rtl/common/tx_scheduler_rr.v SYN_FILES += rtl/common/cmac_pad.v SYN_FILES += rtl/common/mac_ts_insert.v +SYN_FILES += rtl/common/led_sreg_driver.v SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v SYN_FILES += app/dma_bench/rtl/dma_bench.v SYN_FILES += app/dma_bench/rtl/dram_test_ch.v @@ -122,7 +122,6 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v XDC_FILES = fpga.xdc XDC_FILES += placement.xdc XDC_FILES += boot.xdc -XDC_FILES += led.tcl XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw.tcl XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl @@ -135,6 +134,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/cmac_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/cmac_gty_ch_wrapper.tcl +XDC_FILES += ../../../common/syn/vivado/led_sreg_driver.tcl XDC_FILES += app/dma_bench/syn/vivado/dram_test_ch.tcl # IP diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile index 8551e1b80..76d79c4cf 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile @@ -8,7 +8,6 @@ FPGA_ARCH = kintexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/bmc_spi.v -SYN_FILES += rtl/led_sreg_driver.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v @@ -58,6 +57,7 @@ SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v SYN_FILES += rtl/common/tx_scheduler_rr.v SYN_FILES += rtl/common/cmac_pad.v SYN_FILES += rtl/common/mac_ts_insert.v +SYN_FILES += rtl/common/led_sreg_driver.v SYN_FILES += app/template/rtl/mqnic_app_block.v SYN_FILES += lib/axi/rtl/axil_ram.v @@ -119,7 +119,6 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v XDC_FILES = fpga.xdc XDC_FILES += placement.xdc XDC_FILES += boot.xdc -XDC_FILES += led.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl @@ -129,6 +128,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/cmac_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/cmac_gty_ch_wrapper.tcl +XDC_FILES += ../../../common/syn/vivado/led_sreg_driver.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile index da3d649f5..85e737af6 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile @@ -8,7 +8,6 @@ FPGA_ARCH = kintexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/bmc_spi.v -SYN_FILES += rtl/led_sreg_driver.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v @@ -60,6 +59,7 @@ SYN_FILES += rtl/common/tx_scheduler_ctrl_tdma.v SYN_FILES += rtl/common/tdma_scheduler.v SYN_FILES += rtl/common/cmac_pad.v SYN_FILES += rtl/common/mac_ts_insert.v +SYN_FILES += rtl/common/led_sreg_driver.v SYN_FILES += lib/eth/rtl/ptp_clock.v SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v SYN_FILES += lib/eth/rtl/ptp_perout.v @@ -117,7 +117,6 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v XDC_FILES = fpga.xdc XDC_FILES += placement.xdc XDC_FILES += boot.xdc -XDC_FILES += led.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl @@ -127,6 +126,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/cmac_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/cmac_gty_ch_wrapper.tcl +XDC_FILES += ../../../common/syn/vivado/led_sreg_driver.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl diff --git a/fpga/mqnic/fb2CG/fpga_100g/led.tcl b/fpga/mqnic/fb2CG/fpga_100g/led.tcl deleted file mode 100644 index 1e1bd643d..000000000 --- a/fpga/mqnic/fb2CG/fpga_100g/led.tcl +++ /dev/null @@ -1,12 +0,0 @@ -# Timing constraints for led_sreg_driver - -foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == led_sreg_driver || REF_NAME == led_sreg_driver)}] { - puts "Inserting timing constraints for led_sreg_driver instance $inst" - - set select_ffs [get_cells "$inst/led_sync_reg_1_reg[*] $inst/led_sync_reg_2_reg[*]"] - - if {[llength $select_ffs]} { - set_property ASYNC_REG TRUE $select_ffs - set_false_path -to [get_pins "$inst/led_sync_reg_1_reg[*]/D"] - } -} diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile index 2354807f7..a763cf7e9 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile @@ -8,7 +8,6 @@ FPGA_ARCH = kintexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/bmc_spi.v -SYN_FILES += rtl/led_sreg_driver.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v @@ -59,6 +58,7 @@ SYN_FILES += rtl/common/tx_scheduler_rr.v SYN_FILES += rtl/common/tdma_scheduler.v SYN_FILES += rtl/common/tdma_ber.v SYN_FILES += rtl/common/tdma_ber_ch.v +SYN_FILES += rtl/common/led_sreg_driver.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v @@ -130,7 +130,6 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v XDC_FILES = fpga.xdc XDC_FILES += placement.xdc XDC_FILES += boot.xdc -XDC_FILES += led.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl @@ -140,6 +139,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl +XDC_FILES += ../../../common/syn/vivado/led_sreg_driver.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile index 2354807f7..a763cf7e9 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile @@ -8,7 +8,6 @@ FPGA_ARCH = kintexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/bmc_spi.v -SYN_FILES += rtl/led_sreg_driver.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v @@ -59,6 +58,7 @@ SYN_FILES += rtl/common/tx_scheduler_rr.v SYN_FILES += rtl/common/tdma_scheduler.v SYN_FILES += rtl/common/tdma_ber.v SYN_FILES += rtl/common/tdma_ber_ch.v +SYN_FILES += rtl/common/led_sreg_driver.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v @@ -130,7 +130,6 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v XDC_FILES = fpga.xdc XDC_FILES += placement.xdc XDC_FILES += boot.xdc -XDC_FILES += led.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl @@ -140,6 +139,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl +XDC_FILES += ../../../common/syn/vivado/led_sreg_driver.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile index 7ef4e865b..eb8c25ca3 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile @@ -8,7 +8,6 @@ FPGA_ARCH = kintexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/bmc_spi.v -SYN_FILES += rtl/led_sreg_driver.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v @@ -60,6 +59,7 @@ SYN_FILES += rtl/common/tx_scheduler_ctrl_tdma.v SYN_FILES += rtl/common/tdma_scheduler.v SYN_FILES += rtl/common/tdma_ber.v SYN_FILES += rtl/common/tdma_ber_ch.v +SYN_FILES += rtl/common/led_sreg_driver.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v @@ -131,7 +131,6 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v XDC_FILES = fpga.xdc XDC_FILES += placement.xdc XDC_FILES += boot.xdc -XDC_FILES += led.tcl XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl @@ -141,6 +140,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl +XDC_FILES += ../../../common/syn/vivado/led_sreg_driver.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl diff --git a/fpga/mqnic/fb2CG/fpga_25g/led.tcl b/fpga/mqnic/fb2CG/fpga_25g/led.tcl deleted file mode 100644 index 1e1bd643d..000000000 --- a/fpga/mqnic/fb2CG/fpga_25g/led.tcl +++ /dev/null @@ -1,12 +0,0 @@ -# Timing constraints for led_sreg_driver - -foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == led_sreg_driver || REF_NAME == led_sreg_driver)}] { - puts "Inserting timing constraints for led_sreg_driver instance $inst" - - set select_ffs [get_cells "$inst/led_sync_reg_1_reg[*] $inst/led_sync_reg_2_reg[*]"] - - if {[llength $select_ffs]} { - set_property ASYNC_REG TRUE $select_ffs - set_false_path -to [get_pins "$inst/led_sync_reg_1_reg[*]/D"] - } -} diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/led_sreg_driver.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/led_sreg_driver.v deleted file mode 100644 index d157b4665..000000000 --- a/fpga/mqnic/fb2CG/fpga_25g/rtl/led_sreg_driver.v +++ /dev/null @@ -1,161 +0,0 @@ -/* - -Copyright (c) 2020 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * LED shift register driver - */ -module led_sreg_driver #( - // number of LEDs - parameter COUNT = 8, - // invert output - parameter INVERT = 0, - // reverse order - parameter REVERSE = 0, - // interleave A and B inputs, otherwise only use A - parameter INTERLEAVE = 0, - // clock prescale - parameter PRESCALE = 31 -) -( - input wire clk, - input wire rst, - - input wire [COUNT-1:0] led_a, - input wire [COUNT-1:0] led_b, - - output wire sreg_d, - output wire sreg_ld, - output wire sreg_clk -); - -localparam COUNT_INT = INTERLEAVE ? COUNT*2 : COUNT; -localparam CL_COUNT = $clog2(COUNT_INT+1); -localparam CL_PRESCALE = $clog2(PRESCALE+1); - -reg [CL_COUNT-1:0] count_reg = 0; -reg [CL_PRESCALE-1:0] prescale_count_reg = 0; -reg enable_reg = 1'b0; -reg update_reg = 1'b1; -reg cycle_reg = 1'b0; - -reg [COUNT_INT-1:0] led_sync_reg_1 = 0; -reg [COUNT_INT-1:0] led_sync_reg_2 = 0; -reg [COUNT_INT-1:0] led_reg = 0; - -reg sreg_d_reg = 1'b0; -reg sreg_ld_reg = 1'b0; -reg sreg_clk_reg = 1'b0; - -assign sreg_d = INVERT ? !sreg_d_reg : sreg_d_reg; -assign sreg_ld = sreg_ld_reg; -assign sreg_clk = sreg_clk_reg; - -integer i; - -always @(posedge clk) begin - if (INTERLEAVE) begin - for (i = 0; i < COUNT; i = i + 1) begin - led_sync_reg_1[i*2 +: 2] <= {led_b[i], led_a[i]}; - end - end else begin - led_sync_reg_1 <= led_a; - end - led_sync_reg_2 <= led_sync_reg_1; - - enable_reg <= 1'b0; - - if (prescale_count_reg) begin - prescale_count_reg <= prescale_count_reg - 1; - end else begin - enable_reg <= 1'b1; - prescale_count_reg <= PRESCALE; - end - - if (enable_reg) begin - if (cycle_reg) begin - cycle_reg <= 1'b0; - sreg_clk_reg <= 1'b1; - end else if (count_reg) begin - sreg_clk_reg <= 1'b0; - sreg_ld_reg <= 1'b0; - - if (count_reg < COUNT_INT) begin - count_reg <= count_reg + 1; - cycle_reg <= 1'b1; - if (REVERSE) begin - sreg_d_reg <= led_reg[COUNT_INT-1-count_reg]; - end else begin - sreg_d_reg <= led_reg[count_reg]; - end - end else begin - count_reg <= 0; - cycle_reg <= 1'b0; - sreg_d_reg <= 1'b0; - sreg_ld_reg <= 1'b1; - end - end else begin - sreg_clk_reg <= 1'b0; - sreg_ld_reg <= 1'b0; - - if (update_reg) begin - update_reg <= 1'b0; - - count_reg <= 1; - cycle_reg <= 1'b1; - if (REVERSE) begin - sreg_d_reg <= led_reg[COUNT_INT-1]; - end else begin - sreg_d_reg <= led_reg[0]; - end - end - end - end - - if (led_sync_reg_2 != led_reg) begin - led_reg <= led_sync_reg_2; - update_reg <= 1'b1; - end - - if (rst) begin - count_reg <= 0; - prescale_count_reg <= 0; - enable_reg <= 1'b0; - update_reg <= 1'b1; - cycle_reg <= 1'b0; - led_reg <= 0; - sreg_d_reg <= 1'b0; - sreg_ld_reg <= 1'b0; - sreg_clk_reg <= 1'b0; - end -end - -endmodule - -`resetall