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Include instance names in error messages

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This commit is contained in:
Alex Forencich 2019-07-25 16:33:27 -07:00
parent 62cbaa1bd1
commit 521c6d909e
20 changed files with 72 additions and 72 deletions
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10
rtl/axi_adapter_rd.v
View File

@ -133,27 +133,27 @@ parameter SEGMENT_STRB_WIDTH = STRB_WIDTH / SEGMENT_COUNT;
// bus width assertions
initial begin
if (S_WORD_SIZE * S_STRB_WIDTH != S_DATA_WIDTH) begin
$error("Error: AXI slave interface data width not evenly divisble");
$error("Error: AXI slave interface data width not evenly divisble (instance %m)");
$finish;
end
if (M_WORD_SIZE * M_STRB_WIDTH != M_DATA_WIDTH) begin
$error("Error: AXI master interface data width not evenly divisble");
$error("Error: AXI master interface data width not evenly divisble (instance %m)");
$finish;
end
if (S_WORD_SIZE != M_WORD_SIZE) begin
$error("Error: word size mismatch");
$error("Error: word size mismatch (instance %m)");
$finish;
end
if (2**$clog2(S_WORD_WIDTH) != S_WORD_WIDTH) begin
$error("Error: AXI slave interface word width must be even power of two");
$error("Error: AXI slave interface word width must be even power of two (instance %m)");
$finish;
end
if (2**$clog2(M_WORD_WIDTH) != M_WORD_WIDTH) begin
$error("Error: AXI master interface word width must be even power of two");
$error("Error: AXI master interface word width must be even power of two (instance %m)");
$finish;
end
end

10
rtl/axi_adapter_wr.v
View File

@ -145,27 +145,27 @@ parameter SEGMENT_STRB_WIDTH = STRB_WIDTH / SEGMENT_COUNT;
// bus width assertions
initial begin
if (S_WORD_SIZE * S_STRB_WIDTH != S_DATA_WIDTH) begin
$error("Error: AXI slave interface data width not evenly divisble");
$error("Error: AXI slave interface data width not evenly divisble (instance %m)");
$finish;
end
if (M_WORD_SIZE * M_STRB_WIDTH != M_DATA_WIDTH) begin
$error("Error: AXI master interface data width not evenly divisble");
$error("Error: AXI master interface data width not evenly divisble (instance %m)");
$finish;
end
if (S_WORD_SIZE != M_WORD_SIZE) begin
$error("Error: word size mismatch");
$error("Error: word size mismatch (instance %m)");
$finish;
end
if (2**$clog2(S_WORD_WIDTH) != S_WORD_WIDTH) begin
$error("Error: AXI slave interface word width must be even power of two");
$error("Error: AXI slave interface word width must be even power of two (instance %m)");
$finish;
end
if (2**$clog2(M_WORD_WIDTH) != M_WORD_WIDTH) begin
$error("Error: AXI master interface word width must be even power of two");
$error("Error: AXI master interface word width must be even power of two (instance %m)");
$finish;
end
end

10
rtl/axi_axil_adapter_rd.v
View File

@ -107,27 +107,27 @@ parameter SEGMENT_STRB_WIDTH = STRB_WIDTH / SEGMENT_COUNT;
// bus width assertions
initial begin
if (AXI_WORD_SIZE * AXI_STRB_WIDTH != AXI_DATA_WIDTH) begin
$error("Error: AXI slave interface data width not evenly divisble");
$error("Error: AXI slave interface data width not evenly divisble (instance %m)");
$finish;
end
if (AXIL_WORD_SIZE * AXIL_STRB_WIDTH != AXIL_DATA_WIDTH) begin
$error("Error: AXI lite master interface data width not evenly divisble");
$error("Error: AXI lite master interface data width not evenly divisble (instance %m)");
$finish;
end
if (AXI_WORD_SIZE != AXIL_WORD_SIZE) begin
$error("Error: word size mismatch");
$error("Error: word size mismatch (instance %m)");
$finish;
end
if (2**$clog2(AXI_WORD_WIDTH) != AXI_WORD_WIDTH) begin
$error("Error: AXI slave interface word width must be even power of two");
$error("Error: AXI slave interface word width must be even power of two (instance %m)");
$finish;
end
if (2**$clog2(AXIL_WORD_WIDTH) != AXIL_WORD_WIDTH) begin
$error("Error: AXI lite master interface word width must be even power of two");
$error("Error: AXI lite master interface word width must be even power of two (instance %m)");
$finish;
end
end

10
rtl/axi_axil_adapter_wr.v
View File

@ -113,27 +113,27 @@ parameter SEGMENT_STRB_WIDTH = STRB_WIDTH / SEGMENT_COUNT;
// bus width assertions
initial begin
if (AXI_WORD_SIZE * AXI_STRB_WIDTH != AXI_DATA_WIDTH) begin
$error("Error: AXI slave interface data width not evenly divisble");
$error("Error: AXI slave interface data width not evenly divisble (instance %m)");
$finish;
end
if (AXIL_WORD_SIZE * AXIL_STRB_WIDTH != AXIL_DATA_WIDTH) begin
$error("Error: AXI lite master interface data width not evenly divisble");
$error("Error: AXI lite master interface data width not evenly divisble (instance %m)");
$finish;
end
if (AXI_WORD_SIZE != AXIL_WORD_SIZE) begin
$error("Error: word size mismatch");
$error("Error: word size mismatch (instance %m)");
$finish;
end
if (2**$clog2(AXI_WORD_WIDTH) != AXI_WORD_WIDTH) begin
$error("Error: AXI slave interface word width must be even power of two");
$error("Error: AXI slave interface word width must be even power of two (instance %m)");
$finish;
end
if (2**$clog2(AXIL_WORD_WIDTH) != AXIL_WORD_WIDTH) begin
$error("Error: AXI lite master interface word width must be even power of two");
$error("Error: AXI lite master interface word width must be even power of two (instance %m)");
$finish;
end
end

6
rtl/axi_cdma.v
View File

@ -132,17 +132,17 @@ parameter STATUS_FIFO_ADDR_WIDTH = 5;
// bus width assertions
initial begin
if (AXI_WORD_SIZE * AXI_STRB_WIDTH != AXI_DATA_WIDTH) begin
$error("Error: AXI data width not evenly divisble");
$error("Error: AXI data width not evenly divisble (instance %m)");
$finish;
end
if (2**$clog2(AXI_WORD_WIDTH) != AXI_WORD_WIDTH) begin
$error("Error: AXI word width must be even power of two");
$error("Error: AXI word width must be even power of two (instance %m)");
$finish;
end
if (AXI_MAX_BURST_LEN < 1 || AXI_MAX_BURST_LEN > 256) begin
$error("Error: AXI_MAX_BURST_LEN must be between 1 and 256");
$error("Error: AXI_MAX_BURST_LEN must be between 1 and 256 (instance %m)");
$finish;
end
end

2
rtl/axi_cdma_desc_mux.v
View File

@ -89,7 +89,7 @@ parameter CL_PORTS = $clog2(PORTS);
// check configuration
initial begin
if (M_TAG_WIDTH < S_TAG_WIDTH+$clog2(PORTS)) begin
$error("Error: M_TAG_WIDTH must be at least $clog2(PORTS) larger than S_TAG_WIDTH");
$error("Error: M_TAG_WIDTH must be at least $clog2(PORTS) larger than S_TAG_WIDTH (instance %m)");
$finish;
end
end

12
rtl/axi_crossbar_addr.v
View File

@ -118,27 +118,27 @@ integer i, j;
// check configuration
initial begin
if (S_ACCEPT < 1) begin
$error("Error: need at least 1 accept");
$error("Error: need at least 1 accept (instance %m)");
$finish;
end
if (S_THREADS < 1) begin
$error("Error: need at least 1 thread");
$error("Error: need at least 1 thread (instance %m)");
$finish;
end
if (S_THREADS > S_ACCEPT) begin
$warning("Warning: requested thread count larger than accept count; limiting thread count to accept count");
$warning("Warning: requested thread count larger than accept count; limiting thread count to accept count (instance %m)");
end
if (M_REGIONS < 1) begin
$error("Error: need at least 1 region");
$error("Error: need at least 1 region (instance %m)");
$finish;
end
for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
if (M_ADDR_WIDTH[i*32 +: 32] && (M_ADDR_WIDTH[i*32 +: 32] < 12 || M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH)) begin
$error("Error: address width out of range");
$error("Error: address width out of range (instance %m)");
$finish;
end
end
@ -149,7 +149,7 @@ initial begin
if (((M_BASE_ADDR[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32])) <= (M_BASE_ADDR[j*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[j*32 +: 32])))) && ((M_BASE_ADDR[j*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[j*32 +: 32])) <= (M_BASE_ADDR[i*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32 +: 32]))))) begin
$display("%d: %08x / %02d -- %08x-%08x", i, M_BASE_ADDR[i*ADDR_WIDTH +: ADDR_WIDTH], M_ADDR_WIDTH[i*32 +: 32], M_BASE_ADDR[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32]), M_BASE_ADDR[i*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32 +: 32])));
$display("%d: %08x / %02d -- %08x-%08x", j, M_BASE_ADDR[j*ADDR_WIDTH +: ADDR_WIDTH], M_ADDR_WIDTH[j*32 +: 32], M_BASE_ADDR[j*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[j*32 +: 32]), M_BASE_ADDR[j*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[j*32 +: 32])));
$error("Error: address ranges overlap");
$error("Error: address ranges overlap (instance %m)");
$finish;
end
end

4
rtl/axi_crossbar_rd.v
View File

@ -152,13 +152,13 @@ integer i;
// check configuration
initial begin
if (M_ID_WIDTH < S_ID_WIDTH+$clog2(S_COUNT)) begin
$error("Error: M_ID_WIDTH must be at least $clog2(S_COUNT) larger than S_ID_WIDTH");
$error("Error: M_ID_WIDTH must be at least $clog2(S_COUNT) larger than S_ID_WIDTH (instance %m)");
$finish;
end
for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
if (M_ADDR_WIDTH[i*32 +: 32] && (M_ADDR_WIDTH[i*32 +: 32] < 12 || M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH)) begin
$error("Error: value out of range");
$error("Error: value out of range (instance %m)");
$finish;
end
end

4
rtl/axi_crossbar_wr.v
View File

@ -170,13 +170,13 @@ integer i;
// check configuration
initial begin
if (M_ID_WIDTH < S_ID_WIDTH+$clog2(S_COUNT)) begin
$error("Error: M_ID_WIDTH must be at least $clog2(S_COUNT) larger than S_ID_WIDTH");
$error("Error: M_ID_WIDTH must be at least $clog2(S_COUNT) larger than S_ID_WIDTH (instance %m)");
$finish;
end
for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
if (M_ADDR_WIDTH[i*32 +: 32] && (M_ADDR_WIDTH[i*32 +: 32] < 12 || M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH)) begin
$error("Error: value out of range");
$error("Error: value out of range (instance %m)");
$finish;
end
end

2
rtl/axi_dma_desc_mux.v
View File

@ -113,7 +113,7 @@ parameter CL_PORTS = $clog2(PORTS);
// check configuration
initial begin
if (M_TAG_WIDTH < S_TAG_WIDTH+$clog2(PORTS)) begin
$error("Error: M_TAG_WIDTH must be at least $clog2(PORTS) larger than S_TAG_WIDTH");
$error("Error: M_TAG_WIDTH must be at least $clog2(PORTS) larger than S_TAG_WIDTH (instance %m)");
$finish;
end
end

14
rtl/axi_dma_rd.v
View File

@ -148,37 +148,37 @@ parameter CYCLE_COUNT_WIDTH = LEN_WIDTH - AXI_BURST_SIZE + 1;
// bus width assertions
initial begin
if (AXI_WORD_SIZE * AXI_STRB_WIDTH != AXI_DATA_WIDTH) begin
$error("Error: AXI data width not evenly divisble");
$error("Error: AXI data width not evenly divisble (instance %m)");
$finish;
end
if (AXIS_WORD_SIZE * AXIS_KEEP_WIDTH_INT != AXIS_DATA_WIDTH) begin
$error("Error: AXI stream data width not evenly divisble");
$error("Error: AXI stream data width not evenly divisble (instance %m)");
$finish;
end
if (AXI_WORD_SIZE != AXIS_WORD_SIZE) begin
$error("Error: word size mismatch");
$error("Error: word size mismatch (instance %m)");
$finish;
end
if (2**$clog2(AXI_WORD_WIDTH) != AXI_WORD_WIDTH) begin
$error("Error: AXI word width must be even power of two");
$error("Error: AXI word width must be even power of two (instance %m)");
$finish;
end
if (AXI_DATA_WIDTH != AXIS_DATA_WIDTH) begin
$error("Error: AXI interface width must match AXI stream interface width");
$error("Error: AXI interface width must match AXI stream interface width (instance %m)");
$finish;
end
if (AXI_MAX_BURST_LEN < 1 || AXI_MAX_BURST_LEN > 256) begin
$error("Error: AXI_MAX_BURST_LEN must be between 1 and 256");
$error("Error: AXI_MAX_BURST_LEN must be between 1 and 256 (instance %m)");
$finish;
end
if (ENABLE_SG) begin
$error("Error: scatter/gather is not yet implemented");
$error("Error: scatter/gather is not yet implemented (instance %m)");
$finish;
end
end

14
rtl/axi_dma_wr.v
View File

@ -155,37 +155,37 @@ parameter STATUS_FIFO_ADDR_WIDTH = 5;
// bus width assertions
initial begin
if (AXI_WORD_SIZE * AXI_STRB_WIDTH != AXI_DATA_WIDTH) begin
$error("Error: AXI data width not evenly divisble");
$error("Error: AXI data width not evenly divisble (instance %m)");
$finish;
end
if (AXIS_WORD_SIZE * AXIS_KEEP_WIDTH_INT != AXIS_DATA_WIDTH) begin
$error("Error: AXI stream data width not evenly divisble");
$error("Error: AXI stream data width not evenly divisble (instance %m)");
$finish;
end
if (AXI_WORD_SIZE != AXIS_WORD_SIZE) begin
$error("Error: word size mismatch");
$error("Error: word size mismatch (instance %m)");
$finish;
end
if (2**$clog2(AXI_WORD_WIDTH) != AXI_WORD_WIDTH) begin
$error("Error: AXI word width must be even power of two");
$error("Error: AXI word width must be even power of two (instance %m)");
$finish;
end
if (AXI_DATA_WIDTH != AXIS_DATA_WIDTH) begin
$error("Error: AXI interface width must match AXI stream interface width");
$error("Error: AXI interface width must match AXI stream interface width (instance %m)");
$finish;
end
if (AXI_MAX_BURST_LEN < 1 || AXI_MAX_BURST_LEN > 256) begin
$error("Error: AXI_MAX_BURST_LEN must be between 1 and 256");
$error("Error: AXI_MAX_BURST_LEN must be between 1 and 256 (instance %m)");
$finish;
end
if (ENABLE_SG) begin
$error("Error: scatter/gather is not yet implemented");
$error("Error: scatter/gather is not yet implemented (instance %m)");
$finish;
end
end

4
rtl/axi_dp_ram.v
View File

@ -135,12 +135,12 @@ parameter WORD_SIZE = DATA_WIDTH/WORD_WIDTH;
// bus width assertions
initial begin
if (WORD_SIZE * STRB_WIDTH != DATA_WIDTH) begin
$error("Error: AXI data width not evenly divisble");
$error("Error: AXI data width not evenly divisble (instance %m)");
$finish;
end
if (2**$clog2(WORD_WIDTH) != WORD_WIDTH) begin
$error("Error: AXI word width must be even power of two");
$error("Error: AXI word width must be even power of two (instance %m)");
$finish;
end
end

6
rtl/axi_interconnect.v
View File

@ -192,13 +192,13 @@ integer i, j;
// check configuration
initial begin
if (M_REGIONS < 1 || M_REGIONS > 16) begin
$error("Error: M_REGIONS must be between 1 and 16");
$error("Error: M_REGIONS must be between 1 and 16 (instance %m)");
$finish;
end
for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
if (M_ADDR_WIDTH[i*32 +: 32] && (M_ADDR_WIDTH[i*32 +: 32] < 12 || M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH)) begin
$error("Error: address width out of range");
$error("Error: address width out of range (instance %m)");
$finish;
end
end
@ -209,7 +209,7 @@ initial begin
if (((M_BASE_ADDR[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32])) <= (M_BASE_ADDR[j*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[j*32 +: 32])))) && ((M_BASE_ADDR[j*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[j*32 +: 32])) <= (M_BASE_ADDR[i*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32 +: 32]))))) begin
$display("%d: %08x / %02d -- %08x-%08x", i, M_BASE_ADDR[i*ADDR_WIDTH +: ADDR_WIDTH], M_ADDR_WIDTH[i*32 +: 32], M_BASE_ADDR[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32]), M_BASE_ADDR[i*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32 +: 32])));
$display("%d: %08x / %02d -- %08x-%08x", j, M_BASE_ADDR[j*ADDR_WIDTH +: ADDR_WIDTH], M_ADDR_WIDTH[j*32 +: 32], M_BASE_ADDR[j*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[j*32 +: 32]), M_BASE_ADDR[j*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[j*32 +: 32])));
$error("Error: address ranges overlap");
$error("Error: address ranges overlap (instance %m)");
$finish;
end
end

4
rtl/axi_ram.v
View File

@ -90,12 +90,12 @@ parameter WORD_SIZE = DATA_WIDTH/WORD_WIDTH;
// bus width assertions
initial begin
if (WORD_SIZE * STRB_WIDTH != DATA_WIDTH) begin
$error("Error: AXI data width not evenly divisble");
$error("Error: AXI data width not evenly divisble (instance %m)");
$finish;
end
if (2**$clog2(WORD_WIDTH) != WORD_WIDTH) begin
$error("Error: AXI word width must be even power of two");
$error("Error: AXI word width must be even power of two (instance %m)");
$finish;
end
end

4
rtl/axi_ram_rd_if.v
View File

@ -107,12 +107,12 @@ parameter WORD_SIZE = DATA_WIDTH/WORD_WIDTH;
// bus width assertions
initial begin
if (WORD_SIZE * STRB_WIDTH != DATA_WIDTH) begin
$error("Error: AXI data width not evenly divisble");
$error("Error: AXI data width not evenly divisble (instance %m)");
$finish;
end
if (2**$clog2(WORD_WIDTH) != WORD_WIDTH) begin
$error("Error: AXI word width must be even power of two");
$error("Error: AXI word width must be even power of two (instance %m)");
$finish;
end
end

4
rtl/axi_ram_wr_if.v
View File

@ -110,12 +110,12 @@ parameter WORD_SIZE = DATA_WIDTH/WORD_WIDTH;
// bus width assertions
initial begin
if (WORD_SIZE * STRB_WIDTH != DATA_WIDTH) begin
$error("Error: AXI data width not evenly divisble");
$error("Error: AXI data width not evenly divisble (instance %m)");
$finish;
end
if (2**$clog2(WORD_WIDTH) != WORD_WIDTH) begin
$error("Error: AXI word width must be even power of two");
$error("Error: AXI word width must be even power of two (instance %m)");
$finish;
end
end

10
rtl/axil_adapter_rd.v
View File

@ -92,27 +92,27 @@ parameter SEGMENT_STRB_WIDTH = STRB_WIDTH / SEGMENT_COUNT;
// bus width assertions
initial begin
if (S_WORD_SIZE * S_STRB_WIDTH != S_DATA_WIDTH) begin
$error("Error: AXI slave interface data width not evenly divisble");
$error("Error: AXI slave interface data width not evenly divisble (instance %m)");
$finish;
end
if (M_WORD_SIZE * M_STRB_WIDTH != M_DATA_WIDTH) begin
$error("Error: AXI master interface data width not evenly divisble");
$error("Error: AXI master interface data width not evenly divisble (instance %m)");
$finish;
end
if (S_WORD_SIZE != M_WORD_SIZE) begin
$error("Error: word size mismatch");
$error("Error: word size mismatch (instance %m)");
$finish;
end
if (2**$clog2(S_WORD_WIDTH) != S_WORD_WIDTH) begin
$error("Error: AXI slave interface word width must be even power of two");
$error("Error: AXI slave interface word width must be even power of two (instance %m)");
$finish;
end
if (2**$clog2(M_WORD_WIDTH) != M_WORD_WIDTH) begin
$error("Error: AXI master interface word width must be even power of two");
$error("Error: AXI master interface word width must be even power of two (instance %m)");
$finish;
end
end

10
rtl/axil_adapter_wr.v
View File

@ -98,27 +98,27 @@ parameter SEGMENT_STRB_WIDTH = STRB_WIDTH / SEGMENT_COUNT;
// bus width assertions
initial begin
if (S_WORD_SIZE * S_STRB_WIDTH != S_DATA_WIDTH) begin
$error("Error: AXI slave interface data width not evenly divisble");
$error("Error: AXI slave interface data width not evenly divisble (instance %m)");
$finish;
end
if (M_WORD_SIZE * M_STRB_WIDTH != M_DATA_WIDTH) begin
$error("Error: AXI master interface data width not evenly divisble");
$error("Error: AXI master interface data width not evenly divisble (instance %m)");
$finish;
end
if (S_WORD_SIZE != M_WORD_SIZE) begin
$error("Error: word size mismatch");
$error("Error: word size mismatch (instance %m)");
$finish;
end
if (2**$clog2(S_WORD_WIDTH) != S_WORD_WIDTH) begin
$error("Error: AXI slave interface word width must be even power of two");
$error("Error: AXI slave interface word width must be even power of two (instance %m)");
$finish;
end
if (2**$clog2(M_WORD_WIDTH) != M_WORD_WIDTH) begin
$error("Error: AXI master interface word width must be even power of two");
$error("Error: AXI master interface word width must be even power of two (instance %m)");
$finish;
end
end

4
rtl/axil_interconnect.v
View File

@ -119,7 +119,7 @@ integer i, j;
initial begin
for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
if (M_ADDR_WIDTH[i*32 +: 32] && (M_ADDR_WIDTH[i*32 +: 32] < 0 || M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH)) begin
$error("Error: address width out of range");
$error("Error: address width out of range (instance %m)");
$finish;
end
end
@ -130,7 +130,7 @@ initial begin
if (((M_BASE_ADDR[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32])) <= (M_BASE_ADDR[j*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[j*32 +: 32])))) && ((M_BASE_ADDR[j*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[j*32 +: 32])) <= (M_BASE_ADDR[i*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32 +: 32]))))) begin
$display("%d: %08x / %02d -- %08x-%08x", i, M_BASE_ADDR[i*ADDR_WIDTH +: ADDR_WIDTH], M_ADDR_WIDTH[i*32 +: 32], M_BASE_ADDR[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32]), M_BASE_ADDR[i*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32 +: 32])));
$display("%d: %08x / %02d -- %08x-%08x", j, M_BASE_ADDR[j*ADDR_WIDTH +: ADDR_WIDTH], M_ADDR_WIDTH[j*32 +: 32], M_BASE_ADDR[j*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[j*32 +: 32]), M_BASE_ADDR[j*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[j*32 +: 32])));
$error("Error: address ranges overlap");
$error("Error: address ranges overlap (instance %m)");
$finish;
end
end