FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-30 08:32:52 +08:00
Code Issues Projects Releases Wiki Activity

Add combined TX/RX bus with all signals

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-06-05 19:09:15 -07:00
parent df32016724
commit 52e7af8a5d
1 changed files with 11 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
tb/pcie_if.py
View File

@ -54,14 +54,23 @@ class BaseBus(Bus):
return cls(entity, prefix, **kwargs)
class PcieIfBus(BaseBus):
_signals = ["hdr", "valid", "sop", "eop", "ready"]
_optional_signals = ["data", "strb", "error", "tlp_prfx", "vf_active",
"func_num", "vf_num", "data_par", "hdr_par", "tlp_prfx_par",
"seq", "bar_id", "tlp_abort"]
class PcieIfTxBus(BaseBus):
_signals = ["hdr", "valid", "sop", "eop", "ready"]
_optional_signals = ["data", "strb", "tlp_prfx", "data_par", "hdr_par", "tlp_prfx_par", "seq", "err"]
_optional_signals = ["data", "strb", "tlp_prfx",
"data_par", "hdr_par", "tlp_prfx_par", "seq"]
class PcieIfRxBus(BaseBus):
_signals = ["hdr", "valid", "sop", "eop", "ready"]
_optional_signals = ["data", "strb", "error", "tlp_prfx", "vf_active", "func_num", "vf_num", "data_par", "hdr_par", "tlp_prfx_par", "bar_id", "tlp_abort"]
_optional_signals = ["data", "strb", "error", "tlp_prfx", "vf_active", "func_num", "vf_num",
"data_par", "hdr_par", "tlp_prfx_par", "bar_id", "tlp_abort"]
def dword_parity(d):