diff --git a/fpga/lib/eth/example/ExaNIC_X10/fpga/fpga/Makefile b/fpga/lib/eth/example/ExaNIC_X10/fpga/fpga/Makefile
index 5533ee52a..1648c2af9 100644
--- a/fpga/lib/eth/example/ExaNIC_X10/fpga/fpga/Makefile
+++ b/fpga/lib/eth/example/ExaNIC_X10/fpga/fpga/Makefile
@@ -44,6 +44,7 @@ SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
 SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
 SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
 SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
+SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
 
 # XDC files
 XDC_FILES = fpga.xdc
diff --git a/fpga/lib/eth/lib/axis/rtl/axis_adapter.v b/fpga/lib/eth/lib/axis/rtl/axis_adapter.v
index 065ab9f9c..68b31a508 100644
--- a/fpga/lib/eth/lib/axis/rtl/axis_adapter.v
+++ b/fpga/lib/eth/lib/axis/rtl/axis_adapter.v
@@ -109,17 +109,17 @@ parameter SEGMENT_KEEP_WIDTH = KEEP_WIDTH / SEGMENT_COUNT;
 // bus width assertions
 initial begin
     if (S_DATA_WORD_SIZE * S_KEEP_WIDTH_INT != S_DATA_WIDTH) begin
-        $error("Error: input data width not evenly divisble");
+        $error("Error: input data width not evenly divisble (instance %m)");
         $finish;
     end
 
     if (M_DATA_WORD_SIZE * M_KEEP_WIDTH_INT != M_DATA_WIDTH) begin
-        $error("Error: output data width not evenly divisble");
+        $error("Error: output data width not evenly divisble (instance %m)");
         $finish;
     end
 
     if (S_DATA_WORD_SIZE != M_DATA_WORD_SIZE) begin
-        $error("Error: word size mismatch");
+        $error("Error: word size mismatch (instance %m)");
         $finish;
     end
 end
diff --git a/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v b/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v
index a3568b78d..39ac3498d 100644
--- a/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v
+++ b/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v
@@ -120,22 +120,22 @@ parameter ADDR_WIDTH = (KEEP_ENABLE && KEEP_WIDTH > 1) ? $clog2(DEPTH/KEEP_WIDTH
 // check configuration
 initial begin
     if (FRAME_FIFO && !LAST_ENABLE) begin
-        $error("Error: FRAME_FIFO set requires LAST_ENABLE set");
+        $error("Error: FRAME_FIFO set requires LAST_ENABLE set (instance %m)");
         $finish;
     end
 
     if (DROP_BAD_FRAME && !FRAME_FIFO) begin
-        $error("Error: DROP_BAD_FRAME set requires FRAME_FIFO set");
+        $error("Error: DROP_BAD_FRAME set requires FRAME_FIFO set (instance %m)");
         $finish;
     end
 
     if (DROP_WHEN_FULL && !FRAME_FIFO) begin
-        $error("Error: DROP_WHEN_FULL set requires FRAME_FIFO set");
+        $error("Error: DROP_WHEN_FULL set requires FRAME_FIFO set (instance %m)");
         $finish;
     end
 
     if (DROP_BAD_FRAME && (USER_BAD_FRAME_MASK & {USER_WIDTH{1'b1}}) == 0) begin
-        $error("Error: Invalid USER_BAD_FRAME_MASK value");
+        $error("Error: Invalid USER_BAD_FRAME_MASK value (instance %m)");
         $finish;
     end
 end
@@ -280,7 +280,7 @@ end
 always @* begin
     write = 1'b0;
 
-    drop_frame_next = 1'b0;
+    drop_frame_next = drop_frame_reg;
     overflow_next = 1'b0;
     bad_frame_next = 1'b0;
     good_frame_next = 1'b0;
diff --git a/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v b/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
index d87e81083..a22f1cae6 100644
--- a/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
+++ b/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
@@ -133,17 +133,17 @@ parameter KEEP_WIDTH = EXPAND_BUS ? M_KEEP_WIDTH_INT : S_KEEP_WIDTH_INT;
 // bus width assertions
 initial begin
     if (S_DATA_WORD_SIZE * S_KEEP_WIDTH_INT != S_DATA_WIDTH) begin
-        $error("Error: input data width not evenly divisble");
+        $error("Error: input data width not evenly divisble (instance %m)");
         $finish;
     end
 
     if (M_DATA_WORD_SIZE * M_KEEP_WIDTH_INT != M_DATA_WIDTH) begin
-        $error("Error: output data width not evenly divisble");
+        $error("Error: output data width not evenly divisble (instance %m)");
         $finish;
     end
 
     if (S_DATA_WORD_SIZE != M_DATA_WORD_SIZE) begin
-        $error("Error: word size mismatch");
+        $error("Error: word size mismatch (instance %m)");
         $finish;
     end
 end
diff --git a/fpga/lib/eth/lib/axis/rtl/axis_cobs_encode.v b/fpga/lib/eth/lib/axis/rtl/axis_cobs_encode.v
index 7a2d4b385..a0e24181e 100644
--- a/fpga/lib/eth/lib/axis/rtl/axis_cobs_encode.v
+++ b/fpga/lib/eth/lib/axis/rtl/axis_cobs_encode.v
@@ -86,8 +86,6 @@ wire      m_axis_tready_int_early;
 
 reg s_axis_tready_mask;
 
-assign s_axis_tready = code_fifo_in_tready && data_fifo_in_tready && s_axis_tready_mask;
-
 reg [7:0] code_fifo_in_tdata;
 reg code_fifo_in_tvalid;
 reg code_fifo_in_tlast;
@@ -100,6 +98,8 @@ wire code_fifo_out_tlast;
 wire code_fifo_out_tuser;
 reg code_fifo_out_tready;
 
+assign s_axis_tready = code_fifo_in_tready && data_fifo_in_tready && s_axis_tready_mask;
+
 axis_fifo #(
     .DEPTH(256),
     .DATA_WIDTH(8),
diff --git a/fpga/lib/eth/lib/axis/rtl/axis_fifo.v b/fpga/lib/eth/lib/axis/rtl/axis_fifo.v
index 605fc1921..93f419061 100644
--- a/fpga/lib/eth/lib/axis/rtl/axis_fifo.v
+++ b/fpga/lib/eth/lib/axis/rtl/axis_fifo.v
@@ -113,22 +113,22 @@ parameter ADDR_WIDTH = (KEEP_ENABLE && KEEP_WIDTH > 1) ? $clog2(DEPTH/KEEP_WIDTH
 // check configuration
 initial begin
     if (FRAME_FIFO && !LAST_ENABLE) begin
-        $error("Error: FRAME_FIFO set requires LAST_ENABLE set");
+        $error("Error: FRAME_FIFO set requires LAST_ENABLE set (instance %m)");
         $finish;
     end
 
     if (DROP_BAD_FRAME && !FRAME_FIFO) begin
-        $error("Error: DROP_BAD_FRAME set requires FRAME_FIFO set");
+        $error("Error: DROP_BAD_FRAME set requires FRAME_FIFO set (instance %m)");
         $finish;
     end
 
     if (DROP_WHEN_FULL && !FRAME_FIFO) begin
-        $error("Error: DROP_WHEN_FULL set requires FRAME_FIFO set");
+        $error("Error: DROP_WHEN_FULL set requires FRAME_FIFO set (instance %m)");
         $finish;
     end
 
     if (DROP_BAD_FRAME && (USER_BAD_FRAME_MASK & {USER_WIDTH{1'b1}}) == 0) begin
-        $error("Error: Invalid USER_BAD_FRAME_MASK value");
+        $error("Error: Invalid USER_BAD_FRAME_MASK value (instance %m)");
         $finish;
     end
 end
@@ -204,7 +204,7 @@ assign status_good_frame = good_frame_reg;
 always @* begin
     write = 1'b0;
 
-    drop_frame_next = 1'b0;
+    drop_frame_next = drop_frame_reg;
     overflow_next = 1'b0;
     bad_frame_next = 1'b0;
     good_frame_next = 1'b0;
diff --git a/fpga/lib/eth/lib/axis/rtl/axis_fifo_adapter.v b/fpga/lib/eth/lib/axis/rtl/axis_fifo_adapter.v
index ae97f78fc..94c390c96 100644
--- a/fpga/lib/eth/lib/axis/rtl/axis_fifo_adapter.v
+++ b/fpga/lib/eth/lib/axis/rtl/axis_fifo_adapter.v
@@ -129,17 +129,17 @@ parameter KEEP_WIDTH = EXPAND_BUS ? M_KEEP_WIDTH_INT : S_KEEP_WIDTH_INT;
 // bus width assertions
 initial begin
     if (S_DATA_WORD_SIZE * S_KEEP_WIDTH_INT != S_DATA_WIDTH) begin
-        $error("Error: input data width not evenly divisble");
+        $error("Error: input data width not evenly divisble (instance %m)");
         $finish;
     end
 
     if (M_DATA_WORD_SIZE * M_KEEP_WIDTH_INT != M_DATA_WIDTH) begin
-        $error("Error: output data width not evenly divisble");
+        $error("Error: output data width not evenly divisble (instance %m)");
         $finish;
     end
 
     if (S_DATA_WORD_SIZE != M_DATA_WORD_SIZE) begin
-        $error("Error: word size mismatch");
+        $error("Error: word size mismatch (instance %m)");
         $finish;
     end
 end
diff --git a/fpga/lib/eth/lib/axis/rtl/axis_frame_length_adjust.v b/fpga/lib/eth/lib/axis/rtl/axis_frame_length_adjust.v
index b7c216430..55257cb1d 100644
--- a/fpga/lib/eth/lib/axis/rtl/axis_frame_length_adjust.v
+++ b/fpga/lib/eth/lib/axis/rtl/axis_frame_length_adjust.v
@@ -102,7 +102,7 @@ localparam DATA_WORD_WIDTH = DATA_WIDTH / KEEP_WIDTH;
 // bus width assertions
 initial begin
     if (DATA_WORD_WIDTH * KEEP_WIDTH != DATA_WIDTH) begin
-        $error("Error: data width not evenly divisble");
+        $error("Error: data width not evenly divisble (instance %m)");
         $finish;
     end
 end
diff --git a/fpga/lib/eth/lib/axis/rtl/axis_switch.v b/fpga/lib/eth/lib/axis/rtl/axis_switch.v
index c677ec627..0e785851e 100644
--- a/fpga/lib/eth/lib/axis/rtl/axis_switch.v
+++ b/fpga/lib/eth/lib/axis/rtl/axis_switch.v
@@ -55,7 +55,7 @@ module axis_switch #
     // Output interface routing base tdest selection
     // Concatenate M_COUNT DEST_WIDTH sized constants
     // Port selected if M_BASE <= tdest <= M_TOP
-    // set to zero for default routing with tdest as port index
+    // set to zero for default routing with tdest MSBs as port index
     parameter M_BASE = 0,
     // Output interface routing top tdest selection
     // Concatenate M_COUNT DEST_WIDTH sized constants
@@ -112,8 +112,8 @@ integer i, j;
 
 // check configuration
 initial begin
-    if (2**DEST_WIDTH < CL_M_COUNT) begin
-        $error("Error: DEST_WIDTH too small for port count");
+    if (DEST_WIDTH < CL_M_COUNT) begin
+        $error("Error: DEST_WIDTH too small for port count (instance %m)");
         $finish;
     end
 
@@ -126,7 +126,7 @@ initial begin
                 if (M_BASE[i*DEST_WIDTH +: DEST_WIDTH] == M_BASE[j*DEST_WIDTH +: DEST_WIDTH]) begin
                     $display("%d: %08x", i, M_BASE[i*DEST_WIDTH +: DEST_WIDTH]);
                     $display("%d: %08x", j, M_BASE[j*DEST_WIDTH +: DEST_WIDTH]);
-                    $error("Error: ranges overlap");
+                    $error("Error: ranges overlap (instance %m)");
                     $finish;
                 end
             end
@@ -134,7 +134,7 @@ initial begin
     end else begin
         for (i = 0; i < M_COUNT; i = i + 1) begin
             if (M_BASE[i*DEST_WIDTH +: DEST_WIDTH] > M_TOP[i*DEST_WIDTH +: DEST_WIDTH]) begin
-                $error("Error: invalid range");
+                $error("Error: invalid range (instance %m)");
                 $finish;
             end
         end
@@ -144,7 +144,7 @@ initial begin
                 if (M_BASE[i*DEST_WIDTH +: DEST_WIDTH] <= M_TOP[j*DEST_WIDTH +: DEST_WIDTH] && M_BASE[j*DEST_WIDTH +: DEST_WIDTH] <= M_TOP[i*DEST_WIDTH +: DEST_WIDTH]) begin
                     $display("%d: %08x-%08x", i, M_BASE[i*DEST_WIDTH +: DEST_WIDTH], M_TOP[i*DEST_WIDTH +: DEST_WIDTH]);
                     $display("%d: %08x-%08x", j, M_BASE[j*DEST_WIDTH +: DEST_WIDTH], M_TOP[j*DEST_WIDTH +: DEST_WIDTH]);
-                    $error("Error: ranges overlap");
+                    $error("Error: ranges overlap (instance %m)");
                     $finish;
                 end
             end
@@ -188,8 +188,8 @@ generate
                 drop_next = 1'b1;
                 for (k = 0; k < M_COUNT; k = k + 1) begin
                     if (M_BASE == 0) begin
-                        // M_BASE is zero, route with tdest as port index
-                        if (int_s_axis_tdest[m*DEST_WIDTH +: DEST_WIDTH] == k && (M_CONNECT & (1 << (m+k*S_COUNT)))) begin
+                        // M_BASE is zero, route with $clog2(M_COUNT) MSBs of tdest as port index
+                        if (int_s_axis_tdest[m*DEST_WIDTH+(DEST_WIDTH-CL_M_COUNT) +: CL_M_COUNT] == k && (M_CONNECT & (1 << (m+k*S_COUNT)))) begin
                             select_next = k;
                             select_valid_next = 1'b1;
                             drop_next = 1'b0;
diff --git a/fpga/lib/eth/rtl/axis_xgmii_tx_32.v b/fpga/lib/eth/rtl/axis_xgmii_tx_32.v
index ead5affff..15f4a7050 100644
--- a/fpga/lib/eth/rtl/axis_xgmii_tx_32.v
+++ b/fpga/lib/eth/rtl/axis_xgmii_tx_32.v
@@ -121,7 +121,7 @@ localparam [3:0]
     STATE_IFG = 4'd7,
     STATE_WAIT_END = 4'd8;
 
-reg [2:0] state_reg = STATE_IDLE, state_next;
+reg [3:0] state_reg = STATE_IDLE, state_next;
 
 // datapath control signals
 reg reset_crc;
diff --git a/fpga/lib/eth/rtl/eth_mac_phy_10g.v b/fpga/lib/eth/rtl/eth_mac_phy_10g.v
index 31390eb07..4071bc110 100644
--- a/fpga/lib/eth/rtl/eth_mac_phy_10g.v
+++ b/fpga/lib/eth/rtl/eth_mac_phy_10g.v
@@ -33,7 +33,6 @@ module eth_mac_phy_10g #
 (
     parameter DATA_WIDTH = 64,
     parameter KEEP_WIDTH = (DATA_WIDTH/8),
-    parameter CTRL_WIDTH = (DATA_WIDTH/8),
     parameter HDR_WIDTH = (DATA_WIDTH/32),
     parameter ENABLE_PADDING = 1,
     parameter ENABLE_DIC = 1,
@@ -123,7 +122,6 @@ module eth_mac_phy_10g #
 eth_mac_phy_10g_rx #(
     .DATA_WIDTH(DATA_WIDTH),
     .KEEP_WIDTH(KEEP_WIDTH),
-    .CTRL_WIDTH(CTRL_WIDTH),
     .HDR_WIDTH(HDR_WIDTH),
     .PTP_PERIOD_NS(PTP_PERIOD_NS),
     .PTP_PERIOD_FNS(PTP_PERIOD_FNS),
@@ -162,7 +160,6 @@ eth_mac_phy_10g_rx_inst (
 eth_mac_phy_10g_tx #(
     .DATA_WIDTH(DATA_WIDTH),
     .KEEP_WIDTH(KEEP_WIDTH),
-    .CTRL_WIDTH(CTRL_WIDTH),
     .HDR_WIDTH(HDR_WIDTH),
     .ENABLE_PADDING(ENABLE_PADDING),
     .ENABLE_DIC(ENABLE_DIC),
diff --git a/fpga/lib/eth/rtl/eth_mac_phy_10g_fifo.v b/fpga/lib/eth/rtl/eth_mac_phy_10g_fifo.v
index 6af9af9d5..fc293d4c4 100644
--- a/fpga/lib/eth/rtl/eth_mac_phy_10g_fifo.v
+++ b/fpga/lib/eth/rtl/eth_mac_phy_10g_fifo.v
@@ -32,7 +32,6 @@ THE SOFTWARE.
 module eth_mac_phy_10g_fifo #
 (
     parameter DATA_WIDTH = 64,
-    parameter CTRL_WIDTH = (DATA_WIDTH/8),
     parameter HDR_WIDTH = (DATA_WIDTH/32),
     parameter AXIS_DATA_WIDTH = DATA_WIDTH,
     parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8),
@@ -540,7 +539,6 @@ endgenerate
 eth_mac_phy_10g #(
     .DATA_WIDTH(DATA_WIDTH),
     .KEEP_WIDTH(KEEP_WIDTH),
-    .CTRL_WIDTH(CTRL_WIDTH),
     .HDR_WIDTH(HDR_WIDTH),
     .ENABLE_PADDING(ENABLE_PADDING),
     .ENABLE_DIC(ENABLE_DIC),
diff --git a/fpga/lib/eth/rtl/eth_mac_phy_10g_rx.v b/fpga/lib/eth/rtl/eth_mac_phy_10g_rx.v
index f5a975523..4e3c66767 100644
--- a/fpga/lib/eth/rtl/eth_mac_phy_10g_rx.v
+++ b/fpga/lib/eth/rtl/eth_mac_phy_10g_rx.v
@@ -33,7 +33,6 @@ module eth_mac_phy_10g_rx #
 (
     parameter DATA_WIDTH = 64,
     parameter KEEP_WIDTH = (DATA_WIDTH/8),
-    parameter CTRL_WIDTH = (DATA_WIDTH/8),
     parameter HDR_WIDTH = (DATA_WIDTH/32),
     parameter PTP_PERIOD_NS = 4'h6,
     parameter PTP_PERIOD_FNS = 16'h6666,
@@ -96,7 +95,7 @@ initial begin
         $finish;
     end
 
-    if (KEEP_WIDTH * 8 != DATA_WIDTH || CTRL_WIDTH * 8 != DATA_WIDTH) begin
+    if (KEEP_WIDTH * 8 != DATA_WIDTH) begin
         $error("Error: Interface requires byte (8-bit) granularity");
         $finish;
     end
diff --git a/fpga/lib/eth/rtl/eth_mac_phy_10g_tx.v b/fpga/lib/eth/rtl/eth_mac_phy_10g_tx.v
index 56a3713f9..29b7e244b 100644
--- a/fpga/lib/eth/rtl/eth_mac_phy_10g_tx.v
+++ b/fpga/lib/eth/rtl/eth_mac_phy_10g_tx.v
@@ -33,7 +33,6 @@ module eth_mac_phy_10g_tx #
 (
     parameter DATA_WIDTH = 64,
     parameter KEEP_WIDTH = (DATA_WIDTH/8),
-    parameter CTRL_WIDTH = (DATA_WIDTH/8),
     parameter HDR_WIDTH = (DATA_WIDTH/32),
     parameter ENABLE_PADDING = 1,
     parameter ENABLE_DIC = 1,
@@ -98,7 +97,7 @@ initial begin
         $finish;
     end
 
-    if (KEEP_WIDTH * 8 != DATA_WIDTH || CTRL_WIDTH * 8 != DATA_WIDTH) begin
+    if (KEEP_WIDTH * 8 != DATA_WIDTH) begin
         $error("Error: Interface requires byte (8-bit) granularity");
         $finish;
     end
diff --git a/fpga/lib/eth/tb/test_eth_mac_phy_10g.py b/fpga/lib/eth/tb/test_eth_mac_phy_10g.py
index e1f885308..6a3f636bb 100755
--- a/fpga/lib/eth/tb/test_eth_mac_phy_10g.py
+++ b/fpga/lib/eth/tb/test_eth_mac_phy_10g.py
@@ -57,7 +57,6 @@ def bench():
     # Parameters
     DATA_WIDTH = 64
     KEEP_WIDTH = (DATA_WIDTH/8)
-    CTRL_WIDTH = (DATA_WIDTH/8)
     HDR_WIDTH = (DATA_WIDTH/32)
     ENABLE_PADDING = 1
     ENABLE_DIC = 1
diff --git a/fpga/lib/eth/tb/test_eth_mac_phy_10g.v b/fpga/lib/eth/tb/test_eth_mac_phy_10g.v
index 06033637e..1cf7686a9 100644
--- a/fpga/lib/eth/tb/test_eth_mac_phy_10g.v
+++ b/fpga/lib/eth/tb/test_eth_mac_phy_10g.v
@@ -34,7 +34,6 @@ module test_eth_mac_phy_10g;
 // Parameters
 parameter DATA_WIDTH = 64;
 parameter KEEP_WIDTH = (DATA_WIDTH/8);
-parameter CTRL_WIDTH = (DATA_WIDTH/8);
 parameter HDR_WIDTH = (DATA_WIDTH/32);
 parameter ENABLE_PADDING = 1;
 parameter ENABLE_DIC = 1;
@@ -157,7 +156,6 @@ end
 eth_mac_phy_10g #(
     .DATA_WIDTH(DATA_WIDTH),
     .KEEP_WIDTH(KEEP_WIDTH),
-    .CTRL_WIDTH(CTRL_WIDTH),
     .HDR_WIDTH(HDR_WIDTH),
     .ENABLE_PADDING(ENABLE_PADDING),
     .ENABLE_DIC(ENABLE_DIC),