diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/README.md b/fpga/mqnic/fb4CGg3/fpga_25g/README.md new file mode 100644 index 000000000..40bec5c3c --- /dev/null +++ b/fpga/mqnic/fb4CGg3/fpga_25g/README.md @@ -0,0 +1,19 @@ +# Corundum mqnic for fb4CGg3@VU09P + +## Introduction + +This design targets the Silicom fb4CGg3@VU09P FPGA board. + +* FPGA: xcvu9p-flgb2104-2-e +* PHY: 25G BASE-R PHY IP core and internal GTY transceiver +* RAM: 16GB DDR4 2666 (4x 512M x72) + +## How to build + +Run make to build. Ensure that the Xilinx Vivado toolchain components are in PATH. + +Run make to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. + +## How to test + +Run make program to program the fb4CGg3@VU09P board with Vivado. Then load the driver with insmod mqnic.ko. Check dmesg for output from driver initialization. diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/app b/fpga/mqnic/fb4CGg3/fpga_25g/app new file mode 120000 index 000000000..4d46690fb --- /dev/null +++ b/fpga/mqnic/fb4CGg3/fpga_25g/app @@ -0,0 +1 @@ +../../../app/ \ No newline at end of file diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/common/vivado.mk b/fpga/mqnic/fb4CGg3/fpga_25g/common/vivado.mk new file mode 100644 index 000000000..b1144edd1 --- /dev/null +++ b/fpga/mqnic/fb4CGg3/fpga_25g/common/vivado.mk @@ -0,0 +1,137 @@ +################################################################### +# +# Xilinx Vivado FPGA Makefile +# +# Copyright (c) 2016 Alex Forencich +# +################################################################### +# +# Parameters: +# FPGA_TOP - Top module name +# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) +# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) +# SYN_FILES - space-separated list of source files +# INC_FILES - space-separated list of include files +# XDC_FILES - space-separated list of timing constraint files +# XCI_FILES - space-separated list of IP XCI files +# +# Example: +# +# FPGA_TOP = fpga +# FPGA_FAMILY = VirtexUltrascale +# FPGA_DEVICE = xcvu095-ffva2104-2-e +# SYN_FILES = rtl/fpga.v +# XDC_FILES = fpga.xdc +# XCI_FILES = ip/pcspma.xci +# include ../common/vivado.mk +# +################################################################### + +# phony targets +.PHONY: fpga vivado tmpclean clean distclean + +# prevent make from deleting intermediate files and reports +.PRECIOUS: %.xpr %.bit %.mcs %.prm +.SECONDARY: + +CONFIG ?= config.mk +-include ../$(CONFIG) + +FPGA_TOP ?= fpga +PROJECT ?= $(FPGA_TOP) + +SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) + +ifdef XDC_FILES + XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) +else + XDC_FILES_REL = $(PROJECT).xdc +endif + +################################################################### +# Main Targets +# +# all: build everything +# clean: remove output files and project files +################################################################### + +all: fpga + +fpga: $(PROJECT).bit + +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr + +tmpclean:: + -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + +clean:: tmpclean + -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl + -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt + +distclean:: clean + -rm -rf rev + +################################################################### +# Target implementations +################################################################### + +# Vivado project file +create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) + rm -rf defines.v + touch defines.v + for x in $(DEFS); do echo '`define' $$x >> defines.v; done + echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@ + echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@ + echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@ + echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ + for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done + for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl + vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) + +# synthesis run +$(PROJECT).runs/synth_1/$(PROJECT).dcp: $(PROJECT).xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) + echo "open_project $(PROJECT).xpr" > run_synth.tcl + echo "reset_run synth_1" >> run_synth.tcl + echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl + echo "wait_on_run synth_1" >> run_synth.tcl + vivado -nojournal -nolog -mode batch -source run_synth.tcl + +# implementation run +$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp + echo "open_project $(PROJECT).xpr" > run_impl.tcl + echo "reset_run impl_1" >> run_impl.tcl + echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl + echo "wait_on_run impl_1" >> run_impl.tcl + echo "open_run impl_1" >> run_impl.tcl + echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl + echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl + vivado -nojournal -nolog -mode batch -source run_impl.tcl + +# bit file +$(PROJECT).bit $(PROJECT).ltx: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp + echo "open_project $(PROJECT).xpr" > generate_bit.tcl + echo "open_run impl_1" >> generate_bit.tcl + echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl + echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl + vivado -nojournal -nolog -mode batch -source generate_bit.tcl + ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit . + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi + mkdir -p rev + COUNT=100; \ + while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \ + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/fpga.xdc b/fpga/mqnic/fb4CGg3/fpga_25g/fpga.xdc new file mode 100644 index 000000000..b0b36cecd --- /dev/null +++ b/fpga/mqnic/fb4CGg3/fpga_25g/fpga.xdc @@ -0,0 +1,287 @@ +# XDC constraints for the fb4CGg3@VU09P +# part: xcvu9p-flgb2104-2-e + +# General configuration +set_property CFGBVS GND [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property CONFIG_MODE S_SELECTMAP16 [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] + +# System clocks +# init clock 50 MHz +set_property -dict {LOC AV26 IOSTANDARD LVCMOS18} [get_ports init_clk] +create_clock -period 20.000 -name init_clk [get_ports init_clk] + +# DDR4 refclk1 +#set_property -dict {LOC BA34 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk1_p] +#set_property -dict {LOC BB34 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk1_n] +#create_clock -period 3.750 -name clk_ddr4_refclk1 [get_ports clk_ddr4_refclk1_p] + +# DDR4 refclk2 +#set_property -dict {LOC C36 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk2_p] +#set_property -dict {LOC C37 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk2_n] +#create_clock -period 3.750 -name clk_ddr4_refclk2 [get_ports clk_ddr4_refclk2_p] + +# SODIMM A refclk +#set_property -dict {LOC AV27 IOSTANDARD DIFF_SSTL12} [get_ports clk_sodimm_a_refclk_p] +#set_property -dict {LOC AV28 IOSTANDARD DIFF_SSTL12} [get_ports clk_sodimm_a_refclk_n] +#create_clock -period 3.750 -name clk_sodimm_a_refclk [get_ports clk_sodimm_a_refclk_p] + +# SODIMM B refclk +#set_property -dict {LOC H19 IOSTANDARD DIFF_SSTL12} [get_ports clk_sodimm_b_refclk_p] +#set_property -dict {LOC H18 IOSTANDARD DIFF_SSTL12} [get_ports clk_sodimm_b_refclk_n] +#create_clock -period 3.750 -name clk_sodimm_b_refclk [get_ports clk_sodimm_b_refclk_p] + +# LEDs +set_property -dict {LOC AN22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports led_sreg_d] +set_property -dict {LOC AN23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports led_sreg_ld] +set_property -dict {LOC AN21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports led_sreg_clk] +set_property -dict {LOC AM24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_bmc_red[0]}] +set_property -dict {LOC AP24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_bmc_red[1]}] +set_property -dict {LOC AL24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_bmc_green[0]}] +set_property -dict {LOC AN24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {led_bmc_green[1]}] + +set_false_path -to [get_ports {led_sreg_d led_sreg_ld led_sreg_clk led_bmc[*]}] +set_output_delay 0 [get_ports {led_sreg_d led_sreg_ld led_sreg_clk led_bmc[*]}] + +# GPIO +set_property -dict {LOC AU22 IOSTANDARD LVCMOS18} [get_ports pps_in] ;# from u.FL J760 +set_property -dict {LOC AV22 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 4} [get_ports pps_out] ;# to u.FL J761 via U760 and U761 +#set_property -dict {LOC AV23 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 4} [get_ports ref_clk] ;# to u.FL J050 + +set_false_path -to [get_ports {pps_out}] +set_output_delay 0 [get_ports {pps_out}] +set_false_path -from [get_ports {pps_in}] +set_input_delay 0 [get_ports {pps_in}] + +# QSFP28 Interfaces +set_property -dict {LOC AP43} [get_ports qsfp_0_rx_0_p] ;# MGTYRXP3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AP44} [get_ports qsfp_0_rx_0_n] ;# MGTYRXN3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AP38} [get_ports qsfp_0_tx_0_p] ;# MGTYTXP3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AP39} [get_ports qsfp_0_tx_0_n] ;# MGTYTXN3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AT43} [get_ports qsfp_0_rx_1_p] ;# MGTYRXP1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AT44} [get_ports qsfp_0_rx_1_n] ;# MGTYRXN1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AT38} [get_ports qsfp_0_tx_1_p] ;# MGTYTXP1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AT39} [get_ports qsfp_0_tx_1_n] ;# MGTYTXN1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AR45} [get_ports qsfp_0_rx_2_p] ;# MGTYRXP2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AR46} [get_ports qsfp_0_rx_2_n] ;# MGTYRXN2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AR40} [get_ports qsfp_0_tx_2_p] ;# MGTYTXP2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AR41} [get_ports qsfp_0_tx_2_n] ;# MGTYTXN2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AU45} [get_ports qsfp_0_rx_3_p] ;# MGTYRXP0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AU46} [get_ports qsfp_0_rx_3_n] ;# MGTYRXN0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AU40} [get_ports qsfp_0_tx_3_p] ;# MGTYTXP0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AU41} [get_ports qsfp_0_tx_3_n] ;# MGTYTXN0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AU36} [get_ports qsfp_0_mgt_refclk_p] ;# MGTREFCLK1P_121 from U770 +set_property -dict {LOC AU37} [get_ports qsfp_0_mgt_refclk_n] ;# MGTREFCLK1N_121 from U770 +set_property -dict {LOC BA24 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_0_mod_prsnt_n] +set_property -dict {LOC BB22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports qsfp_0_reset_n] +set_property -dict {LOC BC22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports qsfp_0_lp_mode] +set_property -dict {LOC BC21 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_0_intr_n] +set_property -dict {LOC BB21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports qsfp_0_i2c_scl] +set_property -dict {LOC BB20 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports qsfp_0_i2c_sda] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_0_mgt_refclk [get_ports qsfp_0_mgt_refclk_p] + +set_false_path -to [get_ports {qsfp_0_reset_n qsfp_0_lp_mode}] +set_output_delay 0 [get_ports {qsfp_0_reset_n qsfp_0_lp_mode}] +set_false_path -from [get_ports {qsfp_0_mod_prsnt_n qsfp_0_intr_n}] +set_input_delay 0 [get_ports {qsfp_0_mod_prsnt_n qsfp_0_intr_n}] + +set_false_path -to [get_ports {qsfp_0_i2c_scl qsfp_0_i2c_sda}] +set_output_delay 0 [get_ports {qsfp_0_i2c_scl qsfp_0_i2c_sda}] +set_false_path -from [get_ports {qsfp_0_i2c_scl qsfp_0_i2c_sda}] +set_input_delay 0 [get_ports {qsfp_0_i2c_scl qsfp_0_i2c_sda}] + +set_property -dict {LOC AF43} [get_ports qsfp_1_rx_0_p] ;# MGTYRXP3_123 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AF44} [get_ports qsfp_1_rx_0_n] ;# MGTYRXN3_123 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AF38} [get_ports qsfp_1_tx_0_p] ;# MGTYTXP3_123 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AF39} [get_ports qsfp_1_tx_0_n] ;# MGTYTXN3_123 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AH43} [get_ports qsfp_1_rx_1_p] ;# MGTYRXP1_123 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AH44} [get_ports qsfp_1_rx_1_n] ;# MGTYRXN1_123 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AH38} [get_ports qsfp_1_tx_1_p] ;# MGTYTXP1_123 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AH39} [get_ports qsfp_1_tx_1_n] ;# MGTYTXN1_123 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AG45} [get_ports qsfp_1_rx_2_p] ;# MGTYRXP2_123 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AG46} [get_ports qsfp_1_rx_2_n] ;# MGTYRXN2_123 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AG40} [get_ports qsfp_1_tx_2_p] ;# MGTYTXP2_123 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AG41} [get_ports qsfp_1_tx_2_n] ;# MGTYTXN2_123 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AJ45} [get_ports qsfp_1_rx_3_p] ;# MGTYRXP0_123 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AJ46} [get_ports qsfp_1_rx_3_n] ;# MGTYRXN0_123 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AJ40} [get_ports qsfp_1_tx_3_p] ;# MGTYTXP0_123 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AJ41} [get_ports qsfp_1_tx_3_n] ;# MGTYTXN0_123 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AL36} [get_ports qsfp_1_mgt_refclk_p] ;# MGTREFCLK0P_123 from U770 +set_property -dict {LOC AL37} [get_ports qsfp_1_mgt_refclk_n] ;# MGTREFCLK0N_123 from U770 +set_property -dict {LOC BE23 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_1_mod_prsnt_n] +set_property -dict {LOC BF23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports qsfp_1_reset_n] +set_property -dict {LOC BD23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports qsfp_1_lp_mode] +set_property -dict {LOC BF24 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_1_intr_n] +set_property -dict {LOC BC23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports qsfp_1_i2c_scl] +set_property -dict {LOC BA23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports qsfp_1_i2c_sda] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_1_mgt_refclk [get_ports qsfp_1_mgt_refclk_p] + +set_false_path -to [get_ports {qsfp_1_reset_n qsfp_1_lp_mode}] +set_output_delay 0 [get_ports {qsfp_1_reset_n qsfp_1_lp_mode}] +set_false_path -from [get_ports {qsfp_1_mod_prsnt_n qsfp_1_intr_n}] +set_input_delay 0 [get_ports {qsfp_1_mod_prsnt_n qsfp_1_intr_n}] + +set_false_path -to [get_ports {qsfp_1_i2c_scl qsfp_1_i2c_sda}] +set_output_delay 0 [get_ports {qsfp_1_i2c_scl qsfp_1_i2c_sda}] +set_false_path -from [get_ports {qsfp_1_i2c_scl qsfp_1_i2c_sda}] +set_input_delay 0 [get_ports {qsfp_1_i2c_scl qsfp_1_i2c_sda}] + +set_property -dict {LOC V43 } [get_ports qsfp_2_rx_0_p] ;# MGTYRXP3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC V44 } [get_ports qsfp_2_rx_0_n] ;# MGTYRXN3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC V38 } [get_ports qsfp_2_tx_0_p] ;# MGTYTXP3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC V39 } [get_ports qsfp_2_tx_0_n] ;# MGTYTXN3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC Y43 } [get_ports qsfp_2_rx_1_p] ;# MGTYRXP1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC Y44 } [get_ports qsfp_2_rx_1_n] ;# MGTYRXN1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC Y38 } [get_ports qsfp_2_tx_1_p] ;# MGTYTXP1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC Y39 } [get_ports qsfp_2_tx_1_n] ;# MGTYTXN1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC W45 } [get_ports qsfp_2_rx_2_p] ;# MGTYRXP2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC W46 } [get_ports qsfp_2_rx_2_n] ;# MGTYRXN2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC W40 } [get_ports qsfp_2_tx_2_p] ;# MGTYTXP2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC W41 } [get_ports qsfp_2_tx_2_n] ;# MGTYTXN2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC AA45} [get_ports qsfp_2_rx_3_p] ;# MGTYRXP0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC AA46} [get_ports qsfp_2_rx_3_n] ;# MGTYRXN0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC AA40} [get_ports qsfp_2_tx_3_p] ;# MGTYTXP0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC AA41} [get_ports qsfp_2_tx_3_n] ;# MGTYTXN0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC AC36} [get_ports qsfp_2_mgt_refclk_p] ;# MGTREFCLK0P_125 from U770 +set_property -dict {LOC AC37} [get_ports qsfp_2_mgt_refclk_n] ;# MGTREFCLK0N_125 from U770 +set_property -dict {LOC BE20 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_2_mod_prsnt_n] +set_property -dict {LOC BE21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports qsfp_2_reset_n] +set_property -dict {LOC BD20 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports qsfp_2_lp_mode] +set_property -dict {LOC BD21 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_2_intr_n] +set_property -dict {LOC BF22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports qsfp_2_i2c_scl] +set_property -dict {LOC BE22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports qsfp_2_i2c_sda] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_2_mgt_refclk [get_ports qsfp_2_mgt_refclk_p] + +set_false_path -to [get_ports {qsfp_2_reset_n qsfp_2_lp_mode}] +set_output_delay 0 [get_ports {qsfp_2_reset_n qsfp_2_lp_mode}] +set_false_path -from [get_ports {qsfp_2_mod_prsnt_n qsfp_2_intr_n}] +set_input_delay 0 [get_ports {qsfp_2_mod_prsnt_n qsfp_2_intr_n}] + +set_false_path -to [get_ports {qsfp_2_i2c_scl qsfp_2_i2c_sda}] +set_output_delay 0 [get_ports {qsfp_2_i2c_scl qsfp_2_i2c_sda}] +set_false_path -from [get_ports {qsfp_2_i2c_scl qsfp_2_i2c_sda}] +set_input_delay 0 [get_ports {qsfp_2_i2c_scl qsfp_2_i2c_sda}] + +set_property -dict {LOC K43 } [get_ports qsfp_3_rx_0_p] ;# MGTYRXP3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC K44 } [get_ports qsfp_3_rx_0_n] ;# MGTYRXN3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC J40 } [get_ports qsfp_3_tx_0_p] ;# MGTYTXP3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC J41 } [get_ports qsfp_3_tx_0_n] ;# MGTYTXN3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC M43 } [get_ports qsfp_3_rx_1_p] ;# MGTYRXP1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC M44 } [get_ports qsfp_3_rx_1_n] ;# MGTYRXN1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC M38 } [get_ports qsfp_3_tx_1_p] ;# MGTYTXP1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC M39 } [get_ports qsfp_3_tx_1_n] ;# MGTYTXN1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC L45 } [get_ports qsfp_3_rx_2_p] ;# MGTYRXP2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC L46 } [get_ports qsfp_3_rx_2_n] ;# MGTYRXN2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC L40 } [get_ports qsfp_3_tx_2_p] ;# MGTYTXP2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC L41 } [get_ports qsfp_3_tx_2_n] ;# MGTYTXN2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC N45 } [get_ports qsfp_3_rx_3_p] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC N46 } [get_ports qsfp_3_rx_3_n] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC N40 } [get_ports qsfp_3_tx_3_p] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC N41 } [get_ports qsfp_3_tx_3_n] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC R36 } [get_ports qsfp_3_mgt_refclk_p] ;# MGTREFCLK0P_127 from U770 +set_property -dict {LOC R37 } [get_ports qsfp_3_mgt_refclk_n] ;# MGTREFCLK0N_127 from U770 +set_property -dict {LOC AR21 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_3_mod_prsnt_n] +set_property -dict {LOC AT24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports qsfp_3_reset_n] +set_property -dict {LOC AU24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports qsfp_3_lp_mode] +set_property -dict {LOC AT23 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_3_intr_n] +set_property -dict {LOC AR23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports qsfp_3_i2c_scl] +set_property -dict {LOC AT22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports qsfp_3_i2c_sda] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_3_mgt_refclk [get_ports qsfp_3_mgt_refclk_p] + +set_false_path -to [get_ports {qsfp_3_reset_n qsfp_3_lp_mode}] +set_output_delay 0 [get_ports {qsfp_3_reset_n qsfp_3_lp_mode}] +set_false_path -from [get_ports {qsfp_3_mod_prsnt_n qsfp_3_intr_n}] +set_input_delay 0 [get_ports {qsfp_3_mod_prsnt_n qsfp_3_intr_n}] + +set_false_path -to [get_ports {qsfp_3_i2c_scl qsfp_3_i2c_sda}] +set_output_delay 0 [get_ports {qsfp_3_i2c_scl qsfp_3_i2c_sda}] +set_false_path -from [get_ports {qsfp_3_i2c_scl qsfp_3_i2c_sda}] +set_input_delay 0 [get_ports {qsfp_3_i2c_scl qsfp_3_i2c_sda}] + +# PCIe Interface +set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AG4 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AG3 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AG9 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AG8 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AH2 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AH1 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AH7 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AH6 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AJ9 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AJ8 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AK7 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AK6 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AL4 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AL3 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AL9 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AL8 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AM7 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AM6 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AN4 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AN3 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AN9 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AN8 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +set_property -dict {LOC AP7 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +set_property -dict {LOC AP6 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +set_property -dict {LOC AR4 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +set_property -dict {LOC AR3 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +set_property -dict {LOC AR9 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +set_property -dict {LOC AR8 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +set_property -dict {LOC AT2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +set_property -dict {LOC AT1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +set_property -dict {LOC AT7 } [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +set_property -dict {LOC AT6 } [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +set_property -dict {LOC AU4 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +set_property -dict {LOC AU3 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +set_property -dict {LOC AU9 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +set_property -dict {LOC AU8 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +set_property -dict {LOC AV2 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC AV1 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC AV7 } [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC AV6 } [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC AW4 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC AW3 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC BB5 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC BB4 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC BA2 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC BA1 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC BD5 } [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC BD4 } [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC BC2 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC BC1 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC BF5 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC BF4 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC AT11} [get_ports pcie_refclk_0_p] ;# MGTREFCLK0P_225 +set_property -dict {LOC AT10} [get_ports pcie_refclk_0_n] ;# MGTREFCLK0N_225 +#set_property -dict {LOC AH11} [get_ports pcie_refclk_1_p] ;# MGTREFCLK0P_227 +#set_property -dict {LOC AH10} [get_ports pcie_refclk_1_n] ;# MGTREFCLK0N_227 +set_property -dict {LOC AR26 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_rst_n] + +# 100 MHz MGT reference clock +create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_refclk_0_p] +#create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_refclk_1_p] + +set_false_path -from [get_ports {pcie_rst_n}] +set_input_delay 0 [get_ports {pcie_rst_n}] diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/fpga/Makefile b/fpga/mqnic/fb4CGg3/fpga_25g/fpga/Makefile new file mode 100644 index 000000000..b50949749 --- /dev/null +++ b/fpga/mqnic/fb4CGg3/fpga_25g/fpga/Makefile @@ -0,0 +1,160 @@ + +# FPGA settings +FPGA_PART = xcvu9p-flgb2104-2-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +# Files for synthesis +SYN_FILES = rtl/fpga.v +SYN_FILES += rtl/fpga_core.v +SYN_FILES += rtl/sync_signal.v +SYN_FILES += rtl/common/mqnic_core_pcie_us.v +SYN_FILES += rtl/common/mqnic_core_pcie.v +SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_port_tx.v +SYN_FILES += rtl/common/mqnic_port_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v +SYN_FILES += rtl/common/mqnic_l2_egress.v +SYN_FILES += rtl/common/mqnic_l2_ingress.v +SYN_FILES += rtl/common/mqnic_rx_queue_map.v +SYN_FILES += rtl/common/mqnic_ptp.v +SYN_FILES += rtl/common/mqnic_ptp_clock.v +SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v +SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v +SYN_FILES += rtl/common/cpl_write.v +SYN_FILES += rtl/common/cpl_op_mux.v +SYN_FILES += rtl/common/desc_fetch.v +SYN_FILES += rtl/common/desc_op_mux.v +SYN_FILES += rtl/common/event_mux.v +SYN_FILES += rtl/common/queue_manager.v +SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v +SYN_FILES += rtl/common/tx_engine.v +SYN_FILES += rtl/common/rx_engine.v +SYN_FILES += rtl/common/tx_checksum.v +SYN_FILES += rtl/common/rx_hash.v +SYN_FILES += rtl/common/rx_checksum.v +SYN_FILES += rtl/common/rb_drp.v +SYN_FILES += rtl/common/eth_xcvr_phy_10g_gty_wrapper.v +SYN_FILES += rtl/common/eth_xcvr_phy_10g_gty_quad_wrapper.v +SYN_FILES += rtl/common/stats_counter.v +SYN_FILES += rtl/common/stats_collect.v +SYN_FILES += rtl/common/stats_pcie_if.v +SYN_FILES += rtl/common/stats_pcie_tlp.v +SYN_FILES += rtl/common/stats_dma_if_pcie.v +SYN_FILES += rtl/common/stats_dma_latency.v +SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v +SYN_FILES += rtl/common/tx_scheduler_rr.v +SYN_FILES += rtl/common/tdma_scheduler.v +SYN_FILES += rtl/common/tdma_ber.v +SYN_FILES += rtl/common/tdma_ber_ch.v +SYN_FILES += rtl/common/led_sreg_driver.v +SYN_FILES += lib/eth/rtl/eth_mac_10g.v +SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v +SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v +SYN_FILES += lib/eth/rtl/eth_phy_10g.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v +SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v +SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v +SYN_FILES += lib/eth/rtl/lfsr.v +SYN_FILES += lib/eth/rtl/ptp_clock.v +SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_perout.v +SYN_FILES += lib/axi/rtl/axil_interconnect.v +SYN_FILES += lib/axi/rtl/axil_crossbar.v +SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v +SYN_FILES += lib/axi/rtl/axil_crossbar_rd.v +SYN_FILES += lib/axi/rtl/axil_crossbar_wr.v +SYN_FILES += lib/axi/rtl/axil_reg_if.v +SYN_FILES += lib/axi/rtl/axil_reg_if_rd.v +SYN_FILES += lib/axi/rtl/axil_reg_if_wr.v +SYN_FILES += lib/axi/rtl/axil_register_rd.v +SYN_FILES += lib/axi/rtl/axil_register_wr.v +SYN_FILES += lib/axi/rtl/arbiter.v +SYN_FILES += lib/axi/rtl/priority_encoder.v +SYN_FILES += lib/axis/rtl/axis_adapter.v +SYN_FILES += lib/axis/rtl/axis_arb_mux.v +SYN_FILES += lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v +SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v +SYN_FILES += lib/axis/rtl/axis_register.v +SYN_FILES += lib/axis/rtl/sync_reset.v +SYN_FILES += lib/pcie/rtl/pcie_axil_master.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v +SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v +SYN_FILES += lib/pcie/rtl/dma_if_pcie.v +SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v +SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v +SYN_FILES += lib/pcie/rtl/dma_if_mux.v +SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v +SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v +SYN_FILES += lib/pcie/rtl/dma_if_desc_mux.v +SYN_FILES += lib/pcie/rtl/dma_ram_demux_rd.v +SYN_FILES += lib/pcie/rtl/dma_ram_demux_wr.v +SYN_FILES += lib/pcie/rtl/dma_psdpram.v +SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v +SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v +SYN_FILES += lib/pcie/rtl/pcie_us_if.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v +SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v +SYN_FILES += lib/pcie/rtl/pulse_merge.v + +# XDC files +XDC_FILES = fpga.xdc +XDC_FILES += placement.xdc +XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl +XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl +XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl +XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl +XDC_FILES += ../../../common/syn/vivado/led_sreg_driver.tcl + +# IP +IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl +IP_TCL_FILES += ip/eth_xcvr_gty.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/fpga/config.tcl b/fpga/mqnic/fb4CGg3/fpga_25g/fpga/config.tcl new file mode 100644 index 000000000..faf6d9dc3 --- /dev/null +++ b/fpga/mqnic/fb4CGg3/fpga_25g/fpga/config.tcl @@ -0,0 +1,290 @@ +# Copyright 2021, The Regents of the University of California. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +# OF SUCH DAMAGE. +# +# The views and conclusions contained in the software and documentation are those +# of the authors and should not be interpreted as representing official policies, +# either expressed or implied, of The Regents of the University of California. + +set params [dict create] + +# collect build information +set build_date [clock seconds] +set git_hash 00000000 +set git_tag "" + +if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } { + puts "Error running git or project not under version control" +} + +if { [catch {set git_tag [exec git describe --tags HEAD]}] } { + puts "Error running git, project not under version control, or no tag found" +} + +puts "Build date: ${build_date}" +puts "Git hash: ${git_hash}" +puts "Git tag: ${git_tag}" + +if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } { + puts "Failed to extract version from git tag" + set tag_ver 0.0.1 +} + +puts "Tag version: ${tag_ver}" + +# FW and board IDs +set fpga_id [expr 0x4B31093] +set fw_id [expr 0x00000000] +set fw_ver $tag_ver +set board_vendor_id [expr 0x1c2c] +set board_device_id [expr 0x9403] +set board_ver 1.0 +set release_info [expr 0x00000000] + +# PCIe IDs +set pcie_vendor_id [expr 0x1234] +set pcie_device_id [expr 0x1001] +set pcie_class_code [expr 0x020000] +set pcie_revision_id [expr 0x00] +set pcie_subsystem_vendor_id $board_vendor_id +set pcie_subsystem_device_id $board_device_id + +# FW ID block +dict set params FPGA_ID [format "32'h%08x" $fpga_id] +dict set params FW_ID [format "32'h%08x" $fw_id] +dict set params FW_VER [format "32'h%02x%02x%02x%02x" {*}[split $fw_ver .-] 0 0 0 0] +dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id] +dict set params BOARD_VER [format "32'h%02x%02x%02x%02x" {*}[split $board_ver .-] 0 0 0 0] +dict set params BUILD_DATE "32'd${build_date}" +dict set params GIT_HASH "32'h${git_hash}" +dict set params RELEASE_INFO [format "32'h%08x" $release_info] + +# Board configuration +dict set params TDMA_BER_ENABLE "0" + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {25.78125} +set eth_xcvr_sec_line_rate {10.3125} +set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +# Structural configuration +dict set params IF_COUNT "4" +dict set params PORTS_PER_IF "1" +dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] +dict set params PORT_MASK "0" + +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + +# PTP configuration +dict set params PTP_CLOCK_PIPELINE "0" +dict set params PTP_CLOCK_CDC_PIPELINE "0" +dict set params PTP_PORT_CDC_PIPELINE "0" +dict set params PTP_PEROUT_ENABLE "1" +dict set params PTP_PEROUT_COUNT "1" + +# Queue manager configuration +dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" +dict set params TX_QUEUE_OP_TABLE_SIZE "32" +dict set params RX_QUEUE_OP_TABLE_SIZE "32" +dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] +dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] +dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params TX_QUEUE_INDEX_WIDTH "13" +dict set params RX_QUEUE_INDEX_WIDTH "8" +dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] +dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] +dict set params EVENT_QUEUE_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] +dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] +dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] +dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] + +# TX and RX engine configuration +dict set params TX_DESC_TABLE_SIZE "32" +dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] + +# Scheduler configuration +dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] +dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE] +dict set params TDMA_INDEX_WIDTH "6" + +# Interface configuration +dict set params PTP_TS_ENABLE "1" +dict set params TX_CPL_FIFO_DEPTH "32" +dict set params TX_CHECKSUM_ENABLE "1" +dict set params RX_HASH_ENABLE "1" +dict set params RX_CHECKSUM_ENABLE "1" +dict set params TX_FIFO_DEPTH "32768" +dict set params RX_FIFO_DEPTH "32768" +dict set params MAX_TX_SIZE "9214" +dict set params MAX_RX_SIZE "9214" +dict set params TX_RAM_SIZE "32768" +dict set params RX_RAM_SIZE "131072" + +# Application block configuration +dict set params APP_ID "32'h00000000" +dict set params APP_ENABLE "0" +dict set params APP_CTRL_ENABLE "1" +dict set params APP_DMA_ENABLE "1" +dict set params APP_AXIS_DIRECT_ENABLE "1" +dict set params APP_AXIS_SYNC_ENABLE "1" +dict set params APP_AXIS_IF_ENABLE "1" +dict set params APP_STAT_ENABLE "1" + +# DMA interface configuration +dict set params DMA_IMM_ENABLE "0" +dict set params DMA_IMM_WIDTH "32" +dict set params DMA_LEN_WIDTH "16" +dict set params DMA_TAG_WIDTH "16" +dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))] +dict set params RAM_PIPELINE "2" + +# Interrupt configuration +dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] + +# AXI lite interface configuration (control) +dict set params AXIL_CTRL_DATA_WIDTH "32" +dict set params AXIL_CTRL_ADDR_WIDTH "25" + +# AXI lite interface configuration (application control) +dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH] +dict set params AXIL_APP_CTRL_ADDR_WIDTH "24" + +# Ethernet interface configuration +dict set params AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE [expr max($eth_xcvr_line_rate, $eth_xcvr_sec_line_rate) > 16] +dict set params AXIS_ETH_TX_PIPELINE "4" +dict set params AXIS_ETH_TX_FIFO_PIPELINE "4" +dict set params AXIS_ETH_TX_TS_PIPELINE "4" +dict set params AXIS_ETH_RX_PIPELINE "4" +dict set params AXIS_ETH_RX_FIFO_PIPELINE "4" + +# Statistics counter subsystem +dict set params STAT_ENABLE "1" +dict set params STAT_DMA_ENABLE "1" +dict set params STAT_PCIE_ENABLE "1" +dict set params STAT_INC_WIDTH "24" +dict set params STAT_ID_WIDTH "12" + +# PCIe IP core settings +set pcie [get_ips pcie4_uscale_plus_0] + +# Internal interface settings +dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] + +# configure BAR settings +proc configure_bar {pcie pf bar aperture} { + set size_list {Bytes Kilobytes Megabytes Gigabytes Terabytes Petabytes Exabytes} + for { set i 0 } { $i < [llength $size_list] } { incr i } { + set scale [lindex $size_list $i] + + if {$aperture > 0 && $aperture < ($i+1)*10} { + set size [expr 1 << $aperture - ($i*10)] + + puts "${pcie} PF${pf} BAR${bar}: aperture ${aperture} bits ($size $scale)" + + set pcie_config [dict create] + + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_enabled" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_type" {Memory} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_64bit" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_prefetchable" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_scale" $scale + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_size" $size + + set_property -dict $pcie_config $pcie + + return + } + } + puts "${pcie} PF${pf} BAR${bar}: disabled" + set_property "CONFIG.pf${pf}_bar${bar}_enabled" {false} $pcie +} + +# Control BAR (BAR 0) +configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] + +# Application BAR (BAR 2) +configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] + +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + +# Transceiver configuration +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gty_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gty_channel] + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +# set_property generic $param_list [current_fileset] +set_property generic $param_list [get_filesets sources_1] diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/Makefile new file mode 100644 index 000000000..b50949749 --- /dev/null +++ b/fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/Makefile @@ -0,0 +1,160 @@ + +# FPGA settings +FPGA_PART = xcvu9p-flgb2104-2-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +# Files for synthesis +SYN_FILES = rtl/fpga.v +SYN_FILES += rtl/fpga_core.v +SYN_FILES += rtl/sync_signal.v +SYN_FILES += rtl/common/mqnic_core_pcie_us.v +SYN_FILES += rtl/common/mqnic_core_pcie.v +SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v +SYN_FILES += rtl/common/mqnic_interface.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_port_tx.v +SYN_FILES += rtl/common/mqnic_port_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v +SYN_FILES += rtl/common/mqnic_l2_egress.v +SYN_FILES += rtl/common/mqnic_l2_ingress.v +SYN_FILES += rtl/common/mqnic_rx_queue_map.v +SYN_FILES += rtl/common/mqnic_ptp.v +SYN_FILES += rtl/common/mqnic_ptp_clock.v +SYN_FILES += rtl/common/mqnic_ptp_perout.v +SYN_FILES += rtl/common/mqnic_rb_clk_info.v +SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v +SYN_FILES += rtl/common/cpl_write.v +SYN_FILES += rtl/common/cpl_op_mux.v +SYN_FILES += rtl/common/desc_fetch.v +SYN_FILES += rtl/common/desc_op_mux.v +SYN_FILES += rtl/common/event_mux.v +SYN_FILES += rtl/common/queue_manager.v +SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v +SYN_FILES += rtl/common/tx_engine.v +SYN_FILES += rtl/common/rx_engine.v +SYN_FILES += rtl/common/tx_checksum.v +SYN_FILES += rtl/common/rx_hash.v +SYN_FILES += rtl/common/rx_checksum.v +SYN_FILES += rtl/common/rb_drp.v +SYN_FILES += rtl/common/eth_xcvr_phy_10g_gty_wrapper.v +SYN_FILES += rtl/common/eth_xcvr_phy_10g_gty_quad_wrapper.v +SYN_FILES += rtl/common/stats_counter.v +SYN_FILES += rtl/common/stats_collect.v +SYN_FILES += rtl/common/stats_pcie_if.v +SYN_FILES += rtl/common/stats_pcie_tlp.v +SYN_FILES += rtl/common/stats_dma_if_pcie.v +SYN_FILES += rtl/common/stats_dma_latency.v +SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v +SYN_FILES += rtl/common/tx_scheduler_rr.v +SYN_FILES += rtl/common/tdma_scheduler.v +SYN_FILES += rtl/common/tdma_ber.v +SYN_FILES += rtl/common/tdma_ber_ch.v +SYN_FILES += rtl/common/led_sreg_driver.v +SYN_FILES += lib/eth/rtl/eth_mac_10g.v +SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v +SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v +SYN_FILES += lib/eth/rtl/eth_phy_10g.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v +SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v +SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v +SYN_FILES += lib/eth/rtl/lfsr.v +SYN_FILES += lib/eth/rtl/ptp_clock.v +SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_perout.v +SYN_FILES += lib/axi/rtl/axil_interconnect.v +SYN_FILES += lib/axi/rtl/axil_crossbar.v +SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v +SYN_FILES += lib/axi/rtl/axil_crossbar_rd.v +SYN_FILES += lib/axi/rtl/axil_crossbar_wr.v +SYN_FILES += lib/axi/rtl/axil_reg_if.v +SYN_FILES += lib/axi/rtl/axil_reg_if_rd.v +SYN_FILES += lib/axi/rtl/axil_reg_if_wr.v +SYN_FILES += lib/axi/rtl/axil_register_rd.v +SYN_FILES += lib/axi/rtl/axil_register_wr.v +SYN_FILES += lib/axi/rtl/arbiter.v +SYN_FILES += lib/axi/rtl/priority_encoder.v +SYN_FILES += lib/axis/rtl/axis_adapter.v +SYN_FILES += lib/axis/rtl/axis_arb_mux.v +SYN_FILES += lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v +SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v +SYN_FILES += lib/axis/rtl/axis_register.v +SYN_FILES += lib/axis/rtl/sync_reset.v +SYN_FILES += lib/pcie/rtl/pcie_axil_master.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v +SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v +SYN_FILES += lib/pcie/rtl/pcie_msix.v +SYN_FILES += lib/pcie/rtl/irq_rate_limit.v +SYN_FILES += lib/pcie/rtl/dma_if_pcie.v +SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v +SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v +SYN_FILES += lib/pcie/rtl/dma_if_mux.v +SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v +SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v +SYN_FILES += lib/pcie/rtl/dma_if_desc_mux.v +SYN_FILES += lib/pcie/rtl/dma_ram_demux_rd.v +SYN_FILES += lib/pcie/rtl/dma_ram_demux_wr.v +SYN_FILES += lib/pcie/rtl/dma_psdpram.v +SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v +SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v +SYN_FILES += lib/pcie/rtl/pcie_us_if.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v +SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v +SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v +SYN_FILES += lib/pcie/rtl/pulse_merge.v + +# XDC files +XDC_FILES = fpga.xdc +XDC_FILES += placement.xdc +XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl +XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl +XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl +XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl +XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl +XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl +XDC_FILES += ../../../common/syn/vivado/led_sreg_driver.tcl + +# IP +IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl +IP_TCL_FILES += ip/eth_xcvr_gty.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/config.tcl new file mode 100644 index 000000000..5f9b09013 --- /dev/null +++ b/fpga/mqnic/fb4CGg3/fpga_25g/fpga_10g/config.tcl @@ -0,0 +1,290 @@ +# Copyright 2021, The Regents of the University of California. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +# OF SUCH DAMAGE. +# +# The views and conclusions contained in the software and documentation are those +# of the authors and should not be interpreted as representing official policies, +# either expressed or implied, of The Regents of the University of California. + +set params [dict create] + +# collect build information +set build_date [clock seconds] +set git_hash 00000000 +set git_tag "" + +if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } { + puts "Error running git or project not under version control" +} + +if { [catch {set git_tag [exec git describe --tags HEAD]}] } { + puts "Error running git, project not under version control, or no tag found" +} + +puts "Build date: ${build_date}" +puts "Git hash: ${git_hash}" +puts "Git tag: ${git_tag}" + +if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } { + puts "Failed to extract version from git tag" + set tag_ver 0.0.1 +} + +puts "Tag version: ${tag_ver}" + +# FW and board IDs +set fpga_id [expr 0x4B31093] +set fw_id [expr 0x00000000] +set fw_ver $tag_ver +set board_vendor_id [expr 0x1c2c] +set board_device_id [expr 0x9403] +set board_ver 1.0 +set release_info [expr 0x00000000] + +# PCIe IDs +set pcie_vendor_id [expr 0x1234] +set pcie_device_id [expr 0x1001] +set pcie_class_code [expr 0x020000] +set pcie_revision_id [expr 0x00] +set pcie_subsystem_vendor_id $board_vendor_id +set pcie_subsystem_device_id $board_device_id + +# FW ID block +dict set params FPGA_ID [format "32'h%08x" $fpga_id] +dict set params FW_ID [format "32'h%08x" $fw_id] +dict set params FW_VER [format "32'h%02x%02x%02x%02x" {*}[split $fw_ver .-] 0 0 0 0] +dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id] +dict set params BOARD_VER [format "32'h%02x%02x%02x%02x" {*}[split $board_ver .-] 0 0 0 0] +dict set params BUILD_DATE "32'd${build_date}" +dict set params GIT_HASH "32'h${git_hash}" +dict set params RELEASE_INFO [format "32'h%08x" $release_info] + +# Board configuration +dict set params TDMA_BER_ENABLE "0" + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {10.3125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {161.1328125} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +# Structural configuration +dict set params IF_COUNT "4" +dict set params PORTS_PER_IF "1" +dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF] +dict set params PORT_MASK "0" + +# Clock configuration +dict set params CLK_PERIOD_NS_NUM "4" +dict set params CLK_PERIOD_NS_DENOM "1" + +# PTP configuration +dict set params PTP_CLOCK_PIPELINE "0" +dict set params PTP_CLOCK_CDC_PIPELINE "0" +dict set params PTP_PORT_CDC_PIPELINE "0" +dict set params PTP_PEROUT_ENABLE "1" +dict set params PTP_PEROUT_COUNT "1" + +# Queue manager configuration +dict set params EVENT_QUEUE_OP_TABLE_SIZE "32" +dict set params TX_QUEUE_OP_TABLE_SIZE "32" +dict set params RX_QUEUE_OP_TABLE_SIZE "32" +dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE] +dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE] +dict set params EVENT_QUEUE_INDEX_WIDTH "6" +dict set params TX_QUEUE_INDEX_WIDTH "13" +dict set params RX_QUEUE_INDEX_WIDTH "8" +dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH] +dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH] +dict set params EVENT_QUEUE_PIPELINE "3" +dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)] +dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)] +dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE] +dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE] + +# TX and RX engine configuration +dict set params TX_DESC_TABLE_SIZE "32" +dict set params RX_DESC_TABLE_SIZE "32" +dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)] + +# Scheduler configuration +dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE] +dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE] +dict set params TDMA_INDEX_WIDTH "6" + +# Interface configuration +dict set params PTP_TS_ENABLE "1" +dict set params TX_CPL_FIFO_DEPTH "32" +dict set params TX_CHECKSUM_ENABLE "1" +dict set params RX_HASH_ENABLE "1" +dict set params RX_CHECKSUM_ENABLE "1" +dict set params TX_FIFO_DEPTH "32768" +dict set params RX_FIFO_DEPTH "32768" +dict set params MAX_TX_SIZE "9214" +dict set params MAX_RX_SIZE "9214" +dict set params TX_RAM_SIZE "32768" +dict set params RX_RAM_SIZE "32768" + +# Application block configuration +dict set params APP_ID "32'h00000000" +dict set params APP_ENABLE "0" +dict set params APP_CTRL_ENABLE "1" +dict set params APP_DMA_ENABLE "1" +dict set params APP_AXIS_DIRECT_ENABLE "1" +dict set params APP_AXIS_SYNC_ENABLE "1" +dict set params APP_AXIS_IF_ENABLE "1" +dict set params APP_STAT_ENABLE "1" + +# DMA interface configuration +dict set params DMA_IMM_ENABLE "0" +dict set params DMA_IMM_WIDTH "32" +dict set params DMA_LEN_WIDTH "16" +dict set params DMA_TAG_WIDTH "16" +dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))] +dict set params RAM_PIPELINE "2" + +# Interrupt configuration +dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH] + +# AXI lite interface configuration (control) +dict set params AXIL_CTRL_DATA_WIDTH "32" +dict set params AXIL_CTRL_ADDR_WIDTH "25" + +# AXI lite interface configuration (application control) +dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH] +dict set params AXIL_APP_CTRL_ADDR_WIDTH "24" + +# Ethernet interface configuration +dict set params AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE [expr max($eth_xcvr_line_rate, $eth_xcvr_sec_line_rate) > 16] +dict set params AXIS_ETH_TX_PIPELINE "4" +dict set params AXIS_ETH_TX_FIFO_PIPELINE "4" +dict set params AXIS_ETH_TX_TS_PIPELINE "4" +dict set params AXIS_ETH_RX_PIPELINE "4" +dict set params AXIS_ETH_RX_FIFO_PIPELINE "4" + +# Statistics counter subsystem +dict set params STAT_ENABLE "1" +dict set params STAT_DMA_ENABLE "1" +dict set params STAT_PCIE_ENABLE "1" +dict set params STAT_INC_WIDTH "24" +dict set params STAT_ID_WIDTH "12" + +# PCIe IP core settings +set pcie [get_ips pcie4_uscale_plus_0] + +# Internal interface settings +dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] + +# configure BAR settings +proc configure_bar {pcie pf bar aperture} { + set size_list {Bytes Kilobytes Megabytes Gigabytes Terabytes Petabytes Exabytes} + for { set i 0 } { $i < [llength $size_list] } { incr i } { + set scale [lindex $size_list $i] + + if {$aperture > 0 && $aperture < ($i+1)*10} { + set size [expr 1 << $aperture - ($i*10)] + + puts "${pcie} PF${pf} BAR${bar}: aperture ${aperture} bits ($size $scale)" + + set pcie_config [dict create] + + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_enabled" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_type" {Memory} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_64bit" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_prefetchable" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_scale" $scale + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_size" $size + + set_property -dict $pcie_config $pcie + + return + } + } + puts "${pcie} PF${pf} BAR${bar}: disabled" + set_property "CONFIG.pf${pf}_bar${bar}_enabled" {false} $pcie +} + +# Control BAR (BAR 0) +configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] + +# Application BAR (BAR 2) +configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] + +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + +# Transceiver configuration +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gty_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gty_channel] + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +# set_property generic $param_list [current_fileset] +set_property generic $param_list [get_filesets sources_1] diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/ip/eth_xcvr_gty.tcl b/fpga/mqnic/fb4CGg3/fpga_25g/ip/eth_xcvr_gty.tcl new file mode 100644 index 000000000..52254f917 --- /dev/null +++ b/fpga/mqnic/fb4CGg3/fpga_25g/ip/eth_xcvr_gty.tcl @@ -0,0 +1,129 @@ +# Copyright 2022, The Regents of the University of California. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +# OF SUCH DAMAGE. +# +# The views and conclusions contained in the software and documentation are those +# of the authors and should not be interpreted as representing official policies, +# either expressed or implied, of The Regents of the University of California. + +set base_name {eth_xcvr_gty} + +set preset {GTY-10GBASE-R} + +set freerun_freq {125} +set line_rate {25.78125} +set sec_line_rate {10.3125} +set refclk_freq {161.1328125} +set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] +set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] +set user_data_width {64} +set int_data_width $user_data_width +set rx_eq_mode {DFE} +set extra_ports [list] +set extra_pll_ports [list] +# DRP connections +lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out +lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out +# PLL reset and power down +lappend extra_pll_ports qpll0reset_in qpll1reset_in +lappend extra_pll_ports qpll0pd_in qpll1pd_in +# PLL clocking +lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out +lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out +# channel reset +lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out +lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out +# channel power down +lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in +# channel clock selection +lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in +# channel polarity +lappend extra_ports txpolarity_in rxpolarity_in +# channel TX driver +lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in +# channel CDR +lappend extra_ports rxcdrlock_out rxcdrhold_in +# channel EQ +lappend extra_ports rxlpmen_in +# channel digital monitor +lappend extra_ports dmonitorout_out +# channel PRBS +lappend extra_ports txprbsforceerr_in txprbssel_in rxprbscntreset_in rxprbssel_in rxprbserr_out rxprbslocked_out +# channel eye scan +lappend extra_ports eyescandataerror_out +# channel loopback +lappend extra_ports loopback_in + +set config [dict create] + +dict set config TX_LINE_RATE $line_rate +dict set config TX_REFCLK_FREQUENCY $refclk_freq +dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn +dict set config TX_USER_DATA_WIDTH $user_data_width +dict set config TX_INT_DATA_WIDTH $int_data_width +dict set config RX_LINE_RATE $line_rate +dict set config RX_REFCLK_FREQUENCY $refclk_freq +dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn +dict set config RX_USER_DATA_WIDTH $user_data_width +dict set config RX_INT_DATA_WIDTH $int_data_width +dict set config RX_EQ_MODE $rx_eq_mode +if {$sec_line_rate != 0} { + dict set config SECONDARY_QPLL_ENABLE true + dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn + dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate + dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq +} else { + dict set config SECONDARY_QPLL_ENABLE false +} +dict set config ENABLE_OPTIONAL_PORTS $extra_ports +dict set config LOCATE_COMMON {CORE} +dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN} +dict set config LOCATE_TX_USER_CLOCKING {CORE} +dict set config LOCATE_RX_USER_CLOCKING {CORE} +dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE} +dict set config FREERUN_FREQUENCY $freerun_freq +dict set config DISABLE_LOC_XDC {1} + +proc create_gtwizard_ip {name preset config} { + create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name + set ip [get_ips $name] + set_property CONFIG.preset $preset $ip + set config_list {} + dict for {name value} $config { + lappend config_list "CONFIG.${name}" $value + } + set_property -dict $config_list $ip +} + +# variant with channel and common +dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports] +dict set config LOCATE_COMMON {CORE} + +create_gtwizard_ip "${base_name}_full" $preset $config + +# variant with channel only +dict set config ENABLE_OPTIONAL_PORTS $extra_ports +dict set config LOCATE_COMMON {EXAMPLE_DESIGN} + +create_gtwizard_ip "${base_name}_channel" $preset $config diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/ip/pcie4_uscale_plus_0.tcl b/fpga/mqnic/fb4CGg3/fpga_25g/ip/pcie4_uscale_plus_0.tcl new file mode 100644 index 000000000..b9e6322e7 --- /dev/null +++ b/fpga/mqnic/fb4CGg3/fpga_25g/ip/pcie4_uscale_plus_0.tcl @@ -0,0 +1,33 @@ + +create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0 + +set_property -dict [list \ + CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ + CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \ + CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \ + CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \ + CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \ + CONFIG.axisten_if_enable_client_tag {true} \ + CONFIG.axisten_if_width {512_bit} \ + CONFIG.extended_tag_field {true} \ + CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ + CONFIG.axisten_freq {250} \ + CONFIG.PF0_CLASS_CODE {020000} \ + CONFIG.PF0_DEVICE_ID {1001} \ + CONFIG.PF0_SUBSYSTEM_ID {9403} \ + CONFIG.PF0_SUBSYSTEM_VENDOR_ID {1c2c} \ + CONFIG.pf0_bar0_64bit {true} \ + CONFIG.pf0_bar0_prefetchable {true} \ + CONFIG.pf0_bar0_scale {Megabytes} \ + CONFIG.pf0_bar0_size {16} \ + CONFIG.pf0_msi_enabled {false} \ + CONFIG.pf0_msix_enabled {true} \ + CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \ + CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_1:0} \ + CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00010000} \ + CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_1:0} \ + CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00018000} \ + CONFIG.MSI_X_OPTIONS {MSI-X_External} \ + CONFIG.vendor_id {1234} \ + CONFIG.mode_selection {Advanced} \ +] [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/lib b/fpga/mqnic/fb4CGg3/fpga_25g/lib new file mode 120000 index 000000000..9512b3d5e --- /dev/null +++ b/fpga/mqnic/fb4CGg3/fpga_25g/lib @@ -0,0 +1 @@ +../../../lib/ \ No newline at end of file diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/placement.xdc b/fpga/mqnic/fb4CGg3/fpga_25g/placement.xdc new file mode 100644 index 000000000..36e767287 --- /dev/null +++ b/fpga/mqnic/fb4CGg3/fpga_25g/placement.xdc @@ -0,0 +1,34 @@ +# Placement constraints +create_pblock pblock_slr0 +#add_cells_to_pblock [get_pblocks pblock_slr0] [get_cells -quiet ""] +resize_pblock [get_pblocks pblock_slr0] -add {SLR0} + +create_pblock pblock_slr1 +add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/dma_if_mux_inst"] +add_cells_to_pblock -quiet [get_pblocks pblock_slr1] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/dma_if_mux.dma_if_mux_ctrl_inst"] +add_cells_to_pblock -quiet [get_pblocks pblock_slr1] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/dma_if_mux.dma_if_mux_data_inst"] +add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/interface_rx_inst"] +add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/interface_tx_inst"] +add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/tx_fifo_inst"] +add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/rx_fifo_inst"] +resize_pblock [get_pblocks pblock_slr1] -add {SLR1} + +create_pblock pblock_slr2 +#add_cells_to_pblock [get_pblocks pblock_slr2] [get_cells -quiet ""] +resize_pblock [get_pblocks pblock_slr2] -add {SLR2} + +create_pblock pblock_pcie +add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "pcie4_uscale_plus_inst"] +add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/pcie_if_inst"] +add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_axil_master_inst"] +add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/dma_if_pcie_inst"] +add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/pcie_msix_inst"] +resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y5:CLOCKREGION_X5Y8} + +create_pblock pblock_eth +add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp_0_phy_quad_inst qsfp_1_phy_quad_inst"] +add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/mac[*].eth_mac_inst"] +add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"] +add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"] +add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"] +resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X0Y2:CLOCKREGION_X0Y9} diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/rtl/common b/fpga/mqnic/fb4CGg3/fpga_25g/rtl/common new file mode 120000 index 000000000..449c9409c --- /dev/null +++ b/fpga/mqnic/fb4CGg3/fpga_25g/rtl/common @@ -0,0 +1 @@ +../../../../common/rtl/ \ No newline at end of file diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga.v b/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga.v new file mode 100644 index 000000000..fd453efe6 --- /dev/null +++ b/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga.v @@ -0,0 +1,2252 @@ +/* + +Copyright 2019-2021, The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +The views and conclusions contained in the software and documentation are those +of the authors and should not be interpreted as representing official policies, +either expressed or implied, of The Regents of the University of California. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA top-level module + */ +module fpga # +( + // FW and board IDs + parameter FPGA_ID = 32'h4B31093, + parameter FW_ID = 32'h00000000, + parameter FW_VER = 32'h00_00_01_00, + parameter BOARD_ID = 32'h1c2c_9403, + parameter BOARD_VER = 32'h01_00_00_00, + parameter BUILD_DATE = 32'd602976000, + parameter GIT_HASH = 32'hdce357bf, + parameter RELEASE_INFO = 32'h00000000, + + // Board configuration + parameter TDMA_BER_ENABLE = 0, + + // Structural configuration + parameter IF_COUNT = 2, + parameter PORTS_PER_IF = 1, + parameter SCHED_PER_IF = PORTS_PER_IF, + parameter PORT_MASK = 0, + + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + + // PTP configuration + parameter PTP_CLOCK_PIPELINE = 0, + parameter PTP_CLOCK_CDC_PIPELINE = 0, + parameter PTP_PORT_CDC_PIPELINE = 0, + parameter PTP_PEROUT_ENABLE = 1, + parameter PTP_PEROUT_COUNT = 1, + + // Queue manager configuration + parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, + parameter TX_QUEUE_OP_TABLE_SIZE = 32, + parameter RX_QUEUE_OP_TABLE_SIZE = 32, + parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, + parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, + parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter TX_QUEUE_INDEX_WIDTH = 13, + parameter RX_QUEUE_INDEX_WIDTH = 8, + parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, + parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, + parameter EVENT_QUEUE_PIPELINE = 3, + parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), + parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), + parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, + parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + + // TX and RX engine configuration + parameter TX_DESC_TABLE_SIZE = 32, + parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, + + // Scheduler configuration + parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, + parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE, + parameter TDMA_INDEX_WIDTH = 6, + + // Interface configuration + parameter PTP_TS_ENABLE = 1, + parameter TX_CPL_FIFO_DEPTH = 32, + parameter TX_CHECKSUM_ENABLE = 1, + parameter RX_HASH_ENABLE = 1, + parameter RX_CHECKSUM_ENABLE = 1, + parameter TX_FIFO_DEPTH = 32768, + parameter RX_FIFO_DEPTH = 32768, + parameter MAX_TX_SIZE = 9214, + parameter MAX_RX_SIZE = 9214, + parameter TX_RAM_SIZE = 32768, + parameter RX_RAM_SIZE = 32768, + + // Application block configuration + parameter APP_ID = 32'h00000000, + parameter APP_ENABLE = 0, + parameter APP_CTRL_ENABLE = 1, + parameter APP_DMA_ENABLE = 1, + parameter APP_AXIS_DIRECT_ENABLE = 1, + parameter APP_AXIS_SYNC_ENABLE = 1, + parameter APP_AXIS_IF_ENABLE = 1, + parameter APP_STAT_ENABLE = 1, + + // DMA interface configuration + parameter DMA_IMM_ENABLE = 0, + parameter DMA_IMM_WIDTH = 32, + parameter DMA_LEN_WIDTH = 16, + parameter DMA_TAG_WIDTH = 16, + parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE), + parameter RAM_PIPELINE = 2, + + // PCIe interface configuration + parameter AXIS_PCIE_DATA_WIDTH = 512, + parameter PF_COUNT = 1, + parameter VF_COUNT = 0, + + // Interrupt configuration + parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + + // AXI lite interface configuration (control) + parameter AXIL_CTRL_DATA_WIDTH = 32, + parameter AXIL_CTRL_ADDR_WIDTH = 24, + + // AXI lite interface configuration (application control) + parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, + parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, + + // Ethernet interface configuration + parameter AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE = 1, + parameter AXIS_ETH_TX_PIPELINE = 4, + parameter AXIS_ETH_TX_FIFO_PIPELINE = 4, + parameter AXIS_ETH_TX_TS_PIPELINE = 4, + parameter AXIS_ETH_RX_PIPELINE = 4, + parameter AXIS_ETH_RX_FIFO_PIPELINE = 4, + + // Statistics counter subsystem + parameter STAT_ENABLE = 1, + parameter STAT_DMA_ENABLE = 1, + parameter STAT_PCIE_ENABLE = 1, + parameter STAT_INC_WIDTH = 24, + parameter STAT_ID_WIDTH = 12 +) +( + /* + * Clock: 100MHz + */ + input wire init_clk, + + /* + * GPIO + */ + output wire led_sreg_d, + output wire led_sreg_ld, + output wire led_sreg_clk, + output wire [1:0] led_bmc_red, + output wire [1:0] led_bmc_green, + + input wire pps_in, + output wire pps_out, + + /* + * PCI express + */ + input wire [15:0] pcie_rx_p, + input wire [15:0] pcie_rx_n, + output wire [15:0] pcie_tx_p, + output wire [15:0] pcie_tx_n, + input wire pcie_refclk_0_p, + input wire pcie_refclk_0_n, + input wire pcie_rst_n, + + /* + * Ethernet: QSFP28 + */ + output wire qsfp_0_tx_0_p, + output wire qsfp_0_tx_0_n, + input wire qsfp_0_rx_0_p, + input wire qsfp_0_rx_0_n, + output wire qsfp_0_tx_1_p, + output wire qsfp_0_tx_1_n, + input wire qsfp_0_rx_1_p, + input wire qsfp_0_rx_1_n, + output wire qsfp_0_tx_2_p, + output wire qsfp_0_tx_2_n, + input wire qsfp_0_rx_2_p, + input wire qsfp_0_rx_2_n, + output wire qsfp_0_tx_3_p, + output wire qsfp_0_tx_3_n, + input wire qsfp_0_rx_3_p, + input wire qsfp_0_rx_3_n, + input wire qsfp_0_mgt_refclk_p, + input wire qsfp_0_mgt_refclk_n, + input wire qsfp_0_mod_prsnt_n, + output wire qsfp_0_reset_n, + output wire qsfp_0_lp_mode, + input wire qsfp_0_intr_n, + inout wire qsfp_0_i2c_scl, + inout wire qsfp_0_i2c_sda, + + + output wire qsfp_1_tx_0_p, + output wire qsfp_1_tx_0_n, + input wire qsfp_1_rx_0_p, + input wire qsfp_1_rx_0_n, + output wire qsfp_1_tx_1_p, + output wire qsfp_1_tx_1_n, + input wire qsfp_1_rx_1_p, + input wire qsfp_1_rx_1_n, + output wire qsfp_1_tx_2_p, + output wire qsfp_1_tx_2_n, + input wire qsfp_1_rx_2_p, + input wire qsfp_1_rx_2_n, + output wire qsfp_1_tx_3_p, + output wire qsfp_1_tx_3_n, + input wire qsfp_1_rx_3_p, + input wire qsfp_1_rx_3_n, + input wire qsfp_1_mgt_refclk_p, + input wire qsfp_1_mgt_refclk_n, + input wire qsfp_1_mod_prsnt_n, + output wire qsfp_1_reset_n, + output wire qsfp_1_lp_mode, + input wire qsfp_1_intr_n, + inout wire qsfp_1_i2c_scl, + inout wire qsfp_1_i2c_sda, + + output wire qsfp_2_tx_0_p, + output wire qsfp_2_tx_0_n, + input wire qsfp_2_rx_0_p, + input wire qsfp_2_rx_0_n, + output wire qsfp_2_tx_1_p, + output wire qsfp_2_tx_1_n, + input wire qsfp_2_rx_1_p, + input wire qsfp_2_rx_1_n, + output wire qsfp_2_tx_2_p, + output wire qsfp_2_tx_2_n, + input wire qsfp_2_rx_2_p, + input wire qsfp_2_rx_2_n, + output wire qsfp_2_tx_3_p, + output wire qsfp_2_tx_3_n, + input wire qsfp_2_rx_3_p, + input wire qsfp_2_rx_3_n, + input wire qsfp_2_mgt_refclk_p, + input wire qsfp_2_mgt_refclk_n, + input wire qsfp_2_mod_prsnt_n, + output wire qsfp_2_reset_n, + output wire qsfp_2_lp_mode, + input wire qsfp_2_intr_n, + inout wire qsfp_2_i2c_scl, + inout wire qsfp_2_i2c_sda, + + output wire qsfp_3_tx_0_p, + output wire qsfp_3_tx_0_n, + input wire qsfp_3_rx_0_p, + input wire qsfp_3_rx_0_n, + output wire qsfp_3_tx_1_p, + output wire qsfp_3_tx_1_n, + input wire qsfp_3_rx_1_p, + input wire qsfp_3_rx_1_n, + output wire qsfp_3_tx_2_p, + output wire qsfp_3_tx_2_n, + input wire qsfp_3_rx_2_p, + input wire qsfp_3_rx_2_n, + output wire qsfp_3_tx_3_p, + output wire qsfp_3_tx_3_n, + input wire qsfp_3_rx_3_p, + input wire qsfp_3_rx_3_n, + input wire qsfp_3_mgt_refclk_p, + input wire qsfp_3_mgt_refclk_n, + input wire qsfp_3_mod_prsnt_n, + output wire qsfp_3_reset_n, + output wire qsfp_3_lp_mode, + input wire qsfp_3_intr_n, + inout wire qsfp_3_i2c_scl, + inout wire qsfp_3_i2c_sda +); + +// PTP configuration +parameter PTP_CLK_PERIOD_NS_NUM = 1024; +parameter PTP_CLK_PERIOD_NS_DENOM = 165; +parameter PTP_TS_WIDTH = 96; +parameter PTP_USE_SAMPLE_CLOCK = 1; +parameter IF_PTP_PERIOD_NS = 6'h2; +parameter IF_PTP_PERIOD_FNS = 16'h8F5C; + +// Interface configuration +parameter TX_TAG_WIDTH = 16; + +// PCIe interface configuration +parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); +parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161; +parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137; +parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183; +parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81; +parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256; +parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512; +parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512; +parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512; +parameter RQ_SEQ_NUM_WIDTH = 6; +parameter PCIE_TAG_COUNT = 256; + +// Ethernet interface configuration +parameter XGMII_DATA_WIDTH = 64; +parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8; +parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH; +parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; +parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*(AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE ? 2 : 1); +parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1; +parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1; + +// Clock and reset +wire pcie_user_clk; +wire pcie_user_reset; + +wire init_clk_bufg; + +// Internal 125 MHz clock +wire clk_125mhz_mmcm_out; +wire clk_125mhz_int; +wire rst_125mhz_int; + +wire mmcm_rst = pcie_user_reset; +wire mmcm_locked; +wire mmcm_clkfb; + +BUFG +init_clk_bufg_inst ( + .I(init_clk), + .O(init_clk_bufg) +); + +// MMCM instance +// 50 MHz in, 125 MHz out +// PFD range: 10 MHz to 500 MHz +// VCO range: 800 MHz to 1600 MHz +// M = 20, D = 1 sets Fvco = 1000 MHz (in range) +// Divide by 8 to get output frequency of 125 MHz +MMCME3_BASE #( + .BANDWIDTH("OPTIMIZED"), + .CLKOUT0_DIVIDE_F(8), + .CLKOUT0_DUTY_CYCLE(0.5), + .CLKOUT0_PHASE(0), + .CLKOUT1_DIVIDE(1), + .CLKOUT1_DUTY_CYCLE(0.5), + .CLKOUT1_PHASE(0), + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.5), + .CLKOUT2_PHASE(0), + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.5), + .CLKOUT3_PHASE(0), + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.5), + .CLKOUT4_PHASE(0), + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.5), + .CLKOUT5_PHASE(0), + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.5), + .CLKOUT6_PHASE(0), + .CLKFBOUT_MULT_F(20), + .CLKFBOUT_PHASE(0), + .DIVCLK_DIVIDE(1), + .REF_JITTER1(0.010), + .CLKIN1_PERIOD(20.000), + .STARTUP_WAIT("FALSE"), + .CLKOUT4_CASCADE("FALSE") +) +clk_mmcm_inst ( + .CLKIN1(init_clk_bufg), + .CLKFBIN(mmcm_clkfb), + .RST(mmcm_rst), + .PWRDWN(1'b0), + .CLKOUT0(clk_125mhz_mmcm_out), + .CLKOUT0B(), + .CLKOUT1(), + .CLKOUT1B(), + .CLKOUT2(), + .CLKOUT2B(), + .CLKOUT3(), + .CLKOUT3B(), + .CLKOUT4(), + .CLKOUT5(), + .CLKOUT6(), + .CLKFBOUT(mmcm_clkfb), + .CLKFBOUTB(), + .LOCKED(mmcm_locked) +); + +BUFG +clk_125mhz_bufg_inst ( + .I(clk_125mhz_mmcm_out), + .O(clk_125mhz_int) +); + +sync_reset #( + .N(4) +) +sync_reset_125mhz_inst ( + .clk(clk_125mhz_int), + .rst(~mmcm_locked), + .out(rst_125mhz_int) +); + +// GPIO +wire qsfp_0_mod_prsnt_n_int; +wire qsfp_0_intr_n_int; +wire qsfp_0_i2c_scl_i; +wire qsfp_0_i2c_scl_o; +wire qsfp_0_i2c_scl_t; +wire qsfp_0_i2c_sda_i; +wire qsfp_0_i2c_sda_o; +wire qsfp_0_i2c_sda_t; +wire qsfp_1_mod_prsnt_n_int; +wire qsfp_1_intr_n_int; +wire qsfp_1_i2c_scl_i; +wire qsfp_1_i2c_scl_o; +wire qsfp_1_i2c_scl_t; +wire qsfp_1_i2c_sda_i; +wire qsfp_1_i2c_sda_o; +wire qsfp_1_i2c_sda_t; +wire qsfp_2_mod_prsnt_n_int; +wire qsfp_2_intr_n_int; +wire qsfp_2_i2c_scl_i; +wire qsfp_2_i2c_scl_o; +wire qsfp_2_i2c_scl_t; +wire qsfp_2_i2c_sda_i; +wire qsfp_2_i2c_sda_o; +wire qsfp_2_i2c_sda_t; +wire qsfp_3_mod_prsnt_n_int; +wire qsfp_3_intr_n_int; +wire qsfp_3_i2c_scl_i; +wire qsfp_3_i2c_scl_o; +wire qsfp_3_i2c_scl_t; +wire qsfp_3_i2c_sda_i; +wire qsfp_3_i2c_sda_o; +wire qsfp_3_i2c_sda_t; + +reg qsfp_0_i2c_scl_o_reg; +reg qsfp_0_i2c_scl_t_reg; +reg qsfp_0_i2c_sda_o_reg; +reg qsfp_0_i2c_sda_t_reg; +reg qsfp_1_i2c_scl_o_reg; +reg qsfp_1_i2c_scl_t_reg; +reg qsfp_1_i2c_sda_o_reg; +reg qsfp_1_i2c_sda_t_reg; +reg qsfp_2_i2c_scl_o_reg; +reg qsfp_2_i2c_scl_t_reg; +reg qsfp_2_i2c_sda_o_reg; +reg qsfp_2_i2c_sda_t_reg; +reg qsfp_3_i2c_scl_o_reg; +reg qsfp_3_i2c_scl_t_reg; +reg qsfp_3_i2c_sda_o_reg; +reg qsfp_3_i2c_sda_t_reg; + +always @(posedge pcie_user_clk) begin + qsfp_0_i2c_scl_o_reg <= qsfp_0_i2c_scl_o; + qsfp_0_i2c_scl_t_reg <= qsfp_0_i2c_scl_t; + qsfp_0_i2c_sda_o_reg <= qsfp_0_i2c_sda_o; + qsfp_0_i2c_sda_t_reg <= qsfp_0_i2c_sda_t; + qsfp_1_i2c_scl_o_reg <= qsfp_1_i2c_scl_o; + qsfp_1_i2c_scl_t_reg <= qsfp_1_i2c_scl_t; + qsfp_1_i2c_sda_o_reg <= qsfp_1_i2c_sda_o; + qsfp_1_i2c_sda_t_reg <= qsfp_1_i2c_sda_t; + qsfp_2_i2c_scl_o_reg <= qsfp_2_i2c_scl_o; + qsfp_2_i2c_scl_t_reg <= qsfp_2_i2c_scl_t; + qsfp_2_i2c_sda_o_reg <= qsfp_2_i2c_sda_o; + qsfp_2_i2c_sda_t_reg <= qsfp_2_i2c_sda_t; + qsfp_3_i2c_scl_o_reg <= qsfp_3_i2c_scl_o; + qsfp_3_i2c_scl_t_reg <= qsfp_3_i2c_scl_t; + qsfp_3_i2c_sda_o_reg <= qsfp_3_i2c_sda_o; + qsfp_3_i2c_sda_t_reg <= qsfp_3_i2c_sda_t; +end + +sync_signal #( + .WIDTH(16), + .N(2) +) +sync_signal_inst ( + .clk(pcie_user_clk), + .in({qsfp_0_mod_prsnt_n, qsfp_0_intr_n, qsfp_0_i2c_scl, qsfp_0_i2c_sda, + qsfp_1_mod_prsnt_n, qsfp_1_intr_n, qsfp_1_i2c_scl, qsfp_1_i2c_sda, + qsfp_2_mod_prsnt_n, qsfp_2_intr_n, qsfp_2_i2c_scl, qsfp_2_i2c_sda, + qsfp_3_mod_prsnt_n, qsfp_3_intr_n, qsfp_3_i2c_scl, qsfp_3_i2c_sda}), + .out({qsfp_0_mod_prsnt_n_int, qsfp_0_intr_n_int, qsfp_0_i2c_scl_i, qsfp_0_i2c_sda_i, + qsfp_1_mod_prsnt_n_int, qsfp_1_intr_n_int, qsfp_1_i2c_scl_i, qsfp_1_i2c_sda_i, + qsfp_2_mod_prsnt_n_int, qsfp_2_intr_n_int, qsfp_2_i2c_scl_i, qsfp_2_i2c_sda_i, + qsfp_3_mod_prsnt_n_int, qsfp_3_intr_n_int, qsfp_3_i2c_scl_i, qsfp_3_i2c_sda_i}) +); + +assign qsfp_0_i2c_scl = qsfp_0_i2c_scl_t_reg ? 1'bz : qsfp_0_i2c_scl_o_reg; +assign qsfp_0_i2c_sda = qsfp_0_i2c_sda_t_reg ? 1'bz : qsfp_0_i2c_sda_o_reg; +assign qsfp_1_i2c_scl = qsfp_1_i2c_scl_t_reg ? 1'bz : qsfp_1_i2c_scl_o_reg; +assign qsfp_1_i2c_sda = qsfp_1_i2c_sda_t_reg ? 1'bz : qsfp_1_i2c_sda_o_reg; +assign qsfp_2_i2c_scl = qsfp_2_i2c_scl_t_reg ? 1'bz : qsfp_2_i2c_scl_o_reg; +assign qsfp_2_i2c_sda = qsfp_2_i2c_sda_t_reg ? 1'bz : qsfp_2_i2c_sda_o_reg; +assign qsfp_3_i2c_scl = qsfp_3_i2c_scl_t_reg ? 1'bz : qsfp_3_i2c_scl_o_reg; +assign qsfp_3_i2c_sda = qsfp_3_i2c_sda_t_reg ? 1'bz : qsfp_3_i2c_sda_o_reg; + +wire [15:0] led_red; +wire [15:0] led_green; + +led_sreg_driver #( + .COUNT(16), + .INVERT(0), + .REVERSE(1), + .INTERLEAVE(1), + .PRESCALE(15) +) +led_sreg_driver_inst ( + .clk(pcie_user_clk), + .rst(pcie_user_reset), + + .led_a(led_green), + .led_b(led_red), + + .sreg_d(led_sreg_d), + .sreg_ld(led_sreg_ld), + .sreg_clk(led_sreg_clk) +); + +// PCIe +wire pcie_sys_clk; +wire pcie_sys_clk_gt; + +IBUFDS_GTE4 #( + .REFCLK_HROW_CK_SEL(2'b00) +) +ibufds_gte4_pcie_mgt_refclk_inst ( + .I (pcie_refclk_0_p), + .IB (pcie_refclk_0_n), + .CEB (1'b0), + .O (pcie_sys_clk_gt), + .ODIV2 (pcie_sys_clk) +); + +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rq_tdata; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rq_tkeep; +wire axis_rq_tlast; +wire axis_rq_tready; +wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] axis_rq_tuser; +wire axis_rq_tvalid; + +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep; +wire axis_rc_tlast; +wire axis_rc_tready; +wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser; +wire axis_rc_tvalid; + +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep; +wire axis_cq_tlast; +wire axis_cq_tready; +wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser; +wire axis_cq_tvalid; + +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep; +wire axis_cc_tlast; +wire axis_cc_tready; +wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser; +wire axis_cc_tvalid; + +wire [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num0; +wire pcie_rq_seq_num_vld0; +wire [RQ_SEQ_NUM_WIDTH-1:0] pcie_rq_seq_num1; +wire pcie_rq_seq_num_vld1; + +wire [3:0] pcie_tfc_nph_av; +wire [3:0] pcie_tfc_npd_av; + +wire [2:0] cfg_max_payload; +wire [2:0] cfg_max_read_req; + +wire [9:0] cfg_mgmt_addr; +wire [7:0] cfg_mgmt_function_number; +wire cfg_mgmt_write; +wire [31:0] cfg_mgmt_write_data; +wire [3:0] cfg_mgmt_byte_enable; +wire cfg_mgmt_read; +wire [31:0] cfg_mgmt_read_data; +wire cfg_mgmt_read_write_done; + +wire [7:0] cfg_fc_ph; +wire [11:0] cfg_fc_pd; +wire [7:0] cfg_fc_nph; +wire [11:0] cfg_fc_npd; +wire [7:0] cfg_fc_cplh; +wire [11:0] cfg_fc_cpld; +wire [2:0] cfg_fc_sel; + +wire [3:0] cfg_interrupt_msix_enable; +wire [3:0] cfg_interrupt_msix_mask; +wire [251:0] cfg_interrupt_msix_vf_enable; +wire [251:0] cfg_interrupt_msix_vf_mask; +wire [63:0] cfg_interrupt_msix_address; +wire [31:0] cfg_interrupt_msix_data; +wire cfg_interrupt_msix_int; +wire [1:0] cfg_interrupt_msix_vec_pending; +wire cfg_interrupt_msix_vec_pending_status; +wire cfg_interrupt_msix_sent; +wire cfg_interrupt_msix_fail; +wire [7:0] cfg_interrupt_msi_function_number; + +wire status_error_cor; +wire status_error_uncor; + +// extra register for pcie_user_reset signal +wire pcie_user_reset_int; +(* shreg_extract = "no" *) +reg pcie_user_reset_reg_1 = 1'b1; +(* shreg_extract = "no" *) +reg pcie_user_reset_reg_2 = 1'b1; + +always @(posedge pcie_user_clk) begin + pcie_user_reset_reg_1 <= pcie_user_reset_int; + pcie_user_reset_reg_2 <= pcie_user_reset_reg_1; +end + +BUFG +pcie_user_reset_bufg_inst ( + .I(pcie_user_reset_reg_2), + .O(pcie_user_reset) +); + +pcie4_uscale_plus_0 +pcie4_uscale_plus_inst ( + .pci_exp_txn(pcie_tx_n), + .pci_exp_txp(pcie_tx_p), + .pci_exp_rxn(pcie_rx_n), + .pci_exp_rxp(pcie_rx_p), + .user_clk(pcie_user_clk), + .user_reset(pcie_user_reset_int), + .user_lnk_up(), + + .s_axis_rq_tdata(axis_rq_tdata), + .s_axis_rq_tkeep(axis_rq_tkeep), + .s_axis_rq_tlast(axis_rq_tlast), + .s_axis_rq_tready(axis_rq_tready), + .s_axis_rq_tuser(axis_rq_tuser), + .s_axis_rq_tvalid(axis_rq_tvalid), + + .m_axis_rc_tdata(axis_rc_tdata), + .m_axis_rc_tkeep(axis_rc_tkeep), + .m_axis_rc_tlast(axis_rc_tlast), + .m_axis_rc_tready(axis_rc_tready), + .m_axis_rc_tuser(axis_rc_tuser), + .m_axis_rc_tvalid(axis_rc_tvalid), + + .m_axis_cq_tdata(axis_cq_tdata), + .m_axis_cq_tkeep(axis_cq_tkeep), + .m_axis_cq_tlast(axis_cq_tlast), + .m_axis_cq_tready(axis_cq_tready), + .m_axis_cq_tuser(axis_cq_tuser), + .m_axis_cq_tvalid(axis_cq_tvalid), + + .s_axis_cc_tdata(axis_cc_tdata), + .s_axis_cc_tkeep(axis_cc_tkeep), + .s_axis_cc_tlast(axis_cc_tlast), + .s_axis_cc_tready(axis_cc_tready), + .s_axis_cc_tuser(axis_cc_tuser), + .s_axis_cc_tvalid(axis_cc_tvalid), + + .pcie_rq_seq_num0(pcie_rq_seq_num0), + .pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld0), + .pcie_rq_seq_num1(pcie_rq_seq_num1), + .pcie_rq_seq_num_vld1(pcie_rq_seq_num_vld1), + .pcie_rq_tag0(), + .pcie_rq_tag1(), + .pcie_rq_tag_av(), + .pcie_rq_tag_vld0(), + .pcie_rq_tag_vld1(), + + .pcie_tfc_nph_av(pcie_tfc_nph_av), + .pcie_tfc_npd_av(pcie_tfc_npd_av), + + .pcie_cq_np_req(1'b1), + .pcie_cq_np_req_count(), + + .cfg_phy_link_down(), + .cfg_phy_link_status(), + .cfg_negotiated_width(), + .cfg_current_speed(), + .cfg_max_payload(cfg_max_payload), + .cfg_max_read_req(cfg_max_read_req), + .cfg_function_status(), + .cfg_function_power_state(), + .cfg_vf_status(), + .cfg_vf_power_state(), + .cfg_link_power_state(), + + .cfg_mgmt_addr(cfg_mgmt_addr), + .cfg_mgmt_function_number(cfg_mgmt_function_number), + .cfg_mgmt_write(cfg_mgmt_write), + .cfg_mgmt_write_data(cfg_mgmt_write_data), + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), + .cfg_mgmt_read(cfg_mgmt_read), + .cfg_mgmt_read_data(cfg_mgmt_read_data), + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), + .cfg_mgmt_debug_access(1'b0), + + .cfg_err_cor_out(), + .cfg_err_nonfatal_out(), + .cfg_err_fatal_out(), + .cfg_local_error_valid(), + .cfg_local_error_out(), + .cfg_ltssm_state(), + .cfg_rx_pm_state(), + .cfg_tx_pm_state(), + .cfg_rcb_status(), + .cfg_obff_enable(), + .cfg_pl_status_change(), + .cfg_tph_requester_enable(), + .cfg_tph_st_mode(), + .cfg_vf_tph_requester_enable(), + .cfg_vf_tph_st_mode(), + + .cfg_msg_received(), + .cfg_msg_received_data(), + .cfg_msg_received_type(), + .cfg_msg_transmit(1'b0), + .cfg_msg_transmit_type(3'd0), + .cfg_msg_transmit_data(32'd0), + .cfg_msg_transmit_done(), + + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + + .cfg_dsn(64'd0), + + .cfg_power_state_change_ack(1'b1), + .cfg_power_state_change_interrupt(), + + .cfg_err_cor_in(status_error_cor), + .cfg_err_uncor_in(status_error_uncor), + .cfg_flr_in_process(), + .cfg_flr_done(4'd0), + .cfg_vf_flr_in_process(), + .cfg_vf_flr_func_num(8'd0), + .cfg_vf_flr_done(8'd0), + + .cfg_link_training_enable(1'b1), + + .cfg_interrupt_int(4'd0), + .cfg_interrupt_pending(4'd0), + .cfg_interrupt_sent(), + .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), + .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), + .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), + .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), + .cfg_interrupt_msix_address(cfg_interrupt_msix_address), + .cfg_interrupt_msix_data(cfg_interrupt_msix_data), + .cfg_interrupt_msix_int(cfg_interrupt_msix_int), + .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), + .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), + .cfg_interrupt_msi_sent(cfg_interrupt_msix_sent), + .cfg_interrupt_msi_fail(cfg_interrupt_msix_fail), + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + + .cfg_pm_aspm_l1_entry_reject(1'b0), + .cfg_pm_aspm_tx_l0s_entry_disable(1'b0), + + .cfg_hot_reset_out(), + + .cfg_config_space_enable(1'b1), + .cfg_req_pm_transition_l23_ready(1'b0), + .cfg_hot_reset_in(1'b0), + + .cfg_ds_port_number(8'd0), + .cfg_ds_bus_number(8'd0), + .cfg_ds_device_number(5'd0), + + .sys_clk(pcie_sys_clk), + .sys_clk_gt(pcie_sys_clk_gt), + .sys_reset(pcie_rst_n), + + .phy_rdy_out() +); + +// XGMII 10G PHY + +// QSFP0 +wire qsfp_0_tx_clk_0_int; +wire qsfp_0_tx_rst_0_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_0_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_0_int; +wire qsfp_0_tx_prbs31_enable_0_int; +wire qsfp_0_rx_clk_0_int; +wire qsfp_0_rx_rst_0_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_0_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_0_int; +wire qsfp_0_rx_prbs31_enable_0_int; +wire [6:0] qsfp_0_rx_error_count_0_int; +wire qsfp_0_tx_clk_1_int; +wire qsfp_0_tx_rst_1_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_1_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_1_int; +wire qsfp_0_tx_prbs31_enable_1_int; +wire qsfp_0_rx_clk_1_int; +wire qsfp_0_rx_rst_1_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_1_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_1_int; +wire qsfp_0_rx_prbs31_enable_1_int; +wire [6:0] qsfp_0_rx_error_count_1_int; +wire qsfp_0_tx_clk_2_int; +wire qsfp_0_tx_rst_2_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_2_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_2_int; +wire qsfp_0_tx_prbs31_enable_2_int; +wire qsfp_0_rx_clk_2_int; +wire qsfp_0_rx_rst_2_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_2_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_2_int; +wire qsfp_0_rx_prbs31_enable_2_int; +wire [6:0] qsfp_0_rx_error_count_2_int; +wire qsfp_0_tx_clk_3_int; +wire qsfp_0_tx_rst_3_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_3_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_3_int; +wire qsfp_0_tx_prbs31_enable_3_int; +wire qsfp_0_rx_clk_3_int; +wire qsfp_0_rx_rst_3_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_3_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_3_int; +wire qsfp_0_rx_prbs31_enable_3_int; +wire [6:0] qsfp_0_rx_error_count_3_int; + +wire qsfp_0_drp_clk = clk_125mhz_int; +wire qsfp_0_drp_rst = rst_125mhz_int; +wire [23:0] qsfp_0_drp_addr; +wire [15:0] qsfp_0_drp_di; +wire qsfp_0_drp_en; +wire qsfp_0_drp_we; +wire [15:0] qsfp_0_drp_do; +wire qsfp_0_drp_rdy; + +wire qsfp_0_rx_block_lock_0; +wire qsfp_0_rx_status_0; +wire qsfp_0_rx_block_lock_1; +wire qsfp_0_rx_status_1; +wire qsfp_0_rx_block_lock_2; +wire qsfp_0_rx_status_2; +wire qsfp_0_rx_block_lock_3; +wire qsfp_0_rx_status_3; + +wire qsfp_0_gtpowergood; + +wire qsfp_0_mgt_refclk; +wire qsfp_0_mgt_refclk_int; +wire qsfp_0_mgt_refclk_bufg; + +IBUFDS_GTE4 ibufds_gte4_qsfp_0_mgt_refclk_inst ( + .I (qsfp_0_mgt_refclk_p), + .IB (qsfp_0_mgt_refclk_n), + .CEB (1'b0), + .O (qsfp_0_mgt_refclk), + .ODIV2 (qsfp_0_mgt_refclk_int) +); + +BUFG_GT bufg_gt_qsfp_0_mgt_refclk_inst ( + .CE (qsfp_0_gtpowergood), + .CEMASK (1'b1), + .CLR (1'b0), + .CLRMASK (1'b1), + .DIV (3'd0), + .I (qsfp_0_mgt_refclk_int), + .O (qsfp_0_mgt_refclk_bufg) +); + +wire qsfp_0_rst; + +sync_reset #( + .N(4) +) +qsfp_0_sync_reset_inst ( + .clk(qsfp_0_mgt_refclk_bufg), + .rst(rst_125mhz_int), + .out(qsfp_0_rst) +); + +eth_xcvr_phy_10g_gty_quad_wrapper #( + .GT_1_TX_POLARITY(1), + .GT_1_RX_POLARITY(1), + .GT_2_TX_POLARITY(1), + .GT_2_RX_POLARITY(0), + .GT_3_TX_POLARITY(1), + .GT_3_RX_POLARITY(0), + .GT_4_TX_POLARITY(1), + .GT_4_RX_POLARITY(0), + .PRBS31_ENABLE(1), + .TX_SERDES_PIPELINE(1), + .RX_SERDES_PIPELINE(1), + .COUNT_125US(125000/2.56) +) +qsfp_0_phy_quad_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_0_rst), + + /* + * Common + */ + .xcvr_gtpowergood_out(qsfp_0_gtpowergood), + .xcvr_ref_clk(qsfp_0_mgt_refclk), + + /* + * DRP + */ + .drp_clk(qsfp_0_drp_clk), + .drp_rst(qsfp_0_drp_rst), + .drp_addr(qsfp_0_drp_addr), + .drp_di(qsfp_0_drp_di), + .drp_en(qsfp_0_drp_en), + .drp_we(qsfp_0_drp_we), + .drp_do(qsfp_0_drp_do), + .drp_rdy(qsfp_0_drp_rdy), + + /* + * Serial data + */ + .xcvr_txp({qsfp_0_tx_3_p, qsfp_0_tx_2_p, qsfp_0_tx_1_p, qsfp_0_tx_0_p}), + .xcvr_txn({qsfp_0_tx_3_n, qsfp_0_tx_2_n, qsfp_0_tx_1_n, qsfp_0_tx_0_n}), + .xcvr_rxp({qsfp_0_rx_3_p, qsfp_0_rx_2_p, qsfp_0_rx_1_p, qsfp_0_rx_0_p}), + .xcvr_rxn({qsfp_0_rx_3_n, qsfp_0_rx_2_n, qsfp_0_rx_1_n, qsfp_0_rx_0_n}), + + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp_0_tx_clk_0_int), + .phy_1_tx_rst(qsfp_0_tx_rst_0_int), + .phy_1_xgmii_txd(qsfp_0_txd_0_int), + .phy_1_xgmii_txc(qsfp_0_txc_0_int), + .phy_1_rx_clk(qsfp_0_rx_clk_0_int), + .phy_1_rx_rst(qsfp_0_rx_rst_0_int), + .phy_1_xgmii_rxd(qsfp_0_rxd_0_int), + .phy_1_xgmii_rxc(qsfp_0_rxc_0_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(qsfp_0_rx_error_count_0_int), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp_0_rx_block_lock_0), + .phy_1_rx_high_ber(), + .phy_1_rx_status(qsfp_0_rx_status_0), + .phy_1_tx_prbs31_enable(qsfp_0_tx_prbs31_enable_0_int), + .phy_1_rx_prbs31_enable(qsfp_0_rx_prbs31_enable_0_int), + + .phy_2_tx_clk(qsfp_0_tx_clk_1_int), + .phy_2_tx_rst(qsfp_0_tx_rst_1_int), + .phy_2_xgmii_txd(qsfp_0_txd_1_int), + .phy_2_xgmii_txc(qsfp_0_txc_1_int), + .phy_2_rx_clk(qsfp_0_rx_clk_1_int), + .phy_2_rx_rst(qsfp_0_rx_rst_1_int), + .phy_2_xgmii_rxd(qsfp_0_rxd_1_int), + .phy_2_xgmii_rxc(qsfp_0_rxc_1_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(qsfp_0_rx_error_count_1_int), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp_0_rx_block_lock_1), + .phy_2_rx_high_ber(), + .phy_2_rx_status(qsfp_0_rx_status_1), + .phy_2_tx_prbs31_enable(qsfp_0_tx_prbs31_enable_1_int), + .phy_2_rx_prbs31_enable(qsfp_0_rx_prbs31_enable_1_int), + + .phy_3_tx_clk(qsfp_0_tx_clk_2_int), + .phy_3_tx_rst(qsfp_0_tx_rst_2_int), + .phy_3_xgmii_txd(qsfp_0_txd_2_int), + .phy_3_xgmii_txc(qsfp_0_txc_2_int), + .phy_3_rx_clk(qsfp_0_rx_clk_2_int), + .phy_3_rx_rst(qsfp_0_rx_rst_2_int), + .phy_3_xgmii_rxd(qsfp_0_rxd_2_int), + .phy_3_xgmii_rxc(qsfp_0_rxc_2_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(qsfp_0_rx_error_count_2_int), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp_0_rx_block_lock_2), + .phy_3_rx_high_ber(), + .phy_3_rx_status(qsfp_0_rx_status_2), + .phy_3_tx_prbs31_enable(qsfp_0_tx_prbs31_enable_2_int), + .phy_3_rx_prbs31_enable(qsfp_0_rx_prbs31_enable_2_int), + + .phy_4_tx_clk(qsfp_0_tx_clk_3_int), + .phy_4_tx_rst(qsfp_0_tx_rst_3_int), + .phy_4_xgmii_txd(qsfp_0_txd_3_int), + .phy_4_xgmii_txc(qsfp_0_txc_3_int), + .phy_4_rx_clk(qsfp_0_rx_clk_3_int), + .phy_4_rx_rst(qsfp_0_rx_rst_3_int), + .phy_4_xgmii_rxd(qsfp_0_rxd_3_int), + .phy_4_xgmii_rxc(qsfp_0_rxc_3_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(qsfp_0_rx_error_count_3_int), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp_0_rx_block_lock_3), + .phy_4_rx_high_ber(), + .phy_4_rx_status(qsfp_0_rx_status_3), + .phy_4_tx_prbs31_enable(qsfp_0_tx_prbs31_enable_3_int), + .phy_4_rx_prbs31_enable(qsfp_0_rx_prbs31_enable_3_int) +); + +// QSFP1 +wire qsfp_1_tx_clk_0_int; +wire qsfp_1_tx_rst_0_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_0_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_0_int; +wire qsfp_1_tx_prbs31_enable_0_int; +wire qsfp_1_rx_clk_0_int; +wire qsfp_1_rx_rst_0_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_0_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_0_int; +wire qsfp_1_rx_prbs31_enable_0_int; +wire [6:0] qsfp_1_rx_error_count_0_int; +wire qsfp_1_tx_clk_1_int; +wire qsfp_1_tx_rst_1_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_1_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_1_int; +wire qsfp_1_tx_prbs31_enable_1_int; +wire qsfp_1_rx_clk_1_int; +wire qsfp_1_rx_rst_1_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_1_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_1_int; +wire qsfp_1_rx_prbs31_enable_1_int; +wire [6:0] qsfp_1_rx_error_count_1_int; +wire qsfp_1_tx_clk_2_int; +wire qsfp_1_tx_rst_2_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_2_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_2_int; +wire qsfp_1_tx_prbs31_enable_2_int; +wire qsfp_1_rx_clk_2_int; +wire qsfp_1_rx_rst_2_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_2_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_2_int; +wire qsfp_1_rx_prbs31_enable_2_int; +wire [6:0] qsfp_1_rx_error_count_2_int; +wire qsfp_1_tx_clk_3_int; +wire qsfp_1_tx_rst_3_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_3_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_3_int; +wire qsfp_1_tx_prbs31_enable_3_int; +wire qsfp_1_rx_clk_3_int; +wire qsfp_1_rx_rst_3_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_3_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_3_int; +wire qsfp_1_rx_prbs31_enable_3_int; +wire [6:0] qsfp_1_rx_error_count_3_int; + +wire qsfp_1_drp_clk = clk_125mhz_int; +wire qsfp_1_drp_rst = rst_125mhz_int; +wire [23:0] qsfp_1_drp_addr; +wire [15:0] qsfp_1_drp_di; +wire qsfp_1_drp_en; +wire qsfp_1_drp_we; +wire [15:0] qsfp_1_drp_do; +wire qsfp_1_drp_rdy; + +wire qsfp_1_rx_block_lock_0; +wire qsfp_1_rx_status_0; +wire qsfp_1_rx_block_lock_1; +wire qsfp_1_rx_status_1; +wire qsfp_1_rx_block_lock_2; +wire qsfp_1_rx_status_2; +wire qsfp_1_rx_block_lock_3; +wire qsfp_1_rx_status_3; + +wire qsfp_1_gtpowergood; + +wire qsfp_1_mgt_refclk; +wire qsfp_1_mgt_refclk_int; +wire qsfp_1_mgt_refclk_bufg; + +IBUFDS_GTE4 ibufds_gte4_qsfp_1_mgt_refclk_inst ( + .I (qsfp_1_mgt_refclk_p), + .IB (qsfp_1_mgt_refclk_n), + .CEB (1'b0), + .O (qsfp_1_mgt_refclk), + .ODIV2 (qsfp_1_mgt_refclk_int) +); + +BUFG_GT bufg_gt_qsfp_1_mgt_refclk_inst ( + .CE (qsfp_1_gtpowergood), + .CEMASK (1'b1), + .CLR (1'b0), + .CLRMASK (1'b1), + .DIV (3'd0), + .I (qsfp_1_mgt_refclk_int), + .O (qsfp_1_mgt_refclk_bufg) +); + +wire qsfp_1_rst; + +sync_reset #( + .N(4) +) +qsfp_1_sync_reset_inst ( + .clk(qsfp_1_mgt_refclk_bufg), + .rst(rst_125mhz_int), + .out(qsfp_1_rst) +); + +eth_xcvr_phy_10g_gty_quad_wrapper #( + .GT_1_TX_POLARITY(1), + .GT_1_RX_POLARITY(1), + .GT_2_TX_POLARITY(1), + .GT_2_RX_POLARITY(0), + .GT_3_TX_POLARITY(1), + .GT_3_RX_POLARITY(0), + .GT_4_TX_POLARITY(1), + .GT_4_RX_POLARITY(0), + .PRBS31_ENABLE(1), + .TX_SERDES_PIPELINE(1), + .RX_SERDES_PIPELINE(1), + .COUNT_125US(125000/2.56) +) +qsfp_1_phy_quad_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_1_rst), + + /* + * Common + */ + .xcvr_gtpowergood_out(qsfp_1_gtpowergood), + .xcvr_ref_clk(qsfp_1_mgt_refclk), + + /* + * DRP + */ + .drp_clk(qsfp_1_drp_clk), + .drp_rst(qsfp_1_drp_rst), + .drp_addr(qsfp_1_drp_addr), + .drp_di(qsfp_1_drp_di), + .drp_en(qsfp_1_drp_en), + .drp_we(qsfp_1_drp_we), + .drp_do(qsfp_1_drp_do), + .drp_rdy(qsfp_1_drp_rdy), + + /* + * Serial data + */ + .xcvr_txp({qsfp_1_tx_3_p, qsfp_1_tx_2_p, qsfp_1_tx_1_p, qsfp_1_tx_0_p}), + .xcvr_txn({qsfp_1_tx_3_n, qsfp_1_tx_2_n, qsfp_1_tx_1_n, qsfp_1_tx_0_n}), + .xcvr_rxp({qsfp_1_rx_3_p, qsfp_1_rx_2_p, qsfp_1_rx_1_p, qsfp_1_rx_0_p}), + .xcvr_rxn({qsfp_1_rx_3_n, qsfp_1_rx_2_n, qsfp_1_rx_1_n, qsfp_1_rx_0_n}), + + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp_1_tx_clk_0_int), + .phy_1_tx_rst(qsfp_1_tx_rst_0_int), + .phy_1_xgmii_txd(qsfp_1_txd_0_int), + .phy_1_xgmii_txc(qsfp_1_txc_0_int), + .phy_1_rx_clk(qsfp_1_rx_clk_0_int), + .phy_1_rx_rst(qsfp_1_rx_rst_0_int), + .phy_1_xgmii_rxd(qsfp_1_rxd_0_int), + .phy_1_xgmii_rxc(qsfp_1_rxc_0_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(qsfp_1_rx_error_count_0_int), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp_1_rx_block_lock_0), + .phy_1_rx_high_ber(), + .phy_1_rx_status(qsfp_1_rx_status_0), + .phy_1_tx_prbs31_enable(qsfp_1_tx_prbs31_enable_0_int), + .phy_1_rx_prbs31_enable(qsfp_1_rx_prbs31_enable_0_int), + + .phy_2_tx_clk(qsfp_1_tx_clk_1_int), + .phy_2_tx_rst(qsfp_1_tx_rst_1_int), + .phy_2_xgmii_txd(qsfp_1_txd_1_int), + .phy_2_xgmii_txc(qsfp_1_txc_1_int), + .phy_2_rx_clk(qsfp_1_rx_clk_1_int), + .phy_2_rx_rst(qsfp_1_rx_rst_1_int), + .phy_2_xgmii_rxd(qsfp_1_rxd_1_int), + .phy_2_xgmii_rxc(qsfp_1_rxc_1_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(qsfp_1_rx_error_count_1_int), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp_1_rx_block_lock_1), + .phy_2_rx_high_ber(), + .phy_2_rx_status(qsfp_1_rx_status_1), + .phy_2_tx_prbs31_enable(qsfp_1_tx_prbs31_enable_1_int), + .phy_2_rx_prbs31_enable(qsfp_1_rx_prbs31_enable_1_int), + + .phy_3_tx_clk(qsfp_1_tx_clk_2_int), + .phy_3_tx_rst(qsfp_1_tx_rst_2_int), + .phy_3_xgmii_txd(qsfp_1_txd_2_int), + .phy_3_xgmii_txc(qsfp_1_txc_2_int), + .phy_3_rx_clk(qsfp_1_rx_clk_2_int), + .phy_3_rx_rst(qsfp_1_rx_rst_2_int), + .phy_3_xgmii_rxd(qsfp_1_rxd_2_int), + .phy_3_xgmii_rxc(qsfp_1_rxc_2_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(qsfp_1_rx_error_count_2_int), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp_1_rx_block_lock_2), + .phy_3_rx_high_ber(), + .phy_3_rx_status(qsfp_1_rx_status_2), + .phy_3_tx_prbs31_enable(qsfp_1_tx_prbs31_enable_2_int), + .phy_3_rx_prbs31_enable(qsfp_1_rx_prbs31_enable_2_int), + + .phy_4_tx_clk(qsfp_1_tx_clk_3_int), + .phy_4_tx_rst(qsfp_1_tx_rst_3_int), + .phy_4_xgmii_txd(qsfp_1_txd_3_int), + .phy_4_xgmii_txc(qsfp_1_txc_3_int), + .phy_4_rx_clk(qsfp_1_rx_clk_3_int), + .phy_4_rx_rst(qsfp_1_rx_rst_3_int), + .phy_4_xgmii_rxd(qsfp_1_rxd_3_int), + .phy_4_xgmii_rxc(qsfp_1_rxc_3_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(qsfp_1_rx_error_count_3_int), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp_1_rx_block_lock_3), + .phy_4_rx_high_ber(), + .phy_4_rx_status(qsfp_1_rx_status_3), + .phy_4_tx_prbs31_enable(qsfp_1_tx_prbs31_enable_3_int), + .phy_4_rx_prbs31_enable(qsfp_1_rx_prbs31_enable_3_int) +); + +// QSFP2 +wire qsfp_2_tx_clk_0_int; +wire qsfp_2_tx_rst_0_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp_2_txd_0_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp_2_txc_0_int; +wire qsfp_2_tx_prbs31_enable_0_int; +wire qsfp_2_rx_clk_0_int; +wire qsfp_2_rx_rst_0_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp_2_rxd_0_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp_2_rxc_0_int; +wire qsfp_2_rx_prbs31_enable_0_int; +wire [6:0] qsfp_2_rx_error_count_0_int; +wire qsfp_2_tx_clk_1_int; +wire qsfp_2_tx_rst_1_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp_2_txd_1_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp_2_txc_1_int; +wire qsfp_2_tx_prbs31_enable_1_int; +wire qsfp_2_rx_clk_1_int; +wire qsfp_2_rx_rst_1_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp_2_rxd_1_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp_2_rxc_1_int; +wire qsfp_2_rx_prbs31_enable_1_int; +wire [6:0] qsfp_2_rx_error_count_1_int; +wire qsfp_2_tx_clk_2_int; +wire qsfp_2_tx_rst_2_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp_2_txd_2_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp_2_txc_2_int; +wire qsfp_2_tx_prbs31_enable_2_int; +wire qsfp_2_rx_clk_2_int; +wire qsfp_2_rx_rst_2_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp_2_rxd_2_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp_2_rxc_2_int; +wire qsfp_2_rx_prbs31_enable_2_int; +wire [6:0] qsfp_2_rx_error_count_2_int; +wire qsfp_2_tx_clk_3_int; +wire qsfp_2_tx_rst_3_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp_2_txd_3_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp_2_txc_3_int; +wire qsfp_2_tx_prbs31_enable_3_int; +wire qsfp_2_rx_clk_3_int; +wire qsfp_2_rx_rst_3_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp_2_rxd_3_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp_2_rxc_3_int; +wire qsfp_2_rx_prbs31_enable_3_int; +wire [6:0] qsfp_2_rx_error_count_3_int; + +wire qsfp_2_drp_clk = clk_125mhz_int; +wire qsfp_2_drp_rst = rst_125mhz_int; +wire [23:0] qsfp_2_drp_addr; +wire [15:0] qsfp_2_drp_di; +wire qsfp_2_drp_en; +wire qsfp_2_drp_we; +wire [15:0] qsfp_2_drp_do; +wire qsfp_2_drp_rdy; + +wire qsfp_2_rx_block_lock_0; +wire qsfp_2_rx_status_0; +wire qsfp_2_rx_block_lock_1; +wire qsfp_2_rx_status_1; +wire qsfp_2_rx_block_lock_2; +wire qsfp_2_rx_status_2; +wire qsfp_2_rx_block_lock_3; +wire qsfp_2_rx_status_3; + +wire qsfp_2_gtpowergood; + +wire qsfp_2_mgt_refclk; +wire qsfp_2_mgt_refclk_int; +wire qsfp_2_mgt_refclk_bufg; + +IBUFDS_GTE4 ibufds_gte4_qsfp_2_mgt_refclk_inst ( + .I (qsfp_2_mgt_refclk_p), + .IB (qsfp_2_mgt_refclk_n), + .CEB (1'b0), + .O (qsfp_2_mgt_refclk), + .ODIV2 (qsfp_2_mgt_refclk_int) +); + +BUFG_GT bufg_gt_qsfp_2_mgt_refclk_inst ( + .CE (qsfp_2_gtpowergood), + .CEMASK (1'b1), + .CLR (1'b0), + .CLRMASK (1'b1), + .DIV (3'd0), + .I (qsfp_2_mgt_refclk_int), + .O (qsfp_2_mgt_refclk_bufg) +); + +wire qsfp_2_rst; + +sync_reset #( + .N(4) +) +qsfp_2_sync_reset_inst ( + .clk(qsfp_2_mgt_refclk_bufg), + .rst(rst_125mhz_int), + .out(qsfp_2_rst) +); + +eth_xcvr_phy_10g_gty_quad_wrapper #( + .GT_1_TX_POLARITY(1), + .GT_1_RX_POLARITY(1), + .GT_2_TX_POLARITY(1), + .GT_2_RX_POLARITY(0), + .GT_3_TX_POLARITY(1), + .GT_3_RX_POLARITY(0), + .GT_4_TX_POLARITY(1), + .GT_4_RX_POLARITY(0), + .PRBS31_ENABLE(1), + .TX_SERDES_PIPELINE(1), + .RX_SERDES_PIPELINE(1), + .COUNT_125US(125000/2.56) +) +qsfp_2_phy_quad_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_2_rst), + + /* + * Common + */ + .xcvr_gtpowergood_out(qsfp_2_gtpowergood), + .xcvr_ref_clk(qsfp_2_mgt_refclk), + + /* + * DRP + */ + .drp_clk(qsfp_2_drp_clk), + .drp_rst(qsfp_2_drp_rst), + .drp_addr(qsfp_2_drp_addr), + .drp_di(qsfp_2_drp_di), + .drp_en(qsfp_2_drp_en), + .drp_we(qsfp_2_drp_we), + .drp_do(qsfp_2_drp_do), + .drp_rdy(qsfp_2_drp_rdy), + + /* + * Serial data + */ + .xcvr_txp({qsfp_2_tx_3_p, qsfp_2_tx_2_p, qsfp_2_tx_1_p, qsfp_2_tx_0_p}), + .xcvr_txn({qsfp_2_tx_3_n, qsfp_2_tx_2_n, qsfp_2_tx_1_n, qsfp_2_tx_0_n}), + .xcvr_rxp({qsfp_2_rx_3_p, qsfp_2_rx_2_p, qsfp_2_rx_1_p, qsfp_2_rx_0_p}), + .xcvr_rxn({qsfp_2_rx_3_n, qsfp_2_rx_2_n, qsfp_2_rx_1_n, qsfp_2_rx_0_n}), + + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp_2_tx_clk_0_int), + .phy_1_tx_rst(qsfp_2_tx_rst_0_int), + .phy_1_xgmii_txd(qsfp_2_txd_0_int), + .phy_1_xgmii_txc(qsfp_2_txc_0_int), + .phy_1_rx_clk(qsfp_2_rx_clk_0_int), + .phy_1_rx_rst(qsfp_2_rx_rst_0_int), + .phy_1_xgmii_rxd(qsfp_2_rxd_0_int), + .phy_1_xgmii_rxc(qsfp_2_rxc_0_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(qsfp_2_rx_error_count_0_int), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp_2_rx_block_lock_0), + .phy_1_rx_high_ber(), + .phy_1_rx_status(qsfp_2_rx_status_0), + .phy_1_tx_prbs31_enable(qsfp_2_tx_prbs31_enable_0_int), + .phy_1_rx_prbs31_enable(qsfp_2_rx_prbs31_enable_0_int), + + .phy_2_tx_clk(qsfp_2_tx_clk_1_int), + .phy_2_tx_rst(qsfp_2_tx_rst_1_int), + .phy_2_xgmii_txd(qsfp_2_txd_1_int), + .phy_2_xgmii_txc(qsfp_2_txc_1_int), + .phy_2_rx_clk(qsfp_2_rx_clk_1_int), + .phy_2_rx_rst(qsfp_2_rx_rst_1_int), + .phy_2_xgmii_rxd(qsfp_2_rxd_1_int), + .phy_2_xgmii_rxc(qsfp_2_rxc_1_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(qsfp_2_rx_error_count_1_int), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp_2_rx_block_lock_1), + .phy_2_rx_high_ber(), + .phy_2_rx_status(qsfp_2_rx_status_1), + .phy_2_tx_prbs31_enable(qsfp_2_tx_prbs31_enable_1_int), + .phy_2_rx_prbs31_enable(qsfp_2_rx_prbs31_enable_1_int), + + .phy_3_tx_clk(qsfp_2_tx_clk_2_int), + .phy_3_tx_rst(qsfp_2_tx_rst_2_int), + .phy_3_xgmii_txd(qsfp_2_txd_2_int), + .phy_3_xgmii_txc(qsfp_2_txc_2_int), + .phy_3_rx_clk(qsfp_2_rx_clk_2_int), + .phy_3_rx_rst(qsfp_2_rx_rst_2_int), + .phy_3_xgmii_rxd(qsfp_2_rxd_2_int), + .phy_3_xgmii_rxc(qsfp_2_rxc_2_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(qsfp_2_rx_error_count_2_int), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp_2_rx_block_lock_2), + .phy_3_rx_high_ber(), + .phy_3_rx_status(qsfp_2_rx_status_2), + .phy_3_tx_prbs31_enable(qsfp_2_tx_prbs31_enable_2_int), + .phy_3_rx_prbs31_enable(qsfp_2_rx_prbs31_enable_2_int), + + .phy_4_tx_clk(qsfp_2_tx_clk_3_int), + .phy_4_tx_rst(qsfp_2_tx_rst_3_int), + .phy_4_xgmii_txd(qsfp_2_txd_3_int), + .phy_4_xgmii_txc(qsfp_2_txc_3_int), + .phy_4_rx_clk(qsfp_2_rx_clk_3_int), + .phy_4_rx_rst(qsfp_2_rx_rst_3_int), + .phy_4_xgmii_rxd(qsfp_2_rxd_3_int), + .phy_4_xgmii_rxc(qsfp_2_rxc_3_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(qsfp_2_rx_error_count_3_int), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp_2_rx_block_lock_3), + .phy_4_rx_high_ber(), + .phy_4_rx_status(qsfp_2_rx_status_3), + .phy_4_tx_prbs31_enable(qsfp_2_tx_prbs31_enable_3_int), + .phy_4_rx_prbs31_enable(qsfp_2_rx_prbs31_enable_3_int) +); + +// QSFP3 +wire qsfp_3_tx_clk_0_int; +wire qsfp_3_tx_rst_0_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp_3_txd_0_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp_3_txc_0_int; +wire qsfp_3_tx_prbs31_enable_0_int; +wire qsfp_3_rx_clk_0_int; +wire qsfp_3_rx_rst_0_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp_3_rxd_0_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp_3_rxc_0_int; +wire qsfp_3_rx_prbs31_enable_0_int; +wire [6:0] qsfp_3_rx_error_count_0_int; +wire qsfp_3_tx_clk_1_int; +wire qsfp_3_tx_rst_1_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp_3_txd_1_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp_3_txc_1_int; +wire qsfp_3_tx_prbs31_enable_1_int; +wire qsfp_3_rx_clk_1_int; +wire qsfp_3_rx_rst_1_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp_3_rxd_1_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp_3_rxc_1_int; +wire qsfp_3_rx_prbs31_enable_1_int; +wire [6:0] qsfp_3_rx_error_count_1_int; +wire qsfp_3_tx_clk_2_int; +wire qsfp_3_tx_rst_2_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp_3_txd_2_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp_3_txc_2_int; +wire qsfp_3_tx_prbs31_enable_2_int; +wire qsfp_3_rx_clk_2_int; +wire qsfp_3_rx_rst_2_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp_3_rxd_2_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp_3_rxc_2_int; +wire qsfp_3_rx_prbs31_enable_2_int; +wire [6:0] qsfp_3_rx_error_count_2_int; +wire qsfp_3_tx_clk_3_int; +wire qsfp_3_tx_rst_3_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp_3_txd_3_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp_3_txc_3_int; +wire qsfp_3_tx_prbs31_enable_3_int; +wire qsfp_3_rx_clk_3_int; +wire qsfp_3_rx_rst_3_int; +wire [XGMII_DATA_WIDTH-1:0] qsfp_3_rxd_3_int; +wire [XGMII_CTRL_WIDTH-1:0] qsfp_3_rxc_3_int; +wire qsfp_3_rx_prbs31_enable_3_int; +wire [6:0] qsfp_3_rx_error_count_3_int; + +wire qsfp_3_drp_clk = clk_125mhz_int; +wire qsfp_3_drp_rst = rst_125mhz_int; +wire [23:0] qsfp_3_drp_addr; +wire [15:0] qsfp_3_drp_di; +wire qsfp_3_drp_en; +wire qsfp_3_drp_we; +wire [15:0] qsfp_3_drp_do; +wire qsfp_3_drp_rdy; + +wire qsfp_3_rx_block_lock_0; +wire qsfp_3_rx_status_0; +wire qsfp_3_rx_block_lock_1; +wire qsfp_3_rx_status_1; +wire qsfp_3_rx_block_lock_2; +wire qsfp_3_rx_status_2; +wire qsfp_3_rx_block_lock_3; +wire qsfp_3_rx_status_3; + +wire qsfp_3_gtpowergood; + +wire qsfp_3_mgt_refclk; +wire qsfp_3_mgt_refclk_int; +wire qsfp_3_mgt_refclk_bufg; + +IBUFDS_GTE4 ibufds_gte4_qsfp_3_mgt_refclk_inst ( + .I (qsfp_3_mgt_refclk_p), + .IB (qsfp_3_mgt_refclk_n), + .CEB (1'b0), + .O (qsfp_3_mgt_refclk), + .ODIV2 (qsfp_3_mgt_refclk_int) +); + +BUFG_GT bufg_gt_qsfp_3_mgt_refclk_inst ( + .CE (qsfp_3_gtpowergood), + .CEMASK (1'b1), + .CLR (1'b0), + .CLRMASK (1'b1), + .DIV (3'd0), + .I (qsfp_3_mgt_refclk_int), + .O (qsfp_3_mgt_refclk_bufg) +); + +wire qsfp_3_rst; + +sync_reset #( + .N(4) +) +qsfp_3_sync_reset_inst ( + .clk(qsfp_3_mgt_refclk_bufg), + .rst(rst_125mhz_int), + .out(qsfp_3_rst) +); + +eth_xcvr_phy_10g_gty_quad_wrapper #( + .GT_1_TX_POLARITY(1), + .GT_1_RX_POLARITY(1), + .GT_2_TX_POLARITY(1), + .GT_2_RX_POLARITY(0), + .GT_3_TX_POLARITY(1), + .GT_3_RX_POLARITY(0), + .GT_4_TX_POLARITY(1), + .GT_4_RX_POLARITY(0), + .PRBS31_ENABLE(1), + .TX_SERDES_PIPELINE(1), + .RX_SERDES_PIPELINE(1), + .COUNT_125US(125000/2.56) +) +qsfp_3_phy_quad_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_3_rst), + + /* + * Common + */ + .xcvr_gtpowergood_out(qsfp_3_gtpowergood), + .xcvr_ref_clk(qsfp_3_mgt_refclk), + + /* + * DRP + */ + .drp_clk(qsfp_3_drp_clk), + .drp_rst(qsfp_3_drp_rst), + .drp_addr(qsfp_3_drp_addr), + .drp_di(qsfp_3_drp_di), + .drp_en(qsfp_3_drp_en), + .drp_we(qsfp_3_drp_we), + .drp_do(qsfp_3_drp_do), + .drp_rdy(qsfp_3_drp_rdy), + + /* + * Serial data + */ + .xcvr_txp({qsfp_3_tx_3_p, qsfp_3_tx_2_p, qsfp_3_tx_1_p, qsfp_3_tx_0_p}), + .xcvr_txn({qsfp_3_tx_3_n, qsfp_3_tx_2_n, qsfp_3_tx_1_n, qsfp_3_tx_0_n}), + .xcvr_rxp({qsfp_3_rx_3_p, qsfp_3_rx_2_p, qsfp_3_rx_1_p, qsfp_3_rx_0_p}), + .xcvr_rxn({qsfp_3_rx_3_n, qsfp_3_rx_2_n, qsfp_3_rx_1_n, qsfp_3_rx_0_n}), + + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp_3_tx_clk_0_int), + .phy_1_tx_rst(qsfp_3_tx_rst_0_int), + .phy_1_xgmii_txd(qsfp_3_txd_0_int), + .phy_1_xgmii_txc(qsfp_3_txc_0_int), + .phy_1_rx_clk(qsfp_3_rx_clk_0_int), + .phy_1_rx_rst(qsfp_3_rx_rst_0_int), + .phy_1_xgmii_rxd(qsfp_3_rxd_0_int), + .phy_1_xgmii_rxc(qsfp_3_rxc_0_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(qsfp_3_rx_error_count_0_int), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp_3_rx_block_lock_0), + .phy_1_rx_high_ber(), + .phy_1_rx_status(qsfp_3_rx_status_0), + .phy_1_tx_prbs31_enable(qsfp_3_tx_prbs31_enable_0_int), + .phy_1_rx_prbs31_enable(qsfp_3_rx_prbs31_enable_0_int), + + .phy_2_tx_clk(qsfp_3_tx_clk_1_int), + .phy_2_tx_rst(qsfp_3_tx_rst_1_int), + .phy_2_xgmii_txd(qsfp_3_txd_1_int), + .phy_2_xgmii_txc(qsfp_3_txc_1_int), + .phy_2_rx_clk(qsfp_3_rx_clk_1_int), + .phy_2_rx_rst(qsfp_3_rx_rst_1_int), + .phy_2_xgmii_rxd(qsfp_3_rxd_1_int), + .phy_2_xgmii_rxc(qsfp_3_rxc_1_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(qsfp_3_rx_error_count_1_int), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp_3_rx_block_lock_1), + .phy_2_rx_high_ber(), + .phy_2_rx_status(qsfp_3_rx_status_1), + .phy_2_tx_prbs31_enable(qsfp_3_tx_prbs31_enable_1_int), + .phy_2_rx_prbs31_enable(qsfp_3_rx_prbs31_enable_1_int), + + .phy_3_tx_clk(qsfp_3_tx_clk_2_int), + .phy_3_tx_rst(qsfp_3_tx_rst_2_int), + .phy_3_xgmii_txd(qsfp_3_txd_2_int), + .phy_3_xgmii_txc(qsfp_3_txc_2_int), + .phy_3_rx_clk(qsfp_3_rx_clk_2_int), + .phy_3_rx_rst(qsfp_3_rx_rst_2_int), + .phy_3_xgmii_rxd(qsfp_3_rxd_2_int), + .phy_3_xgmii_rxc(qsfp_3_rxc_2_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(qsfp_3_rx_error_count_2_int), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp_3_rx_block_lock_2), + .phy_3_rx_high_ber(), + .phy_3_rx_status(qsfp_3_rx_status_2), + .phy_3_tx_prbs31_enable(qsfp_3_tx_prbs31_enable_2_int), + .phy_3_rx_prbs31_enable(qsfp_3_rx_prbs31_enable_2_int), + + .phy_4_tx_clk(qsfp_3_tx_clk_3_int), + .phy_4_tx_rst(qsfp_3_tx_rst_3_int), + .phy_4_xgmii_txd(qsfp_3_txd_3_int), + .phy_4_xgmii_txc(qsfp_3_txc_3_int), + .phy_4_rx_clk(qsfp_3_rx_clk_3_int), + .phy_4_rx_rst(qsfp_3_rx_rst_3_int), + .phy_4_xgmii_rxd(qsfp_3_rxd_3_int), + .phy_4_xgmii_rxc(qsfp_3_rxc_3_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(qsfp_3_rx_error_count_3_int), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp_3_rx_block_lock_3), + .phy_4_rx_high_ber(), + .phy_4_rx_status(qsfp_3_rx_status_3), + .phy_4_tx_prbs31_enable(qsfp_3_tx_prbs31_enable_3_int), + .phy_4_rx_prbs31_enable(qsfp_3_rx_prbs31_enable_3_int) +); + +wire ptp_clk; +wire ptp_rst; +wire ptp_sample_clk; + +assign ptp_clk = qsfp_0_mgt_refclk_bufg; +assign ptp_rst = qsfp_0_rst; +assign ptp_sample_clk = clk_125mhz_int; + +assign led_green[0] = qsfp_0_rx_status_0; +assign led_green[1] = qsfp_0_rx_status_1; +assign led_green[2] = qsfp_0_rx_status_2; +assign led_green[3] = qsfp_0_rx_status_3; +assign led_green[4] = qsfp_1_rx_status_0; +assign led_green[5] = qsfp_1_rx_status_1; +assign led_green[6] = qsfp_1_rx_status_2; +assign led_green[7] = qsfp_1_rx_status_3; +assign led_green[8] = qsfp_2_rx_status_0; +assign led_green[9] = qsfp_2_rx_status_1; +assign led_green[10] = qsfp_2_rx_status_2; +assign led_green[11] = qsfp_2_rx_status_3; +assign led_green[12] = qsfp_3_rx_status_0; +assign led_green[13] = qsfp_3_rx_status_1; +assign led_green[14] = qsfp_3_rx_status_2; +assign led_green[15] = qsfp_3_rx_status_3; + +fpga_core #( + // FW and board IDs + .FPGA_ID(FPGA_ID), + .FW_ID(FW_ID), + .FW_VER(FW_VER), + .BOARD_ID(BOARD_ID), + .BOARD_VER(BOARD_VER), + .BUILD_DATE(BUILD_DATE), + .GIT_HASH(GIT_HASH), + .RELEASE_INFO(RELEASE_INFO), + + // Board configuration + .TDMA_BER_ENABLE(TDMA_BER_ENABLE), + + // Structural configuration + .IF_COUNT(IF_COUNT), + .PORTS_PER_IF(PORTS_PER_IF), + .SCHED_PER_IF(SCHED_PER_IF), + .PORT_MASK(PORT_MASK), + + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + + // PTP configuration + .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), + .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), + .PTP_TS_WIDTH(PTP_TS_WIDTH), + .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), + .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), + .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), + .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), + .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), + .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), + .IF_PTP_PERIOD_NS(IF_PTP_PERIOD_NS), + .IF_PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS), + + // Queue manager configuration + .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), + .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), + .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), + .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), + .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), + .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), + .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), + .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), + .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), + .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), + .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), + .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), + .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + + // TX and RX engine configuration + .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), + .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), + + // Scheduler configuration + .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), + .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), + .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), + + // Interface configuration + .PTP_TS_ENABLE(PTP_TS_ENABLE), + .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), + .TX_TAG_WIDTH(TX_TAG_WIDTH), + .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), + .RX_HASH_ENABLE(RX_HASH_ENABLE), + .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .TX_FIFO_DEPTH(TX_FIFO_DEPTH), + .RX_FIFO_DEPTH(RX_FIFO_DEPTH), + .MAX_TX_SIZE(MAX_TX_SIZE), + .MAX_RX_SIZE(MAX_RX_SIZE), + .TX_RAM_SIZE(TX_RAM_SIZE), + .RX_RAM_SIZE(RX_RAM_SIZE), + + // Application block configuration + .APP_ID(APP_ID), + .APP_ENABLE(APP_ENABLE), + .APP_CTRL_ENABLE(APP_CTRL_ENABLE), + .APP_DMA_ENABLE(APP_DMA_ENABLE), + .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), + .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), + .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), + .APP_STAT_ENABLE(APP_STAT_ENABLE), + + // DMA interface configuration + .DMA_IMM_ENABLE(DMA_IMM_ENABLE), + .DMA_IMM_WIDTH(DMA_IMM_WIDTH), + .DMA_LEN_WIDTH(DMA_LEN_WIDTH), + .DMA_TAG_WIDTH(DMA_TAG_WIDTH), + .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), + .RAM_PIPELINE(RAM_PIPELINE), + + // PCIe interface configuration + .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), + .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH), + .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), + .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), + .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), + .RC_STRADDLE(RC_STRADDLE), + .RQ_STRADDLE(RQ_STRADDLE), + .CQ_STRADDLE(CQ_STRADDLE), + .CC_STRADDLE(CC_STRADDLE), + .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH), + .PF_COUNT(PF_COUNT), + .VF_COUNT(VF_COUNT), + .PCIE_TAG_COUNT(PCIE_TAG_COUNT), + + // Interrupt configuration + .IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH), + + // AXI lite interface configuration (control) + .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), + + // AXI lite interface configuration (application control) + .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), + .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), + + // Ethernet interface configuration + .XGMII_DATA_WIDTH(XGMII_DATA_WIDTH), + .XGMII_CTRL_WIDTH(XGMII_CTRL_WIDTH), + .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), + .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), + .AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), + .AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), + .AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), + .AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE), + .AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE), + .AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE), + .AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE), + .AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE), + + // Statistics counter subsystem + .STAT_ENABLE(STAT_ENABLE), + .STAT_DMA_ENABLE(STAT_DMA_ENABLE), + .STAT_PCIE_ENABLE(STAT_PCIE_ENABLE), + .STAT_INC_WIDTH(STAT_INC_WIDTH), + .STAT_ID_WIDTH(STAT_ID_WIDTH) +) +core_inst ( + /* + * Clock: 250 MHz + * Synchronous reset + */ + .clk_250mhz(pcie_user_clk), + .rst_250mhz(pcie_user_reset), + + /* + * PTP clock + */ + .ptp_clk(ptp_clk), + .ptp_rst(ptp_rst), + .ptp_sample_clk(ptp_sample_clk), + + /* + * GPIO + */ + .led_red(led_red), + //.led_green(led_green), + .led_bmc_red(led_bmc_red), + .led_bmc_green(led_bmc_green), + + .pps_in(pps_in), + .pps_out(pps_out), + + /* + * PCIe + */ + .m_axis_rq_tdata(axis_rq_tdata), + .m_axis_rq_tkeep(axis_rq_tkeep), + .m_axis_rq_tlast(axis_rq_tlast), + .m_axis_rq_tready(axis_rq_tready), + .m_axis_rq_tuser(axis_rq_tuser), + .m_axis_rq_tvalid(axis_rq_tvalid), + + .s_axis_rc_tdata(axis_rc_tdata), + .s_axis_rc_tkeep(axis_rc_tkeep), + .s_axis_rc_tlast(axis_rc_tlast), + .s_axis_rc_tready(axis_rc_tready), + .s_axis_rc_tuser(axis_rc_tuser), + .s_axis_rc_tvalid(axis_rc_tvalid), + + .s_axis_cq_tdata(axis_cq_tdata), + .s_axis_cq_tkeep(axis_cq_tkeep), + .s_axis_cq_tlast(axis_cq_tlast), + .s_axis_cq_tready(axis_cq_tready), + .s_axis_cq_tuser(axis_cq_tuser), + .s_axis_cq_tvalid(axis_cq_tvalid), + + .m_axis_cc_tdata(axis_cc_tdata), + .m_axis_cc_tkeep(axis_cc_tkeep), + .m_axis_cc_tlast(axis_cc_tlast), + .m_axis_cc_tready(axis_cc_tready), + .m_axis_cc_tuser(axis_cc_tuser), + .m_axis_cc_tvalid(axis_cc_tvalid), + + .s_axis_rq_seq_num_0(pcie_rq_seq_num0), + .s_axis_rq_seq_num_valid_0(pcie_rq_seq_num_vld0), + .s_axis_rq_seq_num_1(pcie_rq_seq_num1), + .s_axis_rq_seq_num_valid_1(pcie_rq_seq_num_vld1), + + .pcie_tfc_nph_av(pcie_tfc_nph_av), + .pcie_tfc_npd_av(pcie_tfc_npd_av), + + .cfg_max_payload(cfg_max_payload), + .cfg_max_read_req(cfg_max_read_req), + + .cfg_mgmt_addr(cfg_mgmt_addr), + .cfg_mgmt_function_number(cfg_mgmt_function_number), + .cfg_mgmt_write(cfg_mgmt_write), + .cfg_mgmt_write_data(cfg_mgmt_write_data), + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), + .cfg_mgmt_read(cfg_mgmt_read), + .cfg_mgmt_read_data(cfg_mgmt_read_data), + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), + + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + + .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), + .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), + .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), + .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), + .cfg_interrupt_msix_address(cfg_interrupt_msix_address), + .cfg_interrupt_msix_data(cfg_interrupt_msix_data), + .cfg_interrupt_msix_int(cfg_interrupt_msix_int), + .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), + .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), + .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent), + .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail), + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + + .status_error_cor(status_error_cor), + .status_error_uncor(status_error_uncor), + + /* + * Ethernet: QSFP28 + */ + .qsfp_0_tx_clk_0(qsfp_0_tx_clk_0_int), + .qsfp_0_tx_rst_0(qsfp_0_tx_rst_0_int), + .qsfp_0_txd_0(qsfp_0_txd_0_int), + .qsfp_0_txc_0(qsfp_0_txc_0_int), + .qsfp_0_tx_prbs31_enable_0(qsfp_0_tx_prbs31_enable_0_int), + .qsfp_0_rx_clk_0(qsfp_0_rx_clk_0_int), + .qsfp_0_rx_rst_0(qsfp_0_rx_rst_0_int), + .qsfp_0_rxd_0(qsfp_0_rxd_0_int), + .qsfp_0_rxc_0(qsfp_0_rxc_0_int), + .qsfp_0_rx_prbs31_enable_0(qsfp_0_rx_prbs31_enable_0_int), + .qsfp_0_rx_error_count_0(qsfp_0_rx_error_count_0_int), + .qsfp_0_rx_status_0(qsfp_0_rx_status_0), + + .qsfp_0_tx_clk_1(qsfp_0_tx_clk_1_int), + .qsfp_0_tx_rst_1(qsfp_0_tx_rst_1_int), + .qsfp_0_txd_1(qsfp_0_txd_1_int), + .qsfp_0_txc_1(qsfp_0_txc_1_int), + .qsfp_0_tx_prbs31_enable_1(qsfp_0_tx_prbs31_enable_1_int), + .qsfp_0_rx_clk_1(qsfp_0_rx_clk_1_int), + .qsfp_0_rx_rst_1(qsfp_0_rx_rst_1_int), + .qsfp_0_rxd_1(qsfp_0_rxd_1_int), + .qsfp_0_rxc_1(qsfp_0_rxc_1_int), + .qsfp_0_rx_prbs31_enable_1(qsfp_0_rx_prbs31_enable_1_int), + .qsfp_0_rx_error_count_1(qsfp_0_rx_error_count_1_int), + .qsfp_0_rx_status_1(qsfp_0_rx_status_1), + + .qsfp_0_tx_clk_2(qsfp_0_tx_clk_2_int), + .qsfp_0_tx_rst_2(qsfp_0_tx_rst_2_int), + .qsfp_0_txd_2(qsfp_0_txd_2_int), + .qsfp_0_txc_2(qsfp_0_txc_2_int), + .qsfp_0_tx_prbs31_enable_2(qsfp_0_tx_prbs31_enable_2_int), + .qsfp_0_rx_clk_2(qsfp_0_rx_clk_2_int), + .qsfp_0_rx_rst_2(qsfp_0_rx_rst_2_int), + .qsfp_0_rxd_2(qsfp_0_rxd_2_int), + .qsfp_0_rxc_2(qsfp_0_rxc_2_int), + .qsfp_0_rx_prbs31_enable_2(qsfp_0_rx_prbs31_enable_2_int), + .qsfp_0_rx_error_count_2(qsfp_0_rx_error_count_2_int), + .qsfp_0_rx_status_2(qsfp_0_rx_status_2), + + .qsfp_0_tx_clk_3(qsfp_0_tx_clk_3_int), + .qsfp_0_tx_rst_3(qsfp_0_tx_rst_3_int), + .qsfp_0_txd_3(qsfp_0_txd_3_int), + .qsfp_0_txc_3(qsfp_0_txc_3_int), + .qsfp_0_tx_prbs31_enable_3(qsfp_0_tx_prbs31_enable_3_int), + .qsfp_0_rx_clk_3(qsfp_0_rx_clk_3_int), + .qsfp_0_rx_rst_3(qsfp_0_rx_rst_3_int), + .qsfp_0_rxd_3(qsfp_0_rxd_3_int), + .qsfp_0_rxc_3(qsfp_0_rxc_3_int), + .qsfp_0_rx_prbs31_enable_3(qsfp_0_rx_prbs31_enable_3_int), + .qsfp_0_rx_error_count_3(qsfp_0_rx_error_count_3_int), + .qsfp_0_rx_status_3(qsfp_0_rx_status_3), + + .qsfp_0_drp_clk(qsfp_0_drp_clk), + .qsfp_0_drp_rst(qsfp_0_drp_rst), + .qsfp_0_drp_addr(qsfp_0_drp_addr), + .qsfp_0_drp_di(qsfp_0_drp_di), + .qsfp_0_drp_en(qsfp_0_drp_en), + .qsfp_0_drp_we(qsfp_0_drp_we), + .qsfp_0_drp_do(qsfp_0_drp_do), + .qsfp_0_drp_rdy(qsfp_0_drp_rdy), + + .qsfp_0_mod_prsnt_n(qsfp_0_mod_prsnt_n_int), + .qsfp_0_reset_n(qsfp_0_reset_n), + .qsfp_0_lp_mode(qsfp_0_lp_mode), + .qsfp_0_intr_n(qsfp_0_intr_n_int), + + .qsfp_0_i2c_scl_i(qsfp_0_i2c_scl_i), + .qsfp_0_i2c_scl_o(qsfp_0_i2c_scl_o), + .qsfp_0_i2c_scl_t(qsfp_0_i2c_scl_t), + .qsfp_0_i2c_sda_i(qsfp_0_i2c_sda_i), + .qsfp_0_i2c_sda_o(qsfp_0_i2c_sda_o), + .qsfp_0_i2c_sda_t(qsfp_0_i2c_sda_t), + + .qsfp_1_tx_clk_0(qsfp_1_tx_clk_0_int), + .qsfp_1_tx_rst_0(qsfp_1_tx_rst_0_int), + .qsfp_1_txd_0(qsfp_1_txd_0_int), + .qsfp_1_txc_0(qsfp_1_txc_0_int), + .qsfp_1_tx_prbs31_enable_0(qsfp_1_tx_prbs31_enable_0_int), + .qsfp_1_rx_clk_0(qsfp_1_rx_clk_0_int), + .qsfp_1_rx_rst_0(qsfp_1_rx_rst_0_int), + .qsfp_1_rxd_0(qsfp_1_rxd_0_int), + .qsfp_1_rxc_0(qsfp_1_rxc_0_int), + .qsfp_1_rx_prbs31_enable_0(qsfp_1_rx_prbs31_enable_0_int), + .qsfp_1_rx_error_count_0(qsfp_1_rx_error_count_0_int), + .qsfp_1_rx_status_0(qsfp_1_rx_status_0), + + .qsfp_1_tx_clk_1(qsfp_1_tx_clk_1_int), + .qsfp_1_tx_rst_1(qsfp_1_tx_rst_1_int), + .qsfp_1_txd_1(qsfp_1_txd_1_int), + .qsfp_1_txc_1(qsfp_1_txc_1_int), + .qsfp_1_tx_prbs31_enable_1(qsfp_1_tx_prbs31_enable_1_int), + .qsfp_1_rx_clk_1(qsfp_1_rx_clk_1_int), + .qsfp_1_rx_rst_1(qsfp_1_rx_rst_1_int), + .qsfp_1_rxd_1(qsfp_1_rxd_1_int), + .qsfp_1_rxc_1(qsfp_1_rxc_1_int), + .qsfp_1_rx_prbs31_enable_1(qsfp_1_rx_prbs31_enable_1_int), + .qsfp_1_rx_error_count_1(qsfp_1_rx_error_count_1_int), + .qsfp_1_rx_status_1(qsfp_1_rx_status_1), + + .qsfp_1_tx_clk_2(qsfp_1_tx_clk_2_int), + .qsfp_1_tx_rst_2(qsfp_1_tx_rst_2_int), + .qsfp_1_txd_2(qsfp_1_txd_2_int), + .qsfp_1_txc_2(qsfp_1_txc_2_int), + .qsfp_1_tx_prbs31_enable_2(qsfp_1_tx_prbs31_enable_2_int), + .qsfp_1_rx_clk_2(qsfp_1_rx_clk_2_int), + .qsfp_1_rx_rst_2(qsfp_1_rx_rst_2_int), + .qsfp_1_rxd_2(qsfp_1_rxd_2_int), + .qsfp_1_rxc_2(qsfp_1_rxc_2_int), + .qsfp_1_rx_prbs31_enable_2(qsfp_1_rx_prbs31_enable_2_int), + .qsfp_1_rx_error_count_2(qsfp_1_rx_error_count_2_int), + .qsfp_1_rx_status_2(qsfp_1_rx_status_2), + + .qsfp_1_tx_clk_3(qsfp_1_tx_clk_3_int), + .qsfp_1_tx_rst_3(qsfp_1_tx_rst_3_int), + .qsfp_1_txd_3(qsfp_1_txd_3_int), + .qsfp_1_txc_3(qsfp_1_txc_3_int), + .qsfp_1_tx_prbs31_enable_3(qsfp_1_tx_prbs31_enable_3_int), + .qsfp_1_rx_clk_3(qsfp_1_rx_clk_3_int), + .qsfp_1_rx_rst_3(qsfp_1_rx_rst_3_int), + .qsfp_1_rxd_3(qsfp_1_rxd_3_int), + .qsfp_1_rxc_3(qsfp_1_rxc_3_int), + .qsfp_1_rx_prbs31_enable_3(qsfp_1_rx_prbs31_enable_3_int), + .qsfp_1_rx_error_count_3(qsfp_1_rx_error_count_3_int), + .qsfp_1_rx_status_3(qsfp_1_rx_status_3), + + .qsfp_1_drp_clk(qsfp_1_drp_clk), + .qsfp_1_drp_rst(qsfp_1_drp_rst), + .qsfp_1_drp_addr(qsfp_1_drp_addr), + .qsfp_1_drp_di(qsfp_1_drp_di), + .qsfp_1_drp_en(qsfp_1_drp_en), + .qsfp_1_drp_we(qsfp_1_drp_we), + .qsfp_1_drp_do(qsfp_1_drp_do), + .qsfp_1_drp_rdy(qsfp_1_drp_rdy), + + .qsfp_1_mod_prsnt_n(qsfp_1_mod_prsnt_n_int), + .qsfp_1_reset_n(qsfp_1_reset_n), + .qsfp_1_lp_mode(qsfp_1_lp_mode), + .qsfp_1_intr_n(qsfp_1_intr_n_int), + + .qsfp_1_i2c_scl_i(qsfp_1_i2c_scl_i), + .qsfp_1_i2c_scl_o(qsfp_1_i2c_scl_o), + .qsfp_1_i2c_scl_t(qsfp_1_i2c_scl_t), + .qsfp_1_i2c_sda_i(qsfp_1_i2c_sda_i), + .qsfp_1_i2c_sda_o(qsfp_1_i2c_sda_o), + .qsfp_1_i2c_sda_t(qsfp_1_i2c_sda_t), + + .qsfp_2_tx_clk_0(qsfp_2_tx_clk_0_int), + .qsfp_2_tx_rst_0(qsfp_2_tx_rst_0_int), + .qsfp_2_txd_0(qsfp_2_txd_0_int), + .qsfp_2_txc_0(qsfp_2_txc_0_int), + .qsfp_2_tx_prbs31_enable_0(qsfp_2_tx_prbs31_enable_0_int), + .qsfp_2_rx_clk_0(qsfp_2_rx_clk_0_int), + .qsfp_2_rx_rst_0(qsfp_2_rx_rst_0_int), + .qsfp_2_rxd_0(qsfp_2_rxd_0_int), + .qsfp_2_rxc_0(qsfp_2_rxc_0_int), + .qsfp_2_rx_prbs31_enable_0(qsfp_2_rx_prbs31_enable_0_int), + .qsfp_2_rx_error_count_0(qsfp_2_rx_error_count_0_int), + .qsfp_2_rx_status_0(qsfp_2_rx_status_0), + + .qsfp_2_tx_clk_1(qsfp_2_tx_clk_1_int), + .qsfp_2_tx_rst_1(qsfp_2_tx_rst_1_int), + .qsfp_2_txd_1(qsfp_2_txd_1_int), + .qsfp_2_txc_1(qsfp_2_txc_1_int), + .qsfp_2_tx_prbs31_enable_1(qsfp_2_tx_prbs31_enable_1_int), + .qsfp_2_rx_clk_1(qsfp_2_rx_clk_1_int), + .qsfp_2_rx_rst_1(qsfp_2_rx_rst_1_int), + .qsfp_2_rxd_1(qsfp_2_rxd_1_int), + .qsfp_2_rxc_1(qsfp_2_rxc_1_int), + .qsfp_2_rx_prbs31_enable_1(qsfp_2_rx_prbs31_enable_1_int), + .qsfp_2_rx_error_count_1(qsfp_2_rx_error_count_1_int), + .qsfp_2_rx_status_1(qsfp_2_rx_status_1), + + .qsfp_2_tx_clk_2(qsfp_2_tx_clk_2_int), + .qsfp_2_tx_rst_2(qsfp_2_tx_rst_2_int), + .qsfp_2_txd_2(qsfp_2_txd_2_int), + .qsfp_2_txc_2(qsfp_2_txc_2_int), + .qsfp_2_tx_prbs31_enable_2(qsfp_2_tx_prbs31_enable_2_int), + .qsfp_2_rx_clk_2(qsfp_2_rx_clk_2_int), + .qsfp_2_rx_rst_2(qsfp_2_rx_rst_2_int), + .qsfp_2_rxd_2(qsfp_2_rxd_2_int), + .qsfp_2_rxc_2(qsfp_2_rxc_2_int), + .qsfp_2_rx_prbs31_enable_2(qsfp_2_rx_prbs31_enable_2_int), + .qsfp_2_rx_error_count_2(qsfp_2_rx_error_count_2_int), + .qsfp_2_rx_status_2(qsfp_2_rx_status_2), + + .qsfp_2_tx_clk_3(qsfp_2_tx_clk_3_int), + .qsfp_2_tx_rst_3(qsfp_2_tx_rst_3_int), + .qsfp_2_txd_3(qsfp_2_txd_3_int), + .qsfp_2_txc_3(qsfp_2_txc_3_int), + .qsfp_2_tx_prbs31_enable_3(qsfp_2_tx_prbs31_enable_3_int), + .qsfp_2_rx_clk_3(qsfp_2_rx_clk_3_int), + .qsfp_2_rx_rst_3(qsfp_2_rx_rst_3_int), + .qsfp_2_rxd_3(qsfp_2_rxd_3_int), + .qsfp_2_rxc_3(qsfp_2_rxc_3_int), + .qsfp_2_rx_prbs31_enable_3(qsfp_2_rx_prbs31_enable_3_int), + .qsfp_2_rx_error_count_3(qsfp_2_rx_error_count_3_int), + .qsfp_2_rx_status_3(qsfp_2_rx_status_3), + + .qsfp_2_drp_clk(qsfp_2_drp_clk), + .qsfp_2_drp_rst(qsfp_2_drp_rst), + .qsfp_2_drp_addr(qsfp_2_drp_addr), + .qsfp_2_drp_di(qsfp_2_drp_di), + .qsfp_2_drp_en(qsfp_2_drp_en), + .qsfp_2_drp_we(qsfp_2_drp_we), + .qsfp_2_drp_do(qsfp_2_drp_do), + .qsfp_2_drp_rdy(qsfp_2_drp_rdy), + + .qsfp_2_mod_prsnt_n(qsfp_2_mod_prsnt_n_int), + .qsfp_2_reset_n(qsfp_2_reset_n), + .qsfp_2_lp_mode(qsfp_2_lp_mode), + .qsfp_2_intr_n(qsfp_2_intr_n_int), + + .qsfp_2_i2c_scl_i(qsfp_2_i2c_scl_i), + .qsfp_2_i2c_scl_o(qsfp_2_i2c_scl_o), + .qsfp_2_i2c_scl_t(qsfp_2_i2c_scl_t), + .qsfp_2_i2c_sda_i(qsfp_2_i2c_sda_i), + .qsfp_2_i2c_sda_o(qsfp_2_i2c_sda_o), + .qsfp_2_i2c_sda_t(qsfp_2_i2c_sda_t), + + .qsfp_3_tx_clk_0(qsfp_3_tx_clk_0_int), + .qsfp_3_tx_rst_0(qsfp_3_tx_rst_0_int), + .qsfp_3_txd_0(qsfp_3_txd_0_int), + .qsfp_3_txc_0(qsfp_3_txc_0_int), + .qsfp_3_tx_prbs31_enable_0(qsfp_3_tx_prbs31_enable_0_int), + .qsfp_3_rx_clk_0(qsfp_3_rx_clk_0_int), + .qsfp_3_rx_rst_0(qsfp_3_rx_rst_0_int), + .qsfp_3_rxd_0(qsfp_3_rxd_0_int), + .qsfp_3_rxc_0(qsfp_3_rxc_0_int), + .qsfp_3_rx_prbs31_enable_0(qsfp_3_rx_prbs31_enable_0_int), + .qsfp_3_rx_error_count_0(qsfp_3_rx_error_count_0_int), + .qsfp_3_rx_status_0(qsfp_3_rx_status_0), + + .qsfp_3_tx_clk_1(qsfp_3_tx_clk_1_int), + .qsfp_3_tx_rst_1(qsfp_3_tx_rst_1_int), + .qsfp_3_txd_1(qsfp_3_txd_1_int), + .qsfp_3_txc_1(qsfp_3_txc_1_int), + .qsfp_3_tx_prbs31_enable_1(qsfp_3_tx_prbs31_enable_1_int), + .qsfp_3_rx_clk_1(qsfp_3_rx_clk_1_int), + .qsfp_3_rx_rst_1(qsfp_3_rx_rst_1_int), + .qsfp_3_rxd_1(qsfp_3_rxd_1_int), + .qsfp_3_rxc_1(qsfp_3_rxc_1_int), + .qsfp_3_rx_prbs31_enable_1(qsfp_3_rx_prbs31_enable_1_int), + .qsfp_3_rx_error_count_1(qsfp_3_rx_error_count_1_int), + .qsfp_3_rx_status_1(qsfp_3_rx_status_1), + + .qsfp_3_tx_clk_2(qsfp_3_tx_clk_2_int), + .qsfp_3_tx_rst_2(qsfp_3_tx_rst_2_int), + .qsfp_3_txd_2(qsfp_3_txd_2_int), + .qsfp_3_txc_2(qsfp_3_txc_2_int), + .qsfp_3_tx_prbs31_enable_2(qsfp_3_tx_prbs31_enable_2_int), + .qsfp_3_rx_clk_2(qsfp_3_rx_clk_2_int), + .qsfp_3_rx_rst_2(qsfp_3_rx_rst_2_int), + .qsfp_3_rxd_2(qsfp_3_rxd_2_int), + .qsfp_3_rxc_2(qsfp_3_rxc_2_int), + .qsfp_3_rx_prbs31_enable_2(qsfp_3_rx_prbs31_enable_2_int), + .qsfp_3_rx_error_count_2(qsfp_3_rx_error_count_2_int), + .qsfp_3_rx_status_2(qsfp_3_rx_status_2), + + .qsfp_3_tx_clk_3(qsfp_3_tx_clk_3_int), + .qsfp_3_tx_rst_3(qsfp_3_tx_rst_3_int), + .qsfp_3_txd_3(qsfp_3_txd_3_int), + .qsfp_3_txc_3(qsfp_3_txc_3_int), + .qsfp_3_tx_prbs31_enable_3(qsfp_3_tx_prbs31_enable_3_int), + .qsfp_3_rx_clk_3(qsfp_3_rx_clk_3_int), + .qsfp_3_rx_rst_3(qsfp_3_rx_rst_3_int), + .qsfp_3_rxd_3(qsfp_3_rxd_3_int), + .qsfp_3_rxc_3(qsfp_3_rxc_3_int), + .qsfp_3_rx_prbs31_enable_3(qsfp_3_rx_prbs31_enable_3_int), + .qsfp_3_rx_error_count_3(qsfp_3_rx_error_count_3_int), + .qsfp_3_rx_status_3(qsfp_3_rx_status_3), + + .qsfp_3_drp_clk(qsfp_3_drp_clk), + .qsfp_3_drp_rst(qsfp_3_drp_rst), + .qsfp_3_drp_addr(qsfp_3_drp_addr), + .qsfp_3_drp_di(qsfp_3_drp_di), + .qsfp_3_drp_en(qsfp_3_drp_en), + .qsfp_3_drp_we(qsfp_3_drp_we), + .qsfp_3_drp_do(qsfp_3_drp_do), + .qsfp_3_drp_rdy(qsfp_3_drp_rdy), + + .qsfp_3_mod_prsnt_n(qsfp_3_mod_prsnt_n_int), + .qsfp_3_reset_n(qsfp_3_reset_n), + .qsfp_3_lp_mode(qsfp_3_lp_mode), + .qsfp_3_intr_n(qsfp_3_intr_n_int), + + .qsfp_3_i2c_scl_i(qsfp_3_i2c_scl_i), + .qsfp_3_i2c_scl_o(qsfp_3_i2c_scl_o), + .qsfp_3_i2c_scl_t(qsfp_3_i2c_scl_t), + .qsfp_3_i2c_sda_i(qsfp_3_i2c_sda_i), + .qsfp_3_i2c_sda_o(qsfp_3_i2c_sda_o), + .qsfp_3_i2c_sda_t(qsfp_3_i2c_sda_t) +); + +endmodule + +`resetall diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga_core.v new file mode 100644 index 000000000..8716d752d --- /dev/null +++ b/fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga_core.v @@ -0,0 +1,1817 @@ +/* + +Copyright 2019-2021, The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +The views and conclusions contained in the software and documentation are those +of the authors and should not be interpreted as representing official policies, +either expressed or implied, of The Regents of the University of California. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA core logic + */ +module fpga_core # +( + // FW and board IDs + parameter FPGA_ID = 32'h4B31093, + parameter FW_ID = 32'h00000000, + parameter FW_VER = 32'h00_00_01_00, + parameter BOARD_ID = 32'h1c2c_9403, + parameter BOARD_VER = 32'h01_00_00_00, + parameter BUILD_DATE = 32'd602976000, + parameter GIT_HASH = 32'hdce357bf, + parameter RELEASE_INFO = 32'h00000000, + + // Board configuration + parameter TDMA_BER_ENABLE = 0, + + // Structural configuration + parameter IF_COUNT = 2, + parameter PORTS_PER_IF = 1, + parameter SCHED_PER_IF = PORTS_PER_IF, + parameter PORT_MASK = 0, + + // Clock configuration + parameter CLK_PERIOD_NS_NUM = 4, + parameter CLK_PERIOD_NS_DENOM = 1, + + // PTP configuration + parameter PTP_CLK_PERIOD_NS_NUM = 1024, + parameter PTP_CLK_PERIOD_NS_DENOM = 165, + parameter PTP_TS_WIDTH = 96, + parameter PTP_CLOCK_PIPELINE = 0, + parameter PTP_CLOCK_CDC_PIPELINE = 0, + parameter PTP_USE_SAMPLE_CLOCK = 1, + parameter PTP_PORT_CDC_PIPELINE = 0, + parameter PTP_PEROUT_ENABLE = 1, + parameter PTP_PEROUT_COUNT = 1, + parameter IF_PTP_PERIOD_NS = 6'h2, + parameter IF_PTP_PERIOD_FNS = 16'h8F5C, + + // Queue manager configuration + parameter EVENT_QUEUE_OP_TABLE_SIZE = 32, + parameter TX_QUEUE_OP_TABLE_SIZE = 32, + parameter RX_QUEUE_OP_TABLE_SIZE = 32, + parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE, + parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE, + parameter EVENT_QUEUE_INDEX_WIDTH = 5, + parameter TX_QUEUE_INDEX_WIDTH = 13, + parameter RX_QUEUE_INDEX_WIDTH = 8, + parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, + parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, + parameter EVENT_QUEUE_PIPELINE = 3, + parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0), + parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0), + parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE, + parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE, + + // TX and RX engine configuration + parameter TX_DESC_TABLE_SIZE = 32, + parameter RX_DESC_TABLE_SIZE = 32, + parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH, + + // Scheduler configuration + parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE, + parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE, + parameter TDMA_INDEX_WIDTH = 6, + + // Interface configuration + parameter PTP_TS_ENABLE = 1, + parameter TX_CPL_FIFO_DEPTH = 32, + parameter TX_TAG_WIDTH = 16, + parameter TX_CHECKSUM_ENABLE = 1, + parameter RX_HASH_ENABLE = 1, + parameter RX_CHECKSUM_ENABLE = 1, + parameter ENABLE_PADDING = 1, + parameter ENABLE_DIC = 1, + parameter MIN_FRAME_LENGTH = 64, + parameter TX_FIFO_DEPTH = 32768, + parameter RX_FIFO_DEPTH = 32768, + parameter MAX_TX_SIZE = 9214, + parameter MAX_RX_SIZE = 9214, + parameter TX_RAM_SIZE = 32768, + parameter RX_RAM_SIZE = 32768, + + // Application block configuration + parameter APP_ID = 32'h00000000, + parameter APP_ENABLE = 0, + parameter APP_CTRL_ENABLE = 1, + parameter APP_DMA_ENABLE = 1, + parameter APP_AXIS_DIRECT_ENABLE = 1, + parameter APP_AXIS_SYNC_ENABLE = 1, + parameter APP_AXIS_IF_ENABLE = 1, + parameter APP_STAT_ENABLE = 1, + + // DMA interface configuration + parameter DMA_IMM_ENABLE = 0, + parameter DMA_IMM_WIDTH = 32, + parameter DMA_LEN_WIDTH = 16, + parameter DMA_TAG_WIDTH = 16, + parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE), + parameter RAM_PIPELINE = 2, + + // PCIe interface configuration + parameter AXIS_PCIE_DATA_WIDTH = 512, + parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32), + parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161, + parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 62 : 137, + parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183, + parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81, + parameter RC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 256, + parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, + parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, + parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512, + parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6, + parameter PF_COUNT = 1, + parameter VF_COUNT = 0, + parameter PCIE_TAG_COUNT = 256, + + // Interrupt configuration + parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH, + + // AXI lite interface configuration (control) + parameter AXIL_CTRL_DATA_WIDTH = 32, + parameter AXIL_CTRL_ADDR_WIDTH = 24, + + // AXI lite interface configuration (application control) + parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH, + parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, + + // Ethernet interface configuration + parameter XGMII_DATA_WIDTH = 64, + parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8, + parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH, + parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8, + parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*2, + parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1, + parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1, + parameter AXIS_ETH_TX_PIPELINE = 4, + parameter AXIS_ETH_TX_FIFO_PIPELINE = 4, + parameter AXIS_ETH_TX_TS_PIPELINE = 4, + parameter AXIS_ETH_RX_PIPELINE = 4, + parameter AXIS_ETH_RX_FIFO_PIPELINE = 4, + + // Statistics counter subsystem + parameter STAT_ENABLE = 1, + parameter STAT_DMA_ENABLE = 1, + parameter STAT_PCIE_ENABLE = 1, + parameter STAT_INC_WIDTH = 24, + parameter STAT_ID_WIDTH = 12 +) +( + /* + * Clock: 250 MHz + * Synchronous reset + */ + input wire clk_250mhz, + input wire rst_250mhz, + + /* + * PTP clock + */ + input wire ptp_clk, + input wire ptp_rst, + input wire ptp_sample_clk, + + /* + * GPIO + */ + output wire [15:0] led_red, + output wire [15:0] led_green, + output wire [1:0] led_bmc_red, + output wire [1:0] led_bmc_green, + + input wire pps_in, + output wire pps_out, + + /* + * PCIe + */ + output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata, + output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep, + output wire m_axis_rq_tlast, + input wire m_axis_rq_tready, + output wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser, + output wire m_axis_rq_tvalid, + + input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata, + input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep, + input wire s_axis_rc_tlast, + output wire s_axis_rc_tready, + input wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser, + input wire s_axis_rc_tvalid, + + input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata, + input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep, + input wire s_axis_cq_tlast, + output wire s_axis_cq_tready, + input wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser, + input wire s_axis_cq_tvalid, + + output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata, + output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep, + output wire m_axis_cc_tlast, + input wire m_axis_cc_tready, + output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser, + output wire m_axis_cc_tvalid, + + input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0, + input wire s_axis_rq_seq_num_valid_0, + input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1, + input wire s_axis_rq_seq_num_valid_1, + + input wire [1:0] pcie_tfc_nph_av, + input wire [1:0] pcie_tfc_npd_av, + + input wire [2:0] cfg_max_payload, + input wire [2:0] cfg_max_read_req, + + output wire [9:0] cfg_mgmt_addr, + output wire [7:0] cfg_mgmt_function_number, + output wire cfg_mgmt_write, + output wire [31:0] cfg_mgmt_write_data, + output wire [3:0] cfg_mgmt_byte_enable, + output wire cfg_mgmt_read, + input wire [31:0] cfg_mgmt_read_data, + input wire cfg_mgmt_read_write_done, + + input wire [7:0] cfg_fc_ph, + input wire [11:0] cfg_fc_pd, + input wire [7:0] cfg_fc_nph, + input wire [11:0] cfg_fc_npd, + input wire [7:0] cfg_fc_cplh, + input wire [11:0] cfg_fc_cpld, + output wire [2:0] cfg_fc_sel, + + input wire [3:0] cfg_interrupt_msix_enable, + input wire [3:0] cfg_interrupt_msix_mask, + input wire [251:0] cfg_interrupt_msix_vf_enable, + input wire [251:0] cfg_interrupt_msix_vf_mask, + output wire [63:0] cfg_interrupt_msix_address, + output wire [31:0] cfg_interrupt_msix_data, + output wire cfg_interrupt_msix_int, + output wire [1:0] cfg_interrupt_msix_vec_pending, + input wire cfg_interrupt_msix_vec_pending_status, + input wire cfg_interrupt_msix_sent, + input wire cfg_interrupt_msix_fail, + output wire [7:0] cfg_interrupt_msi_function_number, + + output wire status_error_cor, + output wire status_error_uncor, + + /* + * Ethernet: QSFP28 + */ + input wire qsfp_0_tx_clk_0, + input wire qsfp_0_tx_rst_0, + output wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_0, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_0, + output wire qsfp_0_tx_prbs31_enable_0, + input wire qsfp_0_rx_clk_0, + input wire qsfp_0_rx_rst_0, + input wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_0, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_0, + output wire qsfp_0_rx_prbs31_enable_0, + input wire [6:0] qsfp_0_rx_error_count_0, + input wire qsfp_0_rx_status_0, + + input wire qsfp_0_tx_clk_1, + input wire qsfp_0_tx_rst_1, + output wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_1, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_1, + output wire qsfp_0_tx_prbs31_enable_1, + input wire qsfp_0_rx_clk_1, + input wire qsfp_0_rx_rst_1, + input wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_1, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_1, + output wire qsfp_0_rx_prbs31_enable_1, + input wire [6:0] qsfp_0_rx_error_count_1, + input wire qsfp_0_rx_status_1, + + input wire qsfp_0_tx_clk_2, + input wire qsfp_0_tx_rst_2, + output wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_2, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_2, + output wire qsfp_0_tx_prbs31_enable_2, + input wire qsfp_0_rx_clk_2, + input wire qsfp_0_rx_rst_2, + input wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_2, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_2, + output wire qsfp_0_rx_prbs31_enable_2, + input wire [6:0] qsfp_0_rx_error_count_2, + input wire qsfp_0_rx_status_2, + + input wire qsfp_0_tx_clk_3, + input wire qsfp_0_tx_rst_3, + output wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_3, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_3, + output wire qsfp_0_tx_prbs31_enable_3, + input wire qsfp_0_rx_clk_3, + input wire qsfp_0_rx_rst_3, + input wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_3, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_3, + output wire qsfp_0_rx_prbs31_enable_3, + input wire [6:0] qsfp_0_rx_error_count_3, + input wire qsfp_0_rx_status_3, + + input wire qsfp_0_drp_clk, + input wire qsfp_0_drp_rst, + output wire [23:0] qsfp_0_drp_addr, + output wire [15:0] qsfp_0_drp_di, + output wire qsfp_0_drp_en, + output wire qsfp_0_drp_we, + input wire [15:0] qsfp_0_drp_do, + input wire qsfp_0_drp_rdy, + + input wire qsfp_0_mod_prsnt_n, + output wire qsfp_0_reset_n, + output wire qsfp_0_lp_mode, + input wire qsfp_0_intr_n, + + input wire qsfp_0_i2c_scl_i, + output wire qsfp_0_i2c_scl_o, + output wire qsfp_0_i2c_scl_t, + input wire qsfp_0_i2c_sda_i, + output wire qsfp_0_i2c_sda_o, + output wire qsfp_0_i2c_sda_t, + + input wire qsfp_1_tx_clk_0, + input wire qsfp_1_tx_rst_0, + output wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_0, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_0, + output wire qsfp_1_tx_prbs31_enable_0, + input wire qsfp_1_rx_clk_0, + input wire qsfp_1_rx_rst_0, + input wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_0, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_0, + output wire qsfp_1_rx_prbs31_enable_0, + input wire [6:0] qsfp_1_rx_error_count_0, + input wire qsfp_1_rx_status_0, + + input wire qsfp_1_tx_clk_1, + input wire qsfp_1_tx_rst_1, + output wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_1, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_1, + output wire qsfp_1_tx_prbs31_enable_1, + input wire qsfp_1_rx_clk_1, + input wire qsfp_1_rx_rst_1, + input wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_1, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_1, + output wire qsfp_1_rx_prbs31_enable_1, + input wire [6:0] qsfp_1_rx_error_count_1, + input wire qsfp_1_rx_status_1, + + input wire qsfp_1_tx_clk_2, + input wire qsfp_1_tx_rst_2, + output wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_2, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_2, + output wire qsfp_1_tx_prbs31_enable_2, + input wire qsfp_1_rx_clk_2, + input wire qsfp_1_rx_rst_2, + input wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_2, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_2, + output wire qsfp_1_rx_prbs31_enable_2, + input wire [6:0] qsfp_1_rx_error_count_2, + input wire qsfp_1_rx_status_2, + + input wire qsfp_1_tx_clk_3, + input wire qsfp_1_tx_rst_3, + output wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_3, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_3, + output wire qsfp_1_tx_prbs31_enable_3, + input wire qsfp_1_rx_clk_3, + input wire qsfp_1_rx_rst_3, + input wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_3, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_3, + output wire qsfp_1_rx_prbs31_enable_3, + input wire [6:0] qsfp_1_rx_error_count_3, + input wire qsfp_1_rx_status_3, + + input wire qsfp_1_drp_clk, + input wire qsfp_1_drp_rst, + output wire [23:0] qsfp_1_drp_addr, + output wire [15:0] qsfp_1_drp_di, + output wire qsfp_1_drp_en, + output wire qsfp_1_drp_we, + input wire [15:0] qsfp_1_drp_do, + input wire qsfp_1_drp_rdy, + + input wire qsfp_1_mod_prsnt_n, + output wire qsfp_1_reset_n, + output wire qsfp_1_lp_mode, + input wire qsfp_1_intr_n, + + input wire qsfp_1_i2c_scl_i, + output wire qsfp_1_i2c_scl_o, + output wire qsfp_1_i2c_scl_t, + input wire qsfp_1_i2c_sda_i, + output wire qsfp_1_i2c_sda_o, + output wire qsfp_1_i2c_sda_t, + + input wire qsfp_2_tx_clk_0, + input wire qsfp_2_tx_rst_0, + output wire [XGMII_DATA_WIDTH-1:0] qsfp_2_txd_0, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp_2_txc_0, + output wire qsfp_2_tx_prbs31_enable_0, + input wire qsfp_2_rx_clk_0, + input wire qsfp_2_rx_rst_0, + input wire [XGMII_DATA_WIDTH-1:0] qsfp_2_rxd_0, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp_2_rxc_0, + output wire qsfp_2_rx_prbs31_enable_0, + input wire [6:0] qsfp_2_rx_error_count_0, + input wire qsfp_2_rx_status_0, + + input wire qsfp_2_tx_clk_1, + input wire qsfp_2_tx_rst_1, + output wire [XGMII_DATA_WIDTH-1:0] qsfp_2_txd_1, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp_2_txc_1, + output wire qsfp_2_tx_prbs31_enable_1, + input wire qsfp_2_rx_clk_1, + input wire qsfp_2_rx_rst_1, + input wire [XGMII_DATA_WIDTH-1:0] qsfp_2_rxd_1, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp_2_rxc_1, + output wire qsfp_2_rx_prbs31_enable_1, + input wire [6:0] qsfp_2_rx_error_count_1, + input wire qsfp_2_rx_status_1, + + input wire qsfp_2_tx_clk_2, + input wire qsfp_2_tx_rst_2, + output wire [XGMII_DATA_WIDTH-1:0] qsfp_2_txd_2, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp_2_txc_2, + output wire qsfp_2_tx_prbs31_enable_2, + input wire qsfp_2_rx_clk_2, + input wire qsfp_2_rx_rst_2, + input wire [XGMII_DATA_WIDTH-1:0] qsfp_2_rxd_2, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp_2_rxc_2, + output wire qsfp_2_rx_prbs31_enable_2, + input wire [6:0] qsfp_2_rx_error_count_2, + input wire qsfp_2_rx_status_2, + + input wire qsfp_2_tx_clk_3, + input wire qsfp_2_tx_rst_3, + output wire [XGMII_DATA_WIDTH-1:0] qsfp_2_txd_3, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp_2_txc_3, + output wire qsfp_2_tx_prbs31_enable_3, + input wire qsfp_2_rx_clk_3, + input wire qsfp_2_rx_rst_3, + input wire [XGMII_DATA_WIDTH-1:0] qsfp_2_rxd_3, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp_2_rxc_3, + output wire qsfp_2_rx_prbs31_enable_3, + input wire [6:0] qsfp_2_rx_error_count_3, + input wire qsfp_2_rx_status_3, + + input wire qsfp_2_drp_clk, + input wire qsfp_2_drp_rst, + output wire [23:0] qsfp_2_drp_addr, + output wire [15:0] qsfp_2_drp_di, + output wire qsfp_2_drp_en, + output wire qsfp_2_drp_we, + input wire [15:0] qsfp_2_drp_do, + input wire qsfp_2_drp_rdy, + + input wire qsfp_2_mod_prsnt_n, + output wire qsfp_2_reset_n, + output wire qsfp_2_lp_mode, + input wire qsfp_2_intr_n, + + input wire qsfp_2_i2c_scl_i, + output wire qsfp_2_i2c_scl_o, + output wire qsfp_2_i2c_scl_t, + input wire qsfp_2_i2c_sda_i, + output wire qsfp_2_i2c_sda_o, + output wire qsfp_2_i2c_sda_t, + + input wire qsfp_3_tx_clk_0, + input wire qsfp_3_tx_rst_0, + output wire [XGMII_DATA_WIDTH-1:0] qsfp_3_txd_0, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp_3_txc_0, + output wire qsfp_3_tx_prbs31_enable_0, + input wire qsfp_3_rx_clk_0, + input wire qsfp_3_rx_rst_0, + input wire [XGMII_DATA_WIDTH-1:0] qsfp_3_rxd_0, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp_3_rxc_0, + output wire qsfp_3_rx_prbs31_enable_0, + input wire [6:0] qsfp_3_rx_error_count_0, + input wire qsfp_3_rx_status_0, + + input wire qsfp_3_tx_clk_1, + input wire qsfp_3_tx_rst_1, + output wire [XGMII_DATA_WIDTH-1:0] qsfp_3_txd_1, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp_3_txc_1, + output wire qsfp_3_tx_prbs31_enable_1, + input wire qsfp_3_rx_clk_1, + input wire qsfp_3_rx_rst_1, + input wire [XGMII_DATA_WIDTH-1:0] qsfp_3_rxd_1, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp_3_rxc_1, + output wire qsfp_3_rx_prbs31_enable_1, + input wire [6:0] qsfp_3_rx_error_count_1, + input wire qsfp_3_rx_status_1, + + input wire qsfp_3_tx_clk_2, + input wire qsfp_3_tx_rst_2, + output wire [XGMII_DATA_WIDTH-1:0] qsfp_3_txd_2, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp_3_txc_2, + output wire qsfp_3_tx_prbs31_enable_2, + input wire qsfp_3_rx_clk_2, + input wire qsfp_3_rx_rst_2, + input wire [XGMII_DATA_WIDTH-1:0] qsfp_3_rxd_2, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp_3_rxc_2, + output wire qsfp_3_rx_prbs31_enable_2, + input wire [6:0] qsfp_3_rx_error_count_2, + input wire qsfp_3_rx_status_2, + + input wire qsfp_3_tx_clk_3, + input wire qsfp_3_tx_rst_3, + output wire [XGMII_DATA_WIDTH-1:0] qsfp_3_txd_3, + output wire [XGMII_CTRL_WIDTH-1:0] qsfp_3_txc_3, + output wire qsfp_3_tx_prbs31_enable_3, + input wire qsfp_3_rx_clk_3, + input wire qsfp_3_rx_rst_3, + input wire [XGMII_DATA_WIDTH-1:0] qsfp_3_rxd_3, + input wire [XGMII_CTRL_WIDTH-1:0] qsfp_3_rxc_3, + output wire qsfp_3_rx_prbs31_enable_3, + input wire [6:0] qsfp_3_rx_error_count_3, + input wire qsfp_3_rx_status_3, + + input wire qsfp_3_drp_clk, + input wire qsfp_3_drp_rst, + output wire [23:0] qsfp_3_drp_addr, + output wire [15:0] qsfp_3_drp_di, + output wire qsfp_3_drp_en, + output wire qsfp_3_drp_we, + input wire [15:0] qsfp_3_drp_do, + input wire qsfp_3_drp_rdy, + + input wire qsfp_3_mod_prsnt_n, + output wire qsfp_3_reset_n, + output wire qsfp_3_lp_mode, + input wire qsfp_3_intr_n, + + input wire qsfp_3_i2c_scl_i, + output wire qsfp_3_i2c_scl_o, + output wire qsfp_3_i2c_scl_t, + input wire qsfp_3_i2c_sda_i, + output wire qsfp_3_i2c_sda_o, + output wire qsfp_3_i2c_sda_t +); + +parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF; + +parameter F_COUNT = PF_COUNT+VF_COUNT; + +parameter AXIL_CTRL_STRB_WIDTH = (AXIL_CTRL_DATA_WIDTH/8); +parameter AXIL_IF_CTRL_ADDR_WIDTH = AXIL_CTRL_ADDR_WIDTH-$clog2(IF_COUNT); +parameter AXIL_CSR_ADDR_WIDTH = AXIL_IF_CTRL_ADDR_WIDTH-5-$clog2((PORTS_PER_IF+3)/8); + +localparam RB_BASE_ADDR = 16'h1000; +localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}}; + +localparam RB_DRP_QSFP_0_BASE = RB_BASE_ADDR + 16'h50; +localparam RB_DRP_QSFP_1_BASE = RB_DRP_QSFP_0_BASE + 16'h20; +localparam RB_DRP_QSFP_2_BASE = RB_DRP_QSFP_1_BASE + 16'h20; +localparam RB_DRP_QSFP_3_BASE = RB_DRP_QSFP_2_BASE + 16'h20; + +initial begin + if (PORT_COUNT > 16) begin + $error("Error: Max port count exceeded (instance %m)"); + $finish; + end +end + +// AXI lite connections +wire [AXIL_CSR_ADDR_WIDTH-1:0] axil_csr_awaddr; +wire [2:0] axil_csr_awprot; +wire axil_csr_awvalid; +wire axil_csr_awready; +wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_csr_wdata; +wire [AXIL_CTRL_STRB_WIDTH-1:0] axil_csr_wstrb; +wire axil_csr_wvalid; +wire axil_csr_wready; +wire [1:0] axil_csr_bresp; +wire axil_csr_bvalid; +wire axil_csr_bready; +wire [AXIL_CSR_ADDR_WIDTH-1:0] axil_csr_araddr; +wire [2:0] axil_csr_arprot; +wire axil_csr_arvalid; +wire axil_csr_arready; +wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_csr_rdata; +wire [1:0] axil_csr_rresp; +wire axil_csr_rvalid; +wire axil_csr_rready; + +// PTP +wire [PTP_TS_WIDTH-1:0] ptp_ts_96; +wire ptp_ts_step; +wire ptp_pps; +wire ptp_pps_str; +wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96; +wire ptp_sync_ts_step; +wire ptp_sync_pps; + +wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked; +wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error; +wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse; + +// control registers +wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_wr_addr; +wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_wr_data; +wire [AXIL_CTRL_STRB_WIDTH-1:0] ctrl_reg_wr_strb; +wire ctrl_reg_wr_en; +wire ctrl_reg_wr_wait; +wire ctrl_reg_wr_ack; +wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_rd_addr; +wire ctrl_reg_rd_en; +wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data; +wire ctrl_reg_rd_wait; +wire ctrl_reg_rd_ack; + +wire qsfp_0_drp_reg_wr_wait; +wire qsfp_0_drp_reg_wr_ack; +wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp_0_drp_reg_rd_data; +wire qsfp_0_drp_reg_rd_wait; +wire qsfp_0_drp_reg_rd_ack; + +wire qsfp_1_drp_reg_wr_wait; +wire qsfp_1_drp_reg_wr_ack; +wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp_1_drp_reg_rd_data; +wire qsfp_1_drp_reg_rd_wait; +wire qsfp_1_drp_reg_rd_ack; + +wire qsfp_2_drp_reg_wr_wait; +wire qsfp_2_drp_reg_wr_ack; +wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp_2_drp_reg_rd_data; +wire qsfp_2_drp_reg_rd_wait; +wire qsfp_2_drp_reg_rd_ack; + +wire qsfp_3_drp_reg_wr_wait; +wire qsfp_3_drp_reg_wr_ack; +wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp_3_drp_reg_rd_data; +wire qsfp_3_drp_reg_rd_wait; +wire qsfp_3_drp_reg_rd_ack; + +reg ctrl_reg_wr_ack_reg = 1'b0; +reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}}; +reg ctrl_reg_rd_ack_reg = 1'b0; + +reg qsfp_0_reset_reg = 1'b0; +reg qsfp_0_lp_mode_reg = 1'b0; +reg qsfp_0_i2c_scl_o_reg = 1'b1; +reg qsfp_0_i2c_sda_o_reg = 1'b1; + +reg qsfp_1_reset_reg = 1'b0; +reg qsfp_1_lp_mode_reg = 1'b0; +reg qsfp_1_i2c_scl_o_reg = 1'b1; +reg qsfp_1_i2c_sda_o_reg = 1'b1; + +reg qsfp_2_reset_reg = 1'b0; +reg qsfp_2_lp_mode_reg = 1'b0; +reg qsfp_2_i2c_scl_o_reg = 1'b1; +reg qsfp_2_i2c_sda_o_reg = 1'b1; + +reg qsfp_3_reset_reg = 1'b0; +reg qsfp_3_lp_mode_reg = 1'b0; +reg qsfp_3_i2c_scl_o_reg = 1'b1; +reg qsfp_3_i2c_sda_o_reg = 1'b1; + +assign ctrl_reg_wr_wait = qsfp_0_drp_reg_wr_wait | qsfp_1_drp_reg_wr_wait | qsfp_2_drp_reg_wr_wait | qsfp_3_drp_reg_wr_wait; +assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg | qsfp_0_drp_reg_wr_ack | qsfp_1_drp_reg_wr_ack | qsfp_2_drp_reg_wr_ack | qsfp_3_drp_reg_wr_ack; +assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg | qsfp_0_drp_reg_rd_data | qsfp_1_drp_reg_rd_data | qsfp_2_drp_reg_rd_data | qsfp_3_drp_reg_rd_data; +assign ctrl_reg_rd_wait = qsfp_0_drp_reg_rd_wait | qsfp_1_drp_reg_rd_wait | qsfp_2_drp_reg_rd_wait | qsfp_3_drp_reg_rd_wait; +assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg | qsfp_0_drp_reg_rd_ack | qsfp_1_drp_reg_rd_ack | qsfp_2_drp_reg_rd_ack | qsfp_3_drp_reg_rd_ack; + +assign qsfp_0_reset_n = !qsfp_0_reset_reg; +assign qsfp_0_lp_mode = qsfp_0_lp_mode_reg; +assign qsfp_0_i2c_scl_o = qsfp_0_i2c_scl_o_reg; +assign qsfp_0_i2c_scl_t = qsfp_0_i2c_scl_o_reg; +assign qsfp_0_i2c_sda_o = qsfp_0_i2c_sda_o_reg; +assign qsfp_0_i2c_sda_t = qsfp_0_i2c_sda_o_reg; + +assign qsfp_1_reset_n = !qsfp_1_reset_reg; +assign qsfp_1_lp_mode = qsfp_1_lp_mode_reg; +assign qsfp_1_i2c_scl_o = qsfp_1_i2c_scl_o_reg; +assign qsfp_1_i2c_scl_t = qsfp_1_i2c_scl_o_reg; +assign qsfp_1_i2c_sda_o = qsfp_1_i2c_sda_o_reg; +assign qsfp_1_i2c_sda_t = qsfp_1_i2c_sda_o_reg; + +assign qsfp_2_reset_n = !qsfp_2_reset_reg; +assign qsfp_2_lp_mode = qsfp_2_lp_mode_reg; +assign qsfp_2_i2c_scl_o = qsfp_2_i2c_scl_o_reg; +assign qsfp_2_i2c_scl_t = qsfp_2_i2c_scl_o_reg; +assign qsfp_2_i2c_sda_o = qsfp_2_i2c_sda_o_reg; +assign qsfp_2_i2c_sda_t = qsfp_2_i2c_sda_o_reg; + +assign qsfp_3_reset_n = !qsfp_3_reset_reg; +assign qsfp_3_lp_mode = qsfp_3_lp_mode_reg; +assign qsfp_3_i2c_scl_o = qsfp_3_i2c_scl_o_reg; +assign qsfp_3_i2c_scl_t = qsfp_3_i2c_scl_o_reg; +assign qsfp_3_i2c_sda_o = qsfp_3_i2c_sda_o_reg; +assign qsfp_3_i2c_sda_t = qsfp_3_i2c_sda_o_reg; + +always @(posedge clk_250mhz) begin + ctrl_reg_wr_ack_reg <= 1'b0; + ctrl_reg_rd_data_reg <= {AXIL_CTRL_DATA_WIDTH{1'b0}}; + ctrl_reg_rd_ack_reg <= 1'b0; + + if (ctrl_reg_wr_en && !ctrl_reg_wr_ack_reg) begin + // write operation + ctrl_reg_wr_ack_reg <= 1'b0; + case ({ctrl_reg_wr_addr >> 2, 2'b00}) + // I2C 0 + RBB+8'h0C: begin + // I2C ctrl: control + if (ctrl_reg_wr_strb[0]) begin + qsfp_0_i2c_scl_o_reg <= ctrl_reg_wr_data[1]; + end + if (ctrl_reg_wr_strb[1]) begin + qsfp_0_i2c_sda_o_reg <= ctrl_reg_wr_data[9]; + end + end + // I2C 1 + RBB+8'h1C: begin + // I2C ctrl: control + if (ctrl_reg_wr_strb[0]) begin + qsfp_1_i2c_scl_o_reg <= ctrl_reg_wr_data[1]; + end + if (ctrl_reg_wr_strb[1]) begin + qsfp_1_i2c_sda_o_reg <= ctrl_reg_wr_data[9]; + end + end + // I2C 2 + RBB+8'h2C: begin + // I2C ctrl: control + if (ctrl_reg_wr_strb[0]) begin + qsfp_2_i2c_scl_o_reg <= ctrl_reg_wr_data[1]; + end + if (ctrl_reg_wr_strb[1]) begin + qsfp_2_i2c_sda_o_reg <= ctrl_reg_wr_data[9]; + end + end + // I2C 3 + RBB+8'h3C: begin + // I2C ctrl: control + if (ctrl_reg_wr_strb[0]) begin + qsfp_3_i2c_scl_o_reg <= ctrl_reg_wr_data[1]; + end + if (ctrl_reg_wr_strb[1]) begin + qsfp_3_i2c_sda_o_reg <= ctrl_reg_wr_data[9]; + end + end + // XCVR GPIO + RBB+8'h4C: begin + // XCVR GPIO: control 0123 + if (ctrl_reg_wr_strb[0]) begin + qsfp_0_reset_reg <= ctrl_reg_wr_data[4]; + qsfp_0_lp_mode_reg <= ctrl_reg_wr_data[5]; + end + if (ctrl_reg_wr_strb[1]) begin + qsfp_1_reset_reg <= ctrl_reg_wr_data[12]; + qsfp_1_lp_mode_reg <= ctrl_reg_wr_data[13]; + end + if (ctrl_reg_wr_strb[2]) begin + qsfp_2_reset_reg <= ctrl_reg_wr_data[20]; + qsfp_2_lp_mode_reg <= ctrl_reg_wr_data[21]; + end + if (ctrl_reg_wr_strb[3]) begin + qsfp_3_reset_reg <= ctrl_reg_wr_data[28]; + qsfp_3_lp_mode_reg <= ctrl_reg_wr_data[29]; + end + end + default: ctrl_reg_wr_ack_reg <= 1'b0; + endcase + end + + if (ctrl_reg_rd_en && !ctrl_reg_rd_ack_reg) begin + // read operation + ctrl_reg_rd_ack_reg <= 1'b1; + case ({ctrl_reg_rd_addr >> 2, 2'b00}) + // I2C 0 + RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C110; // I2C ctrl: Type + RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000100; // I2C ctrl: Version + RBB+8'h08: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h10; // I2C ctrl: Next header + RBB+8'h0C: begin + // I2C ctrl: control + ctrl_reg_rd_data_reg[0] <= qsfp_0_i2c_scl_i; + ctrl_reg_rd_data_reg[1] <= qsfp_0_i2c_scl_o_reg; + ctrl_reg_rd_data_reg[8] <= qsfp_0_i2c_sda_i; + ctrl_reg_rd_data_reg[9] <= qsfp_0_i2c_sda_o_reg; + end + // I2C 1 + RBB+8'h10: ctrl_reg_rd_data_reg <= 32'h0000C110; // I2C ctrl: Type + RBB+8'h14: ctrl_reg_rd_data_reg <= 32'h00000100; // I2C ctrl: Version + RBB+8'h18: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h20; // I2C ctrl: Next header + RBB+8'h1C: begin + // I2C ctrl: control + ctrl_reg_rd_data_reg[0] <= qsfp_1_i2c_scl_i; + ctrl_reg_rd_data_reg[1] <= qsfp_1_i2c_scl_o_reg; + ctrl_reg_rd_data_reg[8] <= qsfp_1_i2c_sda_i; + ctrl_reg_rd_data_reg[9] <= qsfp_1_i2c_sda_o_reg; + end + // I2C 2 + RBB+8'h20: ctrl_reg_rd_data_reg <= 32'h0000C110; // I2C ctrl: Type + RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000100; // I2C ctrl: Version + RBB+8'h28: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h30; // I2C ctrl: Next header + RBB+8'h2C: begin + // I2C ctrl: control + ctrl_reg_rd_data_reg[0] <= qsfp_2_i2c_scl_i; + ctrl_reg_rd_data_reg[1] <= qsfp_2_i2c_scl_o_reg; + ctrl_reg_rd_data_reg[8] <= qsfp_2_i2c_sda_i; + ctrl_reg_rd_data_reg[9] <= qsfp_2_i2c_sda_o_reg; + end + // I2C 3 + RBB+8'h30: ctrl_reg_rd_data_reg <= 32'h0000C110; // I2C ctrl: Type + RBB+8'h34: ctrl_reg_rd_data_reg <= 32'h00000100; // I2C ctrl: Version + RBB+8'h38: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h40; // I2C ctrl: Next header + RBB+8'h3C: begin + // I2C ctrl: control + ctrl_reg_rd_data_reg[0] <= qsfp_3_i2c_scl_i; + ctrl_reg_rd_data_reg[1] <= qsfp_3_i2c_scl_o_reg; + ctrl_reg_rd_data_reg[8] <= qsfp_3_i2c_sda_i; + ctrl_reg_rd_data_reg[9] <= qsfp_3_i2c_sda_o_reg; + end + // XCVR GPIO + RBB+8'h40: ctrl_reg_rd_data_reg <= 32'h0000C101; // XCVR GPIO: Type + RBB+8'h44: ctrl_reg_rd_data_reg <= 32'h00000100; // XCVR GPIO: Version + RBB+8'h48: ctrl_reg_rd_data_reg <= RB_DRP_QSFP_0_BASE; // XCVR GPIO: Next header + RBB+8'h4C: begin + // XCVR GPIO: control 0123 + ctrl_reg_rd_data_reg[0] <= !qsfp_0_mod_prsnt_n; + ctrl_reg_rd_data_reg[1] <= !qsfp_0_intr_n; + ctrl_reg_rd_data_reg[4] <= qsfp_0_reset_reg; + ctrl_reg_rd_data_reg[5] <= qsfp_0_lp_mode_reg; + ctrl_reg_rd_data_reg[8] <= !qsfp_1_mod_prsnt_n; + ctrl_reg_rd_data_reg[9] <= !qsfp_1_intr_n; + ctrl_reg_rd_data_reg[12] <= qsfp_1_reset_reg; + ctrl_reg_rd_data_reg[13] <= qsfp_1_lp_mode_reg; + ctrl_reg_rd_data_reg[16] <= !qsfp_2_mod_prsnt_n; + ctrl_reg_rd_data_reg[17] <= !qsfp_2_intr_n; + ctrl_reg_rd_data_reg[20] <= qsfp_2_reset_reg; + ctrl_reg_rd_data_reg[21] <= qsfp_2_lp_mode_reg; + ctrl_reg_rd_data_reg[24] <= !qsfp_3_mod_prsnt_n; + ctrl_reg_rd_data_reg[25] <= !qsfp_3_intr_n; + ctrl_reg_rd_data_reg[28] <= qsfp_3_reset_reg; + ctrl_reg_rd_data_reg[29] <= qsfp_3_lp_mode_reg; + end + default: ctrl_reg_rd_ack_reg <= 1'b0; + endcase + end + + if (rst_250mhz) begin + ctrl_reg_wr_ack_reg <= 1'b0; + ctrl_reg_rd_ack_reg <= 1'b0; + + qsfp_0_reset_reg <= 1'b0; + qsfp_0_lp_mode_reg <= 1'b0; + qsfp_0_i2c_scl_o_reg <= 1'b1; + qsfp_0_i2c_sda_o_reg <= 1'b1; + + qsfp_1_reset_reg <= 1'b0; + qsfp_1_lp_mode_reg <= 1'b0; + qsfp_1_i2c_scl_o_reg <= 1'b1; + qsfp_1_i2c_sda_o_reg <= 1'b1; + + qsfp_2_reset_reg <= 1'b0; + qsfp_2_lp_mode_reg <= 1'b0; + qsfp_2_i2c_scl_o_reg <= 1'b1; + qsfp_2_i2c_sda_o_reg <= 1'b1; + + qsfp_3_reset_reg <= 1'b0; + qsfp_3_lp_mode_reg <= 1'b0; + qsfp_3_i2c_scl_o_reg <= 1'b1; + qsfp_3_i2c_sda_o_reg <= 1'b1; + end +end + +rb_drp #( + .DRP_ADDR_WIDTH(24), + .DRP_DATA_WIDTH(16), + .DRP_INFO({8'h09, 8'h03, 8'd0, 8'd4}), + .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), + .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .RB_BASE_ADDR(RB_DRP_QSFP_0_BASE), + .RB_NEXT_PTR(RB_DRP_QSFP_1_BASE) +) +qsfp_0_rb_drp_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * Register interface + */ + .reg_wr_addr(ctrl_reg_wr_addr), + .reg_wr_data(ctrl_reg_wr_data), + .reg_wr_strb(ctrl_reg_wr_strb), + .reg_wr_en(ctrl_reg_wr_en), + .reg_wr_wait(qsfp_0_drp_reg_wr_wait), + .reg_wr_ack(qsfp_0_drp_reg_wr_ack), + .reg_rd_addr(ctrl_reg_rd_addr), + .reg_rd_en(ctrl_reg_rd_en), + .reg_rd_data(qsfp_0_drp_reg_rd_data), + .reg_rd_wait(qsfp_0_drp_reg_rd_wait), + .reg_rd_ack(qsfp_0_drp_reg_rd_ack), + + /* + * DRP + */ + .drp_clk(qsfp_0_drp_clk), + .drp_rst(qsfp_0_drp_rst), + .drp_addr(qsfp_0_drp_addr), + .drp_di(qsfp_0_drp_di), + .drp_en(qsfp_0_drp_en), + .drp_we(qsfp_0_drp_we), + .drp_do(qsfp_0_drp_do), + .drp_rdy(qsfp_0_drp_rdy) +); + +rb_drp #( + .DRP_ADDR_WIDTH(24), + .DRP_DATA_WIDTH(16), + .DRP_INFO({8'h09, 8'h03, 8'd0, 8'd4}), + .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), + .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .RB_BASE_ADDR(RB_DRP_QSFP_1_BASE), + .RB_NEXT_PTR(RB_DRP_QSFP_2_BASE) +) +qsfp_1_rb_drp_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * Register interface + */ + .reg_wr_addr(ctrl_reg_wr_addr), + .reg_wr_data(ctrl_reg_wr_data), + .reg_wr_strb(ctrl_reg_wr_strb), + .reg_wr_en(ctrl_reg_wr_en), + .reg_wr_wait(qsfp_1_drp_reg_wr_wait), + .reg_wr_ack(qsfp_1_drp_reg_wr_ack), + .reg_rd_addr(ctrl_reg_rd_addr), + .reg_rd_en(ctrl_reg_rd_en), + .reg_rd_data(qsfp_1_drp_reg_rd_data), + .reg_rd_wait(qsfp_1_drp_reg_rd_wait), + .reg_rd_ack(qsfp_1_drp_reg_rd_ack), + + /* + * DRP + */ + .drp_clk(qsfp_1_drp_clk), + .drp_rst(qsfp_1_drp_rst), + .drp_addr(qsfp_1_drp_addr), + .drp_di(qsfp_1_drp_di), + .drp_en(qsfp_1_drp_en), + .drp_we(qsfp_1_drp_we), + .drp_do(qsfp_1_drp_do), + .drp_rdy(qsfp_1_drp_rdy) +); + +rb_drp #( + .DRP_ADDR_WIDTH(24), + .DRP_DATA_WIDTH(16), + .DRP_INFO({8'h09, 8'h03, 8'd0, 8'd4}), + .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), + .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .RB_BASE_ADDR(RB_DRP_QSFP_2_BASE), + .RB_NEXT_PTR(RB_DRP_QSFP_3_BASE) +) +qsfp_2_rb_drp_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * Register interface + */ + .reg_wr_addr(ctrl_reg_wr_addr), + .reg_wr_data(ctrl_reg_wr_data), + .reg_wr_strb(ctrl_reg_wr_strb), + .reg_wr_en(ctrl_reg_wr_en), + .reg_wr_wait(qsfp_2_drp_reg_wr_wait), + .reg_wr_ack(qsfp_2_drp_reg_wr_ack), + .reg_rd_addr(ctrl_reg_rd_addr), + .reg_rd_en(ctrl_reg_rd_en), + .reg_rd_data(qsfp_2_drp_reg_rd_data), + .reg_rd_wait(qsfp_2_drp_reg_rd_wait), + .reg_rd_ack(qsfp_2_drp_reg_rd_ack), + + /* + * DRP + */ + .drp_clk(qsfp_2_drp_clk), + .drp_rst(qsfp_2_drp_rst), + .drp_addr(qsfp_2_drp_addr), + .drp_di(qsfp_2_drp_di), + .drp_en(qsfp_2_drp_en), + .drp_we(qsfp_2_drp_we), + .drp_do(qsfp_2_drp_do), + .drp_rdy(qsfp_2_drp_rdy) +); + +rb_drp #( + .DRP_ADDR_WIDTH(24), + .DRP_DATA_WIDTH(16), + .DRP_INFO({8'h09, 8'h03, 8'd0, 8'd4}), + .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), + .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .RB_BASE_ADDR(RB_DRP_QSFP_3_BASE), + .RB_NEXT_PTR(0) +) +qsfp_3_rb_drp_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * Register interface + */ + .reg_wr_addr(ctrl_reg_wr_addr), + .reg_wr_data(ctrl_reg_wr_data), + .reg_wr_strb(ctrl_reg_wr_strb), + .reg_wr_en(ctrl_reg_wr_en), + .reg_wr_wait(qsfp_3_drp_reg_wr_wait), + .reg_wr_ack(qsfp_3_drp_reg_wr_ack), + .reg_rd_addr(ctrl_reg_rd_addr), + .reg_rd_en(ctrl_reg_rd_en), + .reg_rd_data(qsfp_3_drp_reg_rd_data), + .reg_rd_wait(qsfp_3_drp_reg_rd_wait), + .reg_rd_ack(qsfp_3_drp_reg_rd_ack), + + /* + * DRP + */ + .drp_clk(qsfp_3_drp_clk), + .drp_rst(qsfp_3_drp_rst), + .drp_addr(qsfp_3_drp_addr), + .drp_di(qsfp_3_drp_di), + .drp_en(qsfp_3_drp_en), + .drp_we(qsfp_3_drp_we), + .drp_do(qsfp_3_drp_do), + .drp_rdy(qsfp_3_drp_rdy) +); + +assign pps_out = ptp_perout_pulse[0]; + +generate + +if (TDMA_BER_ENABLE) begin + + // BER tester + tdma_ber #( + .COUNT(16), + .INDEX_WIDTH(6), + .SLICE_WIDTH(5), + .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_ADDR_WIDTH(8+6+$clog2(16)), + .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .SCHEDULE_START_S(0), + .SCHEDULE_START_NS(0), + .SCHEDULE_PERIOD_S(0), + .SCHEDULE_PERIOD_NS(1000000), + .TIMESLOT_PERIOD_S(0), + .TIMESLOT_PERIOD_NS(100000), + .ACTIVE_PERIOD_S(0), + .ACTIVE_PERIOD_NS(90000) + ) + tdma_ber_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + .phy_tx_clk({qsfp_3_tx_clk_3, qsfp_3_tx_clk_2, qsfp_3_tx_clk_1, qsfp_3_tx_clk_0, qsfp_2_tx_clk_3, qsfp_2_tx_clk_2, qsfp_2_tx_clk_1, qsfp_2_tx_clk_0, qsfp_1_tx_clk_3, qsfp_1_tx_clk_2, qsfp_1_tx_clk_1, qsfp_1_tx_clk_0, qsfp_0_tx_clk_3, qsfp_0_tx_clk_2, qsfp_0_tx_clk_1, qsfp_0_tx_clk_0}), + .phy_rx_clk({qsfp_3_rx_clk_3, qsfp_3_rx_clk_2, qsfp_3_rx_clk_1, qsfp_3_rx_clk_0, qsfp_2_rx_clk_3, qsfp_2_rx_clk_2, qsfp_2_rx_clk_1, qsfp_2_rx_clk_0, qsfp_1_rx_clk_3, qsfp_1_rx_clk_2, qsfp_1_rx_clk_1, qsfp_1_rx_clk_0, qsfp_0_rx_clk_3, qsfp_0_rx_clk_2, qsfp_0_rx_clk_1, qsfp_0_rx_clk_0}), + .phy_rx_error_count({qsfp_3_rx_error_count_3, qsfp_3_rx_error_count_2, qsfp_3_rx_error_count_1, qsfp_3_rx_error_count_0, qsfp_2_rx_error_count_3, qsfp_2_rx_error_count_2, qsfp_2_rx_error_count_1, qsfp_2_rx_error_count_0, qsfp_1_rx_error_count_3, qsfp_1_rx_error_count_2, qsfp_1_rx_error_count_1, qsfp_1_rx_error_count_0, qsfp_0_rx_error_count_3, qsfp_0_rx_error_count_2, qsfp_0_rx_error_count_1, qsfp_0_rx_error_count_0}), + .phy_tx_prbs31_enable({qsfp_3_tx_prbs31_enable_3, qsfp_3_tx_prbs31_enable_2, qsfp_3_tx_prbs31_enable_1, qsfp_3_tx_prbs31_enable_0, qsfp_2_tx_prbs31_enable_3, qsfp_2_tx_prbs31_enable_2, qsfp_2_tx_prbs31_enable_1, qsfp_2_tx_prbs31_enable_0, qsfp_1_tx_prbs31_enable_3, qsfp_1_tx_prbs31_enable_2, qsfp_1_tx_prbs31_enable_1, qsfp_1_tx_prbs31_enable_0, qsfp_0_tx_prbs31_enable_3, qsfp_0_tx_prbs31_enable_2, qsfp_0_tx_prbs31_enable_1, qsfp_0_tx_prbs31_enable_0}), + .phy_rx_prbs31_enable({qsfp_3_rx_prbs31_enable_3, qsfp_3_rx_prbs31_enable_2, qsfp_3_rx_prbs31_enable_1, qsfp_3_rx_prbs31_enable_0, qsfp_2_rx_prbs31_enable_3, qsfp_2_rx_prbs31_enable_2, qsfp_2_rx_prbs31_enable_1, qsfp_2_rx_prbs31_enable_0, qsfp_1_rx_prbs31_enable_3, qsfp_1_rx_prbs31_enable_2, qsfp_1_rx_prbs31_enable_1, qsfp_1_rx_prbs31_enable_0, qsfp_0_rx_prbs31_enable_3, qsfp_0_rx_prbs31_enable_2, qsfp_0_rx_prbs31_enable_1, qsfp_0_rx_prbs31_enable_0}), + .s_axil_awaddr(axil_csr_awaddr), + .s_axil_awprot(axil_csr_awprot), + .s_axil_awvalid(axil_csr_awvalid), + .s_axil_awready(axil_csr_awready), + .s_axil_wdata(axil_csr_wdata), + .s_axil_wstrb(axil_csr_wstrb), + .s_axil_wvalid(axil_csr_wvalid), + .s_axil_wready(axil_csr_wready), + .s_axil_bresp(axil_csr_bresp), + .s_axil_bvalid(axil_csr_bvalid), + .s_axil_bready(axil_csr_bready), + .s_axil_araddr(axil_csr_araddr), + .s_axil_arprot(axil_csr_arprot), + .s_axil_arvalid(axil_csr_arvalid), + .s_axil_arready(axil_csr_arready), + .s_axil_rdata(axil_csr_rdata), + .s_axil_rresp(axil_csr_rresp), + .s_axil_rvalid(axil_csr_rvalid), + .s_axil_rready(axil_csr_rready), + .ptp_ts_96(ptp_sync_ts_96), + .ptp_ts_step(ptp_sync_ts_step) + ); + +end else begin + + assign qsfp_0_tx_prbs31_enable_0 = 1'b0; + assign qsfp_0_rx_prbs31_enable_0 = 1'b0; + assign qsfp_0_tx_prbs31_enable_1 = 1'b0; + assign qsfp_0_rx_prbs31_enable_1 = 1'b0; + assign qsfp_0_tx_prbs31_enable_2 = 1'b0; + assign qsfp_0_rx_prbs31_enable_2 = 1'b0; + assign qsfp_0_tx_prbs31_enable_3 = 1'b0; + assign qsfp_0_rx_prbs31_enable_3 = 1'b0; + assign qsfp_1_tx_prbs31_enable_0 = 1'b0; + assign qsfp_1_rx_prbs31_enable_0 = 1'b0; + assign qsfp_1_tx_prbs31_enable_1 = 1'b0; + assign qsfp_1_rx_prbs31_enable_1 = 1'b0; + assign qsfp_1_tx_prbs31_enable_2 = 1'b0; + assign qsfp_1_rx_prbs31_enable_2 = 1'b0; + assign qsfp_1_tx_prbs31_enable_3 = 1'b0; + assign qsfp_1_rx_prbs31_enable_3 = 1'b0; + assign qsfp_2_tx_prbs31_enable_0 = 1'b0; + assign qsfp_2_rx_prbs31_enable_0 = 1'b0; + assign qsfp_2_tx_prbs31_enable_1 = 1'b0; + assign qsfp_2_rx_prbs31_enable_1 = 1'b0; + assign qsfp_2_tx_prbs31_enable_2 = 1'b0; + assign qsfp_2_rx_prbs31_enable_2 = 1'b0; + assign qsfp_2_tx_prbs31_enable_3 = 1'b0; + assign qsfp_2_rx_prbs31_enable_3 = 1'b0; + assign qsfp_3_tx_prbs31_enable_0 = 1'b0; + assign qsfp_3_rx_prbs31_enable_0 = 1'b0; + assign qsfp_3_tx_prbs31_enable_1 = 1'b0; + assign qsfp_3_rx_prbs31_enable_1 = 1'b0; + assign qsfp_3_tx_prbs31_enable_2 = 1'b0; + assign qsfp_3_rx_prbs31_enable_2 = 1'b0; + assign qsfp_3_tx_prbs31_enable_3 = 1'b0; + assign qsfp_3_rx_prbs31_enable_3 = 1'b0; + +end + +endgenerate + +assign led_red = 16'd0; +assign led_green = 16'd0; +assign led_bmc_green[0] = ptp_pps_str; +assign led_bmc_green[1] = 0; +assign led_bmc_red[0] = 0; +assign led_bmc_red[1] = 0; + +wire [PORT_COUNT-1:0] eth_tx_clk; +wire [PORT_COUNT-1:0] eth_tx_rst; + +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96; +wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step; + +wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata; +wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep; +wire [PORT_COUNT-1:0] axis_eth_tx_tvalid; +wire [PORT_COUNT-1:0] axis_eth_tx_tready; +wire [PORT_COUNT-1:0] axis_eth_tx_tlast; +wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] axis_eth_tx_tuser; + +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts; +wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag; +wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid; +wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready; + +wire [PORT_COUNT-1:0] eth_tx_status; + +wire [PORT_COUNT-1:0] eth_rx_clk; +wire [PORT_COUNT-1:0] eth_rx_rst; + +wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96; +wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step; + +wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata; +wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep; +wire [PORT_COUNT-1:0] axis_eth_rx_tvalid; +wire [PORT_COUNT-1:0] axis_eth_rx_tready; +wire [PORT_COUNT-1:0] axis_eth_rx_tlast; +wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser; + +wire [PORT_COUNT-1:0] eth_rx_status; + +wire [PORT_COUNT-1:0] port_xgmii_tx_clk; +wire [PORT_COUNT-1:0] port_xgmii_tx_rst; +wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0] port_xgmii_txd; +wire [PORT_COUNT*XGMII_CTRL_WIDTH-1:0] port_xgmii_txc; + +wire [PORT_COUNT-1:0] port_xgmii_rx_clk; +wire [PORT_COUNT-1:0] port_xgmii_rx_rst; +wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0] port_xgmii_rxd; +wire [PORT_COUNT*XGMII_CTRL_WIDTH-1:0] port_xgmii_rxc; + +mqnic_port_map_phy_xgmii #( + .PHY_COUNT(16), + .PORT_MASK(PORT_MASK), + .PORT_GROUP_SIZE(4), + + .IF_COUNT(IF_COUNT), + .PORTS_PER_IF(PORTS_PER_IF), + + .PORT_COUNT(PORT_COUNT), + + .XGMII_DATA_WIDTH(XGMII_DATA_WIDTH), + .XGMII_CTRL_WIDTH(XGMII_CTRL_WIDTH) +) +mqnic_port_map_phy_xgmii_inst ( + // towards PHY + .phy_xgmii_tx_clk({qsfp_3_tx_clk_3, qsfp_3_tx_clk_2, qsfp_3_tx_clk_1, qsfp_3_tx_clk_0, qsfp_2_tx_clk_3, qsfp_2_tx_clk_2, qsfp_2_tx_clk_1, qsfp_2_tx_clk_0, qsfp_1_tx_clk_3, qsfp_1_tx_clk_2, qsfp_1_tx_clk_1, qsfp_1_tx_clk_0, qsfp_0_tx_clk_3, qsfp_0_tx_clk_2, qsfp_0_tx_clk_1, qsfp_0_tx_clk_0}), + .phy_xgmii_tx_rst({qsfp_3_tx_rst_3, qsfp_3_tx_rst_2, qsfp_3_tx_rst_1, qsfp_3_tx_rst_0, qsfp_2_tx_rst_3, qsfp_2_tx_rst_2, qsfp_2_tx_rst_1, qsfp_2_tx_rst_0, qsfp_1_tx_rst_3, qsfp_1_tx_rst_2, qsfp_1_tx_rst_1, qsfp_1_tx_rst_0, qsfp_0_tx_rst_3, qsfp_0_tx_rst_2, qsfp_0_tx_rst_1, qsfp_0_tx_rst_0}), + .phy_xgmii_txd({qsfp_3_txd_3, qsfp_3_txd_2, qsfp_3_txd_1, qsfp_3_txd_0, qsfp_2_txd_3, qsfp_2_txd_2, qsfp_2_txd_1, qsfp_2_txd_0, qsfp_1_txd_3, qsfp_1_txd_2, qsfp_1_txd_1, qsfp_1_txd_0, qsfp_0_txd_3, qsfp_0_txd_2, qsfp_0_txd_1, qsfp_0_txd_0}), + .phy_xgmii_txc({qsfp_3_txc_3, qsfp_3_txc_2, qsfp_3_txc_1, qsfp_3_txc_0, qsfp_2_txc_3, qsfp_2_txc_2, qsfp_2_txc_1, qsfp_2_txc_0, qsfp_1_txc_3, qsfp_1_txc_2, qsfp_1_txc_1, qsfp_1_txc_0, qsfp_0_txc_3, qsfp_0_txc_2, qsfp_0_txc_1, qsfp_0_txc_0}), + .phy_tx_status(8'hff), + + .phy_xgmii_rx_clk({qsfp_3_rx_clk_3, qsfp_3_rx_clk_2, qsfp_3_rx_clk_1, qsfp_3_rx_clk_0, qsfp_2_rx_clk_3, qsfp_2_rx_clk_2, qsfp_2_rx_clk_1, qsfp_2_rx_clk_0, qsfp_1_rx_clk_3, qsfp_1_rx_clk_2, qsfp_1_rx_clk_1, qsfp_1_rx_clk_0, qsfp_0_rx_clk_3, qsfp_0_rx_clk_2, qsfp_0_rx_clk_1, qsfp_0_rx_clk_0}), + .phy_xgmii_rx_rst({qsfp_3_rx_rst_3, qsfp_3_rx_rst_2, qsfp_3_rx_rst_1, qsfp_3_rx_rst_0, qsfp_2_rx_rst_3, qsfp_2_rx_rst_2, qsfp_2_rx_rst_1, qsfp_2_rx_rst_0, qsfp_1_rx_rst_3, qsfp_1_rx_rst_2, qsfp_1_rx_rst_1, qsfp_1_rx_rst_0, qsfp_0_rx_rst_3, qsfp_0_rx_rst_2, qsfp_0_rx_rst_1, qsfp_0_rx_rst_0}), + .phy_xgmii_rxd({qsfp_3_rxd_3, qsfp_3_rxd_2, qsfp_3_rxd_1, qsfp_3_rxd_0, qsfp_2_rxd_3, qsfp_2_rxd_2, qsfp_2_rxd_1, qsfp_2_rxd_0, qsfp_1_rxd_3, qsfp_1_rxd_2, qsfp_1_rxd_1, qsfp_1_rxd_0, qsfp_0_rxd_3, qsfp_0_rxd_2, qsfp_0_rxd_1, qsfp_0_rxd_0}), + .phy_xgmii_rxc({qsfp_3_rxc_3, qsfp_3_rxc_2, qsfp_3_rxc_1, qsfp_3_rxc_0, qsfp_2_rxc_3, qsfp_2_rxc_2, qsfp_2_rxc_1, qsfp_2_rxc_0, qsfp_1_rxc_3, qsfp_1_rxc_2, qsfp_1_rxc_1, qsfp_1_rxc_0, qsfp_0_rxc_3, qsfp_0_rxc_2, qsfp_0_rxc_1, qsfp_0_rxc_0}), + .phy_rx_status({qsfp_3_rx_status_3, qsfp_3_rx_status_2, qsfp_3_rx_status_1, qsfp_3_rx_status_0, qsfp_2_rx_status_3, qsfp_2_rx_status_2, qsfp_2_rx_status_1, qsfp_2_rx_status_0, qsfp_1_rx_status_3, qsfp_1_rx_status_2, qsfp_1_rx_status_1, qsfp_1_rx_status_0, qsfp_0_rx_status_3, qsfp_0_rx_status_2, qsfp_0_rx_status_1, qsfp_0_rx_status_0}), + + // towards MAC + .port_xgmii_tx_clk(port_xgmii_tx_clk), + .port_xgmii_tx_rst(port_xgmii_tx_rst), + .port_xgmii_txd(port_xgmii_txd), + .port_xgmii_txc(port_xgmii_txc), + .port_tx_status(eth_tx_status), + + .port_xgmii_rx_clk(port_xgmii_rx_clk), + .port_xgmii_rx_rst(port_xgmii_rx_rst), + .port_xgmii_rxd(port_xgmii_rxd), + .port_xgmii_rxc(port_xgmii_rxc), + .port_rx_status(eth_rx_status) +); + +generate + genvar n; + + for (n = 0; n < PORT_COUNT; n = n + 1) begin : mac + + assign eth_tx_clk[n] = port_xgmii_tx_clk[n]; + assign eth_tx_rst[n] = port_xgmii_tx_rst[n]; + assign eth_rx_clk[n] = port_xgmii_rx_clk[n]; + assign eth_rx_rst[n] = port_xgmii_rx_rst[n]; + + eth_mac_10g #( + .DATA_WIDTH(AXIS_ETH_DATA_WIDTH), + .KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), + .PTP_PERIOD_NS(IF_PTP_PERIOD_NS), + .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS), + .TX_PTP_TS_ENABLE(PTP_TS_ENABLE), + .TX_PTP_TS_WIDTH(PTP_TS_WIDTH), + .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE), + .TX_PTP_TAG_WIDTH(TX_TAG_WIDTH), + .RX_PTP_TS_ENABLE(PTP_TS_ENABLE), + .RX_PTP_TS_WIDTH(PTP_TS_WIDTH), + .TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), + .RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH) + ) + eth_mac_inst ( + .tx_clk(port_xgmii_tx_clk[n]), + .tx_rst(port_xgmii_tx_rst[n]), + .rx_clk(port_xgmii_rx_clk[n]), + .rx_rst(port_xgmii_rx_rst[n]), + + .tx_axis_tdata(axis_eth_tx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), + .tx_axis_tkeep(axis_eth_tx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), + .tx_axis_tvalid(axis_eth_tx_tvalid[n +: 1]), + .tx_axis_tready(axis_eth_tx_tready[n +: 1]), + .tx_axis_tlast(axis_eth_tx_tlast[n +: 1]), + .tx_axis_tuser(axis_eth_tx_tuser[n*AXIS_ETH_TX_USER_WIDTH +: AXIS_ETH_TX_USER_WIDTH]), + + .rx_axis_tdata(axis_eth_rx_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]), + .rx_axis_tkeep(axis_eth_rx_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]), + .rx_axis_tvalid(axis_eth_rx_tvalid[n +: 1]), + .rx_axis_tlast(axis_eth_rx_tlast[n +: 1]), + .rx_axis_tuser(axis_eth_rx_tuser[n*AXIS_ETH_RX_USER_WIDTH +: AXIS_ETH_RX_USER_WIDTH]), + + .xgmii_rxd(port_xgmii_rxd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .xgmii_rxc(port_xgmii_rxc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), + .xgmii_txd(port_xgmii_txd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .xgmii_txc(port_xgmii_txc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), + + .tx_ptp_ts(eth_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .rx_ptp_ts(eth_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), + .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), + + .tx_error_underflow(), + .rx_error_bad_frame(), + .rx_error_bad_fcs(), + + .ifg_delay(8'd12) + ); + + end + +endgenerate + +mqnic_core_pcie_us #( + // FW and board IDs + .FPGA_ID(FPGA_ID), + .FW_ID(FW_ID), + .FW_VER(FW_VER), + .BOARD_ID(BOARD_ID), + .BOARD_VER(BOARD_VER), + .BUILD_DATE(BUILD_DATE), + .GIT_HASH(GIT_HASH), + .RELEASE_INFO(RELEASE_INFO), + + // Structural configuration + .IF_COUNT(IF_COUNT), + .PORTS_PER_IF(PORTS_PER_IF), + .SCHED_PER_IF(SCHED_PER_IF), + + .PORT_COUNT(PORT_COUNT), + + // Clock configuration + .CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM), + .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), + + // PTP configuration + .PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), + .PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), + .PTP_TS_WIDTH(PTP_TS_WIDTH), + .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE), + .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE), + .PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK), + .PTP_SEPARATE_TX_CLOCK(0), + .PTP_SEPARATE_RX_CLOCK(0), + .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE), + .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE), + .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT), + + // Queue manager configuration + .EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE), + .TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE), + .RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE), + .TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE), + .RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE), + .EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), + .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), + .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), + .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), + .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), + .EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE), + .TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE), + .RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE), + .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), + .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), + + // TX and RX engine configuration + .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), + .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH), + + // Scheduler configuration + .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), + .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), + .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), + + // Interface configuration + .PTP_TS_ENABLE(PTP_TS_ENABLE), + .TX_CPL_ENABLE(PTP_TS_ENABLE), + .TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH), + .TX_TAG_WIDTH(TX_TAG_WIDTH), + .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), + .RX_HASH_ENABLE(RX_HASH_ENABLE), + .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .TX_FIFO_DEPTH(TX_FIFO_DEPTH), + .RX_FIFO_DEPTH(RX_FIFO_DEPTH), + .MAX_TX_SIZE(MAX_TX_SIZE), + .MAX_RX_SIZE(MAX_RX_SIZE), + .TX_RAM_SIZE(TX_RAM_SIZE), + .RX_RAM_SIZE(RX_RAM_SIZE), + + // RAM configuration + .DDR_ENABLE(0), + .HBM_ENABLE(0), + + // Application block configuration + .APP_ID(APP_ID), + .APP_ENABLE(APP_ENABLE), + .APP_CTRL_ENABLE(APP_CTRL_ENABLE), + .APP_DMA_ENABLE(APP_DMA_ENABLE), + .APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE), + .APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE), + .APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE), + .APP_STAT_ENABLE(APP_STAT_ENABLE), + .APP_GPIO_IN_WIDTH(32), + .APP_GPIO_OUT_WIDTH(32), + + // DMA interface configuration + .DMA_IMM_ENABLE(DMA_IMM_ENABLE), + .DMA_IMM_WIDTH(DMA_IMM_WIDTH), + .DMA_LEN_WIDTH(DMA_LEN_WIDTH), + .DMA_TAG_WIDTH(DMA_TAG_WIDTH), + .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), + .RAM_PIPELINE(RAM_PIPELINE), + + // PCIe interface configuration + .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), + .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH), + .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH), + .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH), + .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH), + .RC_STRADDLE(RC_STRADDLE), + .RQ_STRADDLE(RQ_STRADDLE), + .CQ_STRADDLE(CQ_STRADDLE), + .CC_STRADDLE(CC_STRADDLE), + .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH), + .PF_COUNT(PF_COUNT), + .VF_COUNT(VF_COUNT), + .F_COUNT(F_COUNT), + .PCIE_TAG_COUNT(PCIE_TAG_COUNT), + + // Interrupt configuration + .IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH), + + // AXI lite interface configuration (control) + .AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), + .AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH), + .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), + .AXIL_CSR_PASSTHROUGH_ENABLE(TDMA_BER_ENABLE), + .RB_NEXT_PTR(RB_BASE_ADDR), + + // AXI lite interface configuration (application control) + .AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH), + .AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH), + + // Ethernet interface configuration + .AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), + .AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), + .AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), + .AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), + .AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), + .AXIS_ETH_RX_USE_READY(0), + .AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE), + .AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE), + .AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE), + .AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE), + .AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE), + + // Statistics counter subsystem + .STAT_ENABLE(STAT_ENABLE), + .STAT_DMA_ENABLE(STAT_DMA_ENABLE), + .STAT_PCIE_ENABLE(STAT_PCIE_ENABLE), + .STAT_INC_WIDTH(STAT_INC_WIDTH), + .STAT_ID_WIDTH(STAT_ID_WIDTH) +) +core_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * AXI input (RC) + */ + .s_axis_rc_tdata(s_axis_rc_tdata), + .s_axis_rc_tkeep(s_axis_rc_tkeep), + .s_axis_rc_tvalid(s_axis_rc_tvalid), + .s_axis_rc_tready(s_axis_rc_tready), + .s_axis_rc_tlast(s_axis_rc_tlast), + .s_axis_rc_tuser(s_axis_rc_tuser), + + /* + * AXI output (RQ) + */ + .m_axis_rq_tdata(m_axis_rq_tdata), + .m_axis_rq_tkeep(m_axis_rq_tkeep), + .m_axis_rq_tvalid(m_axis_rq_tvalid), + .m_axis_rq_tready(m_axis_rq_tready), + .m_axis_rq_tlast(m_axis_rq_tlast), + .m_axis_rq_tuser(m_axis_rq_tuser), + + /* + * AXI input (CQ) + */ + .s_axis_cq_tdata(s_axis_cq_tdata), + .s_axis_cq_tkeep(s_axis_cq_tkeep), + .s_axis_cq_tvalid(s_axis_cq_tvalid), + .s_axis_cq_tready(s_axis_cq_tready), + .s_axis_cq_tlast(s_axis_cq_tlast), + .s_axis_cq_tuser(s_axis_cq_tuser), + + /* + * AXI output (CC) + */ + .m_axis_cc_tdata(m_axis_cc_tdata), + .m_axis_cc_tkeep(m_axis_cc_tkeep), + .m_axis_cc_tvalid(m_axis_cc_tvalid), + .m_axis_cc_tready(m_axis_cc_tready), + .m_axis_cc_tlast(m_axis_cc_tlast), + .m_axis_cc_tuser(m_axis_cc_tuser), + + /* + * Transmit sequence number input + */ + .s_axis_rq_seq_num_0(s_axis_rq_seq_num_0), + .s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0), + .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), + .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + + /* + * Flow control + */ + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + + /* + * Configuration inputs + */ + .cfg_max_read_req(cfg_max_read_req), + .cfg_max_payload(cfg_max_payload), + + /* + * Configuration interface + */ + .cfg_mgmt_addr(cfg_mgmt_addr), + .cfg_mgmt_function_number(cfg_mgmt_function_number), + .cfg_mgmt_write(cfg_mgmt_write), + .cfg_mgmt_write_data(cfg_mgmt_write_data), + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), + .cfg_mgmt_read(cfg_mgmt_read), + .cfg_mgmt_read_data(cfg_mgmt_read_data), + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), + + /* + * Interrupt interface + */ + .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), + .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), + .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), + .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), + .cfg_interrupt_msix_address(cfg_interrupt_msix_address), + .cfg_interrupt_msix_data(cfg_interrupt_msix_data), + .cfg_interrupt_msix_int(cfg_interrupt_msix_int), + .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), + .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), + .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent), + .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail), + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + + /* + * PCIe error outputs + */ + .status_error_cor(status_error_cor), + .status_error_uncor(status_error_uncor), + + /* + * AXI-Lite master interface (passthrough for NIC control and status) + */ + .m_axil_csr_awaddr(axil_csr_awaddr), + .m_axil_csr_awprot(axil_csr_awprot), + .m_axil_csr_awvalid(axil_csr_awvalid), + .m_axil_csr_awready(axil_csr_awready), + .m_axil_csr_wdata(axil_csr_wdata), + .m_axil_csr_wstrb(axil_csr_wstrb), + .m_axil_csr_wvalid(axil_csr_wvalid), + .m_axil_csr_wready(axil_csr_wready), + .m_axil_csr_bresp(axil_csr_bresp), + .m_axil_csr_bvalid(axil_csr_bvalid), + .m_axil_csr_bready(axil_csr_bready), + .m_axil_csr_araddr(axil_csr_araddr), + .m_axil_csr_arprot(axil_csr_arprot), + .m_axil_csr_arvalid(axil_csr_arvalid), + .m_axil_csr_arready(axil_csr_arready), + .m_axil_csr_rdata(axil_csr_rdata), + .m_axil_csr_rresp(axil_csr_rresp), + .m_axil_csr_rvalid(axil_csr_rvalid), + .m_axil_csr_rready(axil_csr_rready), + + /* + * Control register interface + */ + .ctrl_reg_wr_addr(ctrl_reg_wr_addr), + .ctrl_reg_wr_data(ctrl_reg_wr_data), + .ctrl_reg_wr_strb(ctrl_reg_wr_strb), + .ctrl_reg_wr_en(ctrl_reg_wr_en), + .ctrl_reg_wr_wait(ctrl_reg_wr_wait), + .ctrl_reg_wr_ack(ctrl_reg_wr_ack), + .ctrl_reg_rd_addr(ctrl_reg_rd_addr), + .ctrl_reg_rd_en(ctrl_reg_rd_en), + .ctrl_reg_rd_data(ctrl_reg_rd_data), + .ctrl_reg_rd_wait(ctrl_reg_rd_wait), + .ctrl_reg_rd_ack(ctrl_reg_rd_ack), + + /* + * PTP clock + */ + .ptp_clk(ptp_clk), + .ptp_rst(ptp_rst), + .ptp_sample_clk(ptp_sample_clk), + .ptp_pps(ptp_pps), + .ptp_pps_str(ptp_pps_str), + .ptp_ts_96(ptp_ts_96), + .ptp_ts_step(ptp_ts_step), + .ptp_sync_pps(ptp_sync_pps), + .ptp_sync_ts_96(ptp_sync_ts_96), + .ptp_sync_ts_step(ptp_sync_ts_step), + .ptp_perout_locked(ptp_perout_locked), + .ptp_perout_error(ptp_perout_error), + .ptp_perout_pulse(ptp_perout_pulse), + + /* + * Ethernet + */ + .eth_tx_clk(eth_tx_clk), + .eth_tx_rst(eth_tx_rst), + + .eth_tx_ptp_clk(0), + .eth_tx_ptp_rst(0), + .eth_tx_ptp_ts_96(eth_tx_ptp_ts_96), + .eth_tx_ptp_ts_step(eth_tx_ptp_ts_step), + + .m_axis_eth_tx_tdata(axis_eth_tx_tdata), + .m_axis_eth_tx_tkeep(axis_eth_tx_tkeep), + .m_axis_eth_tx_tvalid(axis_eth_tx_tvalid), + .m_axis_eth_tx_tready(axis_eth_tx_tready), + .m_axis_eth_tx_tlast(axis_eth_tx_tlast), + .m_axis_eth_tx_tuser(axis_eth_tx_tuser), + + .s_axis_eth_tx_cpl_ts(axis_eth_tx_ptp_ts), + .s_axis_eth_tx_cpl_tag(axis_eth_tx_ptp_ts_tag), + .s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid), + .s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready), + + .eth_tx_status(eth_tx_status), + + .eth_rx_clk(eth_rx_clk), + .eth_rx_rst(eth_rx_rst), + + .eth_rx_ptp_clk(0), + .eth_rx_ptp_rst(0), + .eth_rx_ptp_ts_96(eth_rx_ptp_ts_96), + .eth_rx_ptp_ts_step(eth_rx_ptp_ts_step), + + .s_axis_eth_rx_tdata(axis_eth_rx_tdata), + .s_axis_eth_rx_tkeep(axis_eth_rx_tkeep), + .s_axis_eth_rx_tvalid(axis_eth_rx_tvalid), + .s_axis_eth_rx_tready(axis_eth_rx_tready), + .s_axis_eth_rx_tlast(axis_eth_rx_tlast), + .s_axis_eth_rx_tuser(axis_eth_rx_tuser), + + .eth_rx_status(eth_rx_status), + + /* + * DDR + */ + .ddr_clk(0), + .ddr_rst(0), + + .m_axi_ddr_awid(), + .m_axi_ddr_awaddr(), + .m_axi_ddr_awlen(), + .m_axi_ddr_awsize(), + .m_axi_ddr_awburst(), + .m_axi_ddr_awlock(), + .m_axi_ddr_awcache(), + .m_axi_ddr_awprot(), + .m_axi_ddr_awqos(), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(), + .m_axi_ddr_awready(0), + .m_axi_ddr_wdata(), + .m_axi_ddr_wstrb(), + .m_axi_ddr_wlast(), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(), + .m_axi_ddr_wready(0), + .m_axi_ddr_bid(0), + .m_axi_ddr_bresp(0), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(0), + .m_axi_ddr_bready(), + .m_axi_ddr_arid(), + .m_axi_ddr_araddr(), + .m_axi_ddr_arlen(), + .m_axi_ddr_arsize(), + .m_axi_ddr_arburst(), + .m_axi_ddr_arlock(), + .m_axi_ddr_arcache(), + .m_axi_ddr_arprot(), + .m_axi_ddr_arqos(), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(), + .m_axi_ddr_arready(0), + .m_axi_ddr_rid(0), + .m_axi_ddr_rdata(0), + .m_axi_ddr_rresp(0), + .m_axi_ddr_rlast(0), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(0), + .m_axi_ddr_rready(), + + .ddr_status(0), + + /* + * HBM + */ + .hbm_clk(0), + .hbm_rst(0), + + .m_axi_hbm_awid(), + .m_axi_hbm_awaddr(), + .m_axi_hbm_awlen(), + .m_axi_hbm_awsize(), + .m_axi_hbm_awburst(), + .m_axi_hbm_awlock(), + .m_axi_hbm_awcache(), + .m_axi_hbm_awprot(), + .m_axi_hbm_awqos(), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(), + .m_axi_hbm_awready(0), + .m_axi_hbm_wdata(), + .m_axi_hbm_wstrb(), + .m_axi_hbm_wlast(), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(), + .m_axi_hbm_wready(0), + .m_axi_hbm_bid(0), + .m_axi_hbm_bresp(0), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(0), + .m_axi_hbm_bready(), + .m_axi_hbm_arid(), + .m_axi_hbm_araddr(), + .m_axi_hbm_arlen(), + .m_axi_hbm_arsize(), + .m_axi_hbm_arburst(), + .m_axi_hbm_arlock(), + .m_axi_hbm_arcache(), + .m_axi_hbm_arprot(), + .m_axi_hbm_arqos(), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(), + .m_axi_hbm_arready(0), + .m_axi_hbm_rid(0), + .m_axi_hbm_rdata(0), + .m_axi_hbm_rresp(0), + .m_axi_hbm_rlast(0), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(0), + .m_axi_hbm_rready(), + + .hbm_status(0), + + /* + * Statistics input + */ + .s_axis_stat_tdata(0), + .s_axis_stat_tid(0), + .s_axis_stat_tvalid(1'b0), + .s_axis_stat_tready(), + + /* + * GPIO + */ + .app_gpio_in(0), + .app_gpio_out(), + + /* + * JTAG + */ + .app_jtag_tdi(1'b0), + .app_jtag_tdo(), + .app_jtag_tms(1'b0), + .app_jtag_tck(1'b0) +); + +endmodule + +`resetall diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/rtl/sync_signal.v b/fpga/mqnic/fb4CGg3/fpga_25g/rtl/sync_signal.v new file mode 100644 index 000000000..74b855fa1 --- /dev/null +++ b/fpga/mqnic/fb4CGg3/fpga_25g/rtl/sync_signal.v @@ -0,0 +1,62 @@ +/* + +Copyright (c) 2014-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog-2001 + +`resetall +`timescale 1 ns / 1 ps +`default_nettype none + +/* + * Synchronizes an asyncronous signal to a given clock by using a pipeline of + * two registers. + */ +module sync_signal #( + parameter WIDTH=1, // width of the input and output signals + parameter N=2 // depth of synchronizer +)( + input wire clk, + input wire [WIDTH-1:0] in, + output wire [WIDTH-1:0] out +); + +reg [WIDTH-1:0] sync_reg[N-1:0]; + +/* + * The synchronized output is the last register in the pipeline. + */ +assign out = sync_reg[N-1]; + +integer k; + +always @(posedge clk) begin + sync_reg[0] <= in; + for (k = 1; k < N; k = k + 1) begin + sync_reg[k] <= sync_reg[k-1]; + end +end + +endmodule + +`resetall diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/Makefile new file mode 100644 index 000000000..d408d33e8 --- /dev/null +++ b/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/Makefile @@ -0,0 +1,286 @@ +# Copyright 2020-2021, The Regents of the University of California. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +# OF SUCH DAMAGE. +# +# The views and conclusions contained in the software and documentation are those +# of the authors and should not be interpreted as representing official policies, +# either expressed or implied, of The Regents of the University of California. + +TOPLEVEL_LANG = verilog + +SIM ?= icarus +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +DUT = fpga_core +TOPLEVEL = $(DUT) +MODULE = test_$(DUT) +VERILOG_SOURCES += ../../rtl/$(DUT).v +VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v +VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v +VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_port.v +VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v +VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v +VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_phy_xgmii.v +VERILOG_SOURCES += ../../rtl/common/cpl_write.v +VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v +VERILOG_SOURCES += ../../rtl/common/desc_fetch.v +VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v +VERILOG_SOURCES += ../../rtl/common/event_mux.v +VERILOG_SOURCES += ../../rtl/common/queue_manager.v +VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/common/tx_fifo.v +VERILOG_SOURCES += ../../rtl/common/rx_fifo.v +VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v +VERILOG_SOURCES += ../../rtl/common/tx_engine.v +VERILOG_SOURCES += ../../rtl/common/rx_engine.v +VERILOG_SOURCES += ../../rtl/common/tx_checksum.v +VERILOG_SOURCES += ../../rtl/common/rx_hash.v +VERILOG_SOURCES += ../../rtl/common/rx_checksum.v +VERILOG_SOURCES += ../../rtl/common/rb_drp.v +VERILOG_SOURCES += ../../rtl/common/stats_counter.v +VERILOG_SOURCES += ../../rtl/common/stats_collect.v +VERILOG_SOURCES += ../../rtl/common/stats_pcie_if.v +VERILOG_SOURCES += ../../rtl/common/stats_pcie_tlp.v +VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v +VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v +VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v +VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v +VERILOG_SOURCES += ../../rtl/common/tdma_scheduler.v +VERILOG_SOURCES += ../../rtl/common/tdma_ber.v +VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v +VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v +VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v +VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v +VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_rd.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_wr.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_rd.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_wr.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_rd.v +VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_wr.v +VERILOG_SOURCES += ../../lib/axi/rtl/arbiter.v +VERILOG_SOURCES += ../../lib/axi/rtl/priority_encoder.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v +VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_desc_mux.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_rd.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_wr.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_sink.v +VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_source.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v +VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v + +# module parameters + +# Structural configuration +export PARAM_IF_COUNT := 4 +export PARAM_PORTS_PER_IF := 1 +export PARAM_SCHED_PER_IF := $(PARAM_PORTS_PER_IF) +export PARAM_PORT_MASK := 0 + +# Clock configuration +export PARAM_CLK_PERIOD_NS_NUM := 4 +export PARAM_CLK_PERIOD_NS_DENOM := 1 + +# PTP configuration +export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024 +export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165 +export PARAM_PTP_CLOCK_PIPELINE := 0 +export PARAM_PTP_CLOCK_CDC_PIPELINE := 0 +export PARAM_PTP_USE_SAMPLE_CLOCK := 1 +export PARAM_PTP_PORT_CDC_PIPELINE := 0 +export PARAM_PTP_PEROUT_ENABLE := 1 +export PARAM_PTP_PEROUT_COUNT := 1 + +# Queue manager configuration +export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32 +export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32 +export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32 +export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE) +export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE) +export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6 +export PARAM_TX_QUEUE_INDEX_WIDTH := 13 +export PARAM_RX_QUEUE_INDEX_WIDTH := 8 +export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH) +export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH) +export PARAM_EVENT_QUEUE_PIPELINE := 3 +export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))") +export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))") +export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) +export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE) + +# TX and RX engine configuration +export PARAM_TX_DESC_TABLE_SIZE := 32 +export PARAM_RX_DESC_TABLE_SIZE := 32 +export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))") + +# Scheduler configuration +export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE) +export PARAM_TX_SCHEDULER_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE) +export PARAM_TDMA_INDEX_WIDTH := 6 + +# Interface configuration +export PARAM_PTP_TS_ENABLE := 1 +export PARAM_TX_CPL_FIFO_DEPTH := 32 +export PARAM_TX_CHECKSUM_ENABLE := 1 +export PARAM_RX_HASH_ENABLE := 1 +export PARAM_RX_CHECKSUM_ENABLE := 1 +export PARAM_TX_FIFO_DEPTH := 32768 +export PARAM_RX_FIFO_DEPTH := 32768 +export PARAM_MAX_TX_SIZE := 9214 +export PARAM_MAX_RX_SIZE := 9214 +export PARAM_TX_RAM_SIZE := 32768 +export PARAM_RX_RAM_SIZE := 131072 + +# Application block configuration +export PARAM_APP_ID := $(shell echo $$((0x00000000)) ) +export PARAM_APP_ENABLE := 0 +export PARAM_APP_CTRL_ENABLE := 1 +export PARAM_APP_DMA_ENABLE := 1 +export PARAM_APP_AXIS_DIRECT_ENABLE := 1 +export PARAM_APP_AXIS_SYNC_ENABLE := 1 +export PARAM_APP_AXIS_IF_ENABLE := 1 +export PARAM_APP_STAT_ENABLE := 1 + +# DMA interface configuration +export PARAM_DMA_IMM_ENABLE := 0 +export PARAM_DMA_IMM_WIDTH := 32 +export PARAM_DMA_LEN_WIDTH := 16 +export PARAM_DMA_TAG_WIDTH := 16 +export PARAM_RAM_ADDR_WIDTH := $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())") +export PARAM_RAM_PIPELINE := 2 + +# PCIe interface configuration +export PARAM_AXIS_PCIE_DATA_WIDTH := 512 +export PARAM_PF_COUNT := 1 +export PARAM_VF_COUNT := 0 + +# Interrupt configuration +export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH) + +# AXI lite interface configuration (control) +export PARAM_AXIL_CTRL_DATA_WIDTH := 32 +export PARAM_AXIL_CTRL_ADDR_WIDTH := 25 + +# AXI lite interface configuration (application control) +export PARAM_AXIL_APP_CTRL_DATA_WIDTH := $(PARAM_AXIL_CTRL_DATA_WIDTH) +export PARAM_AXIL_APP_CTRL_ADDR_WIDTH := 24 + +# Ethernet interface configuration +export PARAM_AXIS_ETH_TX_PIPELINE := 4 +export PARAM_AXIS_ETH_TX_FIFO_PIPELINE := 4 +export PARAM_AXIS_ETH_TX_TS_PIPELINE := 4 +export PARAM_AXIS_ETH_RX_PIPELINE := 4 +export PARAM_AXIS_ETH_RX_FIFO_PIPELINE := 4 + +# Statistics counter subsystem +export PARAM_STAT_ENABLE := 1 +export PARAM_STAT_DMA_ENABLE := 1 +export PARAM_STAT_PCIE_ENABLE := 1 +export PARAM_STAT_INC_WIDTH := 24 +export PARAM_STAT_ID_WIDTH := 12 + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + VERILOG_SOURCES += iverilog_dump.v + COMPILE_ARGS += -s iverilog_dump + endif +else ifeq ($(SIM), verilator) + COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim + +iverilog_dump.v: + echo 'module iverilog_dump();' > $@ + echo 'initial begin' >> $@ + echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ + echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ + echo 'end' >> $@ + echo 'endmodule' >> $@ + +clean:: + @rm -rf iverilog_dump.v + @rm -rf dump.fst $(TOPLEVEL).fst diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/mqnic.py b/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/mqnic.py new file mode 120000 index 000000000..dfa8522e7 --- /dev/null +++ b/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/mqnic.py @@ -0,0 +1 @@ +../../../../../common/tb/mqnic.py \ No newline at end of file diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/test_fpga_core.py new file mode 100644 index 000000000..b257812b0 --- /dev/null +++ b/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -0,0 +1,1050 @@ +""" + +Copyright 2020-2021, The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +The views and conclusions contained in the software and documentation are those +of the authors and should not be interpreted as representing official policies, +either expressed or implied, of The Regents of the University of California. + +""" + +import logging +import os +import sys + +import scapy.utils +from scapy.layers.l2 import Ether +from scapy.layers.inet import IP, UDP + +import cocotb_test.simulator + +import cocotb +from cocotb.log import SimLog +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, FallingEdge, Timer + +from cocotbext.axi import AxiStreamBus +from cocotbext.eth import XgmiiSource, XgmiiSink +from cocotbext.pcie.core import RootComplex +from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice + +try: + import mqnic +except ImportError: + # attempt import from current directory + sys.path.insert(0, os.path.join(os.path.dirname(__file__))) + try: + import mqnic + finally: + del sys.path[0] + + +class TB(object): + def __init__(self, dut, msix_count=32): + self.dut = dut + + self.log = SimLog("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + # PCIe + self.rc = RootComplex() + + self.rc.max_payload_size = 0x1 # 256 bytes + self.rc.max_read_request_size = 0x2 # 512 bytes + + self.dev = UltraScalePlusPcieDevice( + # configuration options + pcie_generation=3, + pcie_link_width=16, + user_clk_frequency=250e6, + alignment="dword", + cq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cq_inst.rx_req_tlp_valid_reg) > 1, + cc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_cc_inst.out_tlp_valid) > 1, + rq_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rq_inst.out_tlp_valid) > 1, + rc_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 1, + rc_4tlp_straddle=len(dut.core_inst.pcie_if_inst.pcie_us_if_rc_inst.rx_cpl_tlp_valid_reg) > 2, + pf_count=1, + max_payload_size=1024, + enable_client_tag=True, + enable_extended_tag=True, + enable_parity=False, + enable_rx_msg_interface=False, + enable_sriov=False, + enable_extended_configuration=False, + + pf0_msi_enable=False, + pf0_msi_count=32, + pf1_msi_enable=False, + pf1_msi_count=1, + pf2_msi_enable=False, + pf2_msi_count=1, + pf3_msi_enable=False, + pf3_msi_count=1, + pf0_msix_enable=True, + pf0_msix_table_size=msix_count-1, + pf0_msix_table_bir=0, + pf0_msix_table_offset=0x00010000, + pf0_msix_pba_bir=0, + pf0_msix_pba_offset=0x00018000, + pf1_msix_enable=False, + pf1_msix_table_size=0, + pf1_msix_table_bir=0, + pf1_msix_table_offset=0x00000000, + pf1_msix_pba_bir=0, + pf1_msix_pba_offset=0x00000000, + pf2_msix_enable=False, + pf2_msix_table_size=0, + pf2_msix_table_bir=0, + pf2_msix_table_offset=0x00000000, + pf2_msix_pba_bir=0, + pf2_msix_pba_offset=0x00000000, + pf3_msix_enable=False, + pf3_msix_table_size=0, + pf3_msix_table_bir=0, + pf3_msix_table_offset=0x00000000, + pf3_msix_pba_bir=0, + pf3_msix_pba_offset=0x00000000, + + # signals + # Clock and Reset Interface + user_clk=dut.clk_250mhz, + user_reset=dut.rst_250mhz, + # user_lnk_up + # sys_clk + # sys_clk_gt + # sys_reset + # phy_rdy_out + + # Requester reQuest Interface + rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), + pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0, + pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0, + pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1, + pcie_rq_seq_num_vld1=dut.s_axis_rq_seq_num_valid_1, + # pcie_rq_tag0 + # pcie_rq_tag1 + # pcie_rq_tag_av + # pcie_rq_tag_vld0 + # pcie_rq_tag_vld1 + + # Requester Completion Interface + rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"), + + # Completer reQuest Interface + cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"), + # pcie_cq_np_req + # pcie_cq_np_req_count + + # Completer Completion Interface + cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"), + + # Transmit Flow Control Interface + # pcie_tfc_nph_av=dut.pcie_tfc_nph_av, + # pcie_tfc_npd_av=dut.pcie_tfc_npd_av, + + # Configuration Management Interface + cfg_mgmt_addr=dut.cfg_mgmt_addr, + cfg_mgmt_function_number=dut.cfg_mgmt_function_number, + cfg_mgmt_write=dut.cfg_mgmt_write, + cfg_mgmt_write_data=dut.cfg_mgmt_write_data, + cfg_mgmt_byte_enable=dut.cfg_mgmt_byte_enable, + cfg_mgmt_read=dut.cfg_mgmt_read, + cfg_mgmt_read_data=dut.cfg_mgmt_read_data, + cfg_mgmt_read_write_done=dut.cfg_mgmt_read_write_done, + # cfg_mgmt_debug_access + + # Configuration Status Interface + # cfg_phy_link_down + # cfg_phy_link_status + # cfg_negotiated_width + # cfg_current_speed + cfg_max_payload=dut.cfg_max_payload, + cfg_max_read_req=dut.cfg_max_read_req, + # cfg_function_status + # cfg_vf_status + # cfg_function_power_state + # cfg_vf_power_state + # cfg_link_power_state + # cfg_err_cor_out + # cfg_err_nonfatal_out + # cfg_err_fatal_out + # cfg_local_error_out + # cfg_local_error_valid + # cfg_rx_pm_state + # cfg_tx_pm_state + # cfg_ltssm_state + # cfg_rcb_status + # cfg_obff_enable + # cfg_pl_status_change + # cfg_tph_requester_enable + # cfg_tph_st_mode + # cfg_vf_tph_requester_enable + # cfg_vf_tph_st_mode + + # Configuration Received Message Interface + # cfg_msg_received + # cfg_msg_received_data + # cfg_msg_received_type + + # Configuration Transmit Message Interface + # cfg_msg_transmit + # cfg_msg_transmit_type + # cfg_msg_transmit_data + # cfg_msg_transmit_done + + # Configuration Flow Control Interface + cfg_fc_ph=dut.cfg_fc_ph, + cfg_fc_pd=dut.cfg_fc_pd, + cfg_fc_nph=dut.cfg_fc_nph, + cfg_fc_npd=dut.cfg_fc_npd, + cfg_fc_cplh=dut.cfg_fc_cplh, + cfg_fc_cpld=dut.cfg_fc_cpld, + cfg_fc_sel=dut.cfg_fc_sel, + + # Configuration Control Interface + # cfg_hot_reset_in + # cfg_hot_reset_out + # cfg_config_space_enable + # cfg_dsn + # cfg_bus_number + # cfg_ds_port_number + # cfg_ds_bus_number + # cfg_ds_device_number + # cfg_ds_function_number + # cfg_power_state_change_ack + # cfg_power_state_change_interrupt + cfg_err_cor_in=dut.status_error_cor, + cfg_err_uncor_in=dut.status_error_uncor, + # cfg_flr_in_process + # cfg_flr_done + # cfg_vf_flr_in_process + # cfg_vf_flr_func_num + # cfg_vf_flr_done + # cfg_pm_aspm_l1_entry_reject + # cfg_pm_aspm_tx_l0s_entry_disable + # cfg_req_pm_transition_l23_ready + # cfg_link_training_enable + + # Configuration Interrupt Controller Interface + # cfg_interrupt_int + # cfg_interrupt_sent + # cfg_interrupt_pending + # cfg_interrupt_msi_enable + # cfg_interrupt_msi_mmenable + # cfg_interrupt_msi_mask_update + # cfg_interrupt_msi_data + # cfg_interrupt_msi_select + # cfg_interrupt_msi_int + # cfg_interrupt_msi_pending_status + # cfg_interrupt_msi_pending_status_data_enable + # cfg_interrupt_msi_pending_status_function_num + # cfg_interrupt_msi_sent + # cfg_interrupt_msi_fail + cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable, + cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask, + cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable, + cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask, + cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address, + cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data, + cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int, + cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending, + cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status, + cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent, + cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail, + # cfg_interrupt_msi_attr + # cfg_interrupt_msi_tph_present + # cfg_interrupt_msi_tph_type + # cfg_interrupt_msi_tph_st_tag + cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number, + + # Configuration Extend Interface + # cfg_ext_read_received + # cfg_ext_write_received + # cfg_ext_register_number + # cfg_ext_function_number + # cfg_ext_write_data + # cfg_ext_write_byte_enable + # cfg_ext_read_data + # cfg_ext_read_data_valid + ) + + # self.dev.log.setLevel(logging.DEBUG) + + self.rc.make_port().connect(self.dev) + + self.driver = mqnic.Driver() + + self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True) + if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'): + self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True) + + cocotb.start_soon(Clock(dut.ptp_clk, 6.206, units="ns").start()) + dut.ptp_rst.setimmediatevalue(0) + cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start()) + + # Ethernet + cocotb.start_soon(Clock(dut.qsfp_0_rx_clk_0, 2.56, units="ns").start()) + self.qsfp_0_0_source = XgmiiSource(dut.qsfp_0_rxd_0, dut.qsfp_0_rxc_0, dut.qsfp_0_rx_clk_0, dut.qsfp_0_rx_rst_0) + cocotb.start_soon(Clock(dut.qsfp_0_tx_clk_0, 2.56, units="ns").start()) + self.qsfp_0_0_sink = XgmiiSink(dut.qsfp_0_txd_0, dut.qsfp_0_txc_0, dut.qsfp_0_tx_clk_0, dut.qsfp_0_tx_rst_0) + + cocotb.start_soon(Clock(dut.qsfp_0_rx_clk_1, 2.56, units="ns").start()) + self.qsfp_0_1_source = XgmiiSource(dut.qsfp_0_rxd_1, dut.qsfp_0_rxc_1, dut.qsfp_0_rx_clk_1, dut.qsfp_0_rx_rst_1) + cocotb.start_soon(Clock(dut.qsfp_0_tx_clk_1, 2.56, units="ns").start()) + self.qsfp_0_1_sink = XgmiiSink(dut.qsfp_0_txd_1, dut.qsfp_0_txc_1, dut.qsfp_0_tx_clk_1, dut.qsfp_0_tx_rst_1) + + cocotb.start_soon(Clock(dut.qsfp_0_rx_clk_2, 2.56, units="ns").start()) + self.qsfp_0_2_source = XgmiiSource(dut.qsfp_0_rxd_2, dut.qsfp_0_rxc_2, dut.qsfp_0_rx_clk_2, dut.qsfp_0_rx_rst_2) + cocotb.start_soon(Clock(dut.qsfp_0_tx_clk_2, 2.56, units="ns").start()) + self.qsfp_0_2_sink = XgmiiSink(dut.qsfp_0_txd_2, dut.qsfp_0_txc_2, dut.qsfp_0_tx_clk_2, dut.qsfp_0_tx_rst_2) + + cocotb.start_soon(Clock(dut.qsfp_0_rx_clk_3, 2.56, units="ns").start()) + self.qsfp_0_3_source = XgmiiSource(dut.qsfp_0_rxd_3, dut.qsfp_0_rxc_3, dut.qsfp_0_rx_clk_3, dut.qsfp_0_rx_rst_3) + cocotb.start_soon(Clock(dut.qsfp_0_tx_clk_3, 2.56, units="ns").start()) + self.qsfp_0_3_sink = XgmiiSink(dut.qsfp_0_txd_3, dut.qsfp_0_txc_3, dut.qsfp_0_tx_clk_3, dut.qsfp_0_tx_rst_3) + + cocotb.start_soon(Clock(dut.qsfp_1_rx_clk_0, 2.56, units="ns").start()) + self.qsfp_1_0_source = XgmiiSource(dut.qsfp_1_rxd_0, dut.qsfp_1_rxc_0, dut.qsfp_1_rx_clk_0, dut.qsfp_1_rx_rst_0) + cocotb.start_soon(Clock(dut.qsfp_1_tx_clk_0, 2.56, units="ns").start()) + self.qsfp_1_0_sink = XgmiiSink(dut.qsfp_1_txd_0, dut.qsfp_1_txc_0, dut.qsfp_1_tx_clk_0, dut.qsfp_1_tx_rst_0) + + cocotb.start_soon(Clock(dut.qsfp_1_rx_clk_1, 2.56, units="ns").start()) + self.qsfp_1_1_source = XgmiiSource(dut.qsfp_1_rxd_1, dut.qsfp_1_rxc_1, dut.qsfp_1_rx_clk_1, dut.qsfp_1_rx_rst_1) + cocotb.start_soon(Clock(dut.qsfp_1_tx_clk_1, 2.56, units="ns").start()) + self.qsfp_1_1_sink = XgmiiSink(dut.qsfp_1_txd_1, dut.qsfp_1_txc_1, dut.qsfp_1_tx_clk_1, dut.qsfp_1_tx_rst_1) + + cocotb.start_soon(Clock(dut.qsfp_1_rx_clk_2, 2.56, units="ns").start()) + self.qsfp_1_2_source = XgmiiSource(dut.qsfp_1_rxd_2, dut.qsfp_1_rxc_2, dut.qsfp_1_rx_clk_2, dut.qsfp_1_rx_rst_2) + cocotb.start_soon(Clock(dut.qsfp_1_tx_clk_2, 2.56, units="ns").start()) + self.qsfp_1_2_sink = XgmiiSink(dut.qsfp_1_txd_2, dut.qsfp_1_txc_2, dut.qsfp_1_tx_clk_2, dut.qsfp_1_tx_rst_2) + + cocotb.start_soon(Clock(dut.qsfp_1_rx_clk_3, 2.56, units="ns").start()) + self.qsfp_1_3_source = XgmiiSource(dut.qsfp_1_rxd_3, dut.qsfp_1_rxc_3, dut.qsfp_1_rx_clk_3, dut.qsfp_1_rx_rst_3) + cocotb.start_soon(Clock(dut.qsfp_1_tx_clk_3, 2.56, units="ns").start()) + self.qsfp_1_3_sink = XgmiiSink(dut.qsfp_1_txd_3, dut.qsfp_1_txc_3, dut.qsfp_1_tx_clk_3, dut.qsfp_1_tx_rst_3) + + cocotb.start_soon(Clock(dut.qsfp_2_rx_clk_0, 2.56, units="ns").start()) + self.qsfp_2_0_source = XgmiiSource(dut.qsfp_2_rxd_0, dut.qsfp_2_rxc_0, dut.qsfp_2_rx_clk_0, dut.qsfp_2_rx_rst_0) + cocotb.start_soon(Clock(dut.qsfp_2_tx_clk_0, 2.56, units="ns").start()) + self.qsfp_2_0_sink = XgmiiSink(dut.qsfp_2_txd_0, dut.qsfp_2_txc_0, dut.qsfp_2_tx_clk_0, dut.qsfp_2_tx_rst_0) + + cocotb.start_soon(Clock(dut.qsfp_2_rx_clk_1, 2.56, units="ns").start()) + self.qsfp_2_1_source = XgmiiSource(dut.qsfp_2_rxd_1, dut.qsfp_2_rxc_1, dut.qsfp_2_rx_clk_1, dut.qsfp_2_rx_rst_1) + cocotb.start_soon(Clock(dut.qsfp_2_tx_clk_1, 2.56, units="ns").start()) + self.qsfp_2_1_sink = XgmiiSink(dut.qsfp_2_txd_1, dut.qsfp_2_txc_1, dut.qsfp_2_tx_clk_1, dut.qsfp_2_tx_rst_1) + + cocotb.start_soon(Clock(dut.qsfp_2_rx_clk_2, 2.56, units="ns").start()) + self.qsfp_2_2_source = XgmiiSource(dut.qsfp_2_rxd_2, dut.qsfp_2_rxc_2, dut.qsfp_2_rx_clk_2, dut.qsfp_2_rx_rst_2) + cocotb.start_soon(Clock(dut.qsfp_2_tx_clk_2, 2.56, units="ns").start()) + self.qsfp_2_2_sink = XgmiiSink(dut.qsfp_2_txd_2, dut.qsfp_2_txc_2, dut.qsfp_2_tx_clk_2, dut.qsfp_2_tx_rst_2) + + cocotb.start_soon(Clock(dut.qsfp_2_rx_clk_3, 2.56, units="ns").start()) + self.qsfp_2_3_source = XgmiiSource(dut.qsfp_2_rxd_3, dut.qsfp_2_rxc_3, dut.qsfp_2_rx_clk_3, dut.qsfp_2_rx_rst_3) + cocotb.start_soon(Clock(dut.qsfp_2_tx_clk_3, 2.56, units="ns").start()) + self.qsfp_2_3_sink = XgmiiSink(dut.qsfp_2_txd_3, dut.qsfp_2_txc_3, dut.qsfp_2_tx_clk_3, dut.qsfp_2_tx_rst_3) + + cocotb.start_soon(Clock(dut.qsfp_3_rx_clk_0, 2.56, units="ns").start()) + self.qsfp_3_0_source = XgmiiSource(dut.qsfp_3_rxd_0, dut.qsfp_3_rxc_0, dut.qsfp_3_rx_clk_0, dut.qsfp_3_rx_rst_0) + cocotb.start_soon(Clock(dut.qsfp_3_tx_clk_0, 2.56, units="ns").start()) + self.qsfp_3_0_sink = XgmiiSink(dut.qsfp_3_txd_0, dut.qsfp_3_txc_0, dut.qsfp_3_tx_clk_0, dut.qsfp_3_tx_rst_0) + + cocotb.start_soon(Clock(dut.qsfp_3_rx_clk_1, 2.56, units="ns").start()) + self.qsfp_3_1_source = XgmiiSource(dut.qsfp_3_rxd_1, dut.qsfp_3_rxc_1, dut.qsfp_3_rx_clk_1, dut.qsfp_3_rx_rst_1) + cocotb.start_soon(Clock(dut.qsfp_3_tx_clk_1, 2.56, units="ns").start()) + self.qsfp_3_1_sink = XgmiiSink(dut.qsfp_3_txd_1, dut.qsfp_3_txc_1, dut.qsfp_3_tx_clk_1, dut.qsfp_3_tx_rst_1) + + cocotb.start_soon(Clock(dut.qsfp_3_rx_clk_2, 2.56, units="ns").start()) + self.qsfp_3_2_source = XgmiiSource(dut.qsfp_3_rxd_2, dut.qsfp_3_rxc_2, dut.qsfp_3_rx_clk_2, dut.qsfp_3_rx_rst_2) + cocotb.start_soon(Clock(dut.qsfp_3_tx_clk_2, 2.56, units="ns").start()) + self.qsfp_3_2_sink = XgmiiSink(dut.qsfp_3_txd_2, dut.qsfp_3_txc_2, dut.qsfp_3_tx_clk_2, dut.qsfp_3_tx_rst_2) + + cocotb.start_soon(Clock(dut.qsfp_3_rx_clk_3, 2.56, units="ns").start()) + self.qsfp_3_3_source = XgmiiSource(dut.qsfp_3_rxd_3, dut.qsfp_3_rxc_3, dut.qsfp_3_rx_clk_3, dut.qsfp_3_rx_rst_3) + cocotb.start_soon(Clock(dut.qsfp_3_tx_clk_3, 2.56, units="ns").start()) + self.qsfp_3_3_sink = XgmiiSink(dut.qsfp_3_txd_3, dut.qsfp_3_txc_3, dut.qsfp_3_tx_clk_3, dut.qsfp_3_tx_rst_3) + + dut.qsfp_0_rx_status_0.setimmediatevalue(1) + dut.qsfp_0_rx_status_1.setimmediatevalue(1) + dut.qsfp_0_rx_status_2.setimmediatevalue(1) + dut.qsfp_0_rx_status_3.setimmediatevalue(1) + + dut.qsfp_1_rx_status_0.setimmediatevalue(1) + dut.qsfp_1_rx_status_1.setimmediatevalue(1) + dut.qsfp_1_rx_status_2.setimmediatevalue(1) + dut.qsfp_1_rx_status_3.setimmediatevalue(1) + + dut.qsfp_2_rx_status_0.setimmediatevalue(1) + dut.qsfp_2_rx_status_1.setimmediatevalue(1) + dut.qsfp_2_rx_status_2.setimmediatevalue(1) + dut.qsfp_2_rx_status_3.setimmediatevalue(1) + + dut.qsfp_3_rx_status_0.setimmediatevalue(1) + dut.qsfp_3_rx_status_1.setimmediatevalue(1) + dut.qsfp_3_rx_status_2.setimmediatevalue(1) + dut.qsfp_3_rx_status_3.setimmediatevalue(1) + + cocotb.start_soon(Clock(dut.qsfp_0_drp_clk, 8, units="ns").start()) + dut.qsfp_0_drp_rst.setimmediatevalue(0) + dut.qsfp_0_drp_do.setimmediatevalue(0) + dut.qsfp_0_drp_rdy.setimmediatevalue(0) + + dut.qsfp_0_i2c_scl_i.setimmediatevalue(1) + dut.qsfp_0_i2c_sda_i.setimmediatevalue(1) + dut.qsfp_0_intr_n.setimmediatevalue(1) + dut.qsfp_0_mod_prsnt_n.setimmediatevalue(0) + + dut.qsfp_0_rx_error_count_0.setimmediatevalue(0) + dut.qsfp_0_rx_error_count_1.setimmediatevalue(0) + dut.qsfp_0_rx_error_count_2.setimmediatevalue(0) + dut.qsfp_0_rx_error_count_3.setimmediatevalue(0) + + cocotb.start_soon(Clock(dut.qsfp_1_drp_clk, 8, units="ns").start()) + dut.qsfp_1_drp_rst.setimmediatevalue(0) + dut.qsfp_1_drp_do.setimmediatevalue(0) + dut.qsfp_1_drp_rdy.setimmediatevalue(0) + + dut.qsfp_1_i2c_scl_i.setimmediatevalue(1) + dut.qsfp_1_i2c_sda_i.setimmediatevalue(1) + dut.qsfp_1_intr_n.setimmediatevalue(1) + dut.qsfp_1_mod_prsnt_n.setimmediatevalue(0) + + dut.qsfp_1_rx_error_count_0.setimmediatevalue(0) + dut.qsfp_1_rx_error_count_1.setimmediatevalue(0) + dut.qsfp_1_rx_error_count_2.setimmediatevalue(0) + dut.qsfp_1_rx_error_count_3.setimmediatevalue(0) + + cocotb.start_soon(Clock(dut.qsfp_2_drp_clk, 8, units="ns").start()) + dut.qsfp_2_drp_rst.setimmediatevalue(0) + dut.qsfp_2_drp_do.setimmediatevalue(0) + dut.qsfp_2_drp_rdy.setimmediatevalue(0) + + dut.qsfp_2_i2c_scl_i.setimmediatevalue(1) + dut.qsfp_2_i2c_sda_i.setimmediatevalue(1) + dut.qsfp_2_intr_n.setimmediatevalue(1) + dut.qsfp_2_mod_prsnt_n.setimmediatevalue(0) + + dut.qsfp_2_rx_error_count_0.setimmediatevalue(0) + dut.qsfp_2_rx_error_count_1.setimmediatevalue(0) + dut.qsfp_2_rx_error_count_2.setimmediatevalue(0) + dut.qsfp_2_rx_error_count_3.setimmediatevalue(0) + + cocotb.start_soon(Clock(dut.qsfp_3_drp_clk, 8, units="ns").start()) + dut.qsfp_3_drp_rst.setimmediatevalue(0) + dut.qsfp_3_drp_do.setimmediatevalue(0) + dut.qsfp_3_drp_rdy.setimmediatevalue(0) + + dut.qsfp_3_i2c_scl_i.setimmediatevalue(1) + dut.qsfp_3_i2c_sda_i.setimmediatevalue(1) + dut.qsfp_3_intr_n.setimmediatevalue(1) + dut.qsfp_3_mod_prsnt_n.setimmediatevalue(0) + + dut.qsfp_3_rx_error_count_0.setimmediatevalue(0) + dut.qsfp_3_rx_error_count_1.setimmediatevalue(0) + dut.qsfp_3_rx_error_count_2.setimmediatevalue(0) + dut.qsfp_3_rx_error_count_3.setimmediatevalue(0) + + dut.pps_in.setimmediatevalue(0) + + self.loopback_enable = False + cocotb.start_soon(self._run_loopback()) + + async def init(self): + + self.dut.ptp_rst.setimmediatevalue(0) + self.dut.qsfp_0_rx_rst_0.setimmediatevalue(0) + self.dut.qsfp_0_tx_rst_0.setimmediatevalue(0) + self.dut.qsfp_0_rx_rst_1.setimmediatevalue(0) + self.dut.qsfp_0_tx_rst_1.setimmediatevalue(0) + self.dut.qsfp_0_rx_rst_2.setimmediatevalue(0) + self.dut.qsfp_0_tx_rst_2.setimmediatevalue(0) + self.dut.qsfp_0_rx_rst_3.setimmediatevalue(0) + self.dut.qsfp_0_tx_rst_3.setimmediatevalue(0) + self.dut.qsfp_1_rx_rst_0.setimmediatevalue(0) + self.dut.qsfp_1_tx_rst_0.setimmediatevalue(0) + self.dut.qsfp_1_rx_rst_1.setimmediatevalue(0) + self.dut.qsfp_1_tx_rst_1.setimmediatevalue(0) + self.dut.qsfp_1_rx_rst_2.setimmediatevalue(0) + self.dut.qsfp_1_tx_rst_2.setimmediatevalue(0) + self.dut.qsfp_1_rx_rst_3.setimmediatevalue(0) + self.dut.qsfp_1_tx_rst_3.setimmediatevalue(0) + self.dut.qsfp_2_rx_rst_0.setimmediatevalue(0) + self.dut.qsfp_2_tx_rst_0.setimmediatevalue(0) + self.dut.qsfp_2_rx_rst_1.setimmediatevalue(0) + self.dut.qsfp_2_tx_rst_1.setimmediatevalue(0) + self.dut.qsfp_2_rx_rst_2.setimmediatevalue(0) + self.dut.qsfp_2_tx_rst_2.setimmediatevalue(0) + self.dut.qsfp_2_rx_rst_3.setimmediatevalue(0) + self.dut.qsfp_2_tx_rst_3.setimmediatevalue(0) + self.dut.qsfp_3_rx_rst_0.setimmediatevalue(0) + self.dut.qsfp_3_tx_rst_0.setimmediatevalue(0) + self.dut.qsfp_3_rx_rst_1.setimmediatevalue(0) + self.dut.qsfp_3_tx_rst_1.setimmediatevalue(0) + self.dut.qsfp_3_rx_rst_2.setimmediatevalue(0) + self.dut.qsfp_3_tx_rst_2.setimmediatevalue(0) + self.dut.qsfp_3_rx_rst_3.setimmediatevalue(0) + self.dut.qsfp_3_tx_rst_3.setimmediatevalue(0) + + await RisingEdge(self.dut.clk_250mhz) + await RisingEdge(self.dut.clk_250mhz) + + self.dut.ptp_rst.setimmediatevalue(1) + self.dut.qsfp_0_rx_rst_0.setimmediatevalue(1) + self.dut.qsfp_0_tx_rst_0.setimmediatevalue(1) + self.dut.qsfp_0_rx_rst_1.setimmediatevalue(1) + self.dut.qsfp_0_tx_rst_1.setimmediatevalue(1) + self.dut.qsfp_0_rx_rst_2.setimmediatevalue(1) + self.dut.qsfp_0_tx_rst_2.setimmediatevalue(1) + self.dut.qsfp_0_rx_rst_3.setimmediatevalue(1) + self.dut.qsfp_0_tx_rst_3.setimmediatevalue(1) + self.dut.qsfp_1_rx_rst_0.setimmediatevalue(1) + self.dut.qsfp_1_tx_rst_0.setimmediatevalue(1) + self.dut.qsfp_1_rx_rst_1.setimmediatevalue(1) + self.dut.qsfp_1_tx_rst_1.setimmediatevalue(1) + self.dut.qsfp_1_rx_rst_2.setimmediatevalue(1) + self.dut.qsfp_1_tx_rst_2.setimmediatevalue(1) + self.dut.qsfp_1_rx_rst_3.setimmediatevalue(1) + self.dut.qsfp_1_tx_rst_3.setimmediatevalue(1) + self.dut.qsfp_2_rx_rst_0.setimmediatevalue(1) + self.dut.qsfp_2_tx_rst_0.setimmediatevalue(1) + self.dut.qsfp_2_rx_rst_1.setimmediatevalue(1) + self.dut.qsfp_2_tx_rst_1.setimmediatevalue(1) + self.dut.qsfp_2_rx_rst_2.setimmediatevalue(1) + self.dut.qsfp_2_tx_rst_2.setimmediatevalue(1) + self.dut.qsfp_2_rx_rst_3.setimmediatevalue(1) + self.dut.qsfp_2_tx_rst_3.setimmediatevalue(1) + self.dut.qsfp_3_rx_rst_0.setimmediatevalue(1) + self.dut.qsfp_3_tx_rst_0.setimmediatevalue(1) + self.dut.qsfp_3_rx_rst_1.setimmediatevalue(1) + self.dut.qsfp_3_tx_rst_1.setimmediatevalue(1) + self.dut.qsfp_3_rx_rst_2.setimmediatevalue(1) + self.dut.qsfp_3_tx_rst_2.setimmediatevalue(1) + self.dut.qsfp_3_rx_rst_3.setimmediatevalue(1) + self.dut.qsfp_3_tx_rst_3.setimmediatevalue(1) + + await FallingEdge(self.dut.rst_250mhz) + await Timer(100, 'ns') + + await RisingEdge(self.dut.clk_250mhz) + await RisingEdge(self.dut.clk_250mhz) + + self.dut.ptp_rst.setimmediatevalue(0) + self.dut.qsfp_0_rx_rst_0.setimmediatevalue(0) + self.dut.qsfp_0_tx_rst_0.setimmediatevalue(0) + self.dut.qsfp_0_rx_rst_1.setimmediatevalue(0) + self.dut.qsfp_0_tx_rst_1.setimmediatevalue(0) + self.dut.qsfp_0_rx_rst_2.setimmediatevalue(0) + self.dut.qsfp_0_tx_rst_2.setimmediatevalue(0) + self.dut.qsfp_0_rx_rst_3.setimmediatevalue(0) + self.dut.qsfp_0_tx_rst_3.setimmediatevalue(0) + self.dut.qsfp_1_rx_rst_0.setimmediatevalue(0) + self.dut.qsfp_1_tx_rst_0.setimmediatevalue(0) + self.dut.qsfp_1_rx_rst_1.setimmediatevalue(0) + self.dut.qsfp_1_tx_rst_1.setimmediatevalue(0) + self.dut.qsfp_1_rx_rst_2.setimmediatevalue(0) + self.dut.qsfp_1_tx_rst_2.setimmediatevalue(0) + self.dut.qsfp_1_rx_rst_3.setimmediatevalue(0) + self.dut.qsfp_1_tx_rst_3.setimmediatevalue(0) + self.dut.qsfp_2_rx_rst_0.setimmediatevalue(0) + self.dut.qsfp_2_tx_rst_0.setimmediatevalue(0) + self.dut.qsfp_2_rx_rst_1.setimmediatevalue(0) + self.dut.qsfp_2_tx_rst_1.setimmediatevalue(0) + self.dut.qsfp_2_rx_rst_2.setimmediatevalue(0) + self.dut.qsfp_2_tx_rst_2.setimmediatevalue(0) + self.dut.qsfp_2_rx_rst_3.setimmediatevalue(0) + self.dut.qsfp_2_tx_rst_3.setimmediatevalue(0) + self.dut.qsfp_3_rx_rst_0.setimmediatevalue(0) + self.dut.qsfp_3_tx_rst_0.setimmediatevalue(0) + self.dut.qsfp_3_rx_rst_1.setimmediatevalue(0) + self.dut.qsfp_3_tx_rst_1.setimmediatevalue(0) + self.dut.qsfp_3_rx_rst_2.setimmediatevalue(0) + self.dut.qsfp_3_tx_rst_2.setimmediatevalue(0) + self.dut.qsfp_3_rx_rst_3.setimmediatevalue(0) + self.dut.qsfp_3_tx_rst_3.setimmediatevalue(0) + + await self.rc.enumerate() + + async def _run_loopback(self): + while True: + await RisingEdge(self.dut.clk_250mhz) + + if self.loopback_enable: + if not self.qsfp_0_0_sink.empty(): + await self.qsfp_0_0_source.send(await self.qsfp_0_0_sink.recv()) + if not self.qsfp_0_1_sink.empty(): + await self.qsfp_0_1_source.send(await self.qsfp_0_1_sink.recv()) + if not self.qsfp_0_2_sink.empty(): + await self.qsfp_0_2_source.send(await self.qsfp_0_2_sink.recv()) + if not self.qsfp_0_3_sink.empty(): + await self.qsfp_0_3_source.send(await self.qsfp_0_3_sink.recv()) + if not self.qsfp_1_0_sink.empty(): + await self.qsfp_1_0_source.send(await self.qsfp_1_0_sink.recv()) + if not self.qsfp_1_1_sink.empty(): + await self.qsfp_1_1_source.send(await self.qsfp_1_1_sink.recv()) + if not self.qsfp_1_2_sink.empty(): + await self.qsfp_1_2_source.send(await self.qsfp_1_2_sink.recv()) + if not self.qsfp_1_3_sink.empty(): + await self.qsfp_1_3_source.send(await self.qsfp_1_3_sink.recv()) + if not self.qsfp_2_0_sink.empty(): + await self.qsfp_2_0_source.send(await self.qsfp_2_0_sink.recv()) + if not self.qsfp_2_1_sink.empty(): + await self.qsfp_2_1_source.send(await self.qsfp_2_1_sink.recv()) + if not self.qsfp_2_2_sink.empty(): + await self.qsfp_2_2_source.send(await self.qsfp_2_2_sink.recv()) + if not self.qsfp_2_3_sink.empty(): + await self.qsfp_2_3_source.send(await self.qsfp_2_3_sink.recv()) + if not self.qsfp_3_0_sink.empty(): + await self.qsfp_3_0_source.send(await self.qsfp_3_0_sink.recv()) + if not self.qsfp_3_1_sink.empty(): + await self.qsfp_3_1_source.send(await self.qsfp_3_1_sink.recv()) + if not self.qsfp_3_2_sink.empty(): + await self.qsfp_3_2_source.send(await self.qsfp_3_2_sink.recv()) + if not self.qsfp_3_3_sink.empty(): + await self.qsfp_3_3_source.send(await self.qsfp_3_3_sink.recv()) + + +@cocotb.test() +async def run_test_nic(dut): + + tb = TB(dut, msix_count=2**len(dut.core_inst.core_pcie_inst.irq_index)) + + await tb.init() + + tb.log.info("Init driver") + await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id)) + await tb.driver.interfaces[0].open() + # await tb.driver.interfaces[1].open() + + # enable queues + tb.log.info("Enable queues") + await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001) + for k in range(tb.driver.interfaces[0].tx_queue_count): + await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003) + + # wait for all writes to complete + await tb.driver.hw_regs.read_dword(0) + tb.log.info("Init complete") + + tb.log.info("Send and receive single packet") + + data = bytearray([x % 256 for x in range(1024)]) + + await tb.driver.interfaces[0].start_xmit(data, 0) + + pkt = await tb.qsfp_0_0_sink.recv() + tb.log.info("Packet: %s", pkt) + + await tb.qsfp_0_0_source.send(pkt) + + pkt = await tb.driver.interfaces[0].recv() + + tb.log.info("Packet: %s", pkt) + assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + + # await tb.driver.interfaces[1].start_xmit(data, 0) + + # pkt = await tb.qsfp_1_0_sink.recv() + # tb.log.info("Packet: %s", pkt) + + # await tb.qsfp_1_0_source.send(pkt) + + # pkt = await tb.driver.interfaces[1].recv() + + # tb.log.info("Packet: %s", pkt) + # assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + + tb.log.info("RX and TX checksum tests") + + payload = bytes([x % 256 for x in range(256)]) + eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5') + ip = IP(src='192.168.1.100', dst='192.168.1.101') + udp = UDP(sport=1, dport=2) + test_pkt = eth / ip / udp / payload + + test_pkt2 = test_pkt.copy() + test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP])) + + await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6) + + pkt = await tb.qsfp_0_0_sink.recv() + tb.log.info("Packet: %s", pkt) + + await tb.qsfp_0_0_source.send(pkt) + + pkt = await tb.driver.interfaces[0].recv() + + tb.log.info("Packet: %s", pkt) + assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + assert Ether(pkt.data).build() == test_pkt.build() + + tb.log.info("Queue mapping offset test") + + data = bytearray([x % 256 for x in range(1024)]) + + tb.loopback_enable = True + + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k) + + await tb.driver.interfaces[0].start_xmit(data, 0) + + pkt = await tb.driver.interfaces[0].recv() + + tb.log.info("Packet: %s", pkt) + assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + assert pkt.queue == k + + tb.loopback_enable = False + + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0) + + tb.log.info("Queue mapping RSS mask test") + + await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003) + + for k in range(4): + await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k) + + tb.loopback_enable = True + + queues = set() + + for k in range(64): + payload = bytes([x % 256 for x in range(256)]) + eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5') + ip = IP(src='192.168.1.100', dst='192.168.1.101') + udp = UDP(sport=1, dport=k+0) + test_pkt = eth / ip / udp / payload + + test_pkt2 = test_pkt.copy() + test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP])) + + await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6) + + for k in range(64): + pkt = await tb.driver.interfaces[0].recv() + + tb.log.info("Packet: %s", pkt) + assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + + queues.add(pkt.queue) + + assert len(queues) == 4 + + tb.loopback_enable = False + + await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0) + + tb.log.info("Multiple small packets") + + count = 64 + + pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)] + + tb.loopback_enable = True + + for p in pkts: + await tb.driver.interfaces[0].start_xmit(p, 0) + + for k in range(count): + pkt = await tb.driver.interfaces[0].recv() + + tb.log.info("Packet: %s", pkt) + assert pkt.data == pkts[k] + assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + + tb.loopback_enable = False + + tb.log.info("Multiple large packets") + + count = 64 + + pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] + + tb.loopback_enable = True + + for p in pkts: + await tb.driver.interfaces[0].start_xmit(p, 0) + + for k in range(count): + pkt = await tb.driver.interfaces[0].recv() + + tb.log.info("Packet: %s", pkt) + assert pkt.data == pkts[k] + assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff + + tb.loopback_enable = False + + await RisingEdge(dut.clk_250mhz) + await RisingEdge(dut.clk_250mhz) + + +# cocotb-test + +tests_dir = os.path.dirname(__file__) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) +app_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'app')) +axi_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axi', 'rtl')) +axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl')) +eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) +pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl')) + + +def test_fpga_core(request): + dut = "fpga_core" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = dut + + verilog_sources = [ + os.path.join(rtl_dir, f"{dut}.v"), + os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), + os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), + os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), + os.path.join(rtl_dir, "common", "mqnic_interface.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_port.v"), + os.path.join(rtl_dir, "common", "mqnic_port_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_port_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_ingress.v"), + os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"), + os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"), + os.path.join(rtl_dir, "common", "mqnic_ptp.v"), + os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), + os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), + os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"), + os.path.join(rtl_dir, "common", "mqnic_port_map_phy_xgmii.v"), + os.path.join(rtl_dir, "common", "cpl_write.v"), + os.path.join(rtl_dir, "common", "cpl_op_mux.v"), + os.path.join(rtl_dir, "common", "desc_fetch.v"), + os.path.join(rtl_dir, "common", "desc_op_mux.v"), + os.path.join(rtl_dir, "common", "event_mux.v"), + os.path.join(rtl_dir, "common", "queue_manager.v"), + os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), + os.path.join(rtl_dir, "common", "tx_fifo.v"), + os.path.join(rtl_dir, "common", "rx_fifo.v"), + os.path.join(rtl_dir, "common", "tx_req_mux.v"), + os.path.join(rtl_dir, "common", "tx_engine.v"), + os.path.join(rtl_dir, "common", "rx_engine.v"), + os.path.join(rtl_dir, "common", "tx_checksum.v"), + os.path.join(rtl_dir, "common", "rx_hash.v"), + os.path.join(rtl_dir, "common", "rx_checksum.v"), + os.path.join(rtl_dir, "common", "rb_drp.v"), + os.path.join(rtl_dir, "common", "stats_counter.v"), + os.path.join(rtl_dir, "common", "stats_collect.v"), + os.path.join(rtl_dir, "common", "stats_pcie_if.v"), + os.path.join(rtl_dir, "common", "stats_pcie_tlp.v"), + os.path.join(rtl_dir, "common", "stats_dma_if_pcie.v"), + os.path.join(rtl_dir, "common", "stats_dma_latency.v"), + os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"), + os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"), + os.path.join(rtl_dir, "common", "tdma_scheduler.v"), + os.path.join(rtl_dir, "common", "tdma_ber.v"), + os.path.join(rtl_dir, "common", "tdma_ber_ch.v"), + os.path.join(eth_rtl_dir, "eth_mac_10g.v"), + os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), + os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), + os.path.join(eth_rtl_dir, "lfsr.v"), + os.path.join(eth_rtl_dir, "ptp_clock.v"), + os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"), + os.path.join(eth_rtl_dir, "ptp_perout.v"), + os.path.join(axi_rtl_dir, "axil_interconnect.v"), + os.path.join(axi_rtl_dir, "axil_crossbar.v"), + os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"), + os.path.join(axi_rtl_dir, "axil_crossbar_rd.v"), + os.path.join(axi_rtl_dir, "axil_crossbar_wr.v"), + os.path.join(axi_rtl_dir, "axil_reg_if.v"), + os.path.join(axi_rtl_dir, "axil_reg_if_rd.v"), + os.path.join(axi_rtl_dir, "axil_reg_if_wr.v"), + os.path.join(axi_rtl_dir, "axil_register_rd.v"), + os.path.join(axi_rtl_dir, "axil_register_wr.v"), + os.path.join(axi_rtl_dir, "arbiter.v"), + os.path.join(axi_rtl_dir, "priority_encoder.v"), + os.path.join(axis_rtl_dir, "axis_adapter.v"), + os.path.join(axis_rtl_dir, "axis_arb_mux.v"), + os.path.join(axis_rtl_dir, "axis_async_fifo.v"), + os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), + os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), + os.path.join(axis_rtl_dir, "axis_register.v"), + os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), + os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"), + os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"), + os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"), + os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"), + os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"), + os.path.join(pcie_rtl_dir, "pcie_msix.v"), + os.path.join(pcie_rtl_dir, "irq_rate_limit.v"), + os.path.join(pcie_rtl_dir, "dma_if_pcie.v"), + os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"), + os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"), + os.path.join(pcie_rtl_dir, "dma_if_mux.v"), + os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"), + os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"), + os.path.join(pcie_rtl_dir, "dma_if_desc_mux.v"), + os.path.join(pcie_rtl_dir, "dma_ram_demux_rd.v"), + os.path.join(pcie_rtl_dir, "dma_ram_demux_wr.v"), + os.path.join(pcie_rtl_dir, "dma_psdpram.v"), + os.path.join(pcie_rtl_dir, "dma_client_axis_sink.v"), + os.path.join(pcie_rtl_dir, "dma_client_axis_source.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"), + os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"), + os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"), + os.path.join(pcie_rtl_dir, "pulse_merge.v"), + ] + + parameters = {} + + # Structural configuration + parameters['IF_COUNT'] = 4 + parameters['PORTS_PER_IF'] = 1 + parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF'] + parameters['PORT_MASK'] = 0 + + # Clock configuration + parameters['CLK_PERIOD_NS_NUM'] = 4 + parameters['CLK_PERIOD_NS_DENOM'] = 1 + + # PTP configuration + parameters['PTP_CLK_PERIOD_NS_NUM'] = 1024 + parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165 + parameters['PTP_CLOCK_PIPELINE'] = 0 + parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 + parameters['PTP_USE_SAMPLE_CLOCK'] = 1 + parameters['PTP_PORT_CDC_PIPELINE'] = 0 + parameters['PTP_PEROUT_ENABLE'] = 1 + parameters['PTP_PEROUT_COUNT'] = 1 + + # Queue manager configuration + parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32 + parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32 + parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32 + parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE'] + parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE'] + parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6 + parameters['TX_QUEUE_INDEX_WIDTH'] = 13 + parameters['RX_QUEUE_INDEX_WIDTH'] = 8 + parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH'] + parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH'] + parameters['EVENT_QUEUE_PIPELINE'] = 3 + parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0) + parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0) + parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] + parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE'] + + # TX and RX engine configuration + parameters['TX_DESC_TABLE_SIZE'] = 32 + parameters['RX_DESC_TABLE_SIZE'] = 32 + parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8) + + # Scheduler configuration + parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE'] + parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE'] + parameters['TDMA_INDEX_WIDTH'] = 6 + + # Interface configuration + parameters['PTP_TS_ENABLE'] = 1 + parameters['TX_CPL_FIFO_DEPTH'] = 32 + parameters['TX_CHECKSUM_ENABLE'] = 1 + parameters['RX_HASH_ENABLE'] = 1 + parameters['RX_CHECKSUM_ENABLE'] = 1 + parameters['TX_FIFO_DEPTH'] = 32768 + parameters['RX_FIFO_DEPTH'] = 32768 + parameters['MAX_TX_SIZE'] = 9214 + parameters['MAX_RX_SIZE'] = 9214 + parameters['TX_RAM_SIZE'] = 32768 + parameters['RX_RAM_SIZE'] = 131072 + + # Application block configuration + parameters['APP_ID'] = 0x00000000 + parameters['APP_ENABLE'] = 0 + parameters['APP_CTRL_ENABLE'] = 1 + parameters['APP_DMA_ENABLE'] = 1 + parameters['APP_AXIS_DIRECT_ENABLE'] = 1 + parameters['APP_AXIS_SYNC_ENABLE'] = 1 + parameters['APP_AXIS_IF_ENABLE'] = 1 + parameters['APP_STAT_ENABLE'] = 1 + + # DMA interface configuration + parameters['DMA_IMM_ENABLE'] = 0 + parameters['DMA_IMM_WIDTH'] = 32 + parameters['DMA_LEN_WIDTH'] = 16 + parameters['DMA_TAG_WIDTH'] = 16 + parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length() + parameters['RAM_PIPELINE'] = 2 + + # PCIe interface configuration + parameters['AXIS_PCIE_DATA_WIDTH'] = 512 + parameters['PF_COUNT'] = 1 + parameters['VF_COUNT'] = 0 + + # Interrupt configuration + parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH'] + + # AXI lite interface configuration (control) + parameters['AXIL_CTRL_DATA_WIDTH'] = 32 + parameters['AXIL_CTRL_ADDR_WIDTH'] = 25 + + # AXI lite interface configuration (application control) + parameters['AXIL_APP_CTRL_DATA_WIDTH'] = parameters['AXIL_CTRL_DATA_WIDTH'] + parameters['AXIL_APP_CTRL_ADDR_WIDTH'] = 24 + + # Ethernet interface configuration + parameters['AXIS_ETH_TX_PIPELINE'] = 4 + parameters['AXIS_ETH_TX_FIFO_PIPELINE'] = 4 + parameters['AXIS_ETH_TX_TS_PIPELINE'] = 4 + parameters['AXIS_ETH_RX_PIPELINE'] = 4 + parameters['AXIS_ETH_RX_FIFO_PIPELINE'] = 4 + + # Statistics counter subsystem + parameters['STAT_ENABLE'] = 1 + parameters['STAT_DMA_ENABLE'] = 1 + parameters['STAT_PCIE_ENABLE'] = 1 + parameters['STAT_INC_WIDTH'] = 24 + parameters['STAT_ID_WIDTH'] = 12 + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + )