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Rework hierarchy to move port-specific logic out of mqnic_core and into mqnic_interface and new port-level modules

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-04-29 14:32:57 -07:00
parent 2d5e82f42a
commit 53f3547ef5
114 changed files with 2896 additions and 1956 deletions
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2
fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile
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@ -48,6 +48,8 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

36
fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
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@ -272,7 +272,7 @@ class TB(object):
# Ethernet
self.port_mac = []
eth_int_if_width = len(dut.core_pcie_inst.core_inst.iface[0].port[0].rx_async_fifo_inst.m_axis_tdata)
eth_int_if_width = len(dut.core_pcie_inst.core_inst.m_axis_tx_tdata) / len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)
eth_clock_period = 6.4
eth_speed = 10e9
@ -290,25 +290,25 @@ class TB(object):
eth_speed = 100e9
for iface in dut.core_pcie_inst.core_inst.iface:
for port in iface.port:
cocotb.start_soon(Clock(port.port_rx_clk, eth_clock_period, units="ns").start())
cocotb.start_soon(Clock(port.port_tx_clk, eth_clock_period, units="ns").start())
for k in range(len(iface.port)):
cocotb.start_soon(Clock(iface.port[k].port_rx_clk, eth_clock_period, units="ns").start())
cocotb.start_soon(Clock(iface.port[k].port_tx_clk, eth_clock_period, units="ns").start())
port.port_rx_rst.setimmediatevalue(0)
port.port_tx_rst.setimmediatevalue(0)
iface.port[k].port_rx_rst.setimmediatevalue(0)
iface.port[k].port_tx_rst.setimmediatevalue(0)
mac = EthMac(
tx_clk=port.port_tx_clk,
tx_rst=port.port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(port, "axis_tx"),
tx_ptp_time=port.ptp.tx_ptp_cdc_inst.output_ts,
tx_ptp_ts=port.ptp.axis_tx_ptp_ts,
tx_ptp_ts_tag=port.ptp.axis_tx_ptp_ts_tag,
tx_ptp_ts_valid=port.ptp.axis_tx_ptp_ts_valid,
rx_clk=port.port_rx_clk,
rx_rst=port.port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(port, "axis_rx"),
rx_ptp_time=port.ptp.rx_ptp_cdc_inst.output_ts,
tx_clk=iface.port[k].port_tx_clk,
tx_rst=iface.port[k].port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_tx_inst, "m_axis_tx"),
tx_ptp_time=iface.port[k].ptp.tx_ptp_cdc_inst.output_ts,
tx_ptp_ts=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts_valid,
rx_clk=iface.port[k].port_rx_clk,
rx_rst=iface.port[k].port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_rx_inst, "s_axis_rx"),
rx_ptp_time=iface.port[k].ptp.rx_ptp_cdc_inst.output_ts,
ifg=12, speed=eth_speed
)
@ -823,6 +823,8 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

2
fpga/app/template/tb/mqnic_core_pcie_us/Makefile
View File

@ -48,6 +48,8 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

36
fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -272,7 +272,7 @@ class TB(object):
# Ethernet
self.port_mac = []
eth_int_if_width = len(dut.core_pcie_inst.core_inst.iface[0].port[0].rx_async_fifo_inst.m_axis_tdata)
eth_int_if_width = len(dut.core_pcie_inst.core_inst.m_axis_tx_tdata) / len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)
eth_clock_period = 6.4
eth_speed = 10e9
@ -290,25 +290,25 @@ class TB(object):
eth_speed = 100e9
for iface in dut.core_pcie_inst.core_inst.iface:
for port in iface.port:
cocotb.start_soon(Clock(port.port_rx_clk, eth_clock_period, units="ns").start())
cocotb.start_soon(Clock(port.port_tx_clk, eth_clock_period, units="ns").start())
for k in range(len(iface.port)):
cocotb.start_soon(Clock(iface.port[k].port_rx_clk, eth_clock_period, units="ns").start())
cocotb.start_soon(Clock(iface.port[k].port_tx_clk, eth_clock_period, units="ns").start())
port.port_rx_rst.setimmediatevalue(0)
port.port_tx_rst.setimmediatevalue(0)
iface.port[k].port_rx_rst.setimmediatevalue(0)
iface.port[k].port_tx_rst.setimmediatevalue(0)
mac = EthMac(
tx_clk=port.port_tx_clk,
tx_rst=port.port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(port, "axis_tx"),
tx_ptp_time=port.ptp.tx_ptp_cdc_inst.output_ts,
tx_ptp_ts=port.ptp.axis_tx_ptp_ts,
tx_ptp_ts_tag=port.ptp.axis_tx_ptp_ts_tag,
tx_ptp_ts_valid=port.ptp.axis_tx_ptp_ts_valid,
rx_clk=port.port_rx_clk,
rx_rst=port.port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(port, "axis_rx"),
rx_ptp_time=port.ptp.rx_ptp_cdc_inst.output_ts,
tx_clk=iface.port[k].port_tx_clk,
tx_rst=iface.port[k].port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_tx_inst, "m_axis_tx"),
tx_ptp_time=iface.port[k].ptp.tx_ptp_cdc_inst.output_ts,
tx_ptp_ts=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts_valid,
rx_clk=iface.port[k].port_rx_clk,
rx_rst=iface.port[k].port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_rx_inst, "s_axis_rx"),
rx_ptp_time=iface.port[k].ptp.rx_ptp_cdc_inst.output_ts,
ifg=12, speed=eth_speed
)
@ -663,6 +663,8 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

1327
fpga/common/rtl/mqnic_core.v
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File diff suppressed because it is too large Load Diff

1533
fpga/common/rtl/mqnic_interface.v
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File diff suppressed because it is too large Load Diff

332
fpga/common/rtl/mqnic_interface_rx.v
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@ -1,6 +1,6 @@
/*
Copyright 2021, The Regents of the University of California.
Copyright 2021-2022, The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
@ -42,214 +42,182 @@ either expressed or implied, of The Regents of the University of California.
*/
module mqnic_interface_rx #
(
// Number of ports
// Structural configuration
parameter PORTS = 1,
// Control register interface address width
parameter REG_ADDR_WIDTH = 7,
// Control register interface data width
parameter REG_DATA_WIDTH = 32,
// Control register interface byte enable width
parameter REG_STRB_WIDTH = (REG_DATA_WIDTH/8),
// Register block base address
parameter RB_BASE_ADDR = 0,
// Register block next block address
parameter RB_NEXT_PTR = 0,
// DMA address width
parameter DMA_ADDR_WIDTH = 64,
// DMA length field width
parameter DMA_LEN_WIDTH = 16,
// DMA tag field width
parameter DMA_TAG_WIDTH = 8,
// Descriptor request tag field width
parameter DESC_REQ_TAG_WIDTH = 8,
// Queue request tag field width
parameter QUEUE_REQ_TAG_WIDTH = 8,
// Queue operation tag field width
parameter QUEUE_OP_TAG_WIDTH = 8,
// Receive queue index width
parameter RX_QUEUE_INDEX_WIDTH = 8,
// Max queue index width
parameter QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
// Receive completion queue index width
parameter RX_CPL_QUEUE_INDEX_WIDTH = 8,
// Max completion queue index width
parameter CPL_QUEUE_INDEX_WIDTH = RX_CPL_QUEUE_INDEX_WIDTH,
// Receive descriptor table size (number of in-flight operations)
parameter RX_DESC_TABLE_SIZE = 16,
// Width of descriptor table field for tracking outstanding DMA operations
parameter DESC_TABLE_DMA_OP_COUNT_WIDTH = 4,
// Max number of in-flight descriptor requests (transmit)
parameter RX_MAX_DESC_REQ = 16,
// Receive descriptor FIFO size
parameter RX_DESC_FIFO_SIZE = RX_MAX_DESC_REQ*8,
// Queue element pointer width
parameter QUEUE_PTR_WIDTH = 16,
// Queue log size field width
parameter LOG_QUEUE_SIZE_WIDTH = 4,
// Log desc block size field width
parameter LOG_BLOCK_SIZE_WIDTH = 2,
// Enable PTP timestamping
parameter PTP_TS_ENABLE = 1,
// PTP timestamp width
// PTP configuration
parameter PTP_TS_WIDTH = 96,
// PTP tag width
parameter PTP_TAG_WIDTH = 16,
// Enable RX RSS
parameter RX_RSS_ENABLE = 1,
// Enable RX hashing
parameter RX_HASH_ENABLE = 1,
// Enable RX checksum offload
parameter RX_CHECKSUM_ENABLE = 1,
// DMA RAM address width
parameter RAM_ADDR_WIDTH = 18,
// DMA RAM segment count
parameter SEG_COUNT = 2,
// DMA RAM segment data width
parameter SEG_DATA_WIDTH = 64,
// DMA RAM segment byte enable width
parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8,
// DMA RAM segment address width
parameter SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(SEG_COUNT*SEG_BE_WIDTH),
// DMA RAM pipeline stages
parameter RAM_PIPELINE = 2,
// Width of AXI stream interfaces in bits
parameter AXIS_DATA_WIDTH = 256,
// AXI stream tkeep signal width (words per cycle)
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
// AXI stream tid signal width
parameter AXIS_RX_ID_WIDTH = PORTS > 1 ? $clog2(PORTS) : 1,
// AXI stream tdest signal width
parameter AXIS_RX_DEST_WIDTH = RX_QUEUE_INDEX_WIDTH,
// AXI stream tuser signal width
parameter AXIS_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
// Max receive packet size
parameter MAX_RX_SIZE = 2048,
// DMA RX RAM size
parameter RX_RAM_SIZE = 8*MAX_RX_SIZE,
// Descriptor size (in bytes)
// Queue manager configuration (interface)
parameter RX_QUEUE_INDEX_WIDTH = 8,
parameter QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
parameter CPL_QUEUE_INDEX_WIDTH = RX_CPL_QUEUE_INDEX_WIDTH,
parameter QUEUE_PTR_WIDTH = 16,
parameter LOG_QUEUE_SIZE_WIDTH = 4,
parameter LOG_BLOCK_SIZE_WIDTH = 2,
// Descriptor management
parameter RX_MAX_DESC_REQ = 16,
parameter RX_DESC_FIFO_SIZE = RX_MAX_DESC_REQ*8,
parameter DESC_SIZE = 16,
// Descriptor size (in bytes)
parameter CPL_SIZE = 32,
// Width of AXI stream descriptor interfaces in bits
parameter AXIS_DESC_DATA_WIDTH = DESC_SIZE*8,
// AXI stream descriptor tkeep signal width (words per cycle)
parameter AXIS_DESC_KEEP_WIDTH = AXIS_DESC_DATA_WIDTH/8
parameter AXIS_DESC_KEEP_WIDTH = AXIS_DESC_DATA_WIDTH/8,
parameter DESC_REQ_TAG_WIDTH = 8,
parameter QUEUE_REQ_TAG_WIDTH = 8,
parameter QUEUE_OP_TAG_WIDTH = 8,
// TX and RX engine configuration (port)
parameter RX_DESC_TABLE_SIZE = 32,
parameter DESC_TABLE_DMA_OP_COUNT_WIDTH = 4,
// Timestamping configuration (port)
parameter PTP_TS_ENABLE = 1,
// Interface configuration (port)
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter RX_FIFO_DEPTH = 32768,
parameter MAX_RX_SIZE = 9214,
parameter RX_RAM_SIZE = 32768,
// DMA interface configuration
parameter DMA_ADDR_WIDTH = 64,
parameter DMA_LEN_WIDTH = 16,
parameter DMA_TAG_WIDTH = 16,
parameter RAM_ADDR_WIDTH = $clog2(RX_RAM_SIZE),
parameter RAM_SEG_COUNT = 2,
parameter RAM_SEG_DATA_WIDTH = 256*2/RAM_SEG_COUNT,
parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8,
parameter RAM_SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH),
parameter RAM_PIPELINE = 2,
// Register interface configuration
parameter REG_ADDR_WIDTH = 7,
parameter REG_DATA_WIDTH = 32,
parameter REG_STRB_WIDTH = (REG_DATA_WIDTH/8),
parameter RB_BASE_ADDR = 0,
parameter RB_NEXT_PTR = 0,
// Streaming interface configuration
parameter AXIS_DATA_WIDTH = 512*2**$clog2(PORTS),
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
parameter AXIS_RX_ID_WIDTH = PORTS > 1 ? $clog2(PORTS) : 1,
parameter AXIS_RX_DEST_WIDTH = RX_QUEUE_INDEX_WIDTH,
parameter AXIS_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1
)
(
input wire clk,
input wire rst,
input wire clk,
input wire rst,
/*
* Control register interface
*/
input wire [REG_ADDR_WIDTH-1:0] ctrl_reg_wr_addr,
input wire [REG_DATA_WIDTH-1:0] ctrl_reg_wr_data,
input wire [REG_STRB_WIDTH-1:0] ctrl_reg_wr_strb,
input wire ctrl_reg_wr_en,
output wire ctrl_reg_wr_wait,
output wire ctrl_reg_wr_ack,
input wire [REG_ADDR_WIDTH-1:0] ctrl_reg_rd_addr,
input wire ctrl_reg_rd_en,
output wire [REG_DATA_WIDTH-1:0] ctrl_reg_rd_data,
output wire ctrl_reg_rd_wait,
output wire ctrl_reg_rd_ack,
input wire [REG_ADDR_WIDTH-1:0] ctrl_reg_wr_addr,
input wire [REG_DATA_WIDTH-1:0] ctrl_reg_wr_data,
input wire [REG_STRB_WIDTH-1:0] ctrl_reg_wr_strb,
input wire ctrl_reg_wr_en,
output wire ctrl_reg_wr_wait,
output wire ctrl_reg_wr_ack,
input wire [REG_ADDR_WIDTH-1:0] ctrl_reg_rd_addr,
input wire ctrl_reg_rd_en,
output wire [REG_DATA_WIDTH-1:0] ctrl_reg_rd_data,
output wire ctrl_reg_rd_wait,
output wire ctrl_reg_rd_ack,
/*
* Descriptor request output
*/
output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_desc_req_queue,
output wire [DESC_REQ_TAG_WIDTH-1:0] m_axis_desc_req_tag,
output wire m_axis_desc_req_valid,
input wire m_axis_desc_req_ready,
output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_desc_req_queue,
output wire [DESC_REQ_TAG_WIDTH-1:0] m_axis_desc_req_tag,
output wire m_axis_desc_req_valid,
input wire m_axis_desc_req_ready,
/*
* Descriptor request status input
*/
input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_queue,
input wire [QUEUE_PTR_WIDTH-1:0] s_axis_desc_req_status_ptr,
input wire [CPL_QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_cpl,
input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_req_status_tag,
input wire s_axis_desc_req_status_empty,
input wire s_axis_desc_req_status_error,
input wire s_axis_desc_req_status_valid,
input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_queue,
input wire [QUEUE_PTR_WIDTH-1:0] s_axis_desc_req_status_ptr,
input wire [CPL_QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_cpl,
input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_req_status_tag,
input wire s_axis_desc_req_status_empty,
input wire s_axis_desc_req_status_error,
input wire s_axis_desc_req_status_valid,
/*
* Descriptor data input
*/
input wire [AXIS_DESC_DATA_WIDTH-1:0] s_axis_desc_tdata,
input wire [AXIS_DESC_KEEP_WIDTH-1:0] s_axis_desc_tkeep,
input wire s_axis_desc_tvalid,
output wire s_axis_desc_tready,
input wire s_axis_desc_tlast,
input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_tid,
input wire s_axis_desc_tuser,
input wire [AXIS_DESC_DATA_WIDTH-1:0] s_axis_desc_tdata,
input wire [AXIS_DESC_KEEP_WIDTH-1:0] s_axis_desc_tkeep,
input wire s_axis_desc_tvalid,
output wire s_axis_desc_tready,
input wire s_axis_desc_tlast,
input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_tid,
input wire s_axis_desc_tuser,
/*
* Completion request output
*/
output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue,
output wire [DESC_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag,
output wire [CPL_SIZE*8-1:0] m_axis_cpl_req_data,
output wire m_axis_cpl_req_valid,
input wire m_axis_cpl_req_ready,
output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue,
output wire [DESC_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag,
output wire [CPL_SIZE*8-1:0] m_axis_cpl_req_data,
output wire m_axis_cpl_req_valid,
input wire m_axis_cpl_req_ready,
/*
* Completion request status input
*/
input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_cpl_req_status_tag,
input wire s_axis_cpl_req_status_full,
input wire s_axis_cpl_req_status_error,
input wire s_axis_cpl_req_status_valid,
input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_cpl_req_status_tag,
input wire s_axis_cpl_req_status_full,
input wire s_axis_cpl_req_status_error,
input wire s_axis_cpl_req_status_valid,
/*
* DMA write descriptor output (data)
*/
output wire [DMA_ADDR_WIDTH-1:0] m_axis_dma_write_desc_dma_addr,
output wire [RAM_ADDR_WIDTH-1:0] m_axis_dma_write_desc_ram_addr,
output wire [DMA_LEN_WIDTH-1:0] m_axis_dma_write_desc_len,
output wire [DMA_TAG_WIDTH-1:0] m_axis_dma_write_desc_tag,
output wire m_axis_dma_write_desc_valid,
input wire m_axis_dma_write_desc_ready,
output wire [DMA_ADDR_WIDTH-1:0] m_axis_dma_write_desc_dma_addr,
output wire [RAM_ADDR_WIDTH-1:0] m_axis_dma_write_desc_ram_addr,
output wire [DMA_LEN_WIDTH-1:0] m_axis_dma_write_desc_len,
output wire [DMA_TAG_WIDTH-1:0] m_axis_dma_write_desc_tag,
output wire m_axis_dma_write_desc_valid,
input wire m_axis_dma_write_desc_ready,
/*
* DMA write descriptor status input (data)
*/
input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_write_desc_status_tag,
input wire [3:0] s_axis_dma_write_desc_status_error,
input wire s_axis_dma_write_desc_status_valid,
input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_write_desc_status_tag,
input wire [3:0] s_axis_dma_write_desc_status_error,
input wire s_axis_dma_write_desc_status_valid,
/*
* RAM interface (data)
*/
input wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_rd_cmd_addr,
input wire [SEG_COUNT-1:0] dma_ram_rd_cmd_valid,
output wire [SEG_COUNT-1:0] dma_ram_rd_cmd_ready,
output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data,
output wire [SEG_COUNT-1:0] dma_ram_rd_resp_valid,
input wire [SEG_COUNT-1:0] dma_ram_rd_resp_ready,
input wire [RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] dma_ram_rd_cmd_addr,
input wire [RAM_SEG_COUNT-1:0] dma_ram_rd_cmd_valid,
output wire [RAM_SEG_COUNT-1:0] dma_ram_rd_cmd_ready,
output wire [RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data,
output wire [RAM_SEG_COUNT-1:0] dma_ram_rd_resp_valid,
input wire [RAM_SEG_COUNT-1:0] dma_ram_rd_resp_ready,
/*
* Receive data input
*/
input wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep,
input wire rx_axis_tvalid,
output wire rx_axis_tready,
input wire rx_axis_tlast,
input wire [AXIS_RX_ID_WIDTH-1:0] rx_axis_tid,
input wire [AXIS_RX_DEST_WIDTH-1:0] rx_axis_tdest,
input wire [AXIS_RX_USER_WIDTH-1:0] rx_axis_tuser,
/*
* PTP clock
*/
input wire [95:0] ptp_ts_96,
input wire ptp_ts_step,
input wire [AXIS_DATA_WIDTH-1:0] s_axis_rx_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] s_axis_rx_tkeep,
input wire s_axis_rx_tvalid,
output wire s_axis_rx_tready,
input wire s_axis_rx_tlast,
input wire [AXIS_RX_ID_WIDTH-1:0] s_axis_rx_tid,
input wire [AXIS_RX_DEST_WIDTH-1:0] s_axis_rx_tdest,
input wire [AXIS_RX_USER_WIDTH-1:0] s_axis_rx_tuser,
/*
* Configuration
*/
input wire [DMA_CLIENT_LEN_WIDTH-1:0] mtu
input wire [DMA_CLIENT_LEN_WIDTH-1:0] mtu
);
parameter DMA_CLIENT_TAG_WIDTH = $clog2(RX_DESC_TABLE_SIZE);
@ -344,7 +312,7 @@ always @(posedge clk) begin
rx_req_cnt_reg <= rx_req_cnt_reg - 1;
end
if (rx_axis_tready && rx_axis_tvalid) begin
if (s_axis_rx_tready && s_axis_rx_tvalid) begin
if (!rx_frame_reg) begin
if (rx_req_valid && rx_req_ready) begin
rx_req_cnt_reg <= rx_req_cnt_reg;
@ -352,7 +320,7 @@ always @(posedge clk) begin
rx_req_cnt_reg <= rx_req_cnt_reg + 1;
end
end
rx_frame_reg <= !rx_axis_tlast;
rx_frame_reg <= !s_axis_rx_tlast;
end
if (rst) begin
@ -386,7 +354,7 @@ rx_engine #(
.MAX_RX_SIZE(MAX_RX_SIZE),
.RX_BUFFER_OFFSET(0),
.RX_BUFFER_SIZE(RX_RAM_SIZE),
.RX_BUFFER_STEP_SIZE(SEG_COUNT*SEG_BE_WIDTH),
.RX_BUFFER_STEP_SIZE(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH),
.DESC_SIZE(DESC_SIZE),
.CPL_SIZE(CPL_SIZE),
.MAX_DESC_REQ(RX_MAX_DESC_REQ),
@ -531,19 +499,19 @@ rx_engine_inst (
.enable(1'b1)
);
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] dma_ram_wr_cmd_be_int;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_wr_cmd_addr_int;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_wr_cmd_data_int;
wire [SEG_COUNT-1:0] dma_ram_wr_cmd_valid_int;
wire [SEG_COUNT-1:0] dma_ram_wr_cmd_ready_int;
wire [SEG_COUNT-1:0] dma_ram_wr_done_int;
wire [RAM_SEG_COUNT*RAM_SEG_BE_WIDTH-1:0] dma_ram_wr_cmd_be_int;
wire [RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] dma_ram_wr_cmd_addr_int;
wire [RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] dma_ram_wr_cmd_data_int;
wire [RAM_SEG_COUNT-1:0] dma_ram_wr_cmd_valid_int;
wire [RAM_SEG_COUNT-1:0] dma_ram_wr_cmd_ready_int;
wire [RAM_SEG_COUNT-1:0] dma_ram_wr_done_int;
dma_psdpram #(
.SIZE(RX_RAM_SIZE),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_COUNT(RAM_SEG_COUNT),
.SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH),
.SEG_BE_WIDTH(RAM_SEG_BE_WIDTH),
.SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH),
.PIPELINE(RAM_PIPELINE)
)
dma_psdpram_rx_inst (
@ -601,14 +569,14 @@ ingress_inst (
/*
* Receive data input
*/
.s_axis_tdata(rx_axis_tdata),
.s_axis_tkeep(rx_axis_tkeep),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tid(rx_axis_tid),
.s_axis_tdest(rx_axis_tdest),
.s_axis_tuser(rx_axis_tuser),
.s_axis_tdata(s_axis_rx_tdata),
.s_axis_tkeep(s_axis_rx_tkeep),
.s_axis_tvalid(s_axis_rx_tvalid),
.s_axis_tready(s_axis_rx_tready),
.s_axis_tlast(s_axis_rx_tlast),
.s_axis_tid(s_axis_rx_tid),
.s_axis_tdest(s_axis_rx_tdest),
.s_axis_tuser(s_axis_rx_tuser),
/*
* Receive data output
@ -632,10 +600,10 @@ ingress_inst (
dma_client_axis_sink #(
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_COUNT(RAM_SEG_COUNT),
.SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH),
.SEG_BE_WIDTH(RAM_SEG_BE_WIDTH),
.SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_ENABLE(AXIS_KEEP_WIDTH > 1),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),

319
fpga/common/rtl/mqnic_interface_tx.v
View File

@ -1,6 +1,6 @@
/*
Copyright 2021, The Regents of the University of California.
Copyright 2021-2022, The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
@ -42,219 +42,184 @@ either expressed or implied, of The Regents of the University of California.
*/
module mqnic_interface_tx #
(
// Number of ports
// Structural configuration
parameter PORTS = 1,
// DMA address width
parameter DMA_ADDR_WIDTH = 64,
// DMA length field width
parameter DMA_LEN_WIDTH = 16,
// DMA tag field width
parameter DMA_TAG_WIDTH = 8,
// Transmit request tag field width
parameter REQ_TAG_WIDTH = 8,
// Descriptor request tag field width
parameter DESC_REQ_TAG_WIDTH = 8,
// Queue request tag field width
parameter QUEUE_REQ_TAG_WIDTH = 8,
// Queue operation tag field width
parameter QUEUE_OP_TAG_WIDTH = 8,
// Transmit queue index width
parameter TX_QUEUE_INDEX_WIDTH = 8,
// Max queue index width
parameter QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
// Transmit completion queue index width
parameter TX_CPL_QUEUE_INDEX_WIDTH = 8,
// Max completion queue index width
parameter CPL_QUEUE_INDEX_WIDTH = TX_CPL_QUEUE_INDEX_WIDTH,
// Transmit descriptor table size (number of in-flight operations)
parameter TX_DESC_TABLE_SIZE = 16,
// Width of descriptor table field for tracking outstanding DMA operations
parameter DESC_TABLE_DMA_OP_COUNT_WIDTH = 4,
// Max number of in-flight descriptor requests (transmit)
parameter TX_MAX_DESC_REQ = 16,
// Transmit descriptor FIFO size
parameter TX_DESC_FIFO_SIZE = TX_MAX_DESC_REQ*8,
// Scheduler operation table size
parameter TX_SCHEDULER_OP_TABLE_SIZE = 32,
// Scheduler pipeline setting
parameter TX_SCHEDULER_PIPELINE = 3,
// Scheduler TDMA index width
parameter TDMA_INDEX_WIDTH = 8,
// Interrupt number width
parameter INT_WIDTH = 8,
// Queue element pointer width
parameter QUEUE_PTR_WIDTH = 16,
// Queue log size field width
parameter LOG_QUEUE_SIZE_WIDTH = 4,
// Log desc block size field width
parameter LOG_BLOCK_SIZE_WIDTH = 2,
// Enable PTP timestamping
parameter PTP_TS_ENABLE = 1,
// PTP timestamp width
// PTP configuration
parameter PTP_TS_WIDTH = 96,
// PTP tag width
parameter PTP_TAG_WIDTH = 16,
// Enable TX checksum offload
parameter TX_CHECKSUM_ENABLE = 1,
// DMA RAM address width
parameter RAM_ADDR_WIDTH = 18,
// DMA RAM segment count
parameter SEG_COUNT = 2,
// DMA RAM segment data width
parameter SEG_DATA_WIDTH = 64,
// DMA RAM segment byte enable width
parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8,
// DMA RAM segment address width
parameter SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(SEG_COUNT*SEG_BE_WIDTH),
// DMA RAM pipeline stages
parameter RAM_PIPELINE = 2,
// Width of AXI stream interfaces in bits
parameter AXIS_DATA_WIDTH = 256,
// AXI stream tkeep signal width (words per cycle)
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
// AXI stream tid signal width
parameter AXIS_TX_ID_WIDTH = TX_QUEUE_INDEX_WIDTH,
// AXI stream tdest signal width
parameter AXIS_TX_DEST_WIDTH = $clog2(PORTS)+4,
// AXI stream tuser signal width
parameter AXIS_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
// Max transmit packet size
parameter MAX_TX_SIZE = 2048,
// DMA TX RAM size
parameter TX_RAM_SIZE = 8*MAX_TX_SIZE,
// Descriptor size (in bytes)
// Queue manager configuration (interface)
parameter TX_QUEUE_INDEX_WIDTH = 13,
parameter QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter CPL_QUEUE_INDEX_WIDTH = TX_CPL_QUEUE_INDEX_WIDTH,
parameter QUEUE_PTR_WIDTH = 16,
parameter LOG_QUEUE_SIZE_WIDTH = 4,
parameter LOG_BLOCK_SIZE_WIDTH = 2,
// Descriptor management
parameter TX_MAX_DESC_REQ = 16,
parameter TX_DESC_FIFO_SIZE = TX_MAX_DESC_REQ*8,
parameter DESC_SIZE = 16,
// Descriptor size (in bytes)
parameter CPL_SIZE = 32,
// Width of AXI stream descriptor interfaces in bits
parameter AXIS_DESC_DATA_WIDTH = DESC_SIZE*8,
// AXI stream descriptor tkeep signal width (words per cycle)
parameter AXIS_DESC_KEEP_WIDTH = AXIS_DESC_DATA_WIDTH/8
parameter AXIS_DESC_KEEP_WIDTH = AXIS_DESC_DATA_WIDTH/8,
parameter REQ_TAG_WIDTH = 8,
parameter DESC_REQ_TAG_WIDTH = 8,
parameter QUEUE_REQ_TAG_WIDTH = 8,
parameter QUEUE_OP_TAG_WIDTH = 8,
// TX and RX engine configuration (port)
parameter TX_DESC_TABLE_SIZE = 32,
parameter DESC_TABLE_DMA_OP_COUNT_WIDTH = 4,
// Timestamping configuration (port)
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214,
parameter TX_RAM_SIZE = 32768,
// DMA interface configuration
parameter DMA_ADDR_WIDTH = 64,
parameter DMA_LEN_WIDTH = 16,
parameter DMA_TAG_WIDTH = 16,
parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE),
parameter RAM_SEG_COUNT = 2,
parameter RAM_SEG_DATA_WIDTH = 256*2/RAM_SEG_COUNT,
parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8,
parameter RAM_SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH),
parameter RAM_PIPELINE = 2,
// Streaming interface configuration
parameter AXIS_DATA_WIDTH = 512*2**$clog2(PORTS),
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
parameter AXIS_TX_ID_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter AXIS_TX_DEST_WIDTH = $clog2(PORTS)+4,
parameter AXIS_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1
)
(
input wire clk,
input wire rst,
input wire clk,
input wire rst,
/*
* Transmit request input (queue index)
*/
input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_tx_req_queue,
input wire [REQ_TAG_WIDTH-1:0] s_axis_tx_req_tag,
input wire [AXIS_TX_DEST_WIDTH-1:0] s_axis_tx_req_dest,
input wire s_axis_tx_req_valid,
output wire s_axis_tx_req_ready,
input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_tx_req_queue,
input wire [REQ_TAG_WIDTH-1:0] s_axis_tx_req_tag,
input wire [AXIS_TX_DEST_WIDTH-1:0] s_axis_tx_req_dest,
input wire s_axis_tx_req_valid,
output wire s_axis_tx_req_ready,
/*
* Transmit request status output
*/
output wire [DMA_CLIENT_LEN_WIDTH-1:0] m_axis_tx_req_status_len,
output wire [REQ_TAG_WIDTH-1:0] m_axis_tx_req_status_tag,
output wire m_axis_tx_req_status_valid,
output wire [DMA_CLIENT_LEN_WIDTH-1:0] m_axis_tx_req_status_len,
output wire [REQ_TAG_WIDTH-1:0] m_axis_tx_req_status_tag,
output wire m_axis_tx_req_status_valid,
/*
* Descriptor request output
*/
output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_desc_req_queue,
output wire [DESC_REQ_TAG_WIDTH-1:0] m_axis_desc_req_tag,
output wire m_axis_desc_req_valid,
input wire m_axis_desc_req_ready,
output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_desc_req_queue,
output wire [DESC_REQ_TAG_WIDTH-1:0] m_axis_desc_req_tag,
output wire m_axis_desc_req_valid,
input wire m_axis_desc_req_ready,
/*
* Descriptor request status input
*/
input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_queue,
input wire [QUEUE_PTR_WIDTH-1:0] s_axis_desc_req_status_ptr,
input wire [CPL_QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_cpl,
input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_req_status_tag,
input wire s_axis_desc_req_status_empty,
input wire s_axis_desc_req_status_error,
input wire s_axis_desc_req_status_valid,
input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_queue,
input wire [QUEUE_PTR_WIDTH-1:0] s_axis_desc_req_status_ptr,
input wire [CPL_QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_cpl,
input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_req_status_tag,
input wire s_axis_desc_req_status_empty,
input wire s_axis_desc_req_status_error,
input wire s_axis_desc_req_status_valid,
/*
* Descriptor data input
*/
input wire [AXIS_DESC_DATA_WIDTH-1:0] s_axis_desc_tdata,
input wire [AXIS_DESC_KEEP_WIDTH-1:0] s_axis_desc_tkeep,
input wire s_axis_desc_tvalid,
output wire s_axis_desc_tready,
input wire s_axis_desc_tlast,
input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_tid,
input wire s_axis_desc_tuser,
input wire [AXIS_DESC_DATA_WIDTH-1:0] s_axis_desc_tdata,
input wire [AXIS_DESC_KEEP_WIDTH-1:0] s_axis_desc_tkeep,
input wire s_axis_desc_tvalid,
output wire s_axis_desc_tready,
input wire s_axis_desc_tlast,
input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_tid,
input wire s_axis_desc_tuser,
/*
* Completion request output
*/
output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue,
output wire [DESC_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag,
output wire [CPL_SIZE*8-1:0] m_axis_cpl_req_data,
output wire m_axis_cpl_req_valid,
input wire m_axis_cpl_req_ready,
output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue,
output wire [DESC_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag,
output wire [CPL_SIZE*8-1:0] m_axis_cpl_req_data,
output wire m_axis_cpl_req_valid,
input wire m_axis_cpl_req_ready,
/*
* Completion request status input
*/
input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_cpl_req_status_tag,
input wire s_axis_cpl_req_status_full,
input wire s_axis_cpl_req_status_error,
input wire s_axis_cpl_req_status_valid,
input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_cpl_req_status_tag,
input wire s_axis_cpl_req_status_full,
input wire s_axis_cpl_req_status_error,
input wire s_axis_cpl_req_status_valid,
/*
* DMA read descriptor output (data)
*/
output wire [DMA_ADDR_WIDTH-1:0] m_axis_dma_read_desc_dma_addr,
output wire [RAM_ADDR_WIDTH-1:0] m_axis_dma_read_desc_ram_addr,
output wire [DMA_LEN_WIDTH-1:0] m_axis_dma_read_desc_len,
output wire [DMA_TAG_WIDTH-1:0] m_axis_dma_read_desc_tag,
output wire m_axis_dma_read_desc_valid,
input wire m_axis_dma_read_desc_ready,
output wire [DMA_ADDR_WIDTH-1:0] m_axis_dma_read_desc_dma_addr,
output wire [RAM_ADDR_WIDTH-1:0] m_axis_dma_read_desc_ram_addr,
output wire [DMA_LEN_WIDTH-1:0] m_axis_dma_read_desc_len,
output wire [DMA_TAG_WIDTH-1:0] m_axis_dma_read_desc_tag,
output wire m_axis_dma_read_desc_valid,
input wire m_axis_dma_read_desc_ready,
/*
* DMA read descriptor status input (data)
*/
input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_read_desc_status_tag,
input wire [3:0] s_axis_dma_read_desc_status_error,
input wire s_axis_dma_read_desc_status_valid,
input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_read_desc_status_tag,
input wire [3:0] s_axis_dma_read_desc_status_error,
input wire s_axis_dma_read_desc_status_valid,
/*
* RAM interface (data)
*/
input wire [SEG_COUNT*SEG_BE_WIDTH-1:0] dma_ram_wr_cmd_be,
input wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_wr_cmd_addr,
input wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_wr_cmd_data,
input wire [SEG_COUNT-1:0] dma_ram_wr_cmd_valid,
output wire [SEG_COUNT-1:0] dma_ram_wr_cmd_ready,
output wire [SEG_COUNT-1:0] dma_ram_wr_done,
input wire [RAM_SEG_COUNT*RAM_SEG_BE_WIDTH-1:0] dma_ram_wr_cmd_be,
input wire [RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] dma_ram_wr_cmd_addr,
input wire [RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] dma_ram_wr_cmd_data,
input wire [RAM_SEG_COUNT-1:0] dma_ram_wr_cmd_valid,
output wire [RAM_SEG_COUNT-1:0] dma_ram_wr_cmd_ready,
output wire [RAM_SEG_COUNT-1:0] dma_ram_wr_done,
/*
* Transmit data output
*/
output wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata,
output wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep,
output wire tx_axis_tvalid,
input wire tx_axis_tready,
output wire tx_axis_tlast,
output wire [AXIS_TX_ID_WIDTH-1:0] tx_axis_tid,
output wire [AXIS_TX_DEST_WIDTH-1:0] tx_axis_tdest,
output wire [AXIS_TX_USER_WIDTH-1:0] tx_axis_tuser,
output wire [AXIS_DATA_WIDTH-1:0] m_axis_tx_tdata,
output wire [AXIS_KEEP_WIDTH-1:0] m_axis_tx_tkeep,
output wire m_axis_tx_tvalid,
input wire m_axis_tx_tready,
output wire m_axis_tx_tlast,
output wire [AXIS_TX_ID_WIDTH-1:0] m_axis_tx_tid,
output wire [AXIS_TX_DEST_WIDTH-1:0] m_axis_tx_tdest,
output wire [AXIS_TX_USER_WIDTH-1:0] m_axis_tx_tuser,
/*
* Transmit timestamp input
*/
input wire [PTP_TS_WIDTH-1:0] s_axis_tx_ptp_ts,
input wire [PTP_TAG_WIDTH-1:0] s_axis_tx_ptp_ts_tag,
input wire s_axis_tx_ptp_ts_valid,
output wire s_axis_tx_ptp_ts_ready,
/*
* PTP clock
*/
input wire [95:0] ptp_ts_96,
input wire ptp_ts_step,
input wire [PTP_TS_WIDTH-1:0] s_axis_tx_ptp_ts,
input wire [PTP_TAG_WIDTH-1:0] s_axis_tx_ptp_ts_tag,
input wire s_axis_tx_ptp_ts_valid,
output wire s_axis_tx_ptp_ts_ready,
/*
* Configuration
*/
input wire [DMA_CLIENT_LEN_WIDTH-1:0] mtu
input wire [DMA_CLIENT_LEN_WIDTH-1:0] mtu
);
parameter DMA_CLIENT_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE);
@ -348,7 +313,7 @@ tx_engine #(
.MAX_TX_SIZE(MAX_TX_SIZE),
.TX_BUFFER_OFFSET(0),
.TX_BUFFER_SIZE(TX_RAM_SIZE),
.TX_BUFFER_STEP_SIZE(SEG_COUNT*SEG_BE_WIDTH),
.TX_BUFFER_STEP_SIZE(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH),
.DESC_SIZE(DESC_SIZE),
.CPL_SIZE(CPL_SIZE),
.MAX_DESC_REQ(TX_MAX_DESC_REQ),
@ -488,19 +453,19 @@ tx_engine_inst (
.enable(1'b1)
);
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_rd_cmd_addr_int;
wire [SEG_COUNT-1:0] dma_ram_rd_cmd_valid_int;
wire [SEG_COUNT-1:0] dma_ram_rd_cmd_ready_int;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data_int;
wire [SEG_COUNT-1:0] dma_ram_rd_resp_valid_int;
wire [SEG_COUNT-1:0] dma_ram_rd_resp_ready_int;
wire [RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] dma_ram_rd_cmd_addr_int;
wire [RAM_SEG_COUNT-1:0] dma_ram_rd_cmd_valid_int;
wire [RAM_SEG_COUNT-1:0] dma_ram_rd_cmd_ready_int;
wire [RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data_int;
wire [RAM_SEG_COUNT-1:0] dma_ram_rd_resp_valid_int;
wire [RAM_SEG_COUNT-1:0] dma_ram_rd_resp_ready_int;
dma_psdpram #(
.SIZE(TX_RAM_SIZE),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_COUNT(RAM_SEG_COUNT),
.SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH),
.SEG_BE_WIDTH(RAM_SEG_BE_WIDTH),
.SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH),
.PIPELINE(RAM_PIPELINE)
)
dma_psdpram_tx_inst (
@ -539,10 +504,10 @@ wire [AXIS_TX_USER_WIDTH-1:0] tx_axis_tuser_int;
dma_client_axis_source #(
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.SEG_COUNT(RAM_SEG_COUNT),
.SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(RAM_SEG_BE_WIDTH),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_ENABLE(AXIS_KEEP_WIDTH > 1),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
@ -635,14 +600,14 @@ egress_inst (
/*
* Transmit data output
*/
.m_axis_tdata(tx_axis_tdata),
.m_axis_tkeep(tx_axis_tkeep),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tid(tx_axis_tid),
.m_axis_tdest(tx_axis_tdest),
.m_axis_tuser(tx_axis_tuser),
.m_axis_tdata(m_axis_tx_tdata),
.m_axis_tkeep(m_axis_tx_tkeep),
.m_axis_tvalid(m_axis_tx_tvalid),
.m_axis_tready(m_axis_tx_tready),
.m_axis_tlast(m_axis_tx_tlast),
.m_axis_tid(m_axis_tx_tid),
.m_axis_tdest(m_axis_tx_tdest),
.m_axis_tuser(m_axis_tx_tuser),
/*
* Transmit checksum command

363
fpga/common/rtl/mqnic_port_rx.v Normal file
View File

@ -0,0 +1,363 @@
/*
Copyright 2022, The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
The views and conclusions contained in the software and documentation are those
of the authors and should not be interpreted as representing official policies,
either expressed or implied, of The Regents of the University of California.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* NIC port RX path
*/
module mqnic_port_rx #
(
// PTP configuration
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_WIDTH = 16,
// Timestamping configuration (port)
parameter PTP_TS_ENABLE = 1,
// Interface configuration (port)
parameter MAX_RX_SIZE = 9214,
// Application block configuration
parameter APP_AXIS_DIRECT_ENABLE = 1,
parameter APP_AXIS_SYNC_ENABLE = 1,
// Streaming interface configuration
parameter AXIS_DATA_WIDTH = 256,
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
parameter AXIS_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_RX_USE_READY = 0,
parameter AXIS_RX_PIPELINE = 0,
parameter AXIS_RX_FIFO_PIPELINE = 2,
parameter AXIS_SYNC_DATA_WIDTH = AXIS_DATA_WIDTH,
parameter AXIS_SYNC_KEEP_WIDTH = AXIS_SYNC_DATA_WIDTH/8,
parameter AXIS_SYNC_RX_USER_WIDTH = AXIS_RX_USER_WIDTH
)
(
input wire clk,
input wire rst,
/*
* Receive data to interface FIFO
*/
output wire [AXIS_SYNC_DATA_WIDTH-1:0] m_axis_if_rx_tdata,
output wire [AXIS_SYNC_KEEP_WIDTH-1:0] m_axis_if_rx_tkeep,
output wire m_axis_if_rx_tvalid,
input wire m_axis_if_rx_tready,
output wire m_axis_if_rx_tlast,
output wire [AXIS_SYNC_RX_USER_WIDTH-1:0] m_axis_if_rx_tuser,
/*
* Application section datapath interface (synchronous MAC interface)
*/
output wire [AXIS_SYNC_DATA_WIDTH-1:0] m_axis_app_sync_rx_tdata,
output wire [AXIS_SYNC_KEEP_WIDTH-1:0] m_axis_app_sync_rx_tkeep,
output wire m_axis_app_sync_rx_tvalid,
input wire m_axis_app_sync_rx_tready,
output wire m_axis_app_sync_rx_tlast,
output wire [AXIS_SYNC_RX_USER_WIDTH-1:0] m_axis_app_sync_rx_tuser,
input wire [AXIS_SYNC_DATA_WIDTH-1:0] s_axis_app_sync_rx_tdata,
input wire [AXIS_SYNC_KEEP_WIDTH-1:0] s_axis_app_sync_rx_tkeep,
input wire s_axis_app_sync_rx_tvalid,
output wire s_axis_app_sync_rx_tready,
input wire s_axis_app_sync_rx_tlast,
input wire [AXIS_SYNC_RX_USER_WIDTH-1:0] s_axis_app_sync_rx_tuser,
/*
* Application section datapath interface (direct MAC interface)
*/
output wire [AXIS_DATA_WIDTH-1:0] m_axis_app_direct_rx_tdata,
output wire [AXIS_KEEP_WIDTH-1:0] m_axis_app_direct_rx_tkeep,
output wire m_axis_app_direct_rx_tvalid,
input wire m_axis_app_direct_rx_tready,
output wire m_axis_app_direct_rx_tlast,
output wire [AXIS_RX_USER_WIDTH-1:0] m_axis_app_direct_rx_tuser,
input wire [AXIS_DATA_WIDTH-1:0] s_axis_app_direct_rx_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] s_axis_app_direct_rx_tkeep,
input wire s_axis_app_direct_rx_tvalid,
output wire s_axis_app_direct_rx_tready,
input wire s_axis_app_direct_rx_tlast,
input wire [AXIS_RX_USER_WIDTH-1:0] s_axis_app_direct_rx_tuser,
/*
* Receive data input
*/
input wire rx_clk,
input wire rx_rst,
input wire [AXIS_DATA_WIDTH-1:0] s_axis_rx_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] s_axis_rx_tkeep,
input wire s_axis_rx_tvalid,
output wire s_axis_rx_tready,
input wire s_axis_rx_tlast,
input wire [AXIS_RX_USER_WIDTH-1:0] s_axis_rx_tuser
);
generate
// RX FIFOs
wire [AXIS_DATA_WIDTH-1:0] axis_rx_l2_tdata;
wire [AXIS_KEEP_WIDTH-1:0] axis_rx_l2_tkeep;
wire axis_rx_l2_tvalid;
wire axis_rx_l2_tready;
wire axis_rx_l2_tlast;
wire [AXIS_RX_USER_WIDTH-1:0] axis_rx_l2_tuser;
wire [AXIS_DATA_WIDTH-1:0] axis_rx_in_tdata;
wire [AXIS_KEEP_WIDTH-1:0] axis_rx_in_tkeep;
wire axis_rx_in_tvalid;
wire axis_rx_in_tready;
wire axis_rx_in_tlast;
wire [AXIS_RX_USER_WIDTH-1:0] axis_rx_in_tuser;
wire [AXIS_SYNC_DATA_WIDTH-1:0] axis_rx_async_fifo_tdata;
wire [AXIS_SYNC_KEEP_WIDTH-1:0] axis_rx_async_fifo_tkeep;
wire axis_rx_async_fifo_tvalid;
wire axis_rx_async_fifo_tready;
wire axis_rx_async_fifo_tlast;
wire [AXIS_RX_USER_WIDTH-1:0] axis_rx_async_fifo_tuser;
wire [AXIS_SYNC_DATA_WIDTH-1:0] axis_rx_pipe_tdata;
wire [AXIS_SYNC_KEEP_WIDTH-1:0] axis_rx_pipe_tkeep;
wire axis_rx_pipe_tvalid;
wire axis_rx_pipe_tready;
wire axis_rx_pipe_tlast;
wire [AXIS_RX_USER_WIDTH-1:0] axis_rx_pipe_tuser;
wire [AXIS_SYNC_DATA_WIDTH-1:0] axis_if_rx_tdata;
wire [AXIS_SYNC_KEEP_WIDTH-1:0] axis_if_rx_tkeep;
wire axis_if_rx_tvalid;
wire axis_if_rx_tready;
wire axis_if_rx_tlast;
wire [AXIS_RX_USER_WIDTH-1:0] axis_if_rx_tuser;
mqnic_l2_ingress #(
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.AXIS_USER_WIDTH(AXIS_RX_USER_WIDTH),
.AXIS_USE_READY(AXIS_RX_USE_READY)
)
mqnic_l2_ingress_inst (
.clk(rx_clk),
.rst(rx_rst),
/*
* Receive data input
*/
.s_axis_tdata(s_axis_rx_tdata),
.s_axis_tkeep(s_axis_rx_tkeep),
.s_axis_tvalid(s_axis_rx_tvalid),
.s_axis_tready(s_axis_rx_tready),
.s_axis_tlast(s_axis_rx_tlast),
.s_axis_tuser(s_axis_rx_tuser),
/*
* Receive data output
*/
.m_axis_tdata(axis_rx_l2_tdata),
.m_axis_tkeep(axis_rx_l2_tkeep),
.m_axis_tvalid(axis_rx_l2_tvalid),
.m_axis_tready(axis_rx_l2_tready),
.m_axis_tlast(axis_rx_l2_tlast),
.m_axis_tuser(axis_rx_l2_tuser)
);
if (APP_AXIS_DIRECT_ENABLE) begin
assign m_axis_app_direct_rx_tdata = axis_rx_l2_tdata;
assign m_axis_app_direct_rx_tkeep = axis_rx_l2_tkeep;
assign m_axis_app_direct_rx_tvalid = axis_rx_l2_tvalid;
assign axis_rx_l2_tready = m_axis_app_direct_rx_tready;
assign m_axis_app_direct_rx_tlast = axis_rx_l2_tlast;
assign m_axis_app_direct_rx_tuser = axis_rx_l2_tuser;
assign axis_rx_in_tdata = s_axis_app_direct_rx_tdata;
assign axis_rx_in_tkeep = s_axis_app_direct_rx_tkeep;
assign axis_rx_in_tvalid = s_axis_app_direct_rx_tvalid;
assign s_axis_app_direct_rx_tready = axis_rx_in_tready;
assign axis_rx_in_tlast = s_axis_app_direct_rx_tlast;
assign axis_rx_in_tuser = s_axis_app_direct_rx_tuser;
end else begin
assign m_axis_app_direct_rx_tdata = 0;
assign m_axis_app_direct_rx_tkeep = 0;
assign m_axis_app_direct_rx_tvalid = 0;
assign m_axis_app_direct_rx_tlast = 0;
assign m_axis_app_direct_rx_tuser = 0;
assign s_axis_app_direct_rx_tready = 0;
assign axis_rx_in_tdata = axis_rx_l2_tdata;
assign axis_rx_in_tkeep = axis_rx_l2_tkeep;
assign axis_rx_in_tvalid = axis_rx_l2_tvalid;
assign axis_rx_l2_tready = axis_rx_in_tready;
assign axis_rx_in_tlast = axis_rx_l2_tlast;
assign axis_rx_in_tuser = axis_rx_l2_tuser;
end
axis_async_fifo_adapter #(
.DEPTH(MAX_RX_SIZE),
.S_DATA_WIDTH(AXIS_DATA_WIDTH),
.S_KEEP_ENABLE(AXIS_KEEP_WIDTH > 1),
.S_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.M_DATA_WIDTH(AXIS_SYNC_DATA_WIDTH),
.M_KEEP_ENABLE(AXIS_SYNC_KEEP_WIDTH > 1),
.M_KEEP_WIDTH(AXIS_SYNC_KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_RX_USER_WIDTH),
.FRAME_FIFO(1),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(1),
.DROP_WHEN_FULL(!AXIS_RX_USE_READY)
)
rx_async_fifo_inst (
// AXI input
.s_clk(rx_clk),
.s_rst(rx_rst),
.s_axis_tdata(axis_rx_in_tdata),
.s_axis_tkeep(axis_rx_in_tkeep),
.s_axis_tvalid(axis_rx_in_tvalid),
.s_axis_tready(axis_rx_in_tready),
.s_axis_tlast(axis_rx_in_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(axis_rx_in_tuser),
// AXI output
.m_clk(clk),
.m_rst(rst),
.m_axis_tdata(axis_rx_async_fifo_tdata),
.m_axis_tkeep(axis_rx_async_fifo_tkeep),
.m_axis_tvalid(axis_rx_async_fifo_tvalid),
.m_axis_tready(axis_rx_async_fifo_tready),
.m_axis_tlast(axis_rx_async_fifo_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(axis_rx_async_fifo_tuser),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
axis_pipeline_fifo #(
.DATA_WIDTH(AXIS_SYNC_DATA_WIDTH),
.KEEP_ENABLE(AXIS_SYNC_KEEP_WIDTH > 1),
.KEEP_WIDTH(AXIS_SYNC_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_RX_USER_WIDTH),
.LENGTH(AXIS_RX_PIPELINE)
)
rx_pipeline_fifo_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(axis_rx_async_fifo_tdata),
.s_axis_tkeep(axis_rx_async_fifo_tkeep),
.s_axis_tvalid(axis_rx_async_fifo_tvalid),
.s_axis_tready(axis_rx_async_fifo_tready),
.s_axis_tlast(axis_rx_async_fifo_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(axis_rx_async_fifo_tuser),
// AXI output
.m_axis_tdata(axis_rx_pipe_tdata),
.m_axis_tkeep(axis_rx_pipe_tkeep),
.m_axis_tvalid(axis_rx_pipe_tvalid),
.m_axis_tready(axis_rx_pipe_tready),
.m_axis_tlast(axis_rx_pipe_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(axis_rx_pipe_tuser)
);
if (APP_AXIS_SYNC_ENABLE) begin
assign m_axis_app_sync_rx_tdata = axis_rx_pipe_tdata;
assign m_axis_app_sync_rx_tkeep = axis_rx_pipe_tkeep;
assign m_axis_app_sync_rx_tvalid = axis_rx_pipe_tvalid;
assign axis_rx_pipe_tready = m_axis_app_sync_rx_tready;
assign m_axis_app_sync_rx_tlast = axis_rx_pipe_tlast;
assign m_axis_app_sync_rx_tuser = axis_rx_pipe_tuser;
assign m_axis_if_rx_tdata = s_axis_app_sync_rx_tdata;
assign m_axis_if_rx_tkeep = s_axis_app_sync_rx_tkeep;
assign m_axis_if_rx_tvalid = s_axis_app_sync_rx_tvalid;
assign s_axis_app_sync_rx_tready = m_axis_if_rx_tready;
assign m_axis_if_rx_tlast = s_axis_app_sync_rx_tlast;
assign m_axis_if_rx_tuser = s_axis_app_sync_rx_tuser;
end else begin
assign m_axis_app_sync_rx_tdata = 0;
assign m_axis_app_sync_rx_tkeep = 0;
assign m_axis_app_sync_rx_tvalid = 0;
assign m_axis_app_sync_rx_tlast = 0;
assign m_axis_app_sync_rx_tuser = 0;
assign s_axis_app_sync_rx_tready = 0;
assign m_axis_if_rx_tdata = axis_rx_pipe_tdata;
assign m_axis_if_rx_tkeep = axis_rx_pipe_tkeep;
assign m_axis_if_rx_tvalid = axis_rx_pipe_tvalid;
assign axis_rx_pipe_tready = m_axis_if_rx_tready;
assign m_axis_if_rx_tlast = axis_rx_pipe_tlast;
assign m_axis_if_rx_tuser = axis_rx_pipe_tuser;
end
endgenerate
endmodule
`resetall

558
fpga/common/rtl/mqnic_port_tx.v Normal file
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@ -0,0 +1,558 @@
/*
Copyright 2022, The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
The views and conclusions contained in the software and documentation are those
of the authors and should not be interpreted as representing official policies,
either expressed or implied, of The Regents of the University of California.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* NIC port TX path
*/
module mqnic_port_tx #
(
// PTP configuration
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_WIDTH = 16,
// Timestamping configuration (port)
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter MAX_TX_SIZE = 9214,
// Application block configuration
parameter APP_AXIS_DIRECT_ENABLE = 1,
parameter APP_AXIS_SYNC_ENABLE = 1,
// Streaming interface configuration
parameter AXIS_DATA_WIDTH = 256,
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
parameter AXIS_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter AXIS_TX_PIPELINE = 0,
parameter AXIS_TX_FIFO_PIPELINE = 2,
parameter AXIS_TX_TS_PIPELINE = 0,
parameter AXIS_SYNC_DATA_WIDTH = AXIS_DATA_WIDTH,
parameter AXIS_SYNC_KEEP_WIDTH = AXIS_SYNC_DATA_WIDTH/8,
parameter AXIS_SYNC_TX_USER_WIDTH = AXIS_TX_USER_WIDTH
)
(
input wire clk,
input wire rst,
/*
* Transmit data from interface FIFO
*/
input wire [AXIS_SYNC_DATA_WIDTH-1:0] s_axis_if_tx_tdata,
input wire [AXIS_SYNC_KEEP_WIDTH-1:0] s_axis_if_tx_tkeep,
input wire s_axis_if_tx_tvalid,
output wire s_axis_if_tx_tready,
input wire s_axis_if_tx_tlast,
input wire [AXIS_SYNC_TX_USER_WIDTH-1:0] s_axis_if_tx_tuser,
output wire [PTP_TS_WIDTH-1:0] m_axis_if_tx_ptp_ts,
output wire [PTP_TAG_WIDTH-1:0] m_axis_if_tx_ptp_ts_tag,
output wire m_axis_if_tx_ptp_ts_valid,
input wire m_axis_if_tx_ptp_ts_ready,
/*
* Application section datapath interface (synchronous MAC interface)
*/
output wire [AXIS_SYNC_DATA_WIDTH-1:0] m_axis_app_sync_tx_tdata,
output wire [AXIS_SYNC_KEEP_WIDTH-1:0] m_axis_app_sync_tx_tkeep,
output wire m_axis_app_sync_tx_tvalid,
input wire m_axis_app_sync_tx_tready,
output wire m_axis_app_sync_tx_tlast,
output wire [AXIS_SYNC_TX_USER_WIDTH-1:0] m_axis_app_sync_tx_tuser,
input wire [AXIS_SYNC_DATA_WIDTH-1:0] s_axis_app_sync_tx_tdata,
input wire [AXIS_SYNC_KEEP_WIDTH-1:0] s_axis_app_sync_tx_tkeep,
input wire s_axis_app_sync_tx_tvalid,
output wire s_axis_app_sync_tx_tready,
input wire s_axis_app_sync_tx_tlast,
input wire [AXIS_SYNC_TX_USER_WIDTH-1:0] s_axis_app_sync_tx_tuser,
output wire [PTP_TS_WIDTH-1:0] m_axis_app_sync_tx_ptp_ts,
output wire [PTP_TAG_WIDTH-1:0] m_axis_app_sync_tx_ptp_ts_tag,
output wire m_axis_app_sync_tx_ptp_ts_valid,
input wire m_axis_app_sync_tx_ptp_ts_ready,
input wire [PTP_TS_WIDTH-1:0] s_axis_app_sync_tx_ptp_ts,
input wire [PTP_TAG_WIDTH-1:0] s_axis_app_sync_tx_ptp_ts_tag,
input wire s_axis_app_sync_tx_ptp_ts_valid,
output wire s_axis_app_sync_tx_ptp_ts_ready,
/*
* Application section datapath interface (direct MAC interface)
*/
output wire [AXIS_DATA_WIDTH-1:0] m_axis_app_direct_tx_tdata,
output wire [AXIS_KEEP_WIDTH-1:0] m_axis_app_direct_tx_tkeep,
output wire m_axis_app_direct_tx_tvalid,
input wire m_axis_app_direct_tx_tready,
output wire m_axis_app_direct_tx_tlast,
output wire [AXIS_TX_USER_WIDTH-1:0] m_axis_app_direct_tx_tuser,
input wire [AXIS_DATA_WIDTH-1:0] s_axis_app_direct_tx_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] s_axis_app_direct_tx_tkeep,
input wire s_axis_app_direct_tx_tvalid,
output wire s_axis_app_direct_tx_tready,
input wire s_axis_app_direct_tx_tlast,
input wire [AXIS_TX_USER_WIDTH-1:0] s_axis_app_direct_tx_tuser,
output wire [PTP_TS_WIDTH-1:0] m_axis_app_direct_tx_ptp_ts,
output wire [PTP_TAG_WIDTH-1:0] m_axis_app_direct_tx_ptp_ts_tag,
output wire m_axis_app_direct_tx_ptp_ts_valid,
input wire m_axis_app_direct_tx_ptp_ts_ready,
input wire [PTP_TS_WIDTH-1:0] s_axis_app_direct_tx_ptp_ts,
input wire [PTP_TAG_WIDTH-1:0] s_axis_app_direct_tx_ptp_ts_tag,
input wire s_axis_app_direct_tx_ptp_ts_valid,
output wire s_axis_app_direct_tx_ptp_ts_ready,
/*
* Transmit data output
*/
input wire tx_clk,
input wire tx_rst,
output wire [AXIS_DATA_WIDTH-1:0] m_axis_tx_tdata,
output wire [AXIS_KEEP_WIDTH-1:0] m_axis_tx_tkeep,
output wire m_axis_tx_tvalid,
input wire m_axis_tx_tready,
output wire m_axis_tx_tlast,
output wire [AXIS_TX_USER_WIDTH-1:0] m_axis_tx_tuser,
input wire [PTP_TS_WIDTH-1:0] s_axis_tx_ptp_ts,
input wire [PTP_TAG_WIDTH-1:0] s_axis_tx_ptp_ts_tag,
input wire s_axis_tx_ptp_ts_valid,
output wire s_axis_tx_ptp_ts_ready
);
generate
if (PTP_TS_ENABLE) begin: ptp
// PTP TS FIFO (TX)
wire [PTP_TS_WIDTH-1:0] axis_tx_in_ptp_ts;
wire [PTP_TAG_WIDTH-1:0] axis_tx_in_ptp_ts_tag;
wire axis_tx_in_ptp_ts_valid;
wire axis_tx_in_ptp_ts_ready;
wire [PTP_TS_WIDTH-1:0] axis_tx_fifo_ptp_ts;
wire [PTP_TAG_WIDTH-1:0] axis_tx_fifo_ptp_ts_tag;
wire axis_tx_fifo_ptp_ts_valid;
wire axis_tx_fifo_ptp_ts_ready;
wire [PTP_TS_WIDTH-1:0] axis_tx_pipe_ptp_ts;
wire [PTP_TAG_WIDTH-1:0] axis_tx_pipe_ptp_ts_tag;
wire axis_tx_pipe_ptp_ts_valid;
wire axis_tx_pipe_ptp_ts_ready;
if (APP_AXIS_DIRECT_ENABLE) begin
assign m_axis_app_direct_tx_ptp_ts = s_axis_tx_ptp_ts;
assign m_axis_app_direct_tx_ptp_ts_tag = s_axis_tx_ptp_ts_tag;
assign m_axis_app_direct_tx_ptp_ts_valid = s_axis_tx_ptp_ts_valid;
assign s_axis_tx_ptp_ts_ready = m_axis_app_direct_tx_ptp_ts_ready;
assign axis_tx_in_ptp_ts = s_axis_app_direct_tx_ptp_ts;
assign axis_tx_in_ptp_ts_tag = s_axis_app_direct_tx_ptp_ts_tag;
assign axis_tx_in_ptp_ts_valid = s_axis_app_direct_tx_ptp_ts_valid;
assign s_axis_app_direct_tx_ptp_ts_ready = axis_tx_in_ptp_ts_ready;
end else begin
assign m_axis_app_direct_tx_ptp_ts = 0;
assign m_axis_app_direct_tx_ptp_ts_tag = 0;
assign m_axis_app_direct_tx_ptp_ts_valid = 0;
assign s_axis_app_direct_tx_ptp_ts_ready = 0;
assign axis_tx_in_ptp_ts = s_axis_tx_ptp_ts;
assign axis_tx_in_ptp_ts_tag = s_axis_tx_ptp_ts_tag;
assign axis_tx_in_ptp_ts_valid = s_axis_tx_ptp_ts_valid;
assign s_axis_tx_ptp_ts_ready = axis_tx_in_ptp_ts_ready;
end
axis_async_fifo #(
.DEPTH(TX_PTP_TS_FIFO_DEPTH),
.DATA_WIDTH(PTP_TS_WIDTH),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),
.ID_ENABLE(1),
.ID_WIDTH(PTP_TAG_WIDTH),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.FRAME_FIFO(0)
)
tx_ptp_ts_fifo_inst (
// AXI input
.s_clk(tx_clk),
.s_rst(tx_rst),
.s_axis_tdata(axis_tx_in_ptp_ts),
.s_axis_tkeep(0),
.s_axis_tvalid(axis_tx_in_ptp_ts_valid),
.s_axis_tready(axis_tx_in_ptp_ts_ready),
.s_axis_tlast(0),
.s_axis_tid(axis_tx_in_ptp_ts_tag),
.s_axis_tdest(0),
.s_axis_tuser(0),
// AXI output
.m_clk(clk),
.m_rst(rst),
.m_axis_tdata(axis_tx_fifo_ptp_ts),
.m_axis_tkeep(),
.m_axis_tvalid(axis_tx_fifo_ptp_ts_valid),
.m_axis_tready(axis_tx_fifo_ptp_ts_ready),
.m_axis_tlast(),
.m_axis_tid(axis_tx_fifo_ptp_ts_tag),
.m_axis_tdest(),
.m_axis_tuser(),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
axis_pipeline_fifo #(
.DATA_WIDTH(PTP_TS_WIDTH),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),
.ID_ENABLE(1),
.ID_WIDTH(PTP_TAG_WIDTH),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.LENGTH(AXIS_TX_TS_PIPELINE)
)
tx_ptp_ts_pipeline_fifo_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(axis_tx_fifo_ptp_ts),
.s_axis_tkeep(0),
.s_axis_tvalid(axis_tx_fifo_ptp_ts_valid),
.s_axis_tready(axis_tx_fifo_ptp_ts_ready),
.s_axis_tlast(0),
.s_axis_tid(axis_tx_fifo_ptp_ts_tag),
.s_axis_tdest(0),
.s_axis_tuser(0),
// AXI output
.m_axis_tdata(axis_tx_pipe_ptp_ts),
.m_axis_tkeep(),
.m_axis_tvalid(axis_tx_pipe_ptp_ts_valid),
.m_axis_tready(axis_tx_pipe_ptp_ts_ready),
.m_axis_tlast(),
.m_axis_tid(axis_tx_pipe_ptp_ts_tag),
.m_axis_tdest(),
.m_axis_tuser()
);
if (APP_AXIS_SYNC_ENABLE) begin
assign m_axis_app_sync_tx_ptp_ts = axis_tx_pipe_ptp_ts;
assign m_axis_app_sync_tx_ptp_ts_tag = axis_tx_pipe_ptp_ts_tag;
assign m_axis_app_sync_tx_ptp_ts_valid = axis_tx_pipe_ptp_ts_valid;
assign axis_tx_pipe_ptp_ts_ready = m_axis_app_sync_tx_ptp_ts_ready;
assign m_axis_if_tx_ptp_ts = s_axis_app_sync_tx_ptp_ts;
assign m_axis_if_tx_ptp_ts_tag = s_axis_app_sync_tx_ptp_ts_tag;
assign m_axis_if_tx_ptp_ts_valid = s_axis_app_sync_tx_ptp_ts_valid;
assign s_axis_app_sync_tx_ptp_ts_ready = m_axis_if_tx_ptp_ts_ready;
end else begin
assign m_axis_app_sync_tx_ptp_ts = 0;
assign m_axis_app_sync_tx_ptp_ts_tag = 0;
assign m_axis_app_sync_tx_ptp_ts_valid = 0;
assign s_axis_app_sync_tx_ptp_ts_ready = 0;
assign m_axis_if_tx_ptp_ts = axis_tx_pipe_ptp_ts;
assign m_axis_if_tx_ptp_ts_tag = axis_tx_pipe_ptp_ts_tag;
assign m_axis_if_tx_ptp_ts_valid = axis_tx_pipe_ptp_ts_valid;
assign axis_tx_pipe_ptp_ts_ready = m_axis_if_tx_ptp_ts_ready;
end
end else begin
assign m_axis_app_direct_tx_ptp_ts = 0;
assign m_axis_app_direct_tx_ptp_ts_tag = 0;
assign m_axis_app_direct_tx_ptp_ts_valid = 0;
assign s_axis_app_direct_tx_ptp_ts_ready = 0;
assign m_axis_app_sync_tx_ptp_ts = 0;
assign m_axis_app_sync_tx_ptp_ts_tag = 0;
assign m_axis_app_sync_tx_ptp_ts_valid = 0;
assign s_axis_app_sync_tx_ptp_ts_ready = 0;
assign m_axis_if_tx_ptp_ts = 0;
assign m_axis_if_tx_ptp_ts_tag = 0;
assign m_axis_if_tx_ptp_ts_valid[m] = 0;
end
// TX FIFOs
wire [AXIS_SYNC_DATA_WIDTH-1:0] axis_tx_pipe_tdata;
wire [AXIS_SYNC_KEEP_WIDTH-1:0] axis_tx_pipe_tkeep;
wire axis_tx_pipe_tvalid;
wire axis_tx_pipe_tready;
wire axis_tx_pipe_tlast;
wire [AXIS_TX_USER_WIDTH-1:0] axis_tx_pipe_tuser;
wire [AXIS_SYNC_DATA_WIDTH-1:0] axis_tx_async_fifo_tdata;
wire [AXIS_SYNC_KEEP_WIDTH-1:0] axis_tx_async_fifo_tkeep;
wire axis_tx_async_fifo_tvalid;
wire axis_tx_async_fifo_tready;
wire axis_tx_async_fifo_tlast;
wire [AXIS_TX_USER_WIDTH-1:0] axis_tx_async_fifo_tuser;
wire [AXIS_DATA_WIDTH-1:0] axis_tx_out_tdata;
wire [AXIS_KEEP_WIDTH-1:0] axis_tx_out_tkeep;
wire axis_tx_out_tvalid;
wire axis_tx_out_tready;
wire axis_tx_out_tlast;
wire [AXIS_TX_USER_WIDTH-1:0] axis_tx_out_tuser;
wire [AXIS_DATA_WIDTH-1:0] axis_tx_l2_tdata;
wire [AXIS_KEEP_WIDTH-1:0] axis_tx_l2_tkeep;
wire axis_tx_l2_tvalid;
wire axis_tx_l2_tready;
wire axis_tx_l2_tlast;
wire [AXIS_TX_USER_WIDTH-1:0] axis_tx_l2_tuser;
if (APP_AXIS_SYNC_ENABLE) begin
assign m_axis_app_sync_tx_tdata = s_axis_if_tx_tdata;
assign m_axis_app_sync_tx_tkeep = s_axis_if_tx_tkeep;
assign m_axis_app_sync_tx_tvalid = s_axis_if_tx_tvalid;
assign s_axis_if_tx_tready = m_axis_app_sync_tx_tready;
assign m_axis_app_sync_tx_tlast = s_axis_if_tx_tlast;
assign m_axis_app_sync_tx_tuser = s_axis_if_tx_tuser;
assign axis_tx_pipe_tdata = s_axis_app_sync_tx_tdata;
assign axis_tx_pipe_tkeep = s_axis_app_sync_tx_tkeep;
assign axis_tx_pipe_tvalid = s_axis_app_sync_tx_tvalid;
assign s_axis_app_sync_tx_tready = axis_tx_pipe_tready;
assign axis_tx_pipe_tlast = s_axis_app_sync_tx_tlast;
assign axis_tx_pipe_tuser = s_axis_app_sync_tx_tuser;
end else begin
assign m_axis_app_sync_tx_tdata = 0;
assign m_axis_app_sync_tx_tkeep = 0;
assign m_axis_app_sync_tx_tvalid = 0;
assign m_axis_app_sync_tx_tlast = 0;
assign m_axis_app_sync_tx_tuser = 0;
assign s_axis_app_sync_tx_tready = 0;
assign axis_tx_pipe_tdata = s_axis_if_tx_tdata;
assign axis_tx_pipe_tkeep = s_axis_if_tx_tkeep;
assign axis_tx_pipe_tvalid = s_axis_if_tx_tvalid;
assign s_axis_if_tx_tready = axis_tx_pipe_tready;
assign axis_tx_pipe_tlast = s_axis_if_tx_tlast;
assign axis_tx_pipe_tuser = s_axis_if_tx_tuser;
end
axis_pipeline_fifo #(
.DATA_WIDTH(AXIS_SYNC_DATA_WIDTH),
.KEEP_ENABLE(AXIS_SYNC_KEEP_WIDTH > 1),
.KEEP_WIDTH(AXIS_SYNC_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_TX_USER_WIDTH),
.LENGTH(AXIS_TX_PIPELINE)
)
tx_pipeline_fifo_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(axis_tx_pipe_tdata),
.s_axis_tkeep(axis_tx_pipe_tkeep),
.s_axis_tvalid(axis_tx_pipe_tvalid),
.s_axis_tready(axis_tx_pipe_tready),
.s_axis_tlast(axis_tx_pipe_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(axis_tx_pipe_tuser),
// AXI output
.m_axis_tdata(axis_tx_async_fifo_tdata),
.m_axis_tkeep(axis_tx_async_fifo_tkeep),
.m_axis_tvalid(axis_tx_async_fifo_tvalid),
.m_axis_tready(axis_tx_async_fifo_tready),
.m_axis_tlast(axis_tx_async_fifo_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(axis_tx_async_fifo_tuser)
);
axis_async_fifo_adapter #(
.DEPTH(MAX_TX_SIZE),
.S_DATA_WIDTH(AXIS_SYNC_DATA_WIDTH),
.S_KEEP_ENABLE(AXIS_SYNC_KEEP_WIDTH > 1),
.S_KEEP_WIDTH(AXIS_SYNC_KEEP_WIDTH),
.M_DATA_WIDTH(AXIS_DATA_WIDTH),
.M_KEEP_ENABLE(AXIS_KEEP_WIDTH > 1),
.M_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_TX_USER_WIDTH),
.FRAME_FIFO(1),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(1),
.DROP_WHEN_FULL(0)
)
tx_async_fifo_inst (
// AXI input
.s_clk(clk),
.s_rst(rst),
.s_axis_tdata(axis_tx_async_fifo_tdata),
.s_axis_tkeep(axis_tx_async_fifo_tkeep),
.s_axis_tvalid(axis_tx_async_fifo_tvalid),
.s_axis_tready(axis_tx_async_fifo_tready),
.s_axis_tlast(axis_tx_async_fifo_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(axis_tx_async_fifo_tuser),
// AXI output
.m_clk(tx_clk),
.m_rst(tx_rst),
.m_axis_tdata(axis_tx_out_tdata),
.m_axis_tkeep(axis_tx_out_tkeep),
.m_axis_tvalid(axis_tx_out_tvalid),
.m_axis_tready(axis_tx_out_tready),
.m_axis_tlast(axis_tx_out_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(axis_tx_out_tuser),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
if (APP_AXIS_DIRECT_ENABLE) begin
assign m_axis_app_direct_tx_tdata = axis_tx_out_tdata;
assign m_axis_app_direct_tx_tkeep = axis_tx_out_tkeep;
assign m_axis_app_direct_tx_tvalid = axis_tx_out_tvalid;
assign axis_tx_out_tready = m_axis_app_direct_tx_tready;
assign m_axis_app_direct_tx_tlast = axis_tx_out_tlast;
assign m_axis_app_direct_tx_tuser = axis_tx_out_tuser;
assign axis_tx_l2_tdata = s_axis_app_direct_tx_tdata;
assign axis_tx_l2_tkeep = s_axis_app_direct_tx_tkeep;
assign axis_tx_l2_tvalid = s_axis_app_direct_tx_tvalid;
assign s_axis_app_direct_tx_tready = axis_tx_l2_tready;
assign axis_tx_l2_tlast = s_axis_app_direct_tx_tlast;
assign axis_tx_l2_tuser = s_axis_app_direct_tx_tuser;
end else begin
assign m_axis_app_direct_tx_tdata = 0;
assign m_axis_app_direct_tx_tkeep = 0;
assign m_axis_app_direct_tx_tvalid = 0;
assign m_axis_app_direct_tx_tlast = 0;
assign m_axis_app_direct_tx_tuser = 0;
assign s_axis_app_direct_tx_tready = 0;
assign axis_tx_l2_tdata = axis_tx_out_tdata;
assign axis_tx_l2_tkeep = axis_tx_out_tkeep;
assign axis_tx_l2_tvalid = axis_tx_out_tvalid;
assign axis_tx_out_tready = axis_tx_l2_tready;
assign axis_tx_l2_tlast = axis_tx_out_tlast;
assign axis_tx_l2_tuser = axis_tx_out_tuser;
end
mqnic_l2_egress #(
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.AXIS_USER_WIDTH(AXIS_TX_USER_WIDTH)
)
mqnic_l2_egress_inst (
.clk(tx_clk),
.rst(tx_rst),
/*
* Transmit data input
*/
.s_axis_tdata(axis_tx_l2_tdata),
.s_axis_tkeep(axis_tx_l2_tkeep),
.s_axis_tvalid(axis_tx_l2_tvalid),
.s_axis_tready(axis_tx_l2_tready),
.s_axis_tlast(axis_tx_l2_tlast),
.s_axis_tuser(axis_tx_l2_tuser),
/*
* Transmit data output
*/
.m_axis_tdata(m_axis_tx_tdata),
.m_axis_tkeep(m_axis_tx_tkeep),
.m_axis_tvalid(m_axis_tx_tvalid),
.m_axis_tready(m_axis_tx_tready),
.m_axis_tlast(m_axis_tx_tlast),
.m_axis_tuser(m_axis_tx_tuser)
);
endgenerate
endmodule
`resetall

2
fpga/common/tb/mqnic_core_axi/Makefile
View File

@ -47,6 +47,8 @@ VERILOG_SOURCES += ../../rtl/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v

36
fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py
View File

@ -88,7 +88,7 @@ class TB(object):
# Ethernet
self.port_mac = []
eth_int_if_width = len(dut.core_inst.iface[0].port[0].rx_async_fifo_inst.m_axis_tdata)
eth_int_if_width = len(dut.core_inst.m_axis_tx_tdata) / len(dut.core_inst.m_axis_tx_tvalid)
eth_clock_period = 6.4
eth_speed = 10e9
@ -106,25 +106,25 @@ class TB(object):
eth_speed = 100e9
for iface in dut.core_inst.iface:
for port in iface.port:
cocotb.start_soon(Clock(port.port_rx_clk, eth_clock_period, units="ns").start())
cocotb.start_soon(Clock(port.port_tx_clk, eth_clock_period, units="ns").start())
for k in range(len(iface.port)):
cocotb.start_soon(Clock(iface.port[k].port_rx_clk, eth_clock_period, units="ns").start())
cocotb.start_soon(Clock(iface.port[k].port_tx_clk, eth_clock_period, units="ns").start())
port.port_rx_rst.setimmediatevalue(0)
port.port_tx_rst.setimmediatevalue(0)
iface.port[k].port_rx_rst.setimmediatevalue(0)
iface.port[k].port_tx_rst.setimmediatevalue(0)
mac = EthMac(
tx_clk=port.port_tx_clk,
tx_rst=port.port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(port, "axis_tx"),
tx_ptp_time=port.ptp.tx_ptp_cdc_inst.output_ts,
tx_ptp_ts=port.ptp.axis_tx_ptp_ts,
tx_ptp_ts_tag=port.ptp.axis_tx_ptp_ts_tag,
tx_ptp_ts_valid=port.ptp.axis_tx_ptp_ts_valid,
rx_clk=port.port_rx_clk,
rx_rst=port.port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(port, "axis_rx"),
rx_ptp_time=port.ptp.rx_ptp_cdc_inst.output_ts,
tx_clk=iface.port[k].port_tx_clk,
tx_rst=iface.port[k].port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_tx_inst, "m_axis_tx"),
tx_ptp_time=iface.port[k].ptp.tx_ptp_cdc_inst.output_ts,
tx_ptp_ts=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts_valid,
rx_clk=iface.port[k].port_rx_clk,
rx_rst=iface.port[k].port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_rx_inst, "s_axis_rx"),
rx_ptp_time=iface.port[k].ptp.rx_ptp_cdc_inst.output_ts,
ifg=12, speed=eth_speed
)
@ -467,6 +467,8 @@ def test_mqnic_core_pcie_axi(request, if_count, ports_per_if, axi_data_width,
os.path.join(rtl_dir, "mqnic_ingress.v"),
os.path.join(rtl_dir, "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "mqnic_port_tx.v"),
os.path.join(rtl_dir, "mqnic_port_rx.v"),
os.path.join(rtl_dir, "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "mqnic_ptp.v"),
os.path.join(rtl_dir, "mqnic_ptp_clock.v"),

2
fpga/common/tb/mqnic_core_pcie_s10/Makefile
View File

@ -48,6 +48,8 @@ VERILOG_SOURCES += ../../rtl/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v

36
fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py
View File

@ -197,7 +197,7 @@ class TB(object):
# Ethernet
self.port_mac = []
eth_int_if_width = len(dut.core_pcie_inst.core_inst.iface[0].port[0].rx_async_fifo_inst.m_axis_tdata)
eth_int_if_width = len(dut.core_pcie_inst.core_inst.m_axis_tx_tdata) / len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)
eth_clock_period = 6.4
eth_speed = 10e9
@ -215,25 +215,25 @@ class TB(object):
eth_speed = 100e9
for iface in dut.core_pcie_inst.core_inst.iface:
for port in iface.port:
cocotb.start_soon(Clock(port.port_rx_clk, eth_clock_period, units="ns").start())
cocotb.start_soon(Clock(port.port_tx_clk, eth_clock_period, units="ns").start())
for k in range(len(iface.port)):
cocotb.start_soon(Clock(iface.port[k].port_rx_clk, eth_clock_period, units="ns").start())
cocotb.start_soon(Clock(iface.port[k].port_tx_clk, eth_clock_period, units="ns").start())
port.port_rx_rst.setimmediatevalue(0)
port.port_tx_rst.setimmediatevalue(0)
iface.port[k].port_rx_rst.setimmediatevalue(0)
iface.port[k].port_tx_rst.setimmediatevalue(0)
mac = EthMac(
tx_clk=port.port_tx_clk,
tx_rst=port.port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(port, "axis_tx"),
tx_ptp_time=port.ptp.tx_ptp_cdc_inst.output_ts,
tx_ptp_ts=port.ptp.axis_tx_ptp_ts,
tx_ptp_ts_tag=port.ptp.axis_tx_ptp_ts_tag,
tx_ptp_ts_valid=port.ptp.axis_tx_ptp_ts_valid,
rx_clk=port.port_rx_clk,
rx_rst=port.port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(port, "axis_rx"),
rx_ptp_time=port.ptp.rx_ptp_cdc_inst.output_ts,
tx_clk=iface.port[k].port_tx_clk,
tx_rst=iface.port[k].port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_tx_inst, "m_axis_tx"),
tx_ptp_time=iface.port[k].ptp.tx_ptp_cdc_inst.output_ts,
tx_ptp_ts=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts_valid,
rx_clk=iface.port[k].port_rx_clk,
rx_rst=iface.port[k].port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_rx_inst, "s_axis_rx"),
rx_ptp_time=iface.port[k].ptp.rx_ptp_cdc_inst.output_ts,
ifg=12, speed=eth_speed
)
@ -582,6 +582,8 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
os.path.join(rtl_dir, "mqnic_ingress.v"),
os.path.join(rtl_dir, "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "mqnic_port_tx.v"),
os.path.join(rtl_dir, "mqnic_port_rx.v"),
os.path.join(rtl_dir, "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "mqnic_ptp.v"),
os.path.join(rtl_dir, "mqnic_ptp_clock.v"),

2
fpga/common/tb/mqnic_core_pcie_us/Makefile
View File

@ -48,6 +48,8 @@ VERILOG_SOURCES += ../../rtl/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v

36
fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -272,7 +272,7 @@ class TB(object):
# Ethernet
self.port_mac = []
eth_int_if_width = len(dut.core_pcie_inst.core_inst.iface[0].port[0].rx_async_fifo_inst.m_axis_tdata)
eth_int_if_width = len(dut.core_pcie_inst.core_inst.m_axis_tx_tdata) / len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)
eth_clock_period = 6.4
eth_speed = 10e9
@ -290,25 +290,25 @@ class TB(object):
eth_speed = 100e9
for iface in dut.core_pcie_inst.core_inst.iface:
for port in iface.port:
cocotb.start_soon(Clock(port.port_rx_clk, eth_clock_period, units="ns").start())
cocotb.start_soon(Clock(port.port_tx_clk, eth_clock_period, units="ns").start())
for k in range(len(iface.port)):
cocotb.start_soon(Clock(iface.port[k].port_rx_clk, eth_clock_period, units="ns").start())
cocotb.start_soon(Clock(iface.port[k].port_tx_clk, eth_clock_period, units="ns").start())
port.port_rx_rst.setimmediatevalue(0)
port.port_tx_rst.setimmediatevalue(0)
iface.port[k].port_rx_rst.setimmediatevalue(0)
iface.port[k].port_tx_rst.setimmediatevalue(0)
mac = EthMac(
tx_clk=port.port_tx_clk,
tx_rst=port.port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(port, "axis_tx"),
tx_ptp_time=port.ptp.tx_ptp_cdc_inst.output_ts,
tx_ptp_ts=port.ptp.axis_tx_ptp_ts,
tx_ptp_ts_tag=port.ptp.axis_tx_ptp_ts_tag,
tx_ptp_ts_valid=port.ptp.axis_tx_ptp_ts_valid,
rx_clk=port.port_rx_clk,
rx_rst=port.port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(port, "axis_rx"),
rx_ptp_time=port.ptp.rx_ptp_cdc_inst.output_ts,
tx_clk=iface.port[k].port_tx_clk,
tx_rst=iface.port[k].port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_tx_inst, "m_axis_tx"),
tx_ptp_time=iface.port[k].ptp.tx_ptp_cdc_inst.output_ts,
tx_ptp_ts=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts_valid,
rx_clk=iface.port[k].port_rx_clk,
rx_rst=iface.port[k].port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_rx_inst, "s_axis_rx"),
rx_ptp_time=iface.port[k].ptp.rx_ptp_cdc_inst.output_ts,
ifg=12, speed=eth_speed
)
@ -657,6 +657,8 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(rtl_dir, "mqnic_ingress.v"),
os.path.join(rtl_dir, "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "mqnic_port_tx.v"),
os.path.join(rtl_dir, "mqnic_port_rx.v"),
os.path.join(rtl_dir, "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "mqnic_ptp.v"),
os.path.join(rtl_dir, "mqnic_ptp_clock.v"),

2
fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile
View File

@ -48,6 +48,8 @@ VERILOG_SOURCES += ../../rtl/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v

36
fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
View File

@ -272,7 +272,7 @@ class TB(object):
# Ethernet
self.port_mac = []
eth_int_if_width = len(dut.core_pcie_inst.core_inst.iface[0].port[0].rx_async_fifo_inst.m_axis_tdata)
eth_int_if_width = len(dut.core_pcie_inst.core_inst.m_axis_tx_tdata) / len(dut.core_pcie_inst.core_inst.m_axis_tx_tvalid)
eth_clock_period = 6.4
eth_speed = 10e9
@ -290,25 +290,25 @@ class TB(object):
eth_speed = 100e9
for iface in dut.core_pcie_inst.core_inst.iface:
for port in iface.port:
cocotb.start_soon(Clock(port.port_rx_clk, eth_clock_period, units="ns").start())
cocotb.start_soon(Clock(port.port_tx_clk, eth_clock_period, units="ns").start())
for k in range(len(iface.port)):
cocotb.start_soon(Clock(iface.port[k].port_rx_clk, eth_clock_period, units="ns").start())
cocotb.start_soon(Clock(iface.port[k].port_tx_clk, eth_clock_period, units="ns").start())
port.port_rx_rst.setimmediatevalue(0)
port.port_tx_rst.setimmediatevalue(0)
iface.port[k].port_rx_rst.setimmediatevalue(0)
iface.port[k].port_tx_rst.setimmediatevalue(0)
mac = EthMac(
tx_clk=port.port_tx_clk,
tx_rst=port.port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(port, "axis_tx"),
tx_ptp_time=port.ptp.tx_ptp_cdc_inst.output_ts,
tx_ptp_ts=port.ptp.axis_tx_ptp_ts,
tx_ptp_ts_tag=port.ptp.axis_tx_ptp_ts_tag,
tx_ptp_ts_valid=port.ptp.axis_tx_ptp_ts_valid,
rx_clk=port.port_rx_clk,
rx_rst=port.port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(port, "axis_rx"),
rx_ptp_time=port.ptp.rx_ptp_cdc_inst.output_ts,
tx_clk=iface.port[k].port_tx_clk,
tx_rst=iface.port[k].port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_tx_inst, "m_axis_tx"),
tx_ptp_time=iface.port[k].ptp.tx_ptp_cdc_inst.output_ts,
tx_ptp_ts=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts,
tx_ptp_ts_tag=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts_tag,
tx_ptp_ts_valid=iface.interface_inst.port[k].port_tx_inst.s_axis_tx_ptp_ts_valid,
rx_clk=iface.port[k].port_rx_clk,
rx_rst=iface.port[k].port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(iface.interface_inst.port[k].port_rx_inst, "s_axis_rx"),
rx_ptp_time=iface.port[k].ptp.rx_ptp_cdc_inst.output_ts,
ifg=12, speed=eth_speed
)
@ -710,6 +710,8 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(rtl_dir, "mqnic_ingress.v"),
os.path.join(rtl_dir, "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "mqnic_port_tx.v"),
os.path.join(rtl_dir, "mqnic_port_rx.v"),
os.path.join(rtl_dir, "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "mqnic_ptp.v"),
os.path.join(rtl_dir, "mqnic_ptp_clock.v"),

2
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile
View File

@ -19,6 +19,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile
View File

@ -19,6 +19,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile
View File

@ -49,6 +49,8 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -584,6 +584,8 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

2
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile
View File

@ -19,6 +19,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile
View File

@ -19,6 +19,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile
View File

@ -19,6 +19,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
View File

@ -49,6 +49,8 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -636,6 +636,8 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

2
fpga/mqnic/AU200/fpga_100g/fpga/Makefile
View File

@ -19,6 +19,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile
View File

@ -49,6 +49,8 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -584,6 +584,8 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

2
fpga/mqnic/AU200/fpga_25g/fpga/Makefile
View File

@ -19,6 +19,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile
View File

@ -19,6 +19,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile
View File

@ -49,6 +49,8 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -636,6 +636,8 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

2
fpga/mqnic/AU250/fpga_100g/fpga/Makefile
View File

@ -19,6 +19,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile
View File

@ -49,6 +49,8 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -584,6 +584,8 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

2
fpga/mqnic/AU250/fpga_25g/fpga/Makefile
View File

@ -19,6 +19,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile
View File

@ -19,6 +19,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile
View File

@ -49,6 +49,8 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -636,6 +636,8 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

2
fpga/mqnic/AU280/fpga_100g/fpga/Makefile
View File

@ -18,6 +18,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile
View File

@ -49,6 +49,8 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -573,6 +573,8 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

2
fpga/mqnic/AU280/fpga_25g/fpga/Makefile
View File

@ -18,6 +18,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile
View File

@ -18,6 +18,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile
View File

@ -49,6 +49,8 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -625,6 +625,8 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

2
fpga/mqnic/AU50/fpga_100g/fpga/Makefile
View File

@ -18,6 +18,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile
View File

@ -49,6 +49,8 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -534,6 +534,8 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

2
fpga/mqnic/AU50/fpga_25g/fpga/Makefile
View File

@ -18,6 +18,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile
View File

@ -18,6 +18,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile
View File

@ -49,6 +49,8 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -550,6 +550,8 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

2
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile
View File

@ -18,6 +18,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile
View File

@ -18,6 +18,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile
View File

@ -49,6 +49,8 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -620,6 +620,8 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

2
fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile
View File

@ -18,6 +18,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/Makefile
View File

@ -49,6 +49,8 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -538,6 +538,8 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

2
fpga/mqnic/ExaNIC_X25/fpga_25g/fpga/Makefile
View File

@ -18,6 +18,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/ExaNIC_X25/fpga_25g/fpga_10g/Makefile
View File

@ -18,6 +18,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/Makefile
View File

@ -49,6 +49,8 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -547,6 +547,8 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

2
fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile
View File

@ -21,6 +21,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile
View File

@ -49,6 +49,8 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -548,6 +548,8 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

2
fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21b/Makefile
View File

@ -20,6 +20,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21c/Makefile
View File

@ -20,6 +20,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/Makefile
View File

@ -49,6 +49,8 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py
View File

@ -545,6 +545,8 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

2
fpga/mqnic/VCU108/fpga_10g/fpga/Makefile
View File

@ -19,6 +19,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/Makefile
View File

@ -49,6 +49,8 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py
View File

@ -557,6 +557,8 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

2
fpga/mqnic/VCU118/fpga_100g/fpga/Makefile
View File

@ -19,6 +19,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile
View File

@ -49,6 +49,8 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -588,6 +588,8 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

2
fpga/mqnic/VCU118/fpga_25g/fpga/Makefile
View File

@ -19,6 +19,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile
View File

@ -19,6 +19,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile
View File

@ -49,6 +49,8 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -640,6 +640,8 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

2
fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile
View File

@ -19,6 +19,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile
View File

@ -49,6 +49,8 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -582,6 +582,8 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

2
fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile
View File

@ -19,6 +19,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile
View File

@ -19,6 +19,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile
View File

@ -49,6 +49,8 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -634,6 +634,8 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

2
fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile
View File

@ -18,6 +18,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile
View File

@ -49,6 +49,8 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -650,6 +650,8 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

2
fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile
View File

@ -18,6 +18,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile
View File

@ -18,6 +18,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile
View File

@ -49,6 +49,8 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -774,6 +774,8 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

2
fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile
View File

@ -19,6 +19,8 @@ SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile
View File

@ -49,6 +49,8 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v

2
fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py
View File

@ -541,6 +541,8 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),

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