Add output registers for I2C interface to improve timing

fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v

@@ -251,6 +251,26 @@ wire eeprom_i2c_sda_i;
 wire eeprom_i2c_sda_o;
 wire eeprom_i2c_sda_t;
 
+reg qsfp_i2c_scl_o_reg;
+reg qsfp_i2c_scl_t_reg;
+reg qsfp_i2c_sda_o_reg;
+reg qsfp_i2c_sda_t_reg;
+reg eeprom_i2c_scl_o_reg;
+reg eeprom_i2c_scl_t_reg;
+reg eeprom_i2c_sda_o_reg;
+reg eeprom_i2c_sda_t_reg;
+
+always @(posedge pcie_user_clk) begin
+    qsfp_i2c_scl_o_reg <= qsfp_i2c_scl_o;
+    qsfp_i2c_scl_t_reg <= qsfp_i2c_scl_t;
+    qsfp_i2c_sda_o_reg <= qsfp_i2c_sda_o;
+    qsfp_i2c_sda_t_reg <= qsfp_i2c_sda_t;
+    eeprom_i2c_scl_o_reg <= eeprom_i2c_scl_o;
+    eeprom_i2c_scl_t_reg <= eeprom_i2c_scl_t;
+    eeprom_i2c_sda_o_reg <= eeprom_i2c_sda_o;
+    eeprom_i2c_sda_t_reg <= eeprom_i2c_sda_t;
+end
+
 debounce_switch #(
     .WIDTH(2),
     .N(4),
@@ -277,10 +297,10 @@ sync_signal_inst (
         eeprom_i2c_scl_i, eeprom_i2c_sda_i})
 );
 
-assign qsfp_i2c_scl = qsfp_i2c_scl_t ? 1'bz : qsfp_i2c_scl_o;
-assign qsfp_i2c_sda = qsfp_i2c_sda_t ? 1'bz : qsfp_i2c_sda_o;
-assign eeprom_i2c_scl = eeprom_i2c_scl_t ? 1'bz : eeprom_i2c_scl_o;
-assign eeprom_i2c_sda = eeprom_i2c_sda_t ? 1'bz : eeprom_i2c_sda_o;
+assign qsfp_i2c_scl = qsfp_i2c_scl_t_reg ? 1'bz : qsfp_i2c_scl_o_reg;
+assign qsfp_i2c_sda = qsfp_i2c_sda_t_reg ? 1'bz : qsfp_i2c_sda_o_reg;
+assign eeprom_i2c_scl = eeprom_i2c_scl_t_reg ? 1'bz : eeprom_i2c_scl_o_reg;
+assign eeprom_i2c_sda = eeprom_i2c_sda_t_reg ? 1'bz : eeprom_i2c_sda_o_reg;
 
 // Flash
 wire qspi_clk_int;

fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v

@@ -252,6 +252,26 @@ wire eeprom_i2c_sda_i;
 wire eeprom_i2c_sda_o;
 wire eeprom_i2c_sda_t;
 
+reg qsfp_i2c_scl_o_reg;
+reg qsfp_i2c_scl_t_reg;
+reg qsfp_i2c_sda_o_reg;
+reg qsfp_i2c_sda_t_reg;
+reg eeprom_i2c_scl_o_reg;
+reg eeprom_i2c_scl_t_reg;
+reg eeprom_i2c_sda_o_reg;
+reg eeprom_i2c_sda_t_reg;
+
+always @(posedge pcie_user_clk) begin
+    qsfp_i2c_scl_o_reg <= qsfp_i2c_scl_o;
+    qsfp_i2c_scl_t_reg <= qsfp_i2c_scl_t;
+    qsfp_i2c_sda_o_reg <= qsfp_i2c_sda_o;
+    qsfp_i2c_sda_t_reg <= qsfp_i2c_sda_t;
+    eeprom_i2c_scl_o_reg <= eeprom_i2c_scl_o;
+    eeprom_i2c_scl_t_reg <= eeprom_i2c_scl_t;
+    eeprom_i2c_sda_o_reg <= eeprom_i2c_sda_o;
+    eeprom_i2c_sda_t_reg <= eeprom_i2c_sda_t;
+end
+
 debounce_switch #(
     .WIDTH(2),
     .N(4),
@@ -278,10 +298,10 @@ sync_signal_inst (
         eeprom_i2c_scl_i, eeprom_i2c_sda_i})
 );
 
-assign qsfp_i2c_scl = qsfp_i2c_scl_t ? 1'bz : qsfp_i2c_scl_o;
-assign qsfp_i2c_sda = qsfp_i2c_sda_t ? 1'bz : qsfp_i2c_sda_o;
-assign eeprom_i2c_scl = eeprom_i2c_scl_t ? 1'bz : eeprom_i2c_scl_o;
-assign eeprom_i2c_sda = eeprom_i2c_sda_t ? 1'bz : eeprom_i2c_sda_o;
+assign qsfp_i2c_scl = qsfp_i2c_scl_t_reg ? 1'bz : qsfp_i2c_scl_o_reg;
+assign qsfp_i2c_sda = qsfp_i2c_sda_t_reg ? 1'bz : qsfp_i2c_sda_o_reg;
+assign eeprom_i2c_scl = eeprom_i2c_scl_t_reg ? 1'bz : eeprom_i2c_scl_o_reg;
+assign eeprom_i2c_sda = eeprom_i2c_sda_t_reg ? 1'bz : eeprom_i2c_sda_o_reg;
 
 // Flash
 wire qspi_clk_int;

fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v

@@ -252,6 +252,26 @@ wire eeprom_i2c_sda_i;
 wire eeprom_i2c_sda_o;
 wire eeprom_i2c_sda_t;
 
+reg qsfp_i2c_scl_o_reg;
+reg qsfp_i2c_scl_t_reg;
+reg qsfp_i2c_sda_o_reg;
+reg qsfp_i2c_sda_t_reg;
+reg eeprom_i2c_scl_o_reg;
+reg eeprom_i2c_scl_t_reg;
+reg eeprom_i2c_sda_o_reg;
+reg eeprom_i2c_sda_t_reg;
+
+always @(posedge pcie_user_clk) begin
+    qsfp_i2c_scl_o_reg <= qsfp_i2c_scl_o;
+    qsfp_i2c_scl_t_reg <= qsfp_i2c_scl_t;
+    qsfp_i2c_sda_o_reg <= qsfp_i2c_sda_o;
+    qsfp_i2c_sda_t_reg <= qsfp_i2c_sda_t;
+    eeprom_i2c_scl_o_reg <= eeprom_i2c_scl_o;
+    eeprom_i2c_scl_t_reg <= eeprom_i2c_scl_t;
+    eeprom_i2c_sda_o_reg <= eeprom_i2c_sda_o;
+    eeprom_i2c_sda_t_reg <= eeprom_i2c_sda_t;
+end
+
 debounce_switch #(
     .WIDTH(2),
     .N(4),
@@ -278,10 +298,10 @@ sync_signal_inst (
         eeprom_i2c_scl_i, eeprom_i2c_sda_i})
 );
 
-assign qsfp_i2c_scl = qsfp_i2c_scl_t ? 1'bz : qsfp_i2c_scl_o;
-assign qsfp_i2c_sda = qsfp_i2c_sda_t ? 1'bz : qsfp_i2c_sda_o;
-assign eeprom_i2c_scl = eeprom_i2c_scl_t ? 1'bz : eeprom_i2c_scl_o;
-assign eeprom_i2c_sda = eeprom_i2c_sda_t ? 1'bz : eeprom_i2c_sda_o;
+assign qsfp_i2c_scl = qsfp_i2c_scl_t_reg ? 1'bz : qsfp_i2c_scl_o_reg;
+assign qsfp_i2c_sda = qsfp_i2c_sda_t_reg ? 1'bz : qsfp_i2c_sda_o_reg;
+assign eeprom_i2c_scl = eeprom_i2c_scl_t_reg ? 1'bz : eeprom_i2c_scl_o_reg;
+assign eeprom_i2c_sda = eeprom_i2c_sda_t_reg ? 1'bz : eeprom_i2c_sda_o_reg;
 
 // Flash
 wire qspi_clk_int;

fpga/mqnic/AU200/fpga_100g/rtl/fpga.v

@@ -247,6 +247,18 @@ wire i2c_sda_i;
 wire i2c_sda_o;
 wire i2c_sda_t;
 
+reg i2c_scl_o_reg;
+reg i2c_scl_t_reg;
+reg i2c_sda_o_reg;
+reg i2c_sda_t_reg;
+
+always @(posedge pcie_user_clk) begin
+    i2c_scl_o_reg <= i2c_scl_o;
+    i2c_scl_t_reg <= i2c_scl_t;
+    i2c_sda_o_reg <= i2c_sda_o;
+    i2c_sda_t_reg <= i2c_sda_t;
+end
+
 debounce_switch #(
     .WIDTH(4),
     .N(4),
@@ -271,8 +283,8 @@ sync_signal_inst (
         i2c_scl_i, i2c_sda_i})
 );
 
-assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
-assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
+assign i2c_scl = i2c_scl_t_reg ? 1'bz : i2c_scl_o_reg;
+assign i2c_sda = i2c_sda_t_reg ? 1'bz : i2c_sda_o_reg;
 
 // Flash
 wire qspi_clk_int;

fpga/mqnic/AU200/fpga_10g/rtl/fpga.v

@@ -244,6 +244,18 @@ wire i2c_sda_i;
 wire i2c_sda_o;
 wire i2c_sda_t;
 
+reg i2c_scl_o_reg;
+reg i2c_scl_t_reg;
+reg i2c_sda_o_reg;
+reg i2c_sda_t_reg;
+
+always @(posedge pcie_user_clk) begin
+    i2c_scl_o_reg <= i2c_scl_o;
+    i2c_scl_t_reg <= i2c_scl_t;
+    i2c_sda_o_reg <= i2c_sda_o;
+    i2c_sda_t_reg <= i2c_sda_t;
+end
+
 debounce_switch #(
     .WIDTH(4),
     .N(4),
@@ -268,8 +280,8 @@ sync_signal_inst (
         i2c_scl_i, i2c_sda_i})
 );
 
-assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
-assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
+assign i2c_scl = i2c_scl_t_reg ? 1'bz : i2c_scl_o_reg;
+assign i2c_sda = i2c_sda_t_reg ? 1'bz : i2c_sda_o_reg;
 
 // Flash
 wire qspi_clk_int;

fpga/mqnic/AU250/fpga_100g/rtl/fpga.v

@@ -247,6 +247,18 @@ wire i2c_sda_i;
 wire i2c_sda_o;
 wire i2c_sda_t;
 
+reg i2c_scl_o_reg;
+reg i2c_scl_t_reg;
+reg i2c_sda_o_reg;
+reg i2c_sda_t_reg;
+
+always @(posedge pcie_user_clk) begin
+    i2c_scl_o_reg <= i2c_scl_o;
+    i2c_scl_t_reg <= i2c_scl_t;
+    i2c_sda_o_reg <= i2c_sda_o;
+    i2c_sda_t_reg <= i2c_sda_t;
+end
+
 debounce_switch #(
     .WIDTH(4),
     .N(4),
@@ -271,8 +283,8 @@ sync_signal_inst (
         i2c_scl_i, i2c_sda_i})
 );
 
-assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
-assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
+assign i2c_scl = i2c_scl_t_reg ? 1'bz : i2c_scl_o_reg;
+assign i2c_sda = i2c_sda_t_reg ? 1'bz : i2c_sda_o_reg;
 
 // Flash
 wire qspi_clk_int;

fpga/mqnic/AU250/fpga_10g/rtl/fpga.v

@@ -244,6 +244,18 @@ wire i2c_sda_i;
 wire i2c_sda_o;
 wire i2c_sda_t;
 
+reg i2c_scl_o_reg;
+reg i2c_scl_t_reg;
+reg i2c_sda_o_reg;
+reg i2c_sda_t_reg;
+
+always @(posedge pcie_user_clk) begin
+    i2c_scl_o_reg <= i2c_scl_o;
+    i2c_scl_t_reg <= i2c_scl_t;
+    i2c_sda_o_reg <= i2c_sda_o;
+    i2c_sda_t_reg <= i2c_sda_t;
+end
+
 debounce_switch #(
     .WIDTH(4),
     .N(4),
@@ -268,8 +280,8 @@ sync_signal_inst (
         i2c_scl_i, i2c_sda_i})
 );
 
-assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
-assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
+assign i2c_scl = i2c_scl_t_reg ? 1'bz : i2c_scl_o_reg;
+assign i2c_sda = i2c_sda_t_reg ? 1'bz : i2c_sda_o_reg;
 
 // Flash
 wire qspi_clk_int;

fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga.v

@@ -242,6 +242,30 @@ wire eeprom_i2c_sda_i;
 wire eeprom_i2c_sda_o;
 wire eeprom_i2c_sda_t;
 
+reg sfp_i2c_scl_o_reg;
+reg sfp_i2c_scl_t_reg;
+reg sfp_1_i2c_sda_o_reg;
+reg sfp_1_i2c_sda_t_reg;
+reg sfp_2_i2c_sda_o_reg;
+reg sfp_2_i2c_sda_t_reg;
+reg eeprom_i2c_scl_o_reg;
+reg eeprom_i2c_scl_t_reg;
+reg eeprom_i2c_sda_o_reg;
+reg eeprom_i2c_sda_t_reg;
+
+always @(posedge pcie_user_clk) begin
+    sfp_i2c_scl_o_reg <= sfp_i2c_scl_o;
+    sfp_i2c_scl_t_reg <= sfp_i2c_scl_t;
+    sfp_1_i2c_sda_o_reg <= sfp_1_i2c_sda_o;
+    sfp_1_i2c_sda_t_reg <= sfp_1_i2c_sda_t;
+    sfp_2_i2c_sda_o_reg <= sfp_2_i2c_sda_o;
+    sfp_2_i2c_sda_t_reg <= sfp_2_i2c_sda_t;
+    eeprom_i2c_scl_o_reg <= eeprom_i2c_scl_o;
+    eeprom_i2c_scl_t_reg <= eeprom_i2c_scl_t;
+    eeprom_i2c_sda_o_reg <= eeprom_i2c_sda_o;
+    eeprom_i2c_sda_t_reg <= eeprom_i2c_sda_t;
+end
+
 sync_signal #(
     .WIDTH(9),
     .N(2)
@@ -256,11 +280,11 @@ sync_signal_inst (
         eeprom_i2c_scl_i, eeprom_i2c_sda_i})
 );
 
-assign sfp_i2c_scl = sfp_i2c_scl_t ? 1'bz : sfp_i2c_scl_o;
-assign sfp_1_i2c_sda = sfp_1_i2c_sda_t ? 1'bz : sfp_1_i2c_sda_o;
-assign sfp_2_i2c_sda = sfp_2_i2c_sda_t ? 1'bz : sfp_2_i2c_sda_o;
-assign eeprom_i2c_scl = eeprom_i2c_scl_t ? 1'bz : eeprom_i2c_scl_o;
-assign eeprom_i2c_sda = eeprom_i2c_sda_t ? 1'bz : eeprom_i2c_sda_o;
+assign sfp_i2c_scl = sfp_i2c_scl_t_reg ? 1'bz : sfp_i2c_scl_o_reg;
+assign sfp_1_i2c_sda = sfp_1_i2c_sda_t_reg ? 1'bz : sfp_1_i2c_sda_o_reg;
+assign sfp_2_i2c_sda = sfp_2_i2c_sda_t_reg ? 1'bz : sfp_2_i2c_sda_o_reg;
+assign eeprom_i2c_scl = eeprom_i2c_scl_t_reg ? 1'bz : eeprom_i2c_scl_o_reg;
+assign eeprom_i2c_sda = eeprom_i2c_sda_t_reg ? 1'bz : eeprom_i2c_sda_o_reg;
 
 // Flash
 wire [15:0] flash_dq_i_int;

fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga.v

@@ -226,6 +226,30 @@ wire eeprom_i2c_sda_i;
 wire eeprom_i2c_sda_o;
 wire eeprom_i2c_sda_t;
 
+reg sfp_i2c_scl_o_reg;
+reg sfp_i2c_scl_t_reg;
+reg sfp_1_i2c_sda_o_reg;
+reg sfp_1_i2c_sda_t_reg;
+reg sfp_2_i2c_sda_o_reg;
+reg sfp_2_i2c_sda_t_reg;
+reg eeprom_i2c_scl_o_reg;
+reg eeprom_i2c_scl_t_reg;
+reg eeprom_i2c_sda_o_reg;
+reg eeprom_i2c_sda_t_reg;
+
+always @(posedge pcie_user_clk) begin
+    sfp_i2c_scl_o_reg <= sfp_i2c_scl_o;
+    sfp_i2c_scl_t_reg <= sfp_i2c_scl_t;
+    sfp_1_i2c_sda_o_reg <= sfp_1_i2c_sda_o;
+    sfp_1_i2c_sda_t_reg <= sfp_1_i2c_sda_t;
+    sfp_2_i2c_sda_o_reg <= sfp_2_i2c_sda_o;
+    sfp_2_i2c_sda_t_reg <= sfp_2_i2c_sda_t;
+    eeprom_i2c_scl_o_reg <= eeprom_i2c_scl_o;
+    eeprom_i2c_scl_t_reg <= eeprom_i2c_scl_t;
+    eeprom_i2c_sda_o_reg <= eeprom_i2c_sda_o;
+    eeprom_i2c_sda_t_reg <= eeprom_i2c_sda_t;
+end
+
 sync_signal #(
     .WIDTH(9),
     .N(2)
@@ -240,11 +264,11 @@ sync_signal_inst (
         eeprom_i2c_scl_i, eeprom_i2c_sda_i})
 );
 
-assign sfp_i2c_scl = sfp_i2c_scl_t ? 1'bz : sfp_i2c_scl_o;
-assign sfp_1_i2c_sda = sfp_1_i2c_sda_t ? 1'bz : sfp_1_i2c_sda_o;
-assign sfp_2_i2c_sda = sfp_2_i2c_sda_t ? 1'bz : sfp_2_i2c_sda_o;
-assign eeprom_i2c_scl = eeprom_i2c_scl_t ? 1'bz : eeprom_i2c_scl_o;
-assign eeprom_i2c_sda = eeprom_i2c_sda_t ? 1'bz : eeprom_i2c_sda_o;
+assign sfp_i2c_scl = sfp_i2c_scl_t_reg ? 1'bz : sfp_i2c_scl_o_reg;
+assign sfp_1_i2c_sda = sfp_1_i2c_sda_t_reg ? 1'bz : sfp_1_i2c_sda_o_reg;
+assign sfp_2_i2c_sda = sfp_2_i2c_sda_t_reg ? 1'bz : sfp_2_i2c_sda_o_reg;
+assign eeprom_i2c_scl = eeprom_i2c_scl_t_reg ? 1'bz : eeprom_i2c_scl_o_reg;
+assign eeprom_i2c_sda = eeprom_i2c_sda_t_reg ? 1'bz : eeprom_i2c_sda_o_reg;
 
 // Flash
 wire [15:0] flash_dq_i_int;

fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v

@@ -268,6 +268,18 @@ wire i2c_sda_i_int;
 wire i2c_sda_o_int;
 wire i2c_sda_t_int;
 
+reg i2c_scl_o_reg;
+reg i2c_scl_t_reg;
+reg i2c_sda_o_reg;
+reg i2c_sda_t_reg;
+
+always @(posedge pcie_user_clk) begin
+    i2c_scl_o_reg <= i2c_scl_o_int;
+    i2c_scl_t_reg <= i2c_scl_t_int;
+    i2c_sda_o_reg <= i2c_sda_o_int;
+    i2c_sda_t_reg <= i2c_sda_t_int;
+end
+
 sync_signal #(
     .WIDTH(14),
     .N(2)
@@ -289,10 +301,10 @@ assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
 assign i2c_sda_i = i2c_sda;
 assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
 
-assign i2c_scl_o = i2c_scl_o_init && i2c_scl_o_int;
-assign i2c_scl_t = i2c_scl_t_init && i2c_scl_t_int;
-assign i2c_sda_o = i2c_sda_o_init && i2c_sda_o_int;
-assign i2c_sda_t = i2c_sda_t_init && i2c_sda_t_int;
+assign i2c_scl_o = i2c_scl_o_init && i2c_scl_o_reg;
+assign i2c_scl_t = i2c_scl_t_init && i2c_scl_t_reg;
+assign i2c_sda_o = i2c_sda_o_init && i2c_sda_o_reg;
+assign i2c_sda_t = i2c_sda_t_init && i2c_sda_t_reg;
 
 assign i2c_scl_i_init = i2c_scl_i;
 assign i2c_sda_i_init = i2c_sda_i;

fpga/mqnic/VCU108/fpga_10g/rtl/fpga.v

@@ -245,6 +245,18 @@ wire i2c_sda_i;
 wire i2c_sda_o;
 wire i2c_sda_t;
 
+reg i2c_scl_o_reg;
+reg i2c_scl_t_reg;
+reg i2c_sda_o_reg;
+reg i2c_sda_t_reg;
+
+always @(posedge pcie_user_clk) begin
+    i2c_scl_o_reg <= i2c_scl_o;
+    i2c_scl_t_reg <= i2c_scl_t;
+    i2c_sda_o_reg <= i2c_sda_o;
+    i2c_sda_t_reg <= i2c_sda_t;
+end
+
 debounce_switch #(
     .WIDTH(9),
     .N(4),
@@ -279,8 +291,8 @@ sync_signal_inst (
         i2c_scl_i, i2c_sda_i})
 );
 
-assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
-assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
+assign i2c_scl = i2c_scl_t_reg ? 1'bz : i2c_scl_o_reg;
+assign i2c_sda = i2c_sda_t_reg ? 1'bz : i2c_sda_o_reg;
 
 // Flash
 wire [3:0] flash_dq_int;

fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v

@@ -272,6 +272,18 @@ wire i2c_sda_i;
 wire i2c_sda_o;
 wire i2c_sda_t;
 
+reg i2c_scl_o_reg;
+reg i2c_scl_t_reg;
+reg i2c_sda_o_reg;
+reg i2c_sda_t_reg;
+
+always @(posedge pcie_user_clk) begin
+    i2c_scl_o_reg <= i2c_scl_o;
+    i2c_scl_t_reg <= i2c_scl_t;
+    i2c_sda_o_reg <= i2c_sda_o;
+    i2c_sda_t_reg <= i2c_sda_t;
+end
+
 debounce_switch #(
     .WIDTH(9),
     .N(4),
@@ -306,8 +318,8 @@ sync_signal_inst (
         i2c_scl_i, i2c_sda_i})
 );
 
-assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
-assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
+assign i2c_scl = i2c_scl_t_reg ? 1'bz : i2c_scl_o_reg;
+assign i2c_sda = i2c_sda_t_reg ? 1'bz : i2c_sda_o_reg;
 
 // Flash
 wire qspi_clk_int;

fpga/mqnic/VCU118/fpga_10g/rtl/fpga.v

@@ -269,6 +269,18 @@ wire i2c_sda_i;
 wire i2c_sda_o;
 wire i2c_sda_t;
 
+reg i2c_scl_o_reg;
+reg i2c_scl_t_reg;
+reg i2c_sda_o_reg;
+reg i2c_sda_t_reg;
+
+always @(posedge pcie_user_clk) begin
+    i2c_scl_o_reg <= i2c_scl_o;
+    i2c_scl_t_reg <= i2c_scl_t;
+    i2c_sda_o_reg <= i2c_sda_o;
+    i2c_sda_t_reg <= i2c_sda_t;
+end
+
 debounce_switch #(
     .WIDTH(9),
     .N(4),
@@ -303,8 +315,8 @@ sync_signal_inst (
         i2c_scl_i, i2c_sda_i})
 );
 
-assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
-assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
+assign i2c_scl = i2c_scl_t_reg ? 1'bz : i2c_scl_o_reg;
+assign i2c_sda = i2c_sda_t_reg ? 1'bz : i2c_sda_o_reg;
 
 // Flash
 wire qspi_clk_int;

fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v

@@ -247,6 +247,18 @@ wire i2c_sda_i;
 wire i2c_sda_o;
 wire i2c_sda_t;
 
+reg i2c_scl_o_reg;
+reg i2c_scl_t_reg;
+reg i2c_sda_o_reg;
+reg i2c_sda_t_reg;
+
+always @(posedge pcie_user_clk) begin
+    i2c_scl_o_reg <= i2c_scl_o;
+    i2c_scl_t_reg <= i2c_scl_t;
+    i2c_sda_o_reg <= i2c_sda_o;
+    i2c_sda_t_reg <= i2c_sda_t;
+end
+
 debounce_switch #(
     .WIDTH(4),
     .N(4),
@@ -271,8 +283,8 @@ sync_signal_inst (
         i2c_scl_i, i2c_sda_i})
 );
 
-assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
-assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
+assign i2c_scl = i2c_scl_t_reg ? 1'bz : i2c_scl_o_reg;
+assign i2c_sda = i2c_sda_t_reg ? 1'bz : i2c_sda_o_reg;
 
 // Flash
 wire qspi_clk_int;

fpga/mqnic/VCU1525/fpga_10g/rtl/fpga.v

@@ -244,6 +244,18 @@ wire i2c_sda_i;
 wire i2c_sda_o;
 wire i2c_sda_t;
 
+reg i2c_scl_o_reg;
+reg i2c_scl_t_reg;
+reg i2c_sda_o_reg;
+reg i2c_sda_t_reg;
+
+always @(posedge pcie_user_clk) begin
+    i2c_scl_o_reg <= i2c_scl_o;
+    i2c_scl_t_reg <= i2c_scl_t;
+    i2c_sda_o_reg <= i2c_sda_o;
+    i2c_sda_t_reg <= i2c_sda_t;
+end
+
 debounce_switch #(
     .WIDTH(4),
     .N(4),
@@ -268,8 +280,8 @@ sync_signal_inst (
         i2c_scl_i, i2c_sda_i})
 );
 
-assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
-assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
+assign i2c_scl = i2c_scl_t_reg ? 1'bz : i2c_scl_o_reg;
+assign i2c_sda = i2c_sda_t_reg ? 1'bz : i2c_sda_o_reg;
 
 // Flash
 wire qspi_clk_int;

fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v

@@ -219,6 +219,18 @@ wire i2c1_sda_i;
 wire i2c1_sda_o;
 wire i2c1_sda_t;
 
+reg i2c1_scl_o_reg;
+reg i2c1_scl_t_reg;
+reg i2c1_sda_o_reg;
+reg i2c1_sda_t_reg;
+
+always @(posedge pcie_user_clk) begin
+    i2c1_scl_o_reg <= i2c1_scl_o;
+    i2c1_scl_t_reg <= i2c1_scl_t;
+    i2c1_sda_o_reg <= i2c1_sda_o;
+    i2c1_sda_t_reg <= i2c1_sda_t;
+end
+
 debounce_switch #(
     .WIDTH(13),
     .N(4),
@@ -251,8 +263,8 @@ sync_signal_inst (
     .out({i2c1_scl_i, i2c1_sda_i})
 );
 
-assign i2c1_scl = i2c1_scl_t ? 1'bz : i2c1_scl_o;
-assign i2c1_sda = i2c1_sda_t ? 1'bz : i2c1_sda_o;
+assign i2c1_scl = i2c1_scl_t_reg ? 1'bz : i2c1_scl_o_reg;
+assign i2c1_sda = i2c1_sda_t_reg ? 1'bz : i2c1_sda_o_reg;
 
 // PCIe
 wire pcie_sys_clk;

fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v

@@ -256,6 +256,26 @@ wire qsfp_1_i2c_sda_i;
 wire qsfp_1_i2c_sda_o;
 wire qsfp_1_i2c_sda_t;
 
+reg qsfp_0_i2c_scl_o_reg;
+reg qsfp_0_i2c_scl_t_reg;
+reg qsfp_0_i2c_sda_o_reg;
+reg qsfp_0_i2c_sda_t_reg;
+reg qsfp_1_i2c_scl_o_reg;
+reg qsfp_1_i2c_scl_t_reg;
+reg qsfp_1_i2c_sda_o_reg;
+reg qsfp_1_i2c_sda_t_reg;
+
+always @(posedge pcie_user_clk) begin
+    qsfp_0_i2c_scl_o_reg <= qsfp_0_i2c_scl_o;
+    qsfp_0_i2c_scl_t_reg <= qsfp_0_i2c_scl_t;
+    qsfp_0_i2c_sda_o_reg <= qsfp_0_i2c_sda_o;
+    qsfp_0_i2c_sda_t_reg <= qsfp_0_i2c_sda_t;
+    qsfp_1_i2c_scl_o_reg <= qsfp_1_i2c_scl_o;
+    qsfp_1_i2c_scl_t_reg <= qsfp_1_i2c_scl_t;
+    qsfp_1_i2c_sda_o_reg <= qsfp_1_i2c_sda_o;
+    qsfp_1_i2c_sda_t_reg <= qsfp_1_i2c_sda_t;
+end
+
 sync_signal #(
     .WIDTH(8),
     .N(2)
@@ -268,10 +288,10 @@ sync_signal_inst (
         qsfp_1_mod_prsnt_n_int, qsfp_1_intr_n_int, qsfp_1_i2c_scl_i, qsfp_1_i2c_sda_i})
 );
 
-assign qsfp_0_i2c_scl = qsfp_0_i2c_scl_t ? 1'bz : qsfp_0_i2c_scl_o;
-assign qsfp_0_i2c_sda = qsfp_0_i2c_sda_t ? 1'bz : qsfp_0_i2c_sda_o;
-assign qsfp_1_i2c_scl = qsfp_1_i2c_scl_t ? 1'bz : qsfp_1_i2c_scl_o;
-assign qsfp_1_i2c_sda = qsfp_1_i2c_sda_t ? 1'bz : qsfp_1_i2c_sda_o;
+assign qsfp_0_i2c_scl = qsfp_0_i2c_scl_t_reg ? 1'bz : qsfp_0_i2c_scl_o_reg;
+assign qsfp_0_i2c_sda = qsfp_0_i2c_sda_t_reg ? 1'bz : qsfp_0_i2c_sda_o_reg;
+assign qsfp_1_i2c_scl = qsfp_1_i2c_scl_t_reg ? 1'bz : qsfp_1_i2c_scl_o_reg;
+assign qsfp_1_i2c_sda = qsfp_1_i2c_sda_t_reg ? 1'bz : qsfp_1_i2c_sda_o_reg;
 
 wire [7:0] led_red;
 wire [7:0] led_green;

fpga/mqnic/fb2CG/fpga_10g/rtl/fpga.v

@@ -253,6 +253,26 @@ wire qsfp_1_i2c_sda_i;
 wire qsfp_1_i2c_sda_o;
 wire qsfp_1_i2c_sda_t;
 
+reg qsfp_0_i2c_scl_o_reg;
+reg qsfp_0_i2c_scl_t_reg;
+reg qsfp_0_i2c_sda_o_reg;
+reg qsfp_0_i2c_sda_t_reg;
+reg qsfp_1_i2c_scl_o_reg;
+reg qsfp_1_i2c_scl_t_reg;
+reg qsfp_1_i2c_sda_o_reg;
+reg qsfp_1_i2c_sda_t_reg;
+
+always @(posedge pcie_user_clk) begin
+    qsfp_0_i2c_scl_o_reg <= qsfp_0_i2c_scl_o;
+    qsfp_0_i2c_scl_t_reg <= qsfp_0_i2c_scl_t;
+    qsfp_0_i2c_sda_o_reg <= qsfp_0_i2c_sda_o;
+    qsfp_0_i2c_sda_t_reg <= qsfp_0_i2c_sda_t;
+    qsfp_1_i2c_scl_o_reg <= qsfp_1_i2c_scl_o;
+    qsfp_1_i2c_scl_t_reg <= qsfp_1_i2c_scl_t;
+    qsfp_1_i2c_sda_o_reg <= qsfp_1_i2c_sda_o;
+    qsfp_1_i2c_sda_t_reg <= qsfp_1_i2c_sda_t;
+end
+
 sync_signal #(
     .WIDTH(8),
     .N(2)
@@ -265,10 +285,10 @@ sync_signal_inst (
         qsfp_1_mod_prsnt_n_int, qsfp_1_intr_n_int, qsfp_1_i2c_scl_i, qsfp_1_i2c_sda_i})
 );
 
-assign qsfp_0_i2c_scl = qsfp_0_i2c_scl_t ? 1'bz : qsfp_0_i2c_scl_o;
-assign qsfp_0_i2c_sda = qsfp_0_i2c_sda_t ? 1'bz : qsfp_0_i2c_sda_o;
-assign qsfp_1_i2c_scl = qsfp_1_i2c_scl_t ? 1'bz : qsfp_1_i2c_scl_o;
-assign qsfp_1_i2c_sda = qsfp_1_i2c_sda_t ? 1'bz : qsfp_1_i2c_sda_o;
+assign qsfp_0_i2c_scl = qsfp_0_i2c_scl_t_reg ? 1'bz : qsfp_0_i2c_scl_o_reg;
+assign qsfp_0_i2c_sda = qsfp_0_i2c_sda_t_reg ? 1'bz : qsfp_0_i2c_sda_o_reg;
+assign qsfp_1_i2c_scl = qsfp_1_i2c_scl_t_reg ? 1'bz : qsfp_1_i2c_scl_o_reg;
+assign qsfp_1_i2c_sda = qsfp_1_i2c_sda_t_reg ? 1'bz : qsfp_1_i2c_sda_o_reg;
 
 wire [7:0] led_red;
 wire [7:0] led_green;

fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v

@@ -253,6 +253,26 @@ wire qsfp_1_i2c_sda_i;
 wire qsfp_1_i2c_sda_o;
 wire qsfp_1_i2c_sda_t;
 
+reg qsfp_0_i2c_scl_o_reg;
+reg qsfp_0_i2c_scl_t_reg;
+reg qsfp_0_i2c_sda_o_reg;
+reg qsfp_0_i2c_sda_t_reg;
+reg qsfp_1_i2c_scl_o_reg;
+reg qsfp_1_i2c_scl_t_reg;
+reg qsfp_1_i2c_sda_o_reg;
+reg qsfp_1_i2c_sda_t_reg;
+
+always @(posedge pcie_user_clk) begin
+    qsfp_0_i2c_scl_o_reg <= qsfp_0_i2c_scl_o;
+    qsfp_0_i2c_scl_t_reg <= qsfp_0_i2c_scl_t;
+    qsfp_0_i2c_sda_o_reg <= qsfp_0_i2c_sda_o;
+    qsfp_0_i2c_sda_t_reg <= qsfp_0_i2c_sda_t;
+    qsfp_1_i2c_scl_o_reg <= qsfp_1_i2c_scl_o;
+    qsfp_1_i2c_scl_t_reg <= qsfp_1_i2c_scl_t;
+    qsfp_1_i2c_sda_o_reg <= qsfp_1_i2c_sda_o;
+    qsfp_1_i2c_sda_t_reg <= qsfp_1_i2c_sda_t;
+end
+
 sync_signal #(
     .WIDTH(8),
     .N(2)
@@ -265,10 +285,10 @@ sync_signal_inst (
         qsfp_1_mod_prsnt_n_int, qsfp_1_intr_n_int, qsfp_1_i2c_scl_i, qsfp_1_i2c_sda_i})
 );
 
-assign qsfp_0_i2c_scl = qsfp_0_i2c_scl_t ? 1'bz : qsfp_0_i2c_scl_o;
-assign qsfp_0_i2c_sda = qsfp_0_i2c_sda_t ? 1'bz : qsfp_0_i2c_sda_o;
-assign qsfp_1_i2c_scl = qsfp_1_i2c_scl_t ? 1'bz : qsfp_1_i2c_scl_o;
-assign qsfp_1_i2c_sda = qsfp_1_i2c_sda_t ? 1'bz : qsfp_1_i2c_sda_o;
+assign qsfp_0_i2c_scl = qsfp_0_i2c_scl_t_reg ? 1'bz : qsfp_0_i2c_scl_o_reg;
+assign qsfp_0_i2c_sda = qsfp_0_i2c_sda_t_reg ? 1'bz : qsfp_0_i2c_sda_o_reg;
+assign qsfp_1_i2c_scl = qsfp_1_i2c_scl_t_reg ? 1'bz : qsfp_1_i2c_scl_o_reg;
+assign qsfp_1_i2c_sda = qsfp_1_i2c_sda_t_reg ? 1'bz : qsfp_1_i2c_sda_o_reg;
 
 wire [7:0] led_red;
 wire [7:0] led_green;

fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v

@@ -252,6 +252,26 @@ wire eeprom_i2c_sda_i;
 wire eeprom_i2c_sda_o;
 wire eeprom_i2c_sda_t;
 
+reg qsfp_i2c_scl_o_reg;
+reg qsfp_i2c_scl_t_reg;
+reg qsfp_i2c_sda_o_reg;
+reg qsfp_i2c_sda_t_reg;
+reg eeprom_i2c_scl_o_reg;
+reg eeprom_i2c_scl_t_reg;
+reg eeprom_i2c_sda_o_reg;
+reg eeprom_i2c_sda_t_reg;
+
+always @(posedge pcie_user_clk) begin
+    qsfp_i2c_scl_o_reg <= qsfp_i2c_scl_o;
+    qsfp_i2c_scl_t_reg <= qsfp_i2c_scl_t;
+    qsfp_i2c_sda_o_reg <= qsfp_i2c_sda_o;
+    qsfp_i2c_sda_t_reg <= qsfp_i2c_sda_t;
+    eeprom_i2c_scl_o_reg <= eeprom_i2c_scl_o;
+    eeprom_i2c_scl_t_reg <= eeprom_i2c_scl_t;
+    eeprom_i2c_sda_o_reg <= eeprom_i2c_sda_o;
+    eeprom_i2c_sda_t_reg <= eeprom_i2c_sda_t;
+end
+
 debounce_switch #(
     .WIDTH(2),
     .N(4),
@@ -278,10 +298,10 @@ sync_signal_inst (
         eeprom_i2c_scl_i, eeprom_i2c_sda_i})
 );
 
-assign qsfp_i2c_scl = qsfp_i2c_scl_t ? 1'bz : qsfp_i2c_scl_o;
-assign qsfp_i2c_sda = qsfp_i2c_sda_t ? 1'bz : qsfp_i2c_sda_o;
-assign eeprom_i2c_scl = eeprom_i2c_scl_t ? 1'bz : eeprom_i2c_scl_o;
-assign eeprom_i2c_sda = eeprom_i2c_sda_t ? 1'bz : eeprom_i2c_sda_o;
+assign qsfp_i2c_scl = qsfp_i2c_scl_t_reg ? 1'bz : qsfp_i2c_scl_o_reg;
+assign qsfp_i2c_sda = qsfp_i2c_sda_t_reg ? 1'bz : qsfp_i2c_sda_o_reg;
+assign eeprom_i2c_scl = eeprom_i2c_scl_t_reg ? 1'bz : eeprom_i2c_scl_o_reg;
+assign eeprom_i2c_sda = eeprom_i2c_sda_t_reg ? 1'bz : eeprom_i2c_sda_o_reg;
 
 // Flash
 wire qspi_clk_int;

fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga.v

@@ -242,6 +242,30 @@ wire eeprom_i2c_sda_i;
 wire eeprom_i2c_sda_o;
 wire eeprom_i2c_sda_t;
 
+reg sfp_i2c_scl_o_reg;
+reg sfp_i2c_scl_t_reg;
+reg sfp_1_i2c_sda_o_reg;
+reg sfp_1_i2c_sda_t_reg;
+reg sfp_2_i2c_sda_o_reg;
+reg sfp_2_i2c_sda_t_reg;
+reg eeprom_i2c_scl_o_reg;
+reg eeprom_i2c_scl_t_reg;
+reg eeprom_i2c_sda_o_reg;
+reg eeprom_i2c_sda_t_reg;
+
+always @(posedge pcie_user_clk) begin
+    sfp_i2c_scl_o_reg <= sfp_i2c_scl_o;
+    sfp_i2c_scl_t_reg <= sfp_i2c_scl_t;
+    sfp_1_i2c_sda_o_reg <= sfp_1_i2c_sda_o;
+    sfp_1_i2c_sda_t_reg <= sfp_1_i2c_sda_t;
+    sfp_2_i2c_sda_o_reg <= sfp_2_i2c_sda_o;
+    sfp_2_i2c_sda_t_reg <= sfp_2_i2c_sda_t;
+    eeprom_i2c_scl_o_reg <= eeprom_i2c_scl_o;
+    eeprom_i2c_scl_t_reg <= eeprom_i2c_scl_t;
+    eeprom_i2c_sda_o_reg <= eeprom_i2c_sda_o;
+    eeprom_i2c_sda_t_reg <= eeprom_i2c_sda_t;
+end
+
 sync_signal #(
     .WIDTH(9),
     .N(2)
@@ -256,11 +280,11 @@ sync_signal_inst (
         eeprom_i2c_scl_i, eeprom_i2c_sda_i})
 );
 
-assign sfp_i2c_scl = sfp_i2c_scl_t ? 1'bz : sfp_i2c_scl_o;
-assign sfp_1_i2c_sda = sfp_1_i2c_sda_t ? 1'bz : sfp_1_i2c_sda_o;
-assign sfp_2_i2c_sda = sfp_2_i2c_sda_t ? 1'bz : sfp_2_i2c_sda_o;
-assign eeprom_i2c_scl = eeprom_i2c_scl_t ? 1'bz : eeprom_i2c_scl_o;
-assign eeprom_i2c_sda = eeprom_i2c_sda_t ? 1'bz : eeprom_i2c_sda_o;
+assign sfp_i2c_scl = sfp_i2c_scl_t_reg ? 1'bz : sfp_i2c_scl_o_reg;
+assign sfp_1_i2c_sda = sfp_1_i2c_sda_t_reg ? 1'bz : sfp_1_i2c_sda_o_reg;
+assign sfp_2_i2c_sda = sfp_2_i2c_sda_t_reg ? 1'bz : sfp_2_i2c_sda_o_reg;
+assign eeprom_i2c_scl = eeprom_i2c_scl_t_reg ? 1'bz : eeprom_i2c_scl_o_reg;
+assign eeprom_i2c_sda = eeprom_i2c_sda_t_reg ? 1'bz : eeprom_i2c_sda_o_reg;
 
 // Flash
 wire [15:0] flash_dq_i_int;

fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga.v

@@ -245,6 +245,18 @@ wire i2c_sda_i;
 wire i2c_sda_o;
 wire i2c_sda_t;
 
+reg i2c_scl_o_reg;
+reg i2c_scl_t_reg;
+reg i2c_sda_o_reg;
+reg i2c_sda_t_reg;
+
+always @(posedge pcie_user_clk) begin
+    i2c_scl_o_reg <= i2c_scl_o;
+    i2c_scl_t_reg <= i2c_scl_t;
+    i2c_sda_o_reg <= i2c_sda_o;
+    i2c_sda_t_reg <= i2c_sda_t;
+end
+
 debounce_switch #(
     .WIDTH(9),
     .N(4),
@@ -279,8 +291,8 @@ sync_signal_inst (
         i2c_scl_i, i2c_sda_i})
 );
 
-assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
-assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
+assign i2c_scl = i2c_scl_t_reg ? 1'bz : i2c_scl_o_reg;
+assign i2c_sda = i2c_sda_t_reg ? 1'bz : i2c_sda_o_reg;
 
 // Flash
 wire [3:0] flash_dq_int;

fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga.v

@@ -269,6 +269,18 @@ wire i2c_sda_i;
 wire i2c_sda_o;
 wire i2c_sda_t;
 
+reg i2c_scl_o_reg;
+reg i2c_scl_t_reg;
+reg i2c_sda_o_reg;
+reg i2c_sda_t_reg;
+
+always @(posedge pcie_user_clk) begin
+    i2c_scl_o_reg <= i2c_scl_o;
+    i2c_scl_t_reg <= i2c_scl_t;
+    i2c_sda_o_reg <= i2c_sda_o;
+    i2c_sda_t_reg <= i2c_sda_t;
+end
+
 debounce_switch #(
     .WIDTH(9),
     .N(4),
@@ -303,8 +315,8 @@ sync_signal_inst (
         i2c_scl_i, i2c_sda_i})
 );
 
-assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
-assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
+assign i2c_scl = i2c_scl_t_reg ? 1'bz : i2c_scl_o_reg;
+assign i2c_sda = i2c_sda_t_reg ? 1'bz : i2c_sda_o_reg;
 
 // Flash
 wire qspi_clk_int;