FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity

Remove string parameters

Browse Source
This commit is contained in:
Alex Forencich 2021-06-02 17:50:26 -07:00
parent 846183bc8b
commit 5415c41c41
22 changed files with 74 additions and 72 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
example/VCU108/fpga_10g/rtl/fpga_core.v
View File

@ -604,8 +604,8 @@ axis_switch #(
.M_CONNECT({3{3'b111}}), .M_CONNECT({3{3'b111}}),
.S_REG_TYPE(0), .S_REG_TYPE(0),
.M_REG_TYPE(2), .M_REG_TYPE(2),
.ARB_TYPE("PRIORITY"), .ARB_TYPE_ROUND_ROBIN(0),
.LSB_PRIORITY("HIGH") .ARB_LSB_HIGH_PRIORITY(1)
) )
axis_switch_inst ( axis_switch_inst (
.clk(clk), .clk(clk),

4
example/VCU118/fpga_10g/rtl/fpga_core.v
View File

@ -645,8 +645,8 @@ axis_switch #(
.M_CONNECT({3{3'b111}}), .M_CONNECT({3{3'b111}}),
.S_REG_TYPE(0), .S_REG_TYPE(0),
.M_REG_TYPE(2), .M_REG_TYPE(2),
.ARB_TYPE("PRIORITY"), .ARB_TYPE_ROUND_ROBIN(0),
.LSB_PRIORITY("HIGH") .ARB_LSB_HIGH_PRIORITY(1)
) )
axis_switch_inst ( axis_switch_inst (
.clk(clk), .clk(clk),

4
example/VCU118/fpga_25g/rtl/fpga_core.v
View File

@ -645,8 +645,8 @@ axis_switch #(
.M_CONNECT({3{3'b111}}), .M_CONNECT({3{3'b111}}),
.S_REG_TYPE(0), .S_REG_TYPE(0),
.M_REG_TYPE(2), .M_REG_TYPE(2),
.ARB_TYPE("PRIORITY"), .ARB_TYPE_ROUND_ROBIN(0),
.LSB_PRIORITY("HIGH") .ARB_LSB_HIGH_PRIORITY(1)
) )
axis_switch_inst ( axis_switch_inst (
.clk(clk), .clk(clk),

15
rtl/eth_arb_mux.v
View File

@ -41,10 +41,10 @@ module eth_arb_mux #
parameter DEST_WIDTH = 8, parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1, parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1, parameter USER_WIDTH = 1,
// arbitration type: "PRIORITY" or "ROUND_ROBIN" // select round robin arbitration
parameter ARB_TYPE = "PRIORITY", parameter ARB_TYPE_ROUND_ROBIN = 0,
// LSB priority: "LOW", "HIGH" // LSB priority selection
parameter LSB_PRIORITY = "HIGH" parameter ARB_LSB_HIGH_PRIORITY = 1
) )
( (
input wire clk, input wire clk,
@ -135,9 +135,10 @@ wire [USER_WIDTH-1:0] current_s_tuser = s_eth_payload_axis_tuser[grant_encoded*
// arbiter instance // arbiter instance
arbiter #( arbiter #(
.PORTS(S_COUNT), .PORTS(S_COUNT),
.TYPE(ARB_TYPE), .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.BLOCK("ACKNOWLEDGE"), .ARB_BLOCK(1),
.LSB_PRIORITY(LSB_PRIORITY) .ARB_BLOCK_ACK(1),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
) )
arb_inst ( arb_inst (
.clk(clk), .clk(clk),

15
rtl/ip_arb_mux.v
View File

@ -41,10 +41,10 @@ module ip_arb_mux #
parameter DEST_WIDTH = 8, parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1, parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1, parameter USER_WIDTH = 1,
// arbitration type: "PRIORITY" or "ROUND_ROBIN" // select round robin arbitration
parameter ARB_TYPE = "PRIORITY", parameter ARB_TYPE_ROUND_ROBIN = 0,
// LSB priority: "LOW", "HIGH" // LSB priority selection
parameter LSB_PRIORITY = "HIGH" parameter ARB_LSB_HIGH_PRIORITY = 1
) )
( (
input wire clk, input wire clk,
@ -187,9 +187,10 @@ wire [USER_WIDTH-1:0] current_s_tuser = s_ip_payload_axis_tuser[grant_encoded*U
// arbiter instance // arbiter instance
arbiter #( arbiter #(
.PORTS(S_COUNT), .PORTS(S_COUNT),
.TYPE(ARB_TYPE), .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.BLOCK("ACKNOWLEDGE"), .ARB_BLOCK(1),
.LSB_PRIORITY(LSB_PRIORITY) .ARB_BLOCK_ACK(1),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
) )
arb_inst ( arb_inst (
.clk(clk), .clk(clk),

4
rtl/ip_complete.v
View File

@ -261,8 +261,8 @@ eth_arb_mux #(
.DEST_ENABLE(0), .DEST_ENABLE(0),
.USER_ENABLE(1), .USER_ENABLE(1),
.USER_WIDTH(1), .USER_WIDTH(1),
.ARB_TYPE("PRIORITY"), .ARB_TYPE_ROUND_ROBIN(0),
.LSB_PRIORITY("HIGH") .ARB_LSB_HIGH_PRIORITY(1)
) )
eth_arb_mux_inst ( eth_arb_mux_inst (
.clk(clk), .clk(clk),

4
rtl/ip_complete_64.v
View File

@ -271,8 +271,8 @@ eth_arb_mux #(
.DEST_ENABLE(0), .DEST_ENABLE(0),
.USER_ENABLE(1), .USER_ENABLE(1),
.USER_WIDTH(1), .USER_WIDTH(1),
.ARB_TYPE("PRIORITY"), .ARB_TYPE_ROUND_ROBIN(0),
.LSB_PRIORITY("HIGH") .ARB_LSB_HIGH_PRIORITY(1)
) )
eth_arb_mux_inst ( eth_arb_mux_inst (
.clk(clk), .clk(clk),

15
rtl/udp_arb_mux.v
View File

@ -41,10 +41,10 @@ module udp_arb_mux #
parameter DEST_WIDTH = 8, parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1, parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1, parameter USER_WIDTH = 1,
// arbitration type: "PRIORITY" or "ROUND_ROBIN" // select round robin arbitration
parameter ARB_TYPE = "PRIORITY", parameter ARB_TYPE_ROUND_ROBIN = 0,
// LSB priority: "LOW", "HIGH" // LSB priority selection
parameter LSB_PRIORITY = "HIGH" parameter ARB_LSB_HIGH_PRIORITY = 1
) )
( (
input wire clk, input wire clk,
@ -203,9 +203,10 @@ wire [USER_WIDTH-1:0] current_s_tuser = s_udp_payload_axis_tuser[grant_encoded*
// arbiter instance // arbiter instance
arbiter #( arbiter #(
.PORTS(S_COUNT), .PORTS(S_COUNT),
.TYPE(ARB_TYPE), .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.BLOCK("ACKNOWLEDGE"), .ARB_BLOCK(1),
.LSB_PRIORITY(LSB_PRIORITY) .ARB_BLOCK_ACK(1),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
) )
arb_inst ( arb_inst (
.clk(clk), .clk(clk),

4
rtl/udp_complete.v
View File

@ -361,8 +361,8 @@ ip_arb_mux #(
.DEST_ENABLE(0), .DEST_ENABLE(0),
.USER_ENABLE(1), .USER_ENABLE(1),
.USER_WIDTH(1), .USER_WIDTH(1),
.ARB_TYPE("PRIORITY"), .ARB_TYPE_ROUND_ROBIN(0),
.LSB_PRIORITY("HIGH") .ARB_LSB_HIGH_PRIORITY(1)
) )
ip_arb_mux_inst ( ip_arb_mux_inst (
.clk(clk), .clk(clk),

4
rtl/udp_complete_64.v
View File

@ -373,8 +373,8 @@ ip_arb_mux #(
.DEST_ENABLE(0), .DEST_ENABLE(0),
.USER_ENABLE(1), .USER_ENABLE(1),
.USER_WIDTH(1), .USER_WIDTH(1),
.ARB_TYPE("PRIORITY"), .ARB_TYPE_ROUND_ROBIN(0),
.LSB_PRIORITY("HIGH") .ARB_LSB_HIGH_PRIORITY(1)
) )
ip_arb_mux_inst ( ip_arb_mux_inst (
.clk(clk), .clk(clk),

4
tb/test_eth_arb_mux_4.py
View File

@ -55,8 +55,8 @@ def bench():
DEST_WIDTH = 8 DEST_WIDTH = 8
USER_ENABLE = 1 USER_ENABLE = 1
USER_WIDTH = 1 USER_WIDTH = 1
ARB_TYPE = "PRIORITY" ARB_TYPE_ROUND_ROBIN = 0
LSB_PRIORITY = "HIGH" ARB_LSB_HIGH_PRIORITY = 1
# Inputs # Inputs
clk = Signal(bool(0)) clk = Signal(bool(0))

8
tb/test_eth_arb_mux_4.v
View File

@ -42,8 +42,8 @@ parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8; parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1; parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1; parameter USER_WIDTH = 1;
parameter ARB_TYPE = "PRIORITY"; parameter ARB_TYPE_ROUND_ROBIN = 0;
parameter LSB_PRIORITY = "HIGH"; parameter ARB_LSB_HIGH_PRIORITY = 1;
// Inputs // Inputs
reg clk = 0; reg clk = 0;
@ -133,8 +133,8 @@ eth_arb_mux #(
.DEST_WIDTH(DEST_WIDTH), .DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE), .USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH), .USER_WIDTH(USER_WIDTH),
.ARB_TYPE(ARB_TYPE), .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.LSB_PRIORITY(LSB_PRIORITY) .ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
) )
UUT ( UUT (
.clk(clk), .clk(clk),

4
tb/test_eth_arb_mux_64_4.py
View File

@ -55,8 +55,8 @@ def bench():
DEST_WIDTH = 8 DEST_WIDTH = 8
USER_ENABLE = 1 USER_ENABLE = 1
USER_WIDTH = 1 USER_WIDTH = 1
ARB_TYPE = "PRIORITY" ARB_TYPE_ROUND_ROBIN = 0
LSB_PRIORITY = "HIGH" ARB_LSB_HIGH_PRIORITY = 1
# Inputs # Inputs
clk = Signal(bool(0)) clk = Signal(bool(0))

8
tb/test_eth_arb_mux_64_4.v
View File

@ -42,8 +42,8 @@ parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8; parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1; parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1; parameter USER_WIDTH = 1;
parameter ARB_TYPE = "PRIORITY"; parameter ARB_TYPE_ROUND_ROBIN = 0;
parameter LSB_PRIORITY = "HIGH"; parameter ARB_LSB_HIGH_PRIORITY = 1;
// Inputs // Inputs
reg clk = 0; reg clk = 0;
@ -133,8 +133,8 @@ eth_arb_mux #(
.DEST_WIDTH(DEST_WIDTH), .DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE), .USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH), .USER_WIDTH(USER_WIDTH),
.ARB_TYPE(ARB_TYPE), .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.LSB_PRIORITY(LSB_PRIORITY) .ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
) )
UUT ( UUT (
.clk(clk), .clk(clk),

4
tb/test_ip_arb_mux_4.py
View File

@ -55,8 +55,8 @@ def bench():
DEST_WIDTH = 8 DEST_WIDTH = 8
USER_ENABLE = 1 USER_ENABLE = 1
USER_WIDTH = 1 USER_WIDTH = 1
ARB_TYPE = "PRIORITY" ARB_TYPE_ROUND_ROBIN = 0
LSB_PRIORITY = "HIGH" ARB_LSB_HIGH_PRIORITY = 1
# Inputs # Inputs
clk = Signal(bool(0)) clk = Signal(bool(0))

8
tb/test_ip_arb_mux_4.v
View File

@ -42,8 +42,8 @@ parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8; parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1; parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1; parameter USER_WIDTH = 1;
parameter ARB_TYPE = "PRIORITY"; parameter ARB_TYPE_ROUND_ROBIN = 0;
parameter LSB_PRIORITY = "HIGH"; parameter ARB_LSB_HIGH_PRIORITY = 1;
// Inputs // Inputs
reg clk = 0; reg clk = 0;
@ -185,8 +185,8 @@ ip_arb_mux #(
.DEST_WIDTH(DEST_WIDTH), .DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE), .USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH), .USER_WIDTH(USER_WIDTH),
.ARB_TYPE(ARB_TYPE), .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.LSB_PRIORITY(LSB_PRIORITY) .ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
) )
UUT ( UUT (
.clk(clk), .clk(clk),

4
tb/test_ip_arb_mux_64_4.py
View File

@ -55,8 +55,8 @@ def bench():
DEST_WIDTH = 8 DEST_WIDTH = 8
USER_ENABLE = 1 USER_ENABLE = 1
USER_WIDTH = 1 USER_WIDTH = 1
ARB_TYPE = "PRIORITY" ARB_TYPE_ROUND_ROBIN = 0
LSB_PRIORITY = "HIGH" ARB_LSB_HIGH_PRIORITY = 1
# Inputs # Inputs
clk = Signal(bool(0)) clk = Signal(bool(0))

8
tb/test_ip_arb_mux_64_4.v
View File

@ -42,8 +42,8 @@ parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8; parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1; parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1; parameter USER_WIDTH = 1;
parameter ARB_TYPE = "PRIORITY"; parameter ARB_TYPE_ROUND_ROBIN = 0;
parameter LSB_PRIORITY = "HIGH"; parameter ARB_LSB_HIGH_PRIORITY = 1;
// Inputs // Inputs
reg clk = 0; reg clk = 0;
@ -185,8 +185,8 @@ ip_arb_mux #(
.DEST_WIDTH(DEST_WIDTH), .DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE), .USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH), .USER_WIDTH(USER_WIDTH),
.ARB_TYPE(ARB_TYPE), .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.LSB_PRIORITY(LSB_PRIORITY) .ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
) )
UUT ( UUT (
.clk(clk), .clk(clk),

4
tb/test_udp_arb_mux_4.py
View File

@ -55,8 +55,8 @@ def bench():
DEST_WIDTH = 8 DEST_WIDTH = 8
USER_ENABLE = 1 USER_ENABLE = 1
USER_WIDTH = 1 USER_WIDTH = 1
ARB_TYPE = "PRIORITY" ARB_TYPE_ROUND_ROBIN = 0
LSB_PRIORITY = "HIGH" ARB_LSB_HIGH_PRIORITY = 1
# Inputs # Inputs
clk = Signal(bool(0)) clk = Signal(bool(0))

8
tb/test_udp_arb_mux_4.v
View File

@ -42,8 +42,8 @@ parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8; parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1; parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1; parameter USER_WIDTH = 1;
parameter ARB_TYPE = "PRIORITY"; parameter ARB_TYPE_ROUND_ROBIN = 0;
parameter LSB_PRIORITY = "HIGH"; parameter ARB_LSB_HIGH_PRIORITY = 1;
// Inputs // Inputs
reg clk = 0; reg clk = 0;
@ -201,8 +201,8 @@ udp_arb_mux #(
.DEST_WIDTH(DEST_WIDTH), .DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE), .USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH), .USER_WIDTH(USER_WIDTH),
.ARB_TYPE(ARB_TYPE), .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.LSB_PRIORITY(LSB_PRIORITY) .ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
) )
UUT ( UUT (
.clk(clk), .clk(clk),

5
tb/test_udp_arb_mux_64_4.py
View File

@ -55,9 +55,8 @@ def bench():
DEST_WIDTH = 8 DEST_WIDTH = 8
USER_ENABLE = 1 USER_ENABLE = 1
USER_WIDTH = 1 USER_WIDTH = 1
ARB_TYPE = "PRIORITY" ARB_TYPE_ROUND_ROBIN = 0
LSB_PRIORITY = "HIGH" ARB_LSB_HIGH_PRIORITY = 1
# Inputs # Inputs
clk = Signal(bool(0)) clk = Signal(bool(0))
rst = Signal(bool(0)) rst = Signal(bool(0))

8
tb/test_udp_arb_mux_64_4.v
View File

@ -42,8 +42,8 @@ parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8; parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1; parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1; parameter USER_WIDTH = 1;
parameter ARB_TYPE = "PRIORITY"; parameter ARB_TYPE_ROUND_ROBIN = 0;
parameter LSB_PRIORITY = "HIGH"; parameter ARB_LSB_HIGH_PRIORITY = 1;
// Inputs // Inputs
reg clk = 0; reg clk = 0;
@ -201,8 +201,8 @@ udp_arb_mux #(
.DEST_WIDTH(DEST_WIDTH), .DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE), .USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH), .USER_WIDTH(USER_WIDTH),
.ARB_TYPE(ARB_TYPE), .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.LSB_PRIORITY(LSB_PRIORITY) .ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
) )
UUT ( UUT (
.clk(clk), .clk(clk),