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fpga/mqnic/XUPP3R: Add missing TCL script for XUSP3S PCIe IP core

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich 2023-11-14 17:54:03 -08:00
parent 3f7a4cee27
commit 545fb3ca22
1 changed files with 32 additions and 0 deletions
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32
fpga/mqnic/XUPP3R/fpga_25g/ip/pcie3_ultrascale_0.tcl Normal file
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create_ip -name pcie3_ultrascale -vendor xilinx.com -library ip -module_name pcie3_ultrascale_0
set_property -dict [list \
CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \
CONFIG.AXISTEN_IF_RC_STRADDLE {true} \
CONFIG.axisten_if_width {256_bit} \
CONFIG.extended_tag_field {true} \
CONFIG.pf0_dev_cap_max_payload {1024_bytes} \
CONFIG.axisten_freq {250} \
CONFIG.PF0_Use_Class_Code_Lookup_Assistant {false} \
CONFIG.pf0_class_code_base {02} \
CONFIG.pf0_class_code_sub {00} \
CONFIG.pf0_class_code_interface {00} \
CONFIG.PF0_DEVICE_ID {1001} \
CONFIG.PF0_SUBSYSTEM_ID {8823} \
CONFIG.PF0_SUBSYSTEM_VENDOR_ID {12ba} \
CONFIG.pf0_bar0_64bit {true} \
CONFIG.pf0_bar0_prefetchable {true} \
CONFIG.pf0_bar0_scale {Megabytes} \
CONFIG.pf0_bar0_size {16} \
CONFIG.pf0_msi_enabled {false} \
CONFIG.pf0_msix_enabled {true} \
CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \
CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_1:0} \
CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00010000} \
CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_1:0} \
CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00018000} \
CONFIG.vendor_id {1234} \
CONFIG.mode_selection {Advanced} \
] [get_ips pcie3_ultrascale_0]