FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity

Cast WL to int

Browse Source
This commit is contained in:
Alex Forencich 2015-03-21 03:19:43 -07:00
parent 4981d7cacd
commit 54bfdaa8c0
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
tb/axis_ep.py
View File

@ -147,7 +147,7 @@ def AXIStreamSource(clk, rst,
b = False b = False
if tkeep is not None: if tkeep is not None:
M = len(tkeep) M = len(tkeep)
WL = (len(tdata)+M-1)/M WL = int((len(tdata)+M-1)/M)
if WL == 8: if WL == 8:
b = True b = True
@ -219,7 +219,7 @@ def AXIStreamSink(clk, rst,
M = 1 M = 1
b = False b = False
M = len(tkeep) M = len(tkeep)
WL = (len(tdata)+M-1)/M WL = int((len(tdata)+M-1)/M)
if WL == 8: if WL == 8:
b = True b = True