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Fix user_clk_frequency setting in testbenches

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This commit is contained in:
Alex Forencich 2020-10-12 23:05:28 -07:00
parent d22d3e8bd1
commit 5546e40812
12 changed files with 12 additions and 12 deletions
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2
example/ADM_PCIE_9V3/fpga_axi_x8/tb/test_fpga_core.py
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@ -147,7 +147,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 8
dev.user_clock_frequency = 256e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
example/AU200/fpga_axi/tb/test_fpga_core.py
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@ -151,7 +151,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 16
dev.user_clock_frequency = 256e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
example/AU250/fpga_axi/tb/test_fpga_core.py
View File

@ -151,7 +151,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 16
dev.user_clock_frequency = 256e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
example/AU280/fpga_axi/tb/test_fpga_core.py
View File

@ -144,7 +144,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 16
dev.user_clock_frequency = 256e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
example/AU50/fpga_axi/tb/test_fpga_core.py
View File

@ -144,7 +144,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 16
dev.user_clock_frequency = 256e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
example/ExaNIC_X10/fpga_axi/tb/test_fpga_core.py
View File

@ -147,7 +147,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 8
dev.user_clock_frequency = 256e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
example/ExaNIC_X25/fpga_axi/tb/test_fpga_core.py
View File

@ -147,7 +147,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 8
dev.user_clock_frequency = 256e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
example/VCU108/fpga_axi/tb/test_fpga_core.py
View File

@ -146,7 +146,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 8
dev.user_clock_frequency = 256e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
example/VCU118/fpga_axi_x8/tb/test_fpga_core.py
View File

@ -151,7 +151,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 8
dev.user_clock_frequency = 256e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
example/VCU1525/fpga_axi/tb/test_fpga_core.py
View File

@ -151,7 +151,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 16
dev.user_clock_frequency = 256e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
example/ZCU106/fpga_axi/tb/test_fpga_core.py
View File

@ -151,7 +151,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 4
dev.user_clock_frequency = 256e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5

2
example/fb2CG/fpga_axi/tb/test_fpga_core.py
View File

@ -148,7 +148,7 @@ def bench():
dev.pcie_generation = 3
dev.pcie_link_width = 16
dev.user_clock_frequency = 256e6
dev.user_clk_frequency = 250e6
dev.functions[0].msi_multiple_message_capable = 5