From 5546e408125de46819888d3b898e94edf5ab4bbe Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Mon, 12 Oct 2020 23:05:28 -0700 Subject: [PATCH] Fix user_clk_frequency setting in testbenches --- example/ADM_PCIE_9V3/fpga_axi_x8/tb/test_fpga_core.py | 2 +- example/AU200/fpga_axi/tb/test_fpga_core.py | 2 +- example/AU250/fpga_axi/tb/test_fpga_core.py | 2 +- example/AU280/fpga_axi/tb/test_fpga_core.py | 2 +- example/AU50/fpga_axi/tb/test_fpga_core.py | 2 +- example/ExaNIC_X10/fpga_axi/tb/test_fpga_core.py | 2 +- example/ExaNIC_X25/fpga_axi/tb/test_fpga_core.py | 2 +- example/VCU108/fpga_axi/tb/test_fpga_core.py | 2 +- example/VCU118/fpga_axi_x8/tb/test_fpga_core.py | 2 +- example/VCU1525/fpga_axi/tb/test_fpga_core.py | 2 +- example/ZCU106/fpga_axi/tb/test_fpga_core.py | 2 +- example/fb2CG/fpga_axi/tb/test_fpga_core.py | 2 +- 12 files changed, 12 insertions(+), 12 deletions(-) diff --git a/example/ADM_PCIE_9V3/fpga_axi_x8/tb/test_fpga_core.py b/example/ADM_PCIE_9V3/fpga_axi_x8/tb/test_fpga_core.py index e50b9eca5..cbf4aa0c7 100755 --- a/example/ADM_PCIE_9V3/fpga_axi_x8/tb/test_fpga_core.py +++ b/example/ADM_PCIE_9V3/fpga_axi_x8/tb/test_fpga_core.py @@ -147,7 +147,7 @@ def bench(): dev.pcie_generation = 3 dev.pcie_link_width = 8 - dev.user_clock_frequency = 256e6 + dev.user_clk_frequency = 250e6 dev.functions[0].msi_multiple_message_capable = 5 diff --git a/example/AU200/fpga_axi/tb/test_fpga_core.py b/example/AU200/fpga_axi/tb/test_fpga_core.py index fd7119f1d..478bc3dbb 100755 --- a/example/AU200/fpga_axi/tb/test_fpga_core.py +++ b/example/AU200/fpga_axi/tb/test_fpga_core.py @@ -151,7 +151,7 @@ def bench(): dev.pcie_generation = 3 dev.pcie_link_width = 16 - dev.user_clock_frequency = 256e6 + dev.user_clk_frequency = 250e6 dev.functions[0].msi_multiple_message_capable = 5 diff --git a/example/AU250/fpga_axi/tb/test_fpga_core.py b/example/AU250/fpga_axi/tb/test_fpga_core.py index fd7119f1d..478bc3dbb 100755 --- a/example/AU250/fpga_axi/tb/test_fpga_core.py +++ b/example/AU250/fpga_axi/tb/test_fpga_core.py @@ -151,7 +151,7 @@ def bench(): dev.pcie_generation = 3 dev.pcie_link_width = 16 - dev.user_clock_frequency = 256e6 + dev.user_clk_frequency = 250e6 dev.functions[0].msi_multiple_message_capable = 5 diff --git a/example/AU280/fpga_axi/tb/test_fpga_core.py b/example/AU280/fpga_axi/tb/test_fpga_core.py index 55212e652..d1d902ceb 100755 --- a/example/AU280/fpga_axi/tb/test_fpga_core.py +++ b/example/AU280/fpga_axi/tb/test_fpga_core.py @@ -144,7 +144,7 @@ def bench(): dev.pcie_generation = 3 dev.pcie_link_width = 16 - dev.user_clock_frequency = 256e6 + dev.user_clk_frequency = 250e6 dev.functions[0].msi_multiple_message_capable = 5 diff --git a/example/AU50/fpga_axi/tb/test_fpga_core.py b/example/AU50/fpga_axi/tb/test_fpga_core.py index 55212e652..d1d902ceb 100755 --- a/example/AU50/fpga_axi/tb/test_fpga_core.py +++ b/example/AU50/fpga_axi/tb/test_fpga_core.py @@ -144,7 +144,7 @@ def bench(): dev.pcie_generation = 3 dev.pcie_link_width = 16 - dev.user_clock_frequency = 256e6 + dev.user_clk_frequency = 250e6 dev.functions[0].msi_multiple_message_capable = 5 diff --git a/example/ExaNIC_X10/fpga_axi/tb/test_fpga_core.py b/example/ExaNIC_X10/fpga_axi/tb/test_fpga_core.py index 463cf492e..56514675a 100755 --- a/example/ExaNIC_X10/fpga_axi/tb/test_fpga_core.py +++ b/example/ExaNIC_X10/fpga_axi/tb/test_fpga_core.py @@ -147,7 +147,7 @@ def bench(): dev.pcie_generation = 3 dev.pcie_link_width = 8 - dev.user_clock_frequency = 256e6 + dev.user_clk_frequency = 250e6 dev.functions[0].msi_multiple_message_capable = 5 diff --git a/example/ExaNIC_X25/fpga_axi/tb/test_fpga_core.py b/example/ExaNIC_X25/fpga_axi/tb/test_fpga_core.py index 5c5ffab20..e7fa7953f 100755 --- a/example/ExaNIC_X25/fpga_axi/tb/test_fpga_core.py +++ b/example/ExaNIC_X25/fpga_axi/tb/test_fpga_core.py @@ -147,7 +147,7 @@ def bench(): dev.pcie_generation = 3 dev.pcie_link_width = 8 - dev.user_clock_frequency = 256e6 + dev.user_clk_frequency = 250e6 dev.functions[0].msi_multiple_message_capable = 5 diff --git a/example/VCU108/fpga_axi/tb/test_fpga_core.py b/example/VCU108/fpga_axi/tb/test_fpga_core.py index 9b03a5786..0e0f0c532 100755 --- a/example/VCU108/fpga_axi/tb/test_fpga_core.py +++ b/example/VCU108/fpga_axi/tb/test_fpga_core.py @@ -146,7 +146,7 @@ def bench(): dev.pcie_generation = 3 dev.pcie_link_width = 8 - dev.user_clock_frequency = 256e6 + dev.user_clk_frequency = 250e6 dev.functions[0].msi_multiple_message_capable = 5 diff --git a/example/VCU118/fpga_axi_x8/tb/test_fpga_core.py b/example/VCU118/fpga_axi_x8/tb/test_fpga_core.py index 81e282707..e28bdd2d3 100755 --- a/example/VCU118/fpga_axi_x8/tb/test_fpga_core.py +++ b/example/VCU118/fpga_axi_x8/tb/test_fpga_core.py @@ -151,7 +151,7 @@ def bench(): dev.pcie_generation = 3 dev.pcie_link_width = 8 - dev.user_clock_frequency = 256e6 + dev.user_clk_frequency = 250e6 dev.functions[0].msi_multiple_message_capable = 5 diff --git a/example/VCU1525/fpga_axi/tb/test_fpga_core.py b/example/VCU1525/fpga_axi/tb/test_fpga_core.py index fd7119f1d..478bc3dbb 100755 --- a/example/VCU1525/fpga_axi/tb/test_fpga_core.py +++ b/example/VCU1525/fpga_axi/tb/test_fpga_core.py @@ -151,7 +151,7 @@ def bench(): dev.pcie_generation = 3 dev.pcie_link_width = 16 - dev.user_clock_frequency = 256e6 + dev.user_clk_frequency = 250e6 dev.functions[0].msi_multiple_message_capable = 5 diff --git a/example/ZCU106/fpga_axi/tb/test_fpga_core.py b/example/ZCU106/fpga_axi/tb/test_fpga_core.py index 8e4535511..48d5e00c7 100755 --- a/example/ZCU106/fpga_axi/tb/test_fpga_core.py +++ b/example/ZCU106/fpga_axi/tb/test_fpga_core.py @@ -151,7 +151,7 @@ def bench(): dev.pcie_generation = 3 dev.pcie_link_width = 4 - dev.user_clock_frequency = 256e6 + dev.user_clk_frequency = 250e6 dev.functions[0].msi_multiple_message_capable = 5 diff --git a/example/fb2CG/fpga_axi/tb/test_fpga_core.py b/example/fb2CG/fpga_axi/tb/test_fpga_core.py index d9d23641f..eca194d3e 100755 --- a/example/fb2CG/fpga_axi/tb/test_fpga_core.py +++ b/example/fb2CG/fpga_axi/tb/test_fpga_core.py @@ -148,7 +148,7 @@ def bench(): dev.pcie_generation = 3 dev.pcie_link_width = 16 - dev.user_clock_frequency = 256e6 + dev.user_clk_frequency = 250e6 dev.functions[0].msi_multiple_message_capable = 5