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Fix timestamp capture/sync logic

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-11-30 14:05:16 -08:00
parent 16cd84123d
commit 5560fa2b32
2 changed files with 12 additions and 10 deletions
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10
rtl/ptp_clock_cdc.v
View File

@ -491,8 +491,6 @@ always @(posedge output_clk) begin
ts_capt_valid_reg <= 1'b1; ts_capt_valid_reg <= 1'b1;
end end
ts_sync_valid_reg <= 1'b0;
if (src_sync_sync2_reg ^ src_sync_sync3_reg) begin if (src_sync_sync2_reg ^ src_sync_sync3_reg) begin
// store captured source TS // store captured source TS
if (TS_WIDTH == 96) begin if (TS_WIDTH == 96) begin
@ -501,7 +499,11 @@ always @(posedge output_clk) begin
src_ts_ns_sync_reg <= src_ts_ns_capt_reg; src_ts_ns_sync_reg <= src_ts_ns_capt_reg;
src_ts_step_sync_reg <= src_ts_step_capt_reg; src_ts_step_sync_reg <= src_ts_step_capt_reg;
ts_sync_valid_reg <= ts_capt_valid_reg; ts_sync_valid_reg <= 1'b1;
end
if (ts_sync_valid_reg && ts_capt_valid_reg) begin
ts_sync_valid_reg <= 1'b0;
ts_capt_valid_reg <= 1'b0; ts_capt_valid_reg <= 1'b0;
end end
@ -595,7 +597,7 @@ always @* begin
ts_ns_next = ts_ns_reg + period_ns_reg; ts_ns_next = ts_ns_reg + period_ns_reg;
end end
if (ts_sync_valid_reg) begin if (ts_sync_valid_reg && ts_capt_valid_reg) begin
// Read new value // Read new value
if (TS_WIDTH == 96) begin if (TS_WIDTH == 96) begin
if (src_ts_step_sync_reg || load_ts_reg) begin if (src_ts_step_sync_reg || load_ts_reg) begin

12
rtl/ptp_td_leaf.v
View File

@ -533,14 +533,11 @@ always @(posedge clk) begin
dst_load_cnt_reg <= dst_load_cnt_reg + 1; dst_load_cnt_reg <= dst_load_cnt_reg + 1;
end end
ts_sync_valid_reg <= 1'b0;
if (src_sync_sync2_reg ^ src_sync_sync3_reg) begin if (src_sync_sync2_reg ^ src_sync_sync3_reg) begin
// store captured source TS // store captured source TS
src_ns_sync_reg <= src_ns_reg >> (SRC_FNS_W-CMP_FNS_W); src_ns_sync_reg <= src_ns_reg >> (SRC_FNS_W-CMP_FNS_W);
ts_sync_valid_reg <= ts_capt_valid_reg; ts_sync_valid_reg <= 1'b1;
ts_capt_valid_reg <= 1'b0;
end end
if (src_marker_sync2_reg ^ src_marker_sync3_reg) begin if (src_marker_sync2_reg ^ src_marker_sync3_reg) begin
@ -548,9 +545,12 @@ always @(posedge clk) begin
end end
phase_err_out_valid_reg <= 1'b0; phase_err_out_valid_reg <= 1'b0;
if (ts_sync_valid_reg) begin if (ts_sync_valid_reg && ts_capt_valid_reg) begin
// coarse phase locking // coarse phase locking
ts_sync_valid_reg <= 1'b0;
ts_capt_valid_reg <= 1'b0;
// phase and frequency detector // phase and frequency detector
phase_last_src_reg <= src_ns_sync_reg[8+CMP_FNS_W]; phase_last_src_reg <= src_ns_sync_reg[8+CMP_FNS_W];
phase_last_dst_reg <= dst_ns_capt_reg[8+CMP_FNS_W]; phase_last_dst_reg <= dst_ns_capt_reg[8+CMP_FNS_W];
@ -827,7 +827,7 @@ always @* begin
end end
end end
if (ts_sync_valid_reg) begin if (ts_sync_valid_reg && ts_capt_valid_reg) begin
// compute difference // compute difference
ts_ns_diff_valid_next = freq_locked_reg; ts_ns_diff_valid_next = freq_locked_reg;
ts_ns_diff_next = src_ns_sync_reg - dst_ns_capt_reg; ts_ns_diff_next = src_ns_sync_reg - dst_ns_capt_reg;