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Use correct clocks

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This commit is contained in:
Alex Forencich 2019-05-14 18:57:01 -07:00
parent 7b33dde069
commit 5581a76c0b
1 changed files with 2 additions and 2 deletions
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4
rtl/axil_dp_ram.v
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@ -288,8 +288,8 @@ always @* begin
end
end
always @(posedge a_clk) begin
if (a_rst) begin
always @(posedge b_clk) begin
if (b_rst) begin
last_read_b_reg <= 1'b0;
s_axil_b_awready_reg <= 1'b0;