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merged changes in pcie

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This commit is contained in:
Alex Forencich 2022-06-05 14:30:42 -07:00
commit 5595953d5a
87 changed files with 1388 additions and 1387 deletions
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6
fpga/lib/pcie/example/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py
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@ -52,8 +52,10 @@ class TB(object):
pcie_link_width=16,
user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
cq_straddle=False,
cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False,
pf_count=1,
max_payload_size=1024,

6
fpga/lib/pcie/example/ADM_PCIE_9V3/fpga_axi/tb/fpga_core/test_fpga_core.py
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@ -53,8 +53,10 @@ class TB(object):
pcie_link_width=16,
user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
cq_straddle=False,
cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False,
pf_count=1,
max_payload_size=1024,

6
fpga/lib/pcie/example/AU200/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -52,8 +52,10 @@ class TB(object):
pcie_link_width=16,
user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
cq_straddle=False,
cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False,
pf_count=1,
max_payload_size=1024,

6
fpga/lib/pcie/example/AU200/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -53,8 +53,10 @@ class TB(object):
pcie_link_width=16,
user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
cq_straddle=False,
cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False,
pf_count=1,
max_payload_size=1024,

6
fpga/lib/pcie/example/AU250/fpga/tb/fpga_core/test_fpga_core.py
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@ -52,8 +52,10 @@ class TB(object):
pcie_link_width=16,
user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
cq_straddle=False,
cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False,
pf_count=1,
max_payload_size=1024,

6
fpga/lib/pcie/example/AU250/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -53,8 +53,10 @@ class TB(object):
pcie_link_width=16,
user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
cq_straddle=False,
cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False,
pf_count=1,
max_payload_size=1024,

6
fpga/lib/pcie/example/AU280/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -52,8 +52,10 @@ class TB(object):
pcie_link_width=16,
user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
cq_straddle=False,
cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False,
pf_count=1,
max_payload_size=1024,

6
fpga/lib/pcie/example/AU280/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -53,8 +53,10 @@ class TB(object):
pcie_link_width=16,
user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
cq_straddle=False,
cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False,
pf_count=1,
max_payload_size=1024,

6
fpga/lib/pcie/example/AU50/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -52,8 +52,10 @@ class TB(object):
pcie_link_width=16,
user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
cq_straddle=False,
cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False,
pf_count=1,
max_payload_size=1024,

6
fpga/lib/pcie/example/AU50/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -53,8 +53,10 @@ class TB(object):
pcie_link_width=16,
user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
cq_straddle=False,
cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False,
pf_count=1,
max_payload_size=1024,

2
fpga/lib/pcie/example/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -52,7 +52,7 @@ class TB(object):
pcie_link_width=8,
user_clk_frequency=250e6,
alignment="dword",
straddle=False,
rc_straddle=False,
pf_count=1,
max_payload_size=1024,
enable_client_tag=True,

2
fpga/lib/pcie/example/ExaNIC_X10/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -53,7 +53,7 @@ class TB(object):
pcie_link_width=8,
user_clk_frequency=250e6,
alignment="dword",
straddle=False,
rc_straddle=False,
pf_count=1,
max_payload_size=1024,
enable_client_tag=True,

6
fpga/lib/pcie/example/ExaNIC_X25/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -52,8 +52,10 @@ class TB(object):
pcie_link_width=8,
user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
cq_straddle=False,
cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False,
pf_count=1,
max_payload_size=1024,

6
fpga/lib/pcie/example/ExaNIC_X25/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -53,8 +53,10 @@ class TB(object):
pcie_link_width=8,
user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
cq_straddle=False,
cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False,
pf_count=1,
max_payload_size=1024,

2
fpga/lib/pcie/example/VCU108/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -52,7 +52,7 @@ class TB(object):
pcie_link_width=8,
user_clk_frequency=250e6,
alignment="dword",
straddle=False,
rc_straddle=False,
pf_count=1,
max_payload_size=1024,
enable_client_tag=True,

2
fpga/lib/pcie/example/VCU108/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -53,7 +53,7 @@ class TB(object):
pcie_link_width=8,
user_clk_frequency=250e6,
alignment="dword",
straddle=False,
rc_straddle=False,
pf_count=1,
max_payload_size=1024,
enable_client_tag=True,

6
fpga/lib/pcie/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -52,8 +52,10 @@ class TB(object):
pcie_link_width=16,
user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
cq_straddle=False,
cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False,
pf_count=1,
max_payload_size=1024,

6
fpga/lib/pcie/example/VCU118/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -53,8 +53,10 @@ class TB(object):
pcie_link_width=16,
user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
cq_straddle=False,
cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False,
pf_count=1,
max_payload_size=1024,

6
fpga/lib/pcie/example/VCU1525/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -52,8 +52,10 @@ class TB(object):
pcie_link_width=16,
user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
cq_straddle=False,
cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False,
pf_count=1,
max_payload_size=1024,

6
fpga/lib/pcie/example/VCU1525/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -53,8 +53,10 @@ class TB(object):
pcie_link_width=16,
user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
cq_straddle=False,
cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False,
pf_count=1,
max_payload_size=1024,

6
fpga/lib/pcie/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -52,8 +52,10 @@ class TB(object):
pcie_link_width=4,
user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
cq_straddle=False,
cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False,
pf_count=1,
max_payload_size=1024,

6
fpga/lib/pcie/example/ZCU106/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -53,8 +53,10 @@ class TB(object):
pcie_link_width=4,
user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
cq_straddle=False,
cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False,
pf_count=1,
max_payload_size=1024,

128
fpga/lib/pcie/example/common/rtl/example_core_pcie.v
View File

@ -33,14 +33,14 @@ THE SOFTWARE.
*/
module example_core_pcie #
(
// TLP data width
parameter TLP_DATA_WIDTH = 256,
// TLP strobe width
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
// TLP header width
parameter TLP_HDR_WIDTH = 128,
// TLP segment count
parameter TLP_SEG_COUNT = 1,
// TLP segment data width
parameter TLP_SEG_DATA_WIDTH = 256,
// TLP segment strobe width
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32,
// TLP segment header width
parameter TLP_SEG_HDR_WIDTH = 128,
// TX sequence number count
parameter TX_SEQ_NUM_COUNT = 1,
// TX sequence number width
@ -81,8 +81,8 @@ module example_core_pcie #
/*
* TLP input (request)
*/
input wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] rx_req_tlp_data,
input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] rx_req_tlp_hdr,
input wire [TLP_DATA_WIDTH-1:0] rx_req_tlp_data,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_req_tlp_hdr,
input wire [TLP_SEG_COUNT*3-1:0] rx_req_tlp_bar_id,
input wire [TLP_SEG_COUNT*8-1:0] rx_req_tlp_func_num,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_valid,
@ -93,9 +93,9 @@ module example_core_pcie #
/*
* TLP output (completion)
*/
output wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] tx_cpl_tlp_data,
output wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] tx_cpl_tlp_strb,
output wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_cpl_tlp_hdr,
output wire [TLP_DATA_WIDTH-1:0] tx_cpl_tlp_data,
output wire [TLP_STRB_WIDTH-1:0] tx_cpl_tlp_strb,
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_cpl_tlp_hdr,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop,
@ -104,8 +104,8 @@ module example_core_pcie #
/*
* TLP input (completion)
*/
input wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] rx_cpl_tlp_data,
input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] rx_cpl_tlp_hdr,
input wire [TLP_DATA_WIDTH-1:0] rx_cpl_tlp_data,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_cpl_tlp_hdr,
input wire [TLP_SEG_COUNT*4-1:0] rx_cpl_tlp_error,
input wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_sop,
@ -115,7 +115,7 @@ module example_core_pcie #
/*
* TLP output (read request)
*/
output wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_rd_req_tlp_hdr,
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_rd_req_tlp_hdr,
output wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_rd_req_tlp_seq,
output wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_sop,
@ -125,9 +125,9 @@ module example_core_pcie #
/*
* TLP output (write request)
*/
output wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] tx_wr_req_tlp_data,
output wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] tx_wr_req_tlp_strb,
output wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr,
output wire [TLP_DATA_WIDTH-1:0] tx_wr_req_tlp_data,
output wire [TLP_STRB_WIDTH-1:0] tx_wr_req_tlp_strb,
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr,
output wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_wr_req_tlp_seq,
output wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_sop,
@ -173,7 +173,7 @@ parameter AXIL_DATA_WIDTH = 32;
parameter AXIL_ADDR_WIDTH = BAR0_APERTURE;
parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8);
parameter AXI_DATA_WIDTH = TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH;
parameter AXI_DATA_WIDTH = TLP_DATA_WIDTH;
parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8);
parameter AXI_ADDR_WIDTH = BAR2_APERTURE;
parameter AXI_ID_WIDTH = 8;
@ -181,7 +181,7 @@ parameter AXI_ID_WIDTH = 8;
parameter RAM_SEL_WIDTH = 2;
parameter RAM_ADDR_WIDTH = 16;
parameter RAM_SEG_COUNT = TLP_SEG_COUNT*2;
parameter RAM_SEG_DATA_WIDTH = (TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH)*2/RAM_SEG_COUNT;
parameter RAM_SEG_DATA_WIDTH = TLP_DATA_WIDTH*2/RAM_SEG_COUNT;
parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8;
parameter RAM_SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH);
@ -254,46 +254,46 @@ wire [2:0] status_error_cor_int;
wire [2:0] status_error_uncor_int;
// PCIe connections
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] ctrl_rx_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] ctrl_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT*3-1:0] ctrl_rx_req_tlp_bar_id;
wire [TLP_SEG_COUNT*8-1:0] ctrl_rx_req_tlp_func_num;
wire [TLP_SEG_COUNT-1:0] ctrl_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] ctrl_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] ctrl_rx_req_tlp_eop;
wire ctrl_rx_req_tlp_ready;
wire [TLP_DATA_WIDTH-1:0] ctrl_rx_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] ctrl_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT*3-1:0] ctrl_rx_req_tlp_bar_id;
wire [TLP_SEG_COUNT*8-1:0] ctrl_rx_req_tlp_func_num;
wire [TLP_SEG_COUNT-1:0] ctrl_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] ctrl_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] ctrl_rx_req_tlp_eop;
wire ctrl_rx_req_tlp_ready;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] ctrl_tx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] ctrl_tx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] ctrl_tx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] ctrl_tx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] ctrl_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] ctrl_tx_cpl_tlp_eop;
wire ctrl_tx_cpl_tlp_ready;
wire [TLP_DATA_WIDTH-1:0] ctrl_tx_cpl_tlp_data;
wire [TLP_STRB_WIDTH-1:0] ctrl_tx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] ctrl_tx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] ctrl_tx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] ctrl_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] ctrl_tx_cpl_tlp_eop;
wire ctrl_tx_cpl_tlp_ready;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] ram_rx_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] ram_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT*3-1:0] ram_rx_req_tlp_bar_id;
wire [TLP_SEG_COUNT*8-1:0] ram_rx_req_tlp_func_num;
wire [TLP_SEG_COUNT-1:0] ram_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] ram_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] ram_rx_req_tlp_eop;
wire ram_rx_req_tlp_ready;
wire [TLP_DATA_WIDTH-1:0] ram_rx_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] ram_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT*3-1:0] ram_rx_req_tlp_bar_id;
wire [TLP_SEG_COUNT*8-1:0] ram_rx_req_tlp_func_num;
wire [TLP_SEG_COUNT-1:0] ram_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] ram_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] ram_rx_req_tlp_eop;
wire ram_rx_req_tlp_ready;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] ram_tx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] ram_tx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] ram_tx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] ram_tx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] ram_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] ram_tx_cpl_tlp_eop;
wire ram_tx_cpl_tlp_ready;
wire [TLP_DATA_WIDTH-1:0] ram_tx_cpl_tlp_data;
wire [TLP_STRB_WIDTH-1:0] ram_tx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] ram_tx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] ram_tx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] ram_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] ram_tx_cpl_tlp_eop;
wire ram_tx_cpl_tlp_ready;
pcie_tlp_demux_bar #(
.PORTS(2),
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.BAR_BASE(0),
.BAR_STRIDE(2),
.BAR_IDS(0)
@ -338,10 +338,10 @@ pcie_tlp_demux_inst (
pcie_tlp_mux #(
.PORTS(2),
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.ARB_TYPE_ROUND_ROBIN(1),
.ARB_LSB_HIGH_PRIORITY(1)
)
@ -379,10 +379,10 @@ pcie_tlp_mux_inst (
);
pcie_axil_master #(
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
@ -485,10 +485,10 @@ wire axi_ram_rvalid;
wire axi_ram_rready;
pcie_axi_master #(
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
@ -620,10 +620,10 @@ axi_ram_inst (
);
dma_if_pcie #(
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.TX_SEQ_NUM_ENABLE(TX_SEQ_NUM_ENABLE),

40
fpga/lib/pcie/example/common/rtl/example_core_pcie_us.v
View File

@ -181,10 +181,10 @@ module example_core_pcie_us #
output wire status_error_uncor
);
parameter TLP_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH;
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32;
parameter TLP_HDR_WIDTH = 128;
parameter TLP_SEG_COUNT = 1;
parameter TLP_SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH/TLP_SEG_COUNT;
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32;
parameter TLP_SEG_HDR_WIDTH = 128;
parameter TX_SEQ_NUM_COUNT = AXIS_PCIE_DATA_WIDTH < 512 ? 1 : 2;
parameter TX_SEQ_NUM_WIDTH = RQ_SEQ_NUM_WIDTH-1;
parameter TX_SEQ_NUM_ENABLE = RQ_SEQ_NUM_ENABLE;
@ -193,8 +193,8 @@ parameter VF_COUNT = 0;
parameter F_COUNT = PF_COUNT+VF_COUNT;
parameter MSI_COUNT = 32;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr;
wire [TLP_DATA_WIDTH-1:0] pcie_rx_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT*3-1:0] pcie_rx_req_tlp_bar_id;
wire [TLP_SEG_COUNT*8-1:0] pcie_rx_req_tlp_func_num;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_valid;
@ -202,15 +202,15 @@ wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_req_tlp_eop;
wire pcie_rx_req_tlp_ready;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr;
wire [TLP_DATA_WIDTH-1:0] pcie_rx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_rx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT*4-1:0] pcie_rx_cpl_tlp_error;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_rx_cpl_tlp_eop;
wire pcie_rx_cpl_tlp_ready;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr;
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_tx_rd_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_rd_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_rd_req_tlp_sop;
@ -220,9 +220,9 @@ wire pcie_tx_rd_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] axis_pcie_rd_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] axis_pcie_rd_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr;
wire [TLP_DATA_WIDTH-1:0] pcie_tx_wr_req_tlp_data;
wire [TLP_STRB_WIDTH-1:0] pcie_tx_wr_req_tlp_strb;
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_tx_wr_req_tlp_hdr;
wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] pcie_tx_wr_req_tlp_seq;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_wr_req_tlp_sop;
@ -232,9 +232,9 @@ wire pcie_tx_wr_req_tlp_ready;
wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] axis_pcie_wr_req_tx_seq_num;
wire [TX_SEQ_NUM_COUNT-1:0] axis_pcie_wr_req_tx_seq_num_valid;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr;
wire [TLP_DATA_WIDTH-1:0] pcie_tx_cpl_tlp_data;
wire [TLP_STRB_WIDTH-1:0] pcie_tx_cpl_tlp_strb;
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] pcie_tx_cpl_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_valid;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop;
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop;
@ -255,10 +255,10 @@ pcie_us_if #(
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.PF_COUNT(1),
@ -459,10 +459,10 @@ pcie_us_if_inst (
);
example_core_pcie #(
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.TX_SEQ_NUM_ENABLE(TX_SEQ_NUM_ENABLE),

18
fpga/lib/pcie/example/common/tb/example_core_pcie/Makefile
View File

@ -48,10 +48,10 @@ VERILOG_SOURCES += ../../../../rtl/priority_encoder.v
VERILOG_SOURCES += ../../../../rtl/pulse_merge.v
# module parameters
export PARAM_TLP_DATA_WIDTH ?= 512
export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
export PARAM_TLP_HDR_WIDTH ?= 128
export PARAM_TLP_SEG_COUNT ?= 1
export PARAM_TLP_SEG_DATA_WIDTH ?= 512
export PARAM_TLP_SEG_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_SEG_DATA_WIDTH) / 32 )
export PARAM_TLP_SEG_HDR_WIDTH ?= 128
export PARAM_TX_SEQ_NUM_COUNT ?= 1
export PARAM_TX_SEQ_NUM_WIDTH ?= 6
export PARAM_TX_SEQ_NUM_ENABLE ?= 1
@ -72,10 +72,10 @@ export PARAM_BAR2_APERTURE ?= 24
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += -P $(TOPLEVEL).TLP_DATA_WIDTH=$(PARAM_TLP_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_STRB_WIDTH=$(PARAM_TLP_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_HDR_WIDTH=$(PARAM_TLP_HDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_COUNT=$(PARAM_TLP_SEG_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_DATA_WIDTH=$(PARAM_TLP_SEG_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_STRB_WIDTH=$(PARAM_TLP_SEG_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_HDR_WIDTH=$(PARAM_TLP_SEG_HDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SEQ_NUM_COUNT=$(PARAM_TX_SEQ_NUM_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SEQ_NUM_WIDTH=$(PARAM_TX_SEQ_NUM_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SEQ_NUM_ENABLE=$(PARAM_TX_SEQ_NUM_ENABLE)
@ -100,10 +100,10 @@ ifeq ($(SIM), icarus)
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
COMPILE_ARGS += -GTLP_DATA_WIDTH=$(PARAM_TLP_DATA_WIDTH)
COMPILE_ARGS += -GTLP_STRB_WIDTH=$(PARAM_TLP_STRB_WIDTH)
COMPILE_ARGS += -GTLP_HDR_WIDTH=$(PARAM_TLP_HDR_WIDTH)
COMPILE_ARGS += -GTLP_SEG_COUNT=$(PARAM_TLP_SEG_COUNT)
COMPILE_ARGS += -GTLP_SEG_DATA_WIDTH=$(PARAM_TLP_SEG_DATA_WIDTH)
COMPILE_ARGS += -GTLP_SEG_STRB_WIDTH=$(PARAM_TLP_SEG_STRB_WIDTH)
COMPILE_ARGS += -GTLP_SEG_HDR_WIDTH=$(PARAM_TLP_SEG_HDR_WIDTH)
COMPILE_ARGS += -GTX_SEQ_NUM_COUNT=$(PARAM_TX_SEQ_NUM_COUNT)
COMPILE_ARGS += -GTX_SEQ_NUM_WIDTH=$(PARAM_TX_SEQ_NUM_WIDTH)
COMPILE_ARGS += -GTX_SEQ_NUM_ENABLE=$(PARAM_TX_SEQ_NUM_ENABLE)

13
fpga/lib/pcie/example/common/tb/example_core_pcie/test_example_core_pcie.py
View File

@ -368,15 +368,10 @@ def test_example_core_pcie(request, pcie_data_width):
parameters = {}
# segmented interface parameters
tlp_seg_count = 1
tlp_seg_data_width = pcie_data_width // tlp_seg_count
tlp_seg_strb_width = tlp_seg_data_width // 32
parameters['TLP_SEG_COUNT'] = tlp_seg_count
parameters['TLP_SEG_DATA_WIDTH'] = tlp_seg_data_width
parameters['TLP_SEG_STRB_WIDTH'] = tlp_seg_strb_width
parameters['TLP_SEG_HDR_WIDTH'] = 128
parameters['TLP_DATA_WIDTH'] = pcie_data_width
parameters['TLP_STRB_WIDTH'] = parameters['TLP_DATA_WIDTH'] // 32
parameters['TLP_HDR_WIDTH'] = 128
parameters['TLP_SEG_COUNT'] = 1
parameters['TX_SEQ_NUM_COUNT'] = 1
parameters['TX_SEQ_NUM_WIDTH'] = 6
parameters['TX_SEQ_NUM_ENABLE'] = 1

6
fpga/lib/pcie/example/common/tb/example_core_pcie_us/test_example_core_pcie_us.py
View File

@ -53,8 +53,10 @@ class TB(object):
# pcie_link_width=16,
user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
cq_straddle=False,
cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False,
pf_count=1,
max_payload_size=1024,

6
fpga/lib/pcie/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -52,8 +52,10 @@ class TB(object):
pcie_link_width=16,
user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
cq_straddle=False,
cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False,
pf_count=1,
max_payload_size=1024,

6
fpga/lib/pcie/example/fb2CG/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -53,8 +53,10 @@ class TB(object):
pcie_link_width=16,
user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
cq_straddle=False,
cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False,
pf_count=1,
max_payload_size=1024,

34
fpga/lib/pcie/rtl/dma_if_pcie.v
View File

@ -33,14 +33,14 @@ THE SOFTWARE.
*/
module dma_if_pcie #
(
// TLP data width
parameter TLP_DATA_WIDTH = 256,
// TLP strobe width
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
// TLP header width
parameter TLP_HDR_WIDTH = 128,
// TLP segment count
parameter TLP_SEG_COUNT = 1,
// TLP segment data width
parameter TLP_SEG_DATA_WIDTH = 256,
// TLP segment strobe width
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32,
// TLP segment header width
parameter TLP_SEG_HDR_WIDTH = 128,
// TX sequence number count
parameter TX_SEQ_NUM_COUNT = 1,
// TX sequence number width
@ -95,8 +95,8 @@ module dma_if_pcie #
/*
* TLP input (completion)
*/
input wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] rx_cpl_tlp_data,
input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] rx_cpl_tlp_hdr,
input wire [TLP_DATA_WIDTH-1:0] rx_cpl_tlp_data,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_cpl_tlp_hdr,
input wire [TLP_SEG_COUNT*4-1:0] rx_cpl_tlp_error,
input wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_sop,
@ -106,7 +106,7 @@ module dma_if_pcie #
/*
* TLP output (read request)
*/
output wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_rd_req_tlp_hdr,
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_rd_req_tlp_hdr,
output wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_rd_req_tlp_seq,
output wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_sop,
@ -116,9 +116,9 @@ module dma_if_pcie #
/*
* TLP output (write request)
*/
output wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] tx_wr_req_tlp_data,
output wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] tx_wr_req_tlp_strb,
output wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr,
output wire [TLP_DATA_WIDTH-1:0] tx_wr_req_tlp_data,
output wire [TLP_STRB_WIDTH-1:0] tx_wr_req_tlp_strb,
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr,
output wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_wr_req_tlp_seq,
output wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_sop,
@ -252,9 +252,9 @@ module dma_if_pcie #
);
dma_if_pcie_rd #(
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.TX_SEQ_NUM_ENABLE(TX_SEQ_NUM_ENABLE),
@ -377,10 +377,10 @@ dma_if_pcie_rd_inst (
);
dma_if_pcie_wr #(
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.TX_SEQ_NUM_ENABLE(TX_SEQ_NUM_ENABLE),

19
fpga/lib/pcie/rtl/dma_if_pcie_rd.v
View File

@ -33,12 +33,12 @@ THE SOFTWARE.
*/
module dma_if_pcie_rd #
(
// TLP data width
parameter TLP_DATA_WIDTH = 256,
// TLP header width
parameter TLP_HDR_WIDTH = 128,
// TLP segment count
parameter TLP_SEG_COUNT = 1,
// TLP segment data width
parameter TLP_SEG_DATA_WIDTH = 256,
// TLP segment header width
parameter TLP_SEG_HDR_WIDTH = 128,
// TX sequence number count
parameter TX_SEQ_NUM_COUNT = 1,
// TX sequence number width
@ -83,8 +83,8 @@ module dma_if_pcie_rd #
/*
* TLP input (completion)
*/
input wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] rx_cpl_tlp_data,
input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] rx_cpl_tlp_hdr,
input wire [TLP_DATA_WIDTH-1:0] rx_cpl_tlp_data,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_cpl_tlp_hdr,
input wire [TLP_SEG_COUNT*4-1:0] rx_cpl_tlp_error,
input wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_sop,
@ -94,7 +94,7 @@ module dma_if_pcie_rd #
/*
* TLP output (read request)
*/
output wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_rd_req_tlp_hdr,
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_rd_req_tlp_hdr,
output wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_rd_req_tlp_seq,
output wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_sop,
@ -182,7 +182,6 @@ parameter RAM_DATA_WIDTH = RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH;
parameter RAM_WORD_WIDTH = RAM_SEG_BE_WIDTH;
parameter RAM_WORD_SIZE = RAM_SEG_DATA_WIDTH/RAM_WORD_WIDTH;
parameter TLP_DATA_WIDTH = TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH;
parameter TLP_DATA_WIDTH_BYTES = TLP_DATA_WIDTH/8;
parameter TLP_DATA_WIDTH_DWORDS = TLP_DATA_WIDTH/32;
@ -212,7 +211,7 @@ initial begin
$finish;
end
if (TLP_SEG_HDR_WIDTH != 128) begin
if (TLP_HDR_WIDTH != 128) begin
$error("Error: TLP segment header width must be 128 (instance %m)");
$finish;
end
@ -408,7 +407,7 @@ reg inc_active_tx;
reg rx_cpl_tlp_ready_reg = 1'b0, rx_cpl_tlp_ready_next;
reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_rd_req_tlp_hdr_reg = 0, tx_rd_req_tlp_hdr_next;
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_rd_req_tlp_hdr_reg = 0, tx_rd_req_tlp_hdr_next;
reg [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_valid_reg = 0, tx_rd_req_tlp_valid_next;
reg s_axis_read_desc_ready_reg = 1'b0, s_axis_read_desc_ready_next;

30
fpga/lib/pcie/rtl/dma_if_pcie_wr.v
View File

@ -33,14 +33,14 @@ THE SOFTWARE.
*/
module dma_if_pcie_wr #
(
// TLP data width
parameter TLP_DATA_WIDTH = 256,
// TLP strobe width
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
// TLP header width
parameter TLP_HDR_WIDTH = 128,
// TLP segment count
parameter TLP_SEG_COUNT = 1,
// TLP segment data width
parameter TLP_SEG_DATA_WIDTH = 256,
// TLP segment strobe width
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32,
// TLP segment header width
parameter TLP_SEG_HDR_WIDTH = 128,
// TX sequence number count
parameter TX_SEQ_NUM_COUNT = 1,
// TX sequence number width
@ -54,7 +54,7 @@ module dma_if_pcie_wr #
// RAM segment count
parameter RAM_SEG_COUNT = TLP_SEG_COUNT*2,
// RAM segment data width
parameter RAM_SEG_DATA_WIDTH = (TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH)*2/RAM_SEG_COUNT,
parameter RAM_SEG_DATA_WIDTH = TLP_DATA_WIDTH*2/RAM_SEG_COUNT,
// RAM segment byte enable width
parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8,
// RAM segment address width
@ -85,9 +85,9 @@ module dma_if_pcie_wr #
/*
* TLP output (write request)
*/
output wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] tx_wr_req_tlp_data,
output wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] tx_wr_req_tlp_strb,
output wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr,
output wire [TLP_DATA_WIDTH-1:0] tx_wr_req_tlp_data,
output wire [TLP_STRB_WIDTH-1:0] tx_wr_req_tlp_strb,
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr,
output wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_wr_req_tlp_seq,
output wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_sop,
@ -169,8 +169,6 @@ parameter RAM_DATA_WIDTH = RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH;
parameter RAM_WORD_WIDTH = RAM_SEG_BE_WIDTH;
parameter RAM_WORD_SIZE = RAM_SEG_DATA_WIDTH/RAM_WORD_WIDTH;
parameter TLP_DATA_WIDTH = TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH;
parameter TLP_STRB_WIDTH = TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH;
parameter TLP_DATA_WIDTH_BYTES = TLP_DATA_WIDTH/8;
parameter TLP_DATA_WIDTH_DWORDS = TLP_DATA_WIDTH/32;
@ -192,7 +190,7 @@ initial begin
$finish;
end
if (TLP_SEG_HDR_WIDTH != 128) begin
if (TLP_HDR_WIDTH != 128) begin
$error("Error: TLP segment header width must be 128 (instance %m)");
$finish;
end
@ -340,9 +338,9 @@ reg [TX_COUNT_WIDTH-1:0] active_tx_count_reg = {TX_COUNT_WIDTH{1'b0}}, active_tx
reg active_tx_count_av_reg = 1'b1, active_tx_count_av_next;
reg inc_active_tx;
reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] tx_wr_req_tlp_data_reg = 0, tx_wr_req_tlp_data_next;
reg [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] tx_wr_req_tlp_strb_reg = 0, tx_wr_req_tlp_strb_next;
reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr_reg = 0, tx_wr_req_tlp_hdr_next;
reg [TLP_DATA_WIDTH-1:0] tx_wr_req_tlp_data_reg = 0, tx_wr_req_tlp_data_next;
reg [TLP_STRB_WIDTH-1:0] tx_wr_req_tlp_strb_reg = 0, tx_wr_req_tlp_strb_next;
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr_reg = 0, tx_wr_req_tlp_hdr_next;
reg [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_wr_req_tlp_seq_reg = 0, tx_wr_req_tlp_seq_next;
reg [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_valid_reg = 0, tx_wr_req_tlp_valid_next;
reg [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_sop_reg = 0, tx_wr_req_tlp_sop_next;

170
fpga/lib/pcie/rtl/pcie_axi_master.v
View File

@ -33,16 +33,16 @@ THE SOFTWARE.
*/
module pcie_axi_master #
(
// TLP data width
parameter TLP_DATA_WIDTH = 256,
// TLP strobe width
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
// TLP header width
parameter TLP_HDR_WIDTH = 128,
// TLP segment count
parameter TLP_SEG_COUNT = 1,
// TLP segment data width
parameter TLP_SEG_DATA_WIDTH = 256,
// TLP segment strobe width
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32,
// TLP segment header width
parameter TLP_SEG_HDR_WIDTH = 128,
// Width of AXI data bus in bits
parameter AXI_DATA_WIDTH = TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH,
parameter AXI_DATA_WIDTH = TLP_DATA_WIDTH,
// Width of AXI address bus in bits
parameter AXI_ADDR_WIDTH = 64,
// Width of AXI wstrb (width of data bus in words)
@ -55,99 +55,99 @@ module pcie_axi_master #
parameter TLP_FORCE_64_BIT_ADDR = 0
)
(
input wire clk,
input wire rst,
input wire clk,
input wire rst,
/*
* TLP input (request)
*/
input wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] rx_req_tlp_data,
input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] rx_req_tlp_hdr,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_eop,
output wire rx_req_tlp_ready,
input wire [TLP_DATA_WIDTH-1:0] rx_req_tlp_data,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_req_tlp_hdr,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_eop,
output wire rx_req_tlp_ready,
/*
* TLP output (completion)
*/
output wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] tx_cpl_tlp_data,
output wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] tx_cpl_tlp_strb,
output wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_cpl_tlp_hdr,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop,
input wire tx_cpl_tlp_ready,
output wire [TLP_DATA_WIDTH-1:0] tx_cpl_tlp_data,
output wire [TLP_STRB_WIDTH-1:0] tx_cpl_tlp_strb,
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_cpl_tlp_hdr,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop,
input wire tx_cpl_tlp_ready,
/*
* AXI Master output
*/
output wire [AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [7:0] m_axi_awlen,
output wire [2:0] m_axi_awsize,
output wire [1:0] m_axi_awburst,
output wire m_axi_awlock,
output wire [3:0] m_axi_awcache,
output wire [2:0] m_axi_awprot,
output wire m_axi_awvalid,
input wire m_axi_awready,
output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [AXI_STRB_WIDTH-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire m_axi_wvalid,
input wire m_axi_wready,
input wire [AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [1:0] m_axi_bresp,
input wire m_axi_bvalid,
output wire m_axi_bready,
output wire [AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [7:0] m_axi_arlen,
output wire [2:0] m_axi_arsize,
output wire [1:0] m_axi_arburst,
output wire m_axi_arlock,
output wire [3:0] m_axi_arcache,
output wire [2:0] m_axi_arprot,
output wire m_axi_arvalid,
input wire m_axi_arready,
input wire [AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire m_axi_rvalid,
output wire m_axi_rready,
output wire [AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [7:0] m_axi_awlen,
output wire [2:0] m_axi_awsize,
output wire [1:0] m_axi_awburst,
output wire m_axi_awlock,
output wire [3:0] m_axi_awcache,
output wire [2:0] m_axi_awprot,
output wire m_axi_awvalid,
input wire m_axi_awready,
output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [AXI_STRB_WIDTH-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire m_axi_wvalid,
input wire m_axi_wready,
input wire [AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [1:0] m_axi_bresp,
input wire m_axi_bvalid,
output wire m_axi_bready,
output wire [AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [7:0] m_axi_arlen,
output wire [2:0] m_axi_arsize,
output wire [1:0] m_axi_arburst,
output wire m_axi_arlock,
output wire [3:0] m_axi_arcache,
output wire [2:0] m_axi_arprot,
output wire m_axi_arvalid,
input wire m_axi_arready,
input wire [AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire m_axi_rvalid,
output wire m_axi_rready,
/*
* Configuration
*/
input wire [15:0] completer_id,
input wire [2:0] max_payload_size,
input wire [15:0] completer_id,
input wire [2:0] max_payload_size,
/*
* Status
*/
output wire status_error_cor,
output wire status_error_uncor
output wire status_error_cor,
output wire status_error_uncor
);
wire [1:0] status_error_uncor_int;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] read_rx_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] read_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] read_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] read_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] read_rx_req_tlp_eop;
wire read_rx_req_tlp_ready;
wire [TLP_DATA_WIDTH-1:0] read_rx_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] read_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] read_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] read_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] read_rx_req_tlp_eop;
wire read_rx_req_tlp_ready;
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] write_rx_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] write_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] write_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] write_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] write_rx_req_tlp_eop;
wire write_rx_req_tlp_ready;
wire [TLP_DATA_WIDTH-1:0] write_rx_req_tlp_data;
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] write_rx_req_tlp_hdr;
wire [TLP_SEG_COUNT-1:0] write_rx_req_tlp_valid;
wire [TLP_SEG_COUNT-1:0] write_rx_req_tlp_sop;
wire [TLP_SEG_COUNT-1:0] write_rx_req_tlp_eop;
wire write_rx_req_tlp_ready;
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] match_tlp_hdr;
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] match_tlp_hdr;
wire [TLP_SEG_COUNT*2-1:0] select;
@ -156,8 +156,8 @@ generate
genvar n;
for (n = 0; n < TLP_SEG_COUNT; n = n + 1) begin
assign select[n*2+1] = match_tlp_hdr[n*TLP_SEG_HDR_WIDTH+120 +: 8] == 8'b010_00000 ||
match_tlp_hdr[n*TLP_SEG_HDR_WIDTH+120 +: 8] == 8'b011_00000;
assign select[n*2+1] = match_tlp_hdr[n*TLP_HDR_WIDTH+120 +: 8] == 8'b010_00000 ||
match_tlp_hdr[n*TLP_HDR_WIDTH+120 +: 8] == 8'b011_00000;
assign select[n*2+0] = !select[n*2+1];
end
@ -165,10 +165,10 @@ endgenerate
pcie_tlp_demux #(
.PORTS(2),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH)
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT)
)
pcie_tlp_demux_inst (
.clk(clk),
@ -218,10 +218,10 @@ pcie_tlp_demux_inst (
);
pcie_axi_master_rd #(
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
@ -287,9 +287,9 @@ pcie_axi_master_rd_inst (
);
pcie_axi_master_wr #(
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),

128
fpga/lib/pcie/rtl/pcie_axi_master_rd.v
View File

@ -33,16 +33,16 @@ THE SOFTWARE.
*/
module pcie_axi_master_rd #
(
// TLP data width
parameter TLP_DATA_WIDTH = 256,
// TLP strobe width
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
// TLP header width
parameter TLP_HDR_WIDTH = 128,
// TLP segment count
parameter TLP_SEG_COUNT = 1,
// TLP segment data width
parameter TLP_SEG_DATA_WIDTH = 256,
// TLP segment strobe width
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32,
// TLP segment header width
parameter TLP_SEG_HDR_WIDTH = 128,
// Width of AXI data bus in bits
parameter AXI_DATA_WIDTH = TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH,
parameter AXI_DATA_WIDTH = TLP_DATA_WIDTH,
// Width of AXI address bus in bits
parameter AXI_ADDR_WIDTH = 64,
// Width of AXI wstrb (width of data bus in words)
@ -55,60 +55,60 @@ module pcie_axi_master_rd #
parameter TLP_FORCE_64_BIT_ADDR = 0
)
(
input wire clk,
input wire rst,
input wire clk,
input wire rst,
/*
* TLP input (request)
*/
input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] rx_req_tlp_hdr,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_eop,
output wire rx_req_tlp_ready,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_req_tlp_hdr,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_eop,
output wire rx_req_tlp_ready,
/*
* TLP output (completion)
*/
output wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] tx_cpl_tlp_data,
output wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] tx_cpl_tlp_strb,
output wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_cpl_tlp_hdr,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop,
input wire tx_cpl_tlp_ready,
output wire [TLP_DATA_WIDTH-1:0] tx_cpl_tlp_data,
output wire [TLP_STRB_WIDTH-1:0] tx_cpl_tlp_strb,
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_cpl_tlp_hdr,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop,
input wire tx_cpl_tlp_ready,
/*
* AXI master interface
*/
output wire [AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [7:0] m_axi_arlen,
output wire [2:0] m_axi_arsize,
output wire [1:0] m_axi_arburst,
output wire m_axi_arlock,
output wire [3:0] m_axi_arcache,
output wire [2:0] m_axi_arprot,
output wire m_axi_arvalid,
input wire m_axi_arready,
input wire [AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire m_axi_rvalid,
output wire m_axi_rready,
output wire [AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [7:0] m_axi_arlen,
output wire [2:0] m_axi_arsize,
output wire [1:0] m_axi_arburst,
output wire m_axi_arlock,
output wire [3:0] m_axi_arcache,
output wire [2:0] m_axi_arprot,
output wire m_axi_arvalid,
input wire m_axi_arready,
input wire [AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire m_axi_rvalid,
output wire m_axi_rready,
/*
* Configuration
*/
input wire [15:0] completer_id,
input wire [2:0] max_payload_size,
input wire [15:0] completer_id,
input wire [2:0] max_payload_size,
/*
* Status
*/
output wire status_error_cor,
output wire status_error_uncor
output wire status_error_cor,
output wire status_error_uncor
);
parameter AXI_WORD_WIDTH = AXI_STRB_WIDTH;
@ -118,8 +118,6 @@ parameter AXI_MAX_BURST_SIZE = AXI_MAX_BURST_LEN*AXI_WORD_WIDTH;
parameter PAYLOAD_MAX = AXI_MAX_BURST_SIZE < 4096 ? $clog2(AXI_MAX_BURST_SIZE/128) : 5;
parameter TLP_DATA_WIDTH = TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH;
parameter TLP_STRB_WIDTH = TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH;
parameter TLP_DATA_WIDTH_BYTES = TLP_DATA_WIDTH/8;
parameter TLP_DATA_WIDTH_DWORDS = TLP_DATA_WIDTH/32;
@ -132,7 +130,7 @@ initial begin
$finish;
end
if (TLP_SEG_HDR_WIDTH != 128) begin
if (TLP_HDR_WIDTH != 128) begin
$error("Error: TLP segment header width must be 128 (instance %m)");
$finish;
end
@ -142,7 +140,7 @@ initial begin
$finish;
end
if (AXI_DATA_WIDTH != TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH) begin
if (AXI_DATA_WIDTH != TLP_DATA_WIDTH) begin
$error("Error: AXI interface width must match PCIe interface width (instance %m)");
$finish;
end
@ -274,14 +272,14 @@ reg status_error_cor_reg = 1'b0, status_error_cor_next;
reg status_error_uncor_reg = 1'b0, status_error_uncor_next;
// internal datapath
reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] tx_cpl_tlp_data_int;
reg [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] tx_cpl_tlp_strb_int;
reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_cpl_tlp_hdr_int;
reg [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid_int;
reg [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop_int;
reg [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop_int;
reg tx_cpl_tlp_ready_int_reg = 1'b0;
wire tx_cpl_tlp_ready_int_early;
reg [TLP_DATA_WIDTH-1:0] tx_cpl_tlp_data_int;
reg [TLP_STRB_WIDTH-1:0] tx_cpl_tlp_strb_int;
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_cpl_tlp_hdr_int;
reg [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid_int;
reg [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop_int;
reg [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop_int;
reg tx_cpl_tlp_ready_int_reg = 1'b0;
wire tx_cpl_tlp_ready_int_early;
assign rx_req_tlp_ready = rx_req_tlp_ready_reg;
@ -887,19 +885,19 @@ always @(posedge clk) begin
end
// output datapath logic
reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] tx_cpl_tlp_data_reg = 0;
reg [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] tx_cpl_tlp_strb_reg = 0;
reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_cpl_tlp_hdr_reg = 0;
reg [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid_reg = 0, tx_cpl_tlp_valid_next;
reg [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop_reg = 0;
reg [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop_reg = 0;
reg [TLP_DATA_WIDTH-1:0] tx_cpl_tlp_data_reg = 0;
reg [TLP_STRB_WIDTH-1:0] tx_cpl_tlp_strb_reg = 0;
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_cpl_tlp_hdr_reg = 0;
reg [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid_reg = 0, tx_cpl_tlp_valid_next;
reg [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop_reg = 0;
reg [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop_reg = 0;
reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] temp_tx_cpl_tlp_data_reg = 0;
reg [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] temp_tx_cpl_tlp_strb_reg = 0;
reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] temp_tx_cpl_tlp_hdr_reg = 0;
reg [TLP_SEG_COUNT-1:0] temp_tx_cpl_tlp_valid_reg = 0, temp_tx_cpl_tlp_valid_next;
reg [TLP_SEG_COUNT-1:0] temp_tx_cpl_tlp_sop_reg = 0;
reg [TLP_SEG_COUNT-1:0] temp_tx_cpl_tlp_eop_reg = 0;
reg [TLP_DATA_WIDTH-1:0] temp_tx_cpl_tlp_data_reg = 0;
reg [TLP_STRB_WIDTH-1:0] temp_tx_cpl_tlp_strb_reg = 0;
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] temp_tx_cpl_tlp_hdr_reg = 0;
reg [TLP_SEG_COUNT-1:0] temp_tx_cpl_tlp_valid_reg = 0, temp_tx_cpl_tlp_valid_next;
reg [TLP_SEG_COUNT-1:0] temp_tx_cpl_tlp_sop_reg = 0;
reg [TLP_SEG_COUNT-1:0] temp_tx_cpl_tlp_eop_reg = 0;
// datapath control
reg store_axis_int_to_output;

71
fpga/lib/pcie/rtl/pcie_axi_master_wr.v
View File

@ -33,14 +33,14 @@ THE SOFTWARE.
*/
module pcie_axi_master_wr #
(
// TLP data width
parameter TLP_DATA_WIDTH = 256,
// TLP header width
parameter TLP_HDR_WIDTH = 128,
// TLP segment count
parameter TLP_SEG_COUNT = 1,
// TLP segment data width
parameter TLP_SEG_DATA_WIDTH = 256,
// TLP segment header width
parameter TLP_SEG_HDR_WIDTH = 128,
// Width of AXI data bus in bits
parameter AXI_DATA_WIDTH = TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH,
parameter AXI_DATA_WIDTH = TLP_DATA_WIDTH,
// Width of AXI address bus in bits
parameter AXI_ADDR_WIDTH = 64,
// Width of AXI wstrb (width of data bus in words)
@ -53,46 +53,46 @@ module pcie_axi_master_wr #
parameter TLP_FORCE_64_BIT_ADDR = 0
)
(
input wire clk,
input wire rst,
input wire clk,
input wire rst,
/*
* TLP input (request)
*/
input wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] rx_req_tlp_data,
input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] rx_req_tlp_hdr,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_eop,
output wire rx_req_tlp_ready,
input wire [TLP_DATA_WIDTH-1:0] rx_req_tlp_data,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_req_tlp_hdr,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_eop,
output wire rx_req_tlp_ready,
/*
* AXI Master output
*/
output wire [AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [7:0] m_axi_awlen,
output wire [2:0] m_axi_awsize,
output wire [1:0] m_axi_awburst,
output wire m_axi_awlock,
output wire [3:0] m_axi_awcache,
output wire [2:0] m_axi_awprot,
output wire m_axi_awvalid,
input wire m_axi_awready,
output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [AXI_STRB_WIDTH-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire m_axi_wvalid,
input wire m_axi_wready,
input wire [AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [1:0] m_axi_bresp,
input wire m_axi_bvalid,
output wire m_axi_bready,
output wire [AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [7:0] m_axi_awlen,
output wire [2:0] m_axi_awsize,
output wire [1:0] m_axi_awburst,
output wire m_axi_awlock,
output wire [3:0] m_axi_awcache,
output wire [2:0] m_axi_awprot,
output wire m_axi_awvalid,
input wire m_axi_awready,
output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [AXI_STRB_WIDTH-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire m_axi_wvalid,
input wire m_axi_wready,
input wire [AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [1:0] m_axi_bresp,
input wire m_axi_bvalid,
output wire m_axi_bready,
/*
* Status
*/
output wire status_error_uncor
output wire status_error_uncor
);
parameter AXI_WORD_WIDTH = AXI_STRB_WIDTH;
@ -100,7 +100,6 @@ parameter AXI_WORD_SIZE = AXI_DATA_WIDTH/AXI_WORD_WIDTH;
parameter AXI_BURST_SIZE = $clog2(AXI_STRB_WIDTH);
parameter AXI_MAX_BURST_SIZE = AXI_MAX_BURST_LEN*AXI_WORD_WIDTH;
parameter TLP_DATA_WIDTH = TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH;
parameter TLP_DATA_WIDTH_BYTES = TLP_DATA_WIDTH/8;
parameter TLP_DATA_WIDTH_DWORDS = TLP_DATA_WIDTH/32;
@ -115,12 +114,12 @@ initial begin
$finish;
end
if (TLP_SEG_HDR_WIDTH != 128) begin
if (TLP_HDR_WIDTH != 128) begin
$error("Error: TLP segment header width must be 128 (instance %m)");
$finish;
end
if (AXI_DATA_WIDTH != TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH) begin
if (AXI_DATA_WIDTH != TLP_DATA_WIDTH) begin
$error("Error: AXI interface width must match PCIe interface width (instance %m)");
$finish;
end

96
fpga/lib/pcie/rtl/pcie_axil_master.v
View File

@ -33,14 +33,14 @@ THE SOFTWARE.
*/
module pcie_axil_master #
(
// TLP data width
parameter TLP_DATA_WIDTH = 256,
// TLP strobe width
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
// TLP header width
parameter TLP_HDR_WIDTH = 128,
// TLP segment count
parameter TLP_SEG_COUNT = 1,
// TLP segment data width
parameter TLP_SEG_DATA_WIDTH = 256,
// TLP segment strobe width
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32,
// TLP segment header width
parameter TLP_SEG_HDR_WIDTH = 128,
// Width of AXI lite data bus in bits
parameter AXIL_DATA_WIDTH = 32,
// Width of AXI lite address bus in bits
@ -51,67 +51,65 @@ module pcie_axil_master #
parameter TLP_FORCE_64_BIT_ADDR = 0
)
(
input wire clk,
input wire rst,
input wire clk,
input wire rst,
/*
* TLP input (request)
*/
input wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] rx_req_tlp_data,
input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] rx_req_tlp_hdr,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_eop,
output wire rx_req_tlp_ready,
input wire [TLP_DATA_WIDTH-1:0] rx_req_tlp_data,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_req_tlp_hdr,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_eop,
output wire rx_req_tlp_ready,
/*
* TLP output (completion)
*/
output wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] tx_cpl_tlp_data,
output wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] tx_cpl_tlp_strb,
output wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_cpl_tlp_hdr,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop,
input wire tx_cpl_tlp_ready,
output wire [TLP_DATA_WIDTH-1:0] tx_cpl_tlp_data,
output wire [TLP_STRB_WIDTH-1:0] tx_cpl_tlp_strb,
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_cpl_tlp_hdr,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop,
input wire tx_cpl_tlp_ready,
/*
* AXI Lite Master output
*/
output wire [AXIL_ADDR_WIDTH-1:0] m_axil_awaddr,
output wire [2:0] m_axil_awprot,
output wire m_axil_awvalid,
input wire m_axil_awready,
output wire [AXIL_DATA_WIDTH-1:0] m_axil_wdata,
output wire [AXIL_STRB_WIDTH-1:0] m_axil_wstrb,
output wire m_axil_wvalid,
input wire m_axil_wready,
input wire [1:0] m_axil_bresp,
input wire m_axil_bvalid,
output wire m_axil_bready,
output wire [AXIL_ADDR_WIDTH-1:0] m_axil_araddr,
output wire [2:0] m_axil_arprot,
output wire m_axil_arvalid,
input wire m_axil_arready,
input wire [AXIL_DATA_WIDTH-1:0] m_axil_rdata,
input wire [1:0] m_axil_rresp,
input wire m_axil_rvalid,
output wire m_axil_rready,
output wire [AXIL_ADDR_WIDTH-1:0] m_axil_awaddr,
output wire [2:0] m_axil_awprot,
output wire m_axil_awvalid,
input wire m_axil_awready,
output wire [AXIL_DATA_WIDTH-1:0] m_axil_wdata,
output wire [AXIL_STRB_WIDTH-1:0] m_axil_wstrb,
output wire m_axil_wvalid,
input wire m_axil_wready,
input wire [1:0] m_axil_bresp,
input wire m_axil_bvalid,
output wire m_axil_bready,
output wire [AXIL_ADDR_WIDTH-1:0] m_axil_araddr,
output wire [2:0] m_axil_arprot,
output wire m_axil_arvalid,
input wire m_axil_arready,
input wire [AXIL_DATA_WIDTH-1:0] m_axil_rdata,
input wire [1:0] m_axil_rresp,
input wire m_axil_rvalid,
output wire m_axil_rready,
/*
* Configuration
*/
input wire [15:0] completer_id,
input wire [15:0] completer_id,
/*
* Status
*/
output wire status_error_cor,
output wire status_error_uncor
output wire status_error_cor,
output wire status_error_uncor
);
parameter TLP_DATA_WIDTH = TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH;
parameter TLP_STRB_WIDTH = TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH;
parameter TLP_DATA_WIDTH_BYTES = TLP_DATA_WIDTH/8;
parameter TLP_DATA_WIDTH_DWORDS = TLP_DATA_WIDTH/32;
@ -126,7 +124,7 @@ initial begin
$finish;
end
if (TLP_SEG_HDR_WIDTH != 128) begin
if (TLP_HDR_WIDTH != 128) begin
$error("Error: TLP segment header width must be 128 (instance %m)");
$finish;
end
@ -276,9 +274,9 @@ reg resp_fifo_rd_valid_reg = 1'b0, resp_fifo_rd_valid_next;
reg rx_req_tlp_ready_reg = 1'b0, rx_req_tlp_ready_next;
reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] tx_cpl_tlp_data_reg = 0, tx_cpl_tlp_data_next;
reg [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] tx_cpl_tlp_strb_reg = 0, tx_cpl_tlp_strb_next;
reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_cpl_tlp_hdr_reg = 0, tx_cpl_tlp_hdr_next;
reg [TLP_DATA_WIDTH-1:0] tx_cpl_tlp_data_reg = 0, tx_cpl_tlp_data_next;
reg [TLP_STRB_WIDTH-1:0] tx_cpl_tlp_strb_reg = 0, tx_cpl_tlp_strb_next;
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_cpl_tlp_hdr_reg = 0, tx_cpl_tlp_hdr_next;
reg [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid_reg = 0, tx_cpl_tlp_valid_next;
reg [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop_reg = 0, tx_cpl_tlp_sop_next;
reg [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop_reg = 0, tx_cpl_tlp_eop_next;

96
fpga/lib/pcie/rtl/pcie_axil_master_minimal.v
View File

@ -33,14 +33,14 @@ THE SOFTWARE.
*/
module pcie_axil_master_minimal #
(
// TLP data width
parameter TLP_DATA_WIDTH = 256,
// TLP strobe width
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
// TLP header width
parameter TLP_HDR_WIDTH = 128,
// TLP segment count
parameter TLP_SEG_COUNT = 1,
// TLP segment data width
parameter TLP_SEG_DATA_WIDTH = 256,
// TLP segment strobe width
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32,
// TLP segment header width
parameter TLP_SEG_HDR_WIDTH = 128,
// Width of AXI lite data bus in bits
parameter AXIL_DATA_WIDTH = 32,
// Width of AXI lite address bus in bits
@ -51,67 +51,65 @@ module pcie_axil_master_minimal #
parameter TLP_FORCE_64_BIT_ADDR = 0
)
(
input wire clk,
input wire rst,
input wire clk,
input wire rst,
/*
* TLP input (request)
*/
input wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] rx_req_tlp_data,
input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] rx_req_tlp_hdr,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_eop,
output wire rx_req_tlp_ready,
input wire [TLP_DATA_WIDTH-1:0] rx_req_tlp_data,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_req_tlp_hdr,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] rx_req_tlp_eop,
output wire rx_req_tlp_ready,
/*
* TLP output (completion)
*/
output wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] tx_cpl_tlp_data,
output wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] tx_cpl_tlp_strb,
output wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_cpl_tlp_hdr,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop,
input wire tx_cpl_tlp_ready,
output wire [TLP_DATA_WIDTH-1:0] tx_cpl_tlp_data,
output wire [TLP_STRB_WIDTH-1:0] tx_cpl_tlp_strb,
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_cpl_tlp_hdr,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop,
output wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop,
input wire tx_cpl_tlp_ready,
/*
* AXI Lite Master output
*/
output wire [AXIL_ADDR_WIDTH-1:0] m_axil_awaddr,
output wire [2:0] m_axil_awprot,
output wire m_axil_awvalid,
input wire m_axil_awready,
output wire [AXIL_DATA_WIDTH-1:0] m_axil_wdata,
output wire [AXIL_STRB_WIDTH-1:0] m_axil_wstrb,
output wire m_axil_wvalid,
input wire m_axil_wready,
input wire [1:0] m_axil_bresp,
input wire m_axil_bvalid,
output wire m_axil_bready,
output wire [AXIL_ADDR_WIDTH-1:0] m_axil_araddr,
output wire [2:0] m_axil_arprot,
output wire m_axil_arvalid,
input wire m_axil_arready,
input wire [AXIL_DATA_WIDTH-1:0] m_axil_rdata,
input wire [1:0] m_axil_rresp,
input wire m_axil_rvalid,
output wire m_axil_rready,
output wire [AXIL_ADDR_WIDTH-1:0] m_axil_awaddr,
output wire [2:0] m_axil_awprot,
output wire m_axil_awvalid,
input wire m_axil_awready,
output wire [AXIL_DATA_WIDTH-1:0] m_axil_wdata,
output wire [AXIL_STRB_WIDTH-1:0] m_axil_wstrb,
output wire m_axil_wvalid,
input wire m_axil_wready,
input wire [1:0] m_axil_bresp,
input wire m_axil_bvalid,
output wire m_axil_bready,
output wire [AXIL_ADDR_WIDTH-1:0] m_axil_araddr,
output wire [2:0] m_axil_arprot,
output wire m_axil_arvalid,
input wire m_axil_arready,
input wire [AXIL_DATA_WIDTH-1:0] m_axil_rdata,
input wire [1:0] m_axil_rresp,
input wire m_axil_rvalid,
output wire m_axil_rready,
/*
* Configuration
*/
input wire [15:0] completer_id,
input wire [15:0] completer_id,
/*
* Status
*/
output wire status_error_cor,
output wire status_error_uncor
output wire status_error_cor,
output wire status_error_uncor
);
parameter TLP_DATA_WIDTH = TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH;
parameter TLP_STRB_WIDTH = TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH;
parameter TLP_DATA_WIDTH_BYTES = TLP_DATA_WIDTH/8;
parameter TLP_DATA_WIDTH_DWORDS = TLP_DATA_WIDTH/32;
@ -124,7 +122,7 @@ initial begin
$finish;
end
if (TLP_SEG_HDR_WIDTH != 128) begin
if (TLP_HDR_WIDTH != 128) begin
$error("Error: TLP segment header width must be 128 (instance %m)");
$finish;
end
@ -238,9 +236,9 @@ reg resp_fifo_rd_valid_reg = 1'b0, resp_fifo_rd_valid_next;
reg rx_req_tlp_ready_reg = 1'b0, rx_req_tlp_ready_next;
reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] tx_cpl_tlp_data_reg = 0, tx_cpl_tlp_data_next;
reg [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] tx_cpl_tlp_strb_reg = 0, tx_cpl_tlp_strb_next;
reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_cpl_tlp_hdr_reg = 0, tx_cpl_tlp_hdr_next;
reg [TLP_DATA_WIDTH-1:0] tx_cpl_tlp_data_reg = 0, tx_cpl_tlp_data_next;
reg [TLP_STRB_WIDTH-1:0] tx_cpl_tlp_strb_reg = 0, tx_cpl_tlp_strb_next;
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_cpl_tlp_hdr_reg = 0, tx_cpl_tlp_hdr_next;
reg [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid_reg = 0, tx_cpl_tlp_valid_next;
reg [AXIL_ADDR_WIDTH-1:0] m_axil_addr_reg = {AXIL_ADDR_WIDTH{1'b0}}, m_axil_addr_next;

78
fpga/lib/pcie/rtl/pcie_msix.v
View File

@ -42,63 +42,63 @@ module pcie_msix #
parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
// TLP interface configuration
parameter TLP_DATA_WIDTH = 256,
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
parameter TLP_HDR_WIDTH = 128,
parameter TLP_SEG_COUNT = 1,
parameter TLP_SEG_DATA_WIDTH = 256,
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32,
parameter TLP_SEG_HDR_WIDTH = 128,
parameter TLP_FORCE_64_BIT_ADDR = 0
)
(
input wire clk,
input wire rst,
input wire clk,
input wire rst,
/*
* AXI lite interface for MSI-X tables
*/
input wire [AXIL_ADDR_WIDTH-1:0] s_axil_awaddr,
input wire [2:0] s_axil_awprot,
input wire s_axil_awvalid,
output wire s_axil_awready,
input wire [AXIL_DATA_WIDTH-1:0] s_axil_wdata,
input wire [AXIL_STRB_WIDTH-1:0] s_axil_wstrb,
input wire s_axil_wvalid,
output wire s_axil_wready,
output wire [1:0] s_axil_bresp,
output wire s_axil_bvalid,
input wire s_axil_bready,
input wire [AXIL_ADDR_WIDTH-1:0] s_axil_araddr,
input wire [2:0] s_axil_arprot,
input wire s_axil_arvalid,
output wire s_axil_arready,
output wire [AXIL_DATA_WIDTH-1:0] s_axil_rdata,
output wire [1:0] s_axil_rresp,
output wire s_axil_rvalid,
input wire s_axil_rready,
input wire [AXIL_ADDR_WIDTH-1:0] s_axil_awaddr,
input wire [2:0] s_axil_awprot,
input wire s_axil_awvalid,
output wire s_axil_awready,
input wire [AXIL_DATA_WIDTH-1:0] s_axil_wdata,
input wire [AXIL_STRB_WIDTH-1:0] s_axil_wstrb,
input wire s_axil_wvalid,
output wire s_axil_wready,
output wire [1:0] s_axil_bresp,
output wire s_axil_bvalid,
input wire s_axil_bready,
input wire [AXIL_ADDR_WIDTH-1:0] s_axil_araddr,
input wire [2:0] s_axil_arprot,
input wire s_axil_arvalid,
output wire s_axil_arready,
output wire [AXIL_DATA_WIDTH-1:0] s_axil_rdata,
output wire [1:0] s_axil_rresp,
output wire s_axil_rvalid,
input wire s_axil_rready,
/*
* Interrupt request input
*/
input wire [IRQ_INDEX_WIDTH-1:0] irq_index,
input wire irq_valid,
output wire irq_ready,
input wire [IRQ_INDEX_WIDTH-1:0] irq_index,
input wire irq_valid,
output wire irq_ready,
/*
* Memory write TLP output
*/
output wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] tx_wr_req_tlp_data,
output wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] tx_wr_req_tlp_strb,
output wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr,
output wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_sop,
output wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_eop,
input wire tx_wr_req_tlp_ready,
output wire [TLP_DATA_WIDTH-1:0] tx_wr_req_tlp_data,
output wire [TLP_STRB_WIDTH-1:0] tx_wr_req_tlp_strb,
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr,
output wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_sop,
output wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_eop,
input wire tx_wr_req_tlp_ready,
/*
* Configuration
*/
input wire [15:0] requester_id,
input wire msix_enable,
input wire msix_mask
input wire [15:0] requester_id,
input wire msix_enable,
input wire msix_mask
);
parameter TBL_ADDR_WIDTH = IRQ_INDEX_WIDTH+1;
@ -184,8 +184,8 @@ reg s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next;
reg irq_ready_reg = 1'b0, irq_ready_next;
reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] tx_wr_req_tlp_data_reg = 0, tx_wr_req_tlp_data_next;
reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr_reg = 0, tx_wr_req_tlp_hdr_next;
reg [TLP_DATA_WIDTH-1:0] tx_wr_req_tlp_data_reg = 0, tx_wr_req_tlp_data_next;
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr_reg = 0, tx_wr_req_tlp_hdr_next;
reg [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_valid_reg = 0, tx_wr_req_tlp_valid_next;
// MSI-X table

216
fpga/lib/pcie/rtl/pcie_s10_if.v
View File

@ -39,14 +39,14 @@ module pcie_s10_if #
parameter SEG_DATA_WIDTH = 256,
// H-Tile/L-Tile AVST segment empty signal width
parameter SEG_EMPTY_WIDTH = $clog2(SEG_DATA_WIDTH/32),
// TLP data width
parameter TLP_DATA_WIDTH = SEG_COUNT*SEG_DATA_WIDTH,
// TLP strobe width
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
// TLP header width
parameter TLP_HDR_WIDTH = 128,
// TLP segment count
parameter TLP_SEG_COUNT = 1,
// TLP segment data width
parameter TLP_SEG_DATA_WIDTH = (SEG_COUNT*SEG_DATA_WIDTH)/TLP_SEG_COUNT,
// TLP segment strobe width
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32,
// TLP segment header width
parameter TLP_SEG_HDR_WIDTH = 128,
// TX sequence number width
parameter TX_SEQ_NUM_WIDTH = 6,
// Tile selection (0 for H-Tile, 1 for L-Tile)
@ -66,166 +66,166 @@ module pcie_s10_if #
parameter MSI_COUNT = 32
)
(
input wire clk,
input wire rst,
input wire clk,
input wire rst,
/*
* H-Tile/L-Tile RX AVST interface
*/
input wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] rx_st_data,
input wire [SEG_COUNT*SEG_EMPTY_WIDTH-1:0] rx_st_empty,
input wire [SEG_COUNT-1:0] rx_st_sop,
input wire [SEG_COUNT-1:0] rx_st_eop,
input wire [SEG_COUNT-1:0] rx_st_valid,
output wire rx_st_ready,
input wire [SEG_COUNT-1:0] rx_st_vf_active,
input wire [SEG_COUNT*2-1:0] rx_st_func_num,
input wire [SEG_COUNT*11-1:0] rx_st_vf_num,
input wire [SEG_COUNT*3-1:0] rx_st_bar_range,
input wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] rx_st_data,
input wire [SEG_COUNT*SEG_EMPTY_WIDTH-1:0] rx_st_empty,
input wire [SEG_COUNT-1:0] rx_st_sop,
input wire [SEG_COUNT-1:0] rx_st_eop,
input wire [SEG_COUNT-1:0] rx_st_valid,
output wire rx_st_ready,
input wire [SEG_COUNT-1:0] rx_st_vf_active,
input wire [SEG_COUNT*2-1:0] rx_st_func_num,
input wire [SEG_COUNT*11-1:0] rx_st_vf_num,
input wire [SEG_COUNT*3-1:0] rx_st_bar_range,
/*
* H-Tile/L-Tile TX AVST interface
*/
output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] tx_st_data,
output wire [SEG_COUNT-1:0] tx_st_sop,
output wire [SEG_COUNT-1:0] tx_st_eop,
output wire [SEG_COUNT-1:0] tx_st_valid,
input wire tx_st_ready,
output wire [SEG_COUNT-1:0] tx_st_err,
output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] tx_st_data,
output wire [SEG_COUNT-1:0] tx_st_sop,
output wire [SEG_COUNT-1:0] tx_st_eop,
output wire [SEG_COUNT-1:0] tx_st_valid,
input wire tx_st_ready,
output wire [SEG_COUNT-1:0] tx_st_err,
/*
* H-Tile/L-Tile TX flow control
*/
input wire [7:0] tx_ph_cdts,
input wire [11:0] tx_pd_cdts,
input wire [7:0] tx_nph_cdts,
input wire [11:0] tx_npd_cdts,
input wire [7:0] tx_cplh_cdts,
input wire [11:0] tx_cpld_cdts,
input wire [SEG_COUNT-1:0] tx_hdr_cdts_consumed,
input wire [SEG_COUNT-1:0] tx_data_cdts_consumed,
input wire [SEG_COUNT*2-1:0] tx_cdts_type,
input wire [SEG_COUNT*1-1:0] tx_cdts_data_value,
input wire [7:0] tx_ph_cdts,
input wire [11:0] tx_pd_cdts,
input wire [7:0] tx_nph_cdts,
input wire [11:0] tx_npd_cdts,
input wire [7:0] tx_cplh_cdts,
input wire [11:0] tx_cpld_cdts,
input wire [SEG_COUNT-1:0] tx_hdr_cdts_consumed,
input wire [SEG_COUNT-1:0] tx_data_cdts_consumed,
input wire [SEG_COUNT*2-1:0] tx_cdts_type,
input wire [SEG_COUNT*1-1:0] tx_cdts_data_value,
/*
* H-Tile/L-Tile MSI interrupt interface
*/
output wire app_msi_req,
input wire app_msi_ack,
output wire [2:0] app_msi_tc,
output wire [4:0] app_msi_num,
output wire [1:0] app_msi_func_num,
output wire app_msi_req,
input wire app_msi_ack,
output wire [2:0] app_msi_tc,
output wire [4:0] app_msi_num,
output wire [1:0] app_msi_func_num,
/*
* H-Tile/L-Tile configuration interface
*/
input wire [31:0] tl_cfg_ctl,
input wire [4:0] tl_cfg_add,
input wire [1:0] tl_cfg_func,
input wire [31:0] tl_cfg_ctl,
input wire [4:0] tl_cfg_add,
input wire [1:0] tl_cfg_func,
/*
* TLP output (request to BAR)
*/
output wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] rx_req_tlp_data,
output wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] rx_req_tlp_hdr,
output wire [TLP_SEG_COUNT*3-1:0] rx_req_tlp_bar_id,
output wire [TLP_SEG_COUNT*8-1:0] rx_req_tlp_func_num,
output wire [TLP_SEG_COUNT-1:0] rx_req_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] rx_req_tlp_sop,
output wire [TLP_SEG_COUNT-1:0] rx_req_tlp_eop,
input wire rx_req_tlp_ready,
output wire [TLP_DATA_WIDTH-1:0] rx_req_tlp_data,
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_req_tlp_hdr,
output wire [TLP_SEG_COUNT*3-1:0] rx_req_tlp_bar_id,
output wire [TLP_SEG_COUNT*8-1:0] rx_req_tlp_func_num,
output wire [TLP_SEG_COUNT-1:0] rx_req_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] rx_req_tlp_sop,
output wire [TLP_SEG_COUNT-1:0] rx_req_tlp_eop,
input wire rx_req_tlp_ready,
/*
* TLP output (completion to DMA)
*/
output wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] rx_cpl_tlp_data,
output wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] rx_cpl_tlp_hdr,
output wire [TLP_SEG_COUNT*4-1:0] rx_cpl_tlp_error,
output wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_sop,
output wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_eop,
input wire rx_cpl_tlp_ready,
output wire [TLP_DATA_WIDTH-1:0] rx_cpl_tlp_data,
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_cpl_tlp_hdr,
output wire [TLP_SEG_COUNT*4-1:0] rx_cpl_tlp_error,
output wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_sop,
output wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_eop,
input wire rx_cpl_tlp_ready,
/*
* TLP input (read request from DMA)
*/
input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_rd_req_tlp_hdr,
input wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_rd_req_tlp_seq,
input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_eop,
output wire tx_rd_req_tlp_ready,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_rd_req_tlp_hdr,
input wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_rd_req_tlp_seq,
input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_eop,
output wire tx_rd_req_tlp_ready,
/*
* Transmit sequence number output (DMA read request)
*/
output wire [SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] m_axis_rd_req_tx_seq_num,
output wire [SEG_COUNT-1:0] m_axis_rd_req_tx_seq_num_valid,
output wire [SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] m_axis_rd_req_tx_seq_num,
output wire [SEG_COUNT-1:0] m_axis_rd_req_tx_seq_num_valid,
/*
* TLP input (write request from DMA)
*/
input wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] tx_wr_req_tlp_data,
input wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] tx_wr_req_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr,
input wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_wr_req_tlp_seq,
input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_eop,
output wire tx_wr_req_tlp_ready,
input wire [TLP_DATA_WIDTH-1:0] tx_wr_req_tlp_data,
input wire [TLP_STRB_WIDTH-1:0] tx_wr_req_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr,
input wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_wr_req_tlp_seq,
input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_eop,
output wire tx_wr_req_tlp_ready,
/*
* Transmit sequence number output (DMA write request)
*/
output wire [SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] m_axis_wr_req_tx_seq_num,
output wire [SEG_COUNT-1:0] m_axis_wr_req_tx_seq_num_valid,
output wire [SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] m_axis_wr_req_tx_seq_num,
output wire [SEG_COUNT-1:0] m_axis_wr_req_tx_seq_num_valid,
/*
* TLP input (completion from BAR)
*/
input wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] tx_cpl_tlp_data,
input wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] tx_cpl_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_cpl_tlp_hdr,
input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop,
output wire tx_cpl_tlp_ready,
input wire [TLP_DATA_WIDTH-1:0] tx_cpl_tlp_data,
input wire [TLP_STRB_WIDTH-1:0] tx_cpl_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_cpl_tlp_hdr,
input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop,
output wire tx_cpl_tlp_ready,
/*
* TLP input (write request from MSI)
*/
input wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] tx_msi_wr_req_tlp_data,
input wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] tx_msi_wr_req_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_msi_wr_req_tlp_hdr,
input wire [TLP_SEG_COUNT-1:0] tx_msi_wr_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_msi_wr_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] tx_msi_wr_req_tlp_eop,
output wire tx_msi_wr_req_tlp_ready,
input wire [TLP_DATA_WIDTH-1:0] tx_msi_wr_req_tlp_data,
input wire [TLP_STRB_WIDTH-1:0] tx_msi_wr_req_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_msi_wr_req_tlp_hdr,
input wire [TLP_SEG_COUNT-1:0] tx_msi_wr_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_msi_wr_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] tx_msi_wr_req_tlp_eop,
output wire tx_msi_wr_req_tlp_ready,
/*
* Flow control
*/
output wire [7:0] tx_fc_ph_av,
output wire [11:0] tx_fc_pd_av,
output wire [7:0] tx_fc_nph_av,
output wire [11:0] tx_fc_npd_av,
output wire [7:0] tx_fc_cplh_av,
output wire [11:0] tx_fc_cpld_av,
output wire [7:0] tx_fc_ph_av,
output wire [11:0] tx_fc_pd_av,
output wire [7:0] tx_fc_nph_av,
output wire [11:0] tx_fc_npd_av,
output wire [7:0] tx_fc_cplh_av,
output wire [11:0] tx_fc_cpld_av,
/*
* Configuration outputs
*/
output wire [F_COUNT-1:0] ext_tag_enable,
output wire [7:0] bus_num,
output wire [F_COUNT*3-1:0] max_read_request_size,
output wire [F_COUNT*3-1:0] max_payload_size,
output wire [F_COUNT*3-1:0] msix_enable,
output wire [F_COUNT*3-1:0] msix_mask,
output wire [F_COUNT-1:0] ext_tag_enable,
output wire [7:0] bus_num,
output wire [F_COUNT*3-1:0] max_read_request_size,
output wire [F_COUNT*3-1:0] max_payload_size,
output wire [F_COUNT*3-1:0] msix_enable,
output wire [F_COUNT*3-1:0] msix_mask,
/*
* MSI request inputs
*/
input wire [MSI_COUNT-1:0] msi_irq
input wire [MSI_COUNT-1:0] msi_irq
);
wire [PF_COUNT-1:0] cfg_msi_enable;
@ -235,10 +235,10 @@ wire [PF_COUNT*32-1:0] cfg_msi_mask;
pcie_s10_if_rx #(
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.IO_BAR_INDEX(IO_BAR_INDEX)
)
pcie_s10_if_rx_inst (
@ -286,10 +286,10 @@ pcie_s10_if_rx_inst (
pcie_s10_if_tx #(
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH)
)
pcie_s10_if_tx_inst (

92
fpga/lib/pcie/rtl/pcie_s10_if_rx.v
View File

@ -39,14 +39,14 @@ module pcie_s10_if_rx #
parameter SEG_DATA_WIDTH = 256,
// H-Tile/L-Tile AVST segment empty signal width
parameter SEG_EMPTY_WIDTH = $clog2(SEG_DATA_WIDTH/32),
// TLP data width
parameter TLP_DATA_WIDTH = SEG_COUNT*SEG_DATA_WIDTH,
// TLP strobe width
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
// TLP header width
parameter TLP_HDR_WIDTH = 128,
// TLP segment count
parameter TLP_SEG_COUNT = 1,
// TLP segment data width
parameter TLP_SEG_DATA_WIDTH = (SEG_COUNT*SEG_DATA_WIDTH)/TLP_SEG_COUNT,
// TLP segment strobe width
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32,
// TLP segment header width
parameter TLP_SEG_HDR_WIDTH = 128,
// IO bar index
// rx_st_bar_range = 6 is mapped to IO_BAR_INDEX on rx_req_tlp_bar_id
parameter IO_BAR_INDEX = 5
@ -70,8 +70,8 @@ module pcie_s10_if_rx #
/*
* TLP output (request to BAR)
*/
output wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] rx_req_tlp_data,
output wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] rx_req_tlp_hdr,
output wire [TLP_DATA_WIDTH-1:0] rx_req_tlp_data,
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_req_tlp_hdr,
output wire [TLP_SEG_COUNT*3-1:0] rx_req_tlp_bar_id,
output wire [TLP_SEG_COUNT*8-1:0] rx_req_tlp_func_num,
output wire [TLP_SEG_COUNT-1:0] rx_req_tlp_valid,
@ -82,8 +82,8 @@ module pcie_s10_if_rx #
/*
* TLP output (completion to DMA)
*/
output wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] rx_cpl_tlp_data,
output wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] rx_cpl_tlp_hdr,
output wire [TLP_DATA_WIDTH-1:0] rx_cpl_tlp_data,
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_cpl_tlp_hdr,
output wire [TLP_SEG_COUNT*4-1:0] rx_cpl_tlp_error,
output wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_sop,
@ -111,12 +111,12 @@ initial begin
$finish;
end
if (TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH != SEG_COUNT*SEG_DATA_WIDTH) begin
if (TLP_DATA_WIDTH != SEG_COUNT*SEG_DATA_WIDTH) begin
$error("Error: Interface widths must match (instance %m)");
$finish;
end
if (TLP_SEG_HDR_WIDTH != 128) begin
if (TLP_HDR_WIDTH != 128) begin
$error("Error: TLP segment header width must be 128 (instance %m)");
$finish;
end
@ -134,16 +134,16 @@ reg payload_offset_reg = 0, payload_offset_next;
reg cpl_reg = 1'b0, cpl_next;
// internal datapath
reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] rx_req_tlp_data_int;
reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] rx_req_tlp_hdr_int;
reg [TLP_SEG_COUNT*3-1:0] rx_req_tlp_bar_id_int;
reg [TLP_SEG_COUNT*8-1:0] rx_req_tlp_func_num_int;
reg [TLP_SEG_COUNT-1:0] rx_req_tlp_sop_int;
reg [TLP_SEG_COUNT-1:0] rx_req_tlp_eop_int;
wire rx_req_tlp_ready_int;
reg [TLP_SEG_COUNT-1:0] rx_req_tlp_valid_int;
wire rx_cpl_tlp_ready_int;
reg [TLP_SEG_COUNT-1:0] rx_cpl_tlp_valid_int;
reg [TLP_DATA_WIDTH-1:0] rx_req_tlp_data_int;
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_req_tlp_hdr_int;
reg [TLP_SEG_COUNT*3-1:0] rx_req_tlp_bar_id_int;
reg [TLP_SEG_COUNT*8-1:0] rx_req_tlp_func_num_int;
reg [TLP_SEG_COUNT-1:0] rx_req_tlp_sop_int;
reg [TLP_SEG_COUNT-1:0] rx_req_tlp_eop_int;
wire rx_req_tlp_ready_int;
reg [TLP_SEG_COUNT-1:0] rx_req_tlp_valid_int;
wire rx_cpl_tlp_ready_int;
reg [TLP_SEG_COUNT-1:0] rx_cpl_tlp_valid_int;
reg [SEG_COUNT*SEG_DATA_WIDTH-1:0] rx_st_data_int_reg = 0, rx_st_data_int_next;
reg [SEG_COUNT*SEG_EMPTY_WIDTH-1:0] rx_st_empty_int_reg = 0, rx_st_empty_int_next;
@ -318,13 +318,13 @@ always @(posedge clk) begin
end
// output datapath logic (request TLP)
reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] rx_req_tlp_data_reg = 0;
reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] rx_req_tlp_hdr_reg = 0;
reg [TLP_SEG_COUNT*3-1:0] rx_req_tlp_bar_id_reg = 0;
reg [TLP_SEG_COUNT*8-1:0] rx_req_tlp_func_num_reg = 0;
reg [TLP_SEG_COUNT-1:0] rx_req_tlp_valid_reg = 0;
reg [TLP_SEG_COUNT-1:0] rx_req_tlp_sop_reg = 0;
reg [TLP_SEG_COUNT-1:0] rx_req_tlp_eop_reg = 0;
reg [TLP_DATA_WIDTH-1:0] rx_req_tlp_data_reg = 0;
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_req_tlp_hdr_reg = 0;
reg [TLP_SEG_COUNT*3-1:0] rx_req_tlp_bar_id_reg = 0;
reg [TLP_SEG_COUNT*8-1:0] rx_req_tlp_func_num_reg = 0;
reg [TLP_SEG_COUNT-1:0] rx_req_tlp_valid_reg = 0;
reg [TLP_SEG_COUNT-1:0] rx_req_tlp_sop_reg = 0;
reg [TLP_SEG_COUNT-1:0] rx_req_tlp_eop_reg = 0;
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_req_fifo_wr_ptr_reg = 0;
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_req_fifo_rd_ptr_reg = 0;
@ -334,19 +334,19 @@ wire out_req_fifo_full = out_req_fifo_wr_ptr_reg == (out_req_fifo_rd_ptr_reg ^ {
wire out_req_fifo_empty = out_req_fifo_wr_ptr_reg == out_req_fifo_rd_ptr_reg;
(* ramstyle = "no_rw_check, mlab" *)
reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] out_req_fifo_rx_req_tlp_data[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
reg [TLP_DATA_WIDTH-1:0] out_req_fifo_rx_req_tlp_data[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ramstyle = "no_rw_check, mlab" *)
reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] out_req_fifo_rx_req_tlp_hdr[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] out_req_fifo_rx_req_tlp_hdr[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ramstyle = "no_rw_check, mlab" *)
reg [TLP_SEG_COUNT*3-1:0] out_req_fifo_rx_req_tlp_bar_id[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
reg [TLP_SEG_COUNT*3-1:0] out_req_fifo_rx_req_tlp_bar_id[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ramstyle = "no_rw_check, mlab" *)
reg [TLP_SEG_COUNT*8-1:0] out_req_fifo_rx_req_tlp_func_num[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
reg [TLP_SEG_COUNT*8-1:0] out_req_fifo_rx_req_tlp_func_num[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ramstyle = "no_rw_check, mlab" *)
reg [TLP_SEG_COUNT-1:0] out_req_fifo_rx_req_tlp_valid[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
reg [TLP_SEG_COUNT-1:0] out_req_fifo_rx_req_tlp_valid[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ramstyle = "no_rw_check, mlab" *)
reg [TLP_SEG_COUNT-1:0] out_req_fifo_rx_req_tlp_sop[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
reg [TLP_SEG_COUNT-1:0] out_req_fifo_rx_req_tlp_sop[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ramstyle = "no_rw_check, mlab" *)
reg [TLP_SEG_COUNT-1:0] out_req_fifo_rx_req_tlp_eop[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
reg [TLP_SEG_COUNT-1:0] out_req_fifo_rx_req_tlp_eop[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
assign rx_req_tlp_ready_int = !out_req_fifo_watermark_reg;
@ -392,11 +392,11 @@ always @(posedge clk) begin
end
// output datapath logic (completion TLP)
reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] rx_cpl_tlp_data_reg = 0;
reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] rx_cpl_tlp_hdr_reg = 0;
reg [TLP_SEG_COUNT-1:0] rx_cpl_tlp_valid_reg = 0;
reg [TLP_SEG_COUNT-1:0] rx_cpl_tlp_sop_reg = 0;
reg [TLP_SEG_COUNT-1:0] rx_cpl_tlp_eop_reg = 0;
reg [TLP_DATA_WIDTH-1:0] rx_cpl_tlp_data_reg = 0;
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_cpl_tlp_hdr_reg = 0;
reg [TLP_SEG_COUNT-1:0] rx_cpl_tlp_valid_reg = 0;
reg [TLP_SEG_COUNT-1:0] rx_cpl_tlp_sop_reg = 0;
reg [TLP_SEG_COUNT-1:0] rx_cpl_tlp_eop_reg = 0;
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_cpl_fifo_wr_ptr_reg = 0;
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_cpl_fifo_rd_ptr_reg = 0;
@ -406,15 +406,15 @@ wire out_cpl_fifo_full = out_cpl_fifo_wr_ptr_reg == (out_cpl_fifo_rd_ptr_reg ^ {
wire out_cpl_fifo_empty = out_cpl_fifo_wr_ptr_reg == out_cpl_fifo_rd_ptr_reg;
(* ramstyle = "no_rw_check, mlab" *)
reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] out_cpl_fifo_rx_cpl_tlp_data[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
reg [TLP_DATA_WIDTH-1:0] out_cpl_fifo_rx_cpl_tlp_data[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ramstyle = "no_rw_check, mlab" *)
reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] out_cpl_fifo_rx_cpl_tlp_hdr[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] out_cpl_fifo_rx_cpl_tlp_hdr[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ramstyle = "no_rw_check, mlab" *)
reg [TLP_SEG_COUNT-1:0] out_cpl_fifo_rx_cpl_tlp_valid[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
reg [TLP_SEG_COUNT-1:0] out_cpl_fifo_rx_cpl_tlp_valid[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ramstyle = "no_rw_check, mlab" *)
reg [TLP_SEG_COUNT-1:0] out_cpl_fifo_rx_cpl_tlp_sop[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
reg [TLP_SEG_COUNT-1:0] out_cpl_fifo_rx_cpl_tlp_sop[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ramstyle = "no_rw_check, mlab" *)
reg [TLP_SEG_COUNT-1:0] out_cpl_fifo_rx_cpl_tlp_eop[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
reg [TLP_SEG_COUNT-1:0] out_cpl_fifo_rx_cpl_tlp_eop[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
assign rx_cpl_tlp_ready_int = !out_cpl_fifo_watermark_reg;

102
fpga/lib/pcie/rtl/pcie_s10_if_tx.v
View File

@ -37,88 +37,86 @@ module pcie_s10_if_tx #
parameter SEG_COUNT = 1,
// H-Tile/L-Tile AVST segment data width
parameter SEG_DATA_WIDTH = 256,
// TLP data width
parameter TLP_DATA_WIDTH = SEG_COUNT*SEG_DATA_WIDTH,
// TLP strobe width
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
// TLP header width
parameter TLP_HDR_WIDTH = 128,
// TLP segment count
parameter TLP_SEG_COUNT = 1,
// TLP segment data width
parameter TLP_SEG_DATA_WIDTH = (SEG_COUNT*SEG_DATA_WIDTH)/TLP_SEG_COUNT,
// TLP segment strobe width
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32,
// TLP segment header width
parameter TLP_SEG_HDR_WIDTH = 128,
// TX sequence number width
parameter TX_SEQ_NUM_WIDTH = 6
)
(
input wire clk,
input wire rst,
input wire clk,
input wire rst,
// H-Tile/L-Tile TX AVST interface
output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] tx_st_data,
output wire [SEG_COUNT-1:0] tx_st_sop,
output wire [SEG_COUNT-1:0] tx_st_eop,
output wire [SEG_COUNT-1:0] tx_st_valid,
input wire tx_st_ready,
output wire [SEG_COUNT-1:0] tx_st_err,
output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] tx_st_data,
output wire [SEG_COUNT-1:0] tx_st_sop,
output wire [SEG_COUNT-1:0] tx_st_eop,
output wire [SEG_COUNT-1:0] tx_st_valid,
input wire tx_st_ready,
output wire [SEG_COUNT-1:0] tx_st_err,
/*
* TLP input (read request from DMA)
*/
input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_rd_req_tlp_hdr,
input wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_rd_req_tlp_seq,
input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_eop,
output wire tx_rd_req_tlp_ready,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_rd_req_tlp_hdr,
input wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_rd_req_tlp_seq,
input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_eop,
output wire tx_rd_req_tlp_ready,
/*
* Transmit sequence number output (DMA read request)
*/
output wire [SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] m_axis_rd_req_tx_seq_num,
output wire [SEG_COUNT-1:0] m_axis_rd_req_tx_seq_num_valid,
output wire [SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] m_axis_rd_req_tx_seq_num,
output wire [SEG_COUNT-1:0] m_axis_rd_req_tx_seq_num_valid,
/*
* TLP input (write request from DMA)
*/
input wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] tx_wr_req_tlp_data,
input wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] tx_wr_req_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr,
input wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_wr_req_tlp_seq,
input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_eop,
output wire tx_wr_req_tlp_ready,
input wire [TLP_DATA_WIDTH-1:0] tx_wr_req_tlp_data,
input wire [TLP_STRB_WIDTH-1:0] tx_wr_req_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr,
input wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_wr_req_tlp_seq,
input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_eop,
output wire tx_wr_req_tlp_ready,
/*
* Transmit sequence number output (DMA write request)
*/
output wire [SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] m_axis_wr_req_tx_seq_num,
output wire [SEG_COUNT-1:0] m_axis_wr_req_tx_seq_num_valid,
output wire [SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] m_axis_wr_req_tx_seq_num,
output wire [SEG_COUNT-1:0] m_axis_wr_req_tx_seq_num_valid,
/*
* TLP input (completion from BAR)
*/
input wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] tx_cpl_tlp_data,
input wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] tx_cpl_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_cpl_tlp_hdr,
input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop,
output wire tx_cpl_tlp_ready,
input wire [TLP_DATA_WIDTH-1:0] tx_cpl_tlp_data,
input wire [TLP_STRB_WIDTH-1:0] tx_cpl_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_cpl_tlp_hdr,
input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop,
output wire tx_cpl_tlp_ready,
/*
* TLP input (write request from MSI)
*/
input wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] tx_msi_wr_req_tlp_data,
input wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] tx_msi_wr_req_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_msi_wr_req_tlp_hdr,
input wire [TLP_SEG_COUNT-1:0] tx_msi_wr_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_msi_wr_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] tx_msi_wr_req_tlp_eop,
output wire tx_msi_wr_req_tlp_ready
input wire [TLP_DATA_WIDTH-1:0] tx_msi_wr_req_tlp_data,
input wire [TLP_STRB_WIDTH-1:0] tx_msi_wr_req_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_msi_wr_req_tlp_hdr,
input wire [TLP_SEG_COUNT-1:0] tx_msi_wr_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_msi_wr_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] tx_msi_wr_req_tlp_eop,
output wire tx_msi_wr_req_tlp_ready
);
parameter TLP_DATA_WIDTH = TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH;
parameter TLP_STRB_WIDTH = TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH;
parameter TLP_DATA_WIDTH_BYTES = TLP_DATA_WIDTH/8;
parameter TLP_DATA_WIDTH_DWORDS = TLP_DATA_WIDTH/32;
@ -141,12 +139,12 @@ initial begin
$finish;
end
if (TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH != SEG_COUNT*SEG_DATA_WIDTH) begin
if (TLP_DATA_WIDTH != SEG_COUNT*SEG_DATA_WIDTH) begin
$error("Error: Interface widths must match (instance %m)");
$finish;
end
if (TLP_SEG_HDR_WIDTH != 128) begin
if (TLP_HDR_WIDTH != 128) begin
$error("Error: TLP segment header width must be 128 (instance %m)");
$finish;
end
@ -173,10 +171,10 @@ reg [1:0] tlp_output_state_reg = TLP_OUTPUT_STATE_IDLE, tlp_output_state_next;
reg wr_req_payload_offset_reg = 1'b0, wr_req_payload_offset_next;
reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] wr_req_tlp_data_reg = 0, wr_req_tlp_data_next;
reg [TLP_DATA_WIDTH-1:0] wr_req_tlp_data_reg = 0, wr_req_tlp_data_next;
reg [TLP_SEG_COUNT-1:0] wr_req_tlp_eop_reg = 0, wr_req_tlp_eop_next;
reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] cpl_tlp_data_reg = 0, cpl_tlp_data_next;
reg [TLP_DATA_WIDTH-1:0] cpl_tlp_data_reg = 0, cpl_tlp_data_next;
reg [TLP_SEG_COUNT-1:0] cpl_tlp_eop_reg = 0, cpl_tlp_eop_next;
reg tx_rd_req_tlp_ready_reg = 1'b0, tx_rd_req_tlp_ready_next;

150
fpga/lib/pcie/rtl/pcie_tlp_demux.v
View File

@ -35,60 +35,60 @@ module pcie_tlp_demux #
(
// Output count
parameter PORTS = 2,
// TLP data width
parameter TLP_DATA_WIDTH = 256,
// TLP strobe width
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
// TLP header width
parameter TLP_HDR_WIDTH = 128,
// TLP segment count
parameter TLP_SEG_COUNT = 1,
// TLP segment data width
parameter TLP_SEG_DATA_WIDTH = 256,
// TLP segment strobe width
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32,
// TLP segment header width
parameter TLP_SEG_HDR_WIDTH = 128
parameter TLP_SEG_COUNT = 1
)
(
input wire clk,
input wire rst,
input wire clk,
input wire rst,
/*
* TLP input
*/
input wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] in_tlp_data,
input wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] in_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] in_tlp_hdr,
input wire [TLP_SEG_COUNT*3-1:0] in_tlp_bar_id,
input wire [TLP_SEG_COUNT*8-1:0] in_tlp_func_num,
input wire [TLP_SEG_COUNT*4-1:0] in_tlp_error,
input wire [TLP_SEG_COUNT-1:0] in_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] in_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] in_tlp_eop,
output wire in_tlp_ready,
input wire [TLP_DATA_WIDTH-1:0] in_tlp_data,
input wire [TLP_STRB_WIDTH-1:0] in_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] in_tlp_hdr,
input wire [TLP_SEG_COUNT*3-1:0] in_tlp_bar_id,
input wire [TLP_SEG_COUNT*8-1:0] in_tlp_func_num,
input wire [TLP_SEG_COUNT*4-1:0] in_tlp_error,
input wire [TLP_SEG_COUNT-1:0] in_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] in_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] in_tlp_eop,
output wire in_tlp_ready,
/*
* TLP output
*/
output wire [PORTS*TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] out_tlp_data,
output wire [PORTS*TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] out_tlp_strb,
output wire [PORTS*TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] out_tlp_hdr,
output wire [PORTS*TLP_SEG_COUNT*3-1:0] out_tlp_bar_id,
output wire [PORTS*TLP_SEG_COUNT*8-1:0] out_tlp_func_num,
output wire [PORTS*TLP_SEG_COUNT*4-1:0] out_tlp_error,
output wire [PORTS*TLP_SEG_COUNT-1:0] out_tlp_valid,
output wire [PORTS*TLP_SEG_COUNT-1:0] out_tlp_sop,
output wire [PORTS*TLP_SEG_COUNT-1:0] out_tlp_eop,
input wire [PORTS-1:0] out_tlp_ready,
output wire [PORTS*TLP_DATA_WIDTH-1:0] out_tlp_data,
output wire [PORTS*TLP_STRB_WIDTH-1:0] out_tlp_strb,
output wire [PORTS*TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] out_tlp_hdr,
output wire [PORTS*TLP_SEG_COUNT*3-1:0] out_tlp_bar_id,
output wire [PORTS*TLP_SEG_COUNT*8-1:0] out_tlp_func_num,
output wire [PORTS*TLP_SEG_COUNT*4-1:0] out_tlp_error,
output wire [PORTS*TLP_SEG_COUNT-1:0] out_tlp_valid,
output wire [PORTS*TLP_SEG_COUNT-1:0] out_tlp_sop,
output wire [PORTS*TLP_SEG_COUNT-1:0] out_tlp_eop,
input wire [PORTS-1:0] out_tlp_ready,
/*
* Fields
*/
output wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] match_tlp_hdr,
output wire [TLP_SEG_COUNT*3-1:0] match_tlp_bar_id,
output wire [TLP_SEG_COUNT*8-1:0] match_tlp_func_num,
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] match_tlp_hdr,
output wire [TLP_SEG_COUNT*3-1:0] match_tlp_bar_id,
output wire [TLP_SEG_COUNT*8-1:0] match_tlp_func_num,
/*
* Control
*/
input wire enable,
input wire [TLP_SEG_COUNT-1:0] drop,
input wire [TLP_SEG_COUNT*PORTS-1:0] select
input wire enable,
input wire [TLP_SEG_COUNT-1:0] drop,
input wire [TLP_SEG_COUNT*PORTS-1:0] select
);
parameter CL_PORTS = $clog2(PORTS);
@ -100,12 +100,12 @@ initial begin
$finish;
end
if (TLP_SEG_HDR_WIDTH != 128) begin
if (TLP_HDR_WIDTH != 128) begin
$error("Error: TLP segment header width must be 128 (instance %m)");
$finish;
end
if (TLP_SEG_STRB_WIDTH*32 != TLP_SEG_DATA_WIDTH) begin
if (TLP_STRB_WIDTH*32 != TLP_DATA_WIDTH) begin
$error("Error: PCIe interface requires dword (32-bit) granularity (instance %m)");
$finish;
end
@ -117,28 +117,28 @@ reg frame_reg = 1'b0, frame_ctl, frame_next;
reg in_tlp_ready_reg = 1'b0, in_tlp_ready_next;
reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] temp_in_tlp_data_reg = 0;
reg [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] temp_in_tlp_strb_reg = 0;
reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] temp_in_tlp_hdr_reg = 0;
reg [TLP_SEG_COUNT*3-1:0] temp_in_tlp_bar_id_reg = 0;
reg [TLP_SEG_COUNT*8-1:0] temp_in_tlp_func_num_reg = 0;
reg [TLP_SEG_COUNT*4-1:0] temp_in_tlp_error_reg = 0;
reg [TLP_SEG_COUNT-1:0] temp_in_tlp_valid_reg = 1'b0;
reg [TLP_SEG_COUNT-1:0] temp_in_tlp_sop_reg = 1'b0;
reg [TLP_SEG_COUNT-1:0] temp_in_tlp_eop_reg = 1'b0;
reg [TLP_DATA_WIDTH-1:0] temp_in_tlp_data_reg = 0;
reg [TLP_STRB_WIDTH-1:0] temp_in_tlp_strb_reg = 0;
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] temp_in_tlp_hdr_reg = 0;
reg [TLP_SEG_COUNT*3-1:0] temp_in_tlp_bar_id_reg = 0;
reg [TLP_SEG_COUNT*8-1:0] temp_in_tlp_func_num_reg = 0;
reg [TLP_SEG_COUNT*4-1:0] temp_in_tlp_error_reg = 0;
reg [TLP_SEG_COUNT-1:0] temp_in_tlp_valid_reg = 1'b0;
reg [TLP_SEG_COUNT-1:0] temp_in_tlp_sop_reg = 1'b0;
reg [TLP_SEG_COUNT-1:0] temp_in_tlp_eop_reg = 1'b0;
// internal datapath
reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] out_tlp_data_int;
reg [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] out_tlp_strb_int;
reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] out_tlp_hdr_int;
reg [TLP_SEG_COUNT*3-1:0] out_tlp_bar_id_int;
reg [TLP_SEG_COUNT*8-1:0] out_tlp_func_num_int;
reg [TLP_SEG_COUNT*4-1:0] out_tlp_error_int;
reg [PORTS*TLP_SEG_COUNT-1:0] out_tlp_valid_int;
reg [TLP_SEG_COUNT-1:0] out_tlp_sop_int;
reg [TLP_SEG_COUNT-1:0] out_tlp_eop_int;
reg out_tlp_ready_int_reg = 1'b0;
wire out_tlp_ready_int_early;
reg [TLP_DATA_WIDTH-1:0] out_tlp_data_int;
reg [TLP_STRB_WIDTH-1:0] out_tlp_strb_int;
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] out_tlp_hdr_int;
reg [TLP_SEG_COUNT*3-1:0] out_tlp_bar_id_int;
reg [TLP_SEG_COUNT*8-1:0] out_tlp_func_num_int;
reg [TLP_SEG_COUNT*4-1:0] out_tlp_error_int;
reg [PORTS*TLP_SEG_COUNT-1:0] out_tlp_valid_int;
reg [TLP_SEG_COUNT-1:0] out_tlp_sop_int;
reg [TLP_SEG_COUNT-1:0] out_tlp_eop_int;
reg out_tlp_ready_int_reg = 1'b0;
wire out_tlp_ready_int_early;
assign in_tlp_ready = in_tlp_ready_reg && enable;
@ -213,25 +213,25 @@ always @(posedge clk) begin
end
// output datapath logic
reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] out_tlp_data_reg = 0;
reg [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] out_tlp_strb_reg = 0;
reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] out_tlp_hdr_reg = 0;
reg [TLP_SEG_COUNT*3-1:0] out_tlp_bar_id_reg = 0;
reg [TLP_SEG_COUNT*8-1:0] out_tlp_func_num_reg = 0;
reg [TLP_SEG_COUNT*4-1:0] out_tlp_error_reg = 0;
reg [PORTS*TLP_SEG_COUNT-1:0] out_tlp_valid_reg = 1, out_tlp_valid_next;
reg [TLP_SEG_COUNT-1:0] out_tlp_sop_reg = 0;
reg [TLP_SEG_COUNT-1:0] out_tlp_eop_reg = 0;
reg [TLP_DATA_WIDTH-1:0] out_tlp_data_reg = 0;
reg [TLP_STRB_WIDTH-1:0] out_tlp_strb_reg = 0;
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] out_tlp_hdr_reg = 0;
reg [TLP_SEG_COUNT*3-1:0] out_tlp_bar_id_reg = 0;
reg [TLP_SEG_COUNT*8-1:0] out_tlp_func_num_reg = 0;
reg [TLP_SEG_COUNT*4-1:0] out_tlp_error_reg = 0;
reg [PORTS*TLP_SEG_COUNT-1:0] out_tlp_valid_reg = 1, out_tlp_valid_next;
reg [TLP_SEG_COUNT-1:0] out_tlp_sop_reg = 0;
reg [TLP_SEG_COUNT-1:0] out_tlp_eop_reg = 0;
reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] temp_out_tlp_data_reg = 0;
reg [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] temp_out_tlp_strb_reg = 0;
reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] temp_out_tlp_hdr_reg = 0;
reg [TLP_SEG_COUNT*3-1:0] temp_out_tlp_bar_id_reg = 0;
reg [TLP_SEG_COUNT*8-1:0] temp_out_tlp_func_num_reg = 0;
reg [TLP_SEG_COUNT*4-1:0] temp_out_tlp_error_reg = 0;
reg [PORTS*TLP_SEG_COUNT-1:0] temp_out_tlp_valid_reg = 0, temp_out_tlp_valid_next;
reg [TLP_SEG_COUNT-1:0] temp_out_tlp_sop_reg = 0;
reg [TLP_SEG_COUNT-1:0] temp_out_tlp_eop_reg = 0;
reg [TLP_DATA_WIDTH-1:0] temp_out_tlp_data_reg = 0;
reg [TLP_STRB_WIDTH-1:0] temp_out_tlp_strb_reg = 0;
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] temp_out_tlp_hdr_reg = 0;
reg [TLP_SEG_COUNT*3-1:0] temp_out_tlp_bar_id_reg = 0;
reg [TLP_SEG_COUNT*8-1:0] temp_out_tlp_func_num_reg = 0;
reg [TLP_SEG_COUNT*4-1:0] temp_out_tlp_error_reg = 0;
reg [PORTS*TLP_SEG_COUNT-1:0] temp_out_tlp_valid_reg = 0, temp_out_tlp_valid_next;
reg [TLP_SEG_COUNT-1:0] temp_out_tlp_sop_reg = 0;
reg [TLP_SEG_COUNT-1:0] temp_out_tlp_eop_reg = 0;
// datapath control
reg store_int_to_output;

66
fpga/lib/pcie/rtl/pcie_tlp_demux_bar.v
View File

@ -35,14 +35,14 @@ module pcie_tlp_demux_bar #
(
// Output count
parameter PORTS = 2,
// TLP data width
parameter TLP_DATA_WIDTH = 256,
// TLP strobe width
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
// TLP header width
parameter TLP_HDR_WIDTH = 128,
// TLP segment count
parameter TLP_SEG_COUNT = 1,
// TLP segment data width
parameter TLP_SEG_DATA_WIDTH = 256,
// TLP segment strobe width
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32,
// TLP segment header width
parameter TLP_SEG_HDR_WIDTH = 128,
// Base BAR
parameter BAR_BASE = 0,
// BAR stride
@ -51,41 +51,41 @@ module pcie_tlp_demux_bar #
parameter BAR_IDS = 0
)
(
input wire clk,
input wire rst,
input wire clk,
input wire rst,
/*
* TLP input
*/
input wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] in_tlp_data,
input wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] in_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] in_tlp_hdr,
input wire [TLP_SEG_COUNT*3-1:0] in_tlp_bar_id,
input wire [TLP_SEG_COUNT*8-1:0] in_tlp_func_num,
input wire [TLP_SEG_COUNT*4-1:0] in_tlp_error,
input wire [TLP_SEG_COUNT-1:0] in_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] in_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] in_tlp_eop,
output wire in_tlp_ready,
input wire [TLP_DATA_WIDTH-1:0] in_tlp_data,
input wire [TLP_STRB_WIDTH-1:0] in_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] in_tlp_hdr,
input wire [TLP_SEG_COUNT*3-1:0] in_tlp_bar_id,
input wire [TLP_SEG_COUNT*8-1:0] in_tlp_func_num,
input wire [TLP_SEG_COUNT*4-1:0] in_tlp_error,
input wire [TLP_SEG_COUNT-1:0] in_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] in_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] in_tlp_eop,
output wire in_tlp_ready,
/*
* TLP output
*/
output wire [PORTS*TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] out_tlp_data,
output wire [PORTS*TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] out_tlp_strb,
output wire [PORTS*TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] out_tlp_hdr,
output wire [PORTS*TLP_SEG_COUNT*3-1:0] out_tlp_bar_id,
output wire [PORTS*TLP_SEG_COUNT*8-1:0] out_tlp_func_num,
output wire [PORTS*TLP_SEG_COUNT*4-1:0] out_tlp_error,
output wire [PORTS*TLP_SEG_COUNT-1:0] out_tlp_valid,
output wire [PORTS*TLP_SEG_COUNT-1:0] out_tlp_sop,
output wire [PORTS*TLP_SEG_COUNT-1:0] out_tlp_eop,
input wire [PORTS-1:0] out_tlp_ready,
output wire [PORTS*TLP_DATA_WIDTH-1:0] out_tlp_data,
output wire [PORTS*TLP_STRB_WIDTH-1:0] out_tlp_strb,
output wire [PORTS*TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] out_tlp_hdr,
output wire [PORTS*TLP_SEG_COUNT*3-1:0] out_tlp_bar_id,
output wire [PORTS*TLP_SEG_COUNT*8-1:0] out_tlp_func_num,
output wire [PORTS*TLP_SEG_COUNT*4-1:0] out_tlp_error,
output wire [PORTS*TLP_SEG_COUNT-1:0] out_tlp_valid,
output wire [PORTS*TLP_SEG_COUNT-1:0] out_tlp_sop,
output wire [PORTS*TLP_SEG_COUNT-1:0] out_tlp_eop,
input wire [PORTS-1:0] out_tlp_ready,
/*
* Control
*/
input wire enable
input wire enable
);
// default BAR number computation
@ -148,10 +148,10 @@ endgenerate
pcie_tlp_demux #(
.PORTS(PORTS),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH)
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT)
)
pcie_tlp_demux_inst (
.clk(clk),

162
fpga/lib/pcie/rtl/pcie_tlp_mux.v
View File

@ -35,50 +35,50 @@ module pcie_tlp_mux #
(
// Input count
parameter PORTS = 2,
// TLP data width
parameter TLP_DATA_WIDTH = 256,
// TLP strobe width
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
// TLP header width
parameter TLP_HDR_WIDTH = 128,
// TLP segment count
parameter TLP_SEG_COUNT = 1,
// TLP segment data width
parameter TLP_SEG_DATA_WIDTH = 256,
// TLP segment strobe width
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32,
// TLP segment header width
parameter TLP_SEG_HDR_WIDTH = 128,
// select round robin arbitration
parameter ARB_TYPE_ROUND_ROBIN = 0,
// LSB priority selection
parameter ARB_LSB_HIGH_PRIORITY = 1
)
(
input wire clk,
input wire rst,
input wire clk,
input wire rst,
/*
* TLP input
*/
input wire [PORTS*TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] in_tlp_data,
input wire [PORTS*TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] in_tlp_strb,
input wire [PORTS*TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] in_tlp_hdr,
input wire [PORTS*TLP_SEG_COUNT*3-1:0] in_tlp_bar_id,
input wire [PORTS*TLP_SEG_COUNT*8-1:0] in_tlp_func_num,
input wire [PORTS*TLP_SEG_COUNT*4-1:0] in_tlp_error,
input wire [PORTS*TLP_SEG_COUNT-1:0] in_tlp_valid,
input wire [PORTS*TLP_SEG_COUNT-1:0] in_tlp_sop,
input wire [PORTS*TLP_SEG_COUNT-1:0] in_tlp_eop,
output wire [PORTS-1:0] in_tlp_ready,
input wire [PORTS*TLP_DATA_WIDTH-1:0] in_tlp_data,
input wire [PORTS*TLP_STRB_WIDTH-1:0] in_tlp_strb,
input wire [PORTS*TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] in_tlp_hdr,
input wire [PORTS*TLP_SEG_COUNT*3-1:0] in_tlp_bar_id,
input wire [PORTS*TLP_SEG_COUNT*8-1:0] in_tlp_func_num,
input wire [PORTS*TLP_SEG_COUNT*4-1:0] in_tlp_error,
input wire [PORTS*TLP_SEG_COUNT-1:0] in_tlp_valid,
input wire [PORTS*TLP_SEG_COUNT-1:0] in_tlp_sop,
input wire [PORTS*TLP_SEG_COUNT-1:0] in_tlp_eop,
output wire [PORTS-1:0] in_tlp_ready,
/*
* TLP output
*/
output wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] out_tlp_data,
output wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] out_tlp_strb,
output wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] out_tlp_hdr,
output wire [TLP_SEG_COUNT*3-1:0] out_tlp_bar_id,
output wire [TLP_SEG_COUNT*8-1:0] out_tlp_func_num,
output wire [TLP_SEG_COUNT*4-1:0] out_tlp_error,
output wire [TLP_SEG_COUNT-1:0] out_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] out_tlp_sop,
output wire [TLP_SEG_COUNT-1:0] out_tlp_eop,
input wire out_tlp_ready
output wire [TLP_DATA_WIDTH-1:0] out_tlp_data,
output wire [TLP_STRB_WIDTH-1:0] out_tlp_strb,
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] out_tlp_hdr,
output wire [TLP_SEG_COUNT*3-1:0] out_tlp_bar_id,
output wire [TLP_SEG_COUNT*8-1:0] out_tlp_func_num,
output wire [TLP_SEG_COUNT*4-1:0] out_tlp_error,
output wire [TLP_SEG_COUNT-1:0] out_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] out_tlp_sop,
output wire [TLP_SEG_COUNT-1:0] out_tlp_eop,
input wire out_tlp_ready
);
parameter CL_PORTS = $clog2(PORTS);
@ -90,12 +90,12 @@ initial begin
$finish;
end
if (TLP_SEG_HDR_WIDTH != 128) begin
if (TLP_HDR_WIDTH != 128) begin
$error("Error: TLP segment header width must be 128 (instance %m)");
$finish;
end
if (TLP_SEG_STRB_WIDTH*32 != TLP_SEG_DATA_WIDTH) begin
if (TLP_STRB_WIDTH*32 != TLP_DATA_WIDTH) begin
$error("Error: PCIe interface requires dword (32-bit) granularity (instance %m)");
$finish;
end
@ -108,42 +108,42 @@ wire grant_valid;
wire [CL_PORTS-1:0] grant_encoded;
// input registers to pipeline arbitration delay
reg [PORTS*TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] in_tlp_data_reg = 0;
reg [PORTS*TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] in_tlp_strb_reg = 0;
reg [PORTS*TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] in_tlp_hdr_reg = 0;
reg [PORTS*TLP_SEG_COUNT*3-1:0] in_tlp_bar_id_reg = 0;
reg [PORTS*TLP_SEG_COUNT*8-1:0] in_tlp_func_num_reg = 0;
reg [PORTS*TLP_SEG_COUNT*4-1:0] in_tlp_error_reg = 0;
reg [PORTS*TLP_SEG_COUNT-1:0] in_tlp_valid_reg = 0;
reg [PORTS*TLP_SEG_COUNT-1:0] in_tlp_sop_reg = 0;
reg [PORTS*TLP_SEG_COUNT-1:0] in_tlp_eop_reg = 0;
reg [PORTS*TLP_DATA_WIDTH-1:0] in_tlp_data_reg = 0;
reg [PORTS*TLP_STRB_WIDTH-1:0] in_tlp_strb_reg = 0;
reg [PORTS*TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] in_tlp_hdr_reg = 0;
reg [PORTS*TLP_SEG_COUNT*3-1:0] in_tlp_bar_id_reg = 0;
reg [PORTS*TLP_SEG_COUNT*8-1:0] in_tlp_func_num_reg = 0;
reg [PORTS*TLP_SEG_COUNT*4-1:0] in_tlp_error_reg = 0;
reg [PORTS*TLP_SEG_COUNT-1:0] in_tlp_valid_reg = 0;
reg [PORTS*TLP_SEG_COUNT-1:0] in_tlp_sop_reg = 0;
reg [PORTS*TLP_SEG_COUNT-1:0] in_tlp_eop_reg = 0;
// internal datapath
reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] out_tlp_data_int;
reg [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] out_tlp_strb_int;
reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] out_tlp_hdr_int;
reg [TLP_SEG_COUNT*3-1:0] out_tlp_bar_id_int;
reg [TLP_SEG_COUNT*8-1:0] out_tlp_func_num_int;
reg [TLP_SEG_COUNT*4-1:0] out_tlp_error_int;
reg [TLP_SEG_COUNT-1:0] out_tlp_valid_int;
reg [TLP_SEG_COUNT-1:0] out_tlp_sop_int;
reg [TLP_SEG_COUNT-1:0] out_tlp_eop_int;
reg out_tlp_ready_int_reg = 1'b0;
wire out_tlp_ready_int_early;
reg [TLP_DATA_WIDTH-1:0] out_tlp_data_int;
reg [TLP_STRB_WIDTH-1:0] out_tlp_strb_int;
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] out_tlp_hdr_int;
reg [TLP_SEG_COUNT*3-1:0] out_tlp_bar_id_int;
reg [TLP_SEG_COUNT*8-1:0] out_tlp_func_num_int;
reg [TLP_SEG_COUNT*4-1:0] out_tlp_error_int;
reg [TLP_SEG_COUNT-1:0] out_tlp_valid_int;
reg [TLP_SEG_COUNT-1:0] out_tlp_sop_int;
reg [TLP_SEG_COUNT-1:0] out_tlp_eop_int;
reg out_tlp_ready_int_reg = 1'b0;
wire out_tlp_ready_int_early;
assign in_tlp_ready = ~in_tlp_valid_reg | ({PORTS{out_tlp_ready_int_reg}} & grant);
// mux for incoming packet
wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] current_in_tlp_data = in_tlp_data_reg[grant_encoded*TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH +: TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH];
wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] current_in_tlp_strb = in_tlp_strb_reg[grant_encoded*TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH +: TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH];
wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] current_in_tlp_hdr = in_tlp_hdr_reg[grant_encoded*TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH +: TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH];
wire [TLP_SEG_COUNT*3-1:0] current_in_tlp_bar_id = in_tlp_bar_id_reg[grant_encoded*TLP_SEG_COUNT*3 +: TLP_SEG_COUNT*3];
wire [TLP_SEG_COUNT*8-1:0] current_in_tlp_func_num = in_tlp_func_num_reg[grant_encoded*TLP_SEG_COUNT*8 +: TLP_SEG_COUNT*8];
wire [TLP_SEG_COUNT*4-1:0] current_in_tlp_error = in_tlp_error_reg[grant_encoded*TLP_SEG_COUNT*4 +: TLP_SEG_COUNT*4];
wire [TLP_SEG_COUNT-1:0] current_in_tlp_valid = in_tlp_valid_reg[grant_encoded*TLP_SEG_COUNT +: TLP_SEG_COUNT];
wire [TLP_SEG_COUNT-1:0] current_in_tlp_sop = in_tlp_sop_reg[grant_encoded*TLP_SEG_COUNT +: TLP_SEG_COUNT];
wire [TLP_SEG_COUNT-1:0] current_in_tlp_eop = in_tlp_eop_reg[grant_encoded*TLP_SEG_COUNT +: TLP_SEG_COUNT];
wire current_in_tlp_ready = in_tlp_ready[grant_encoded];
wire [TLP_DATA_WIDTH-1:0] current_in_tlp_data = in_tlp_data_reg[grant_encoded*TLP_DATA_WIDTH +: TLP_DATA_WIDTH];
wire [TLP_STRB_WIDTH-1:0] current_in_tlp_strb = in_tlp_strb_reg[grant_encoded*TLP_STRB_WIDTH +: TLP_STRB_WIDTH];
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] current_in_tlp_hdr = in_tlp_hdr_reg[grant_encoded*TLP_SEG_COUNT*TLP_HDR_WIDTH +: TLP_SEG_COUNT*TLP_HDR_WIDTH];
wire [TLP_SEG_COUNT*3-1:0] current_in_tlp_bar_id = in_tlp_bar_id_reg[grant_encoded*TLP_SEG_COUNT*3 +: TLP_SEG_COUNT*3];
wire [TLP_SEG_COUNT*8-1:0] current_in_tlp_func_num = in_tlp_func_num_reg[grant_encoded*TLP_SEG_COUNT*8 +: TLP_SEG_COUNT*8];
wire [TLP_SEG_COUNT*4-1:0] current_in_tlp_error = in_tlp_error_reg[grant_encoded*TLP_SEG_COUNT*4 +: TLP_SEG_COUNT*4];
wire [TLP_SEG_COUNT-1:0] current_in_tlp_valid = in_tlp_valid_reg[grant_encoded*TLP_SEG_COUNT +: TLP_SEG_COUNT];
wire [TLP_SEG_COUNT-1:0] current_in_tlp_sop = in_tlp_sop_reg[grant_encoded*TLP_SEG_COUNT +: TLP_SEG_COUNT];
wire [TLP_SEG_COUNT-1:0] current_in_tlp_eop = in_tlp_eop_reg[grant_encoded*TLP_SEG_COUNT +: TLP_SEG_COUNT];
wire current_in_tlp_ready = in_tlp_ready[grant_encoded];
// arbiter instance
arbiter #(
@ -185,9 +185,9 @@ always @(posedge clk) begin
// register inputs
for (i = 0; i < PORTS; i = i + 1) begin
if (in_tlp_ready[i]) begin
in_tlp_data_reg[i*TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH +: TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH] <= in_tlp_data[i*TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH +: TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH];
in_tlp_strb_reg[i*TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH +: TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH] <= in_tlp_strb[i*TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH +: TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH];
in_tlp_hdr_reg[i*TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH +: TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH] <= in_tlp_hdr[i*TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH +: TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH];
in_tlp_data_reg[i*TLP_DATA_WIDTH +: TLP_DATA_WIDTH] <= in_tlp_data[i*TLP_DATA_WIDTH +: TLP_DATA_WIDTH];
in_tlp_strb_reg[i*TLP_STRB_WIDTH +: TLP_STRB_WIDTH] <= in_tlp_strb[i*TLP_STRB_WIDTH +: TLP_STRB_WIDTH];
in_tlp_hdr_reg[i*TLP_SEG_COUNT*TLP_HDR_WIDTH +: TLP_SEG_COUNT*TLP_HDR_WIDTH] <= in_tlp_hdr[i*TLP_SEG_COUNT*TLP_HDR_WIDTH +: TLP_SEG_COUNT*TLP_HDR_WIDTH];
in_tlp_bar_id_reg[i*TLP_SEG_COUNT*3 +: TLP_SEG_COUNT*3] <= in_tlp_bar_id[i*TLP_SEG_COUNT*3 +: TLP_SEG_COUNT*3];
in_tlp_func_num_reg[i*TLP_SEG_COUNT*8 +: TLP_SEG_COUNT*8] <= in_tlp_func_num[i*TLP_SEG_COUNT*8 +: TLP_SEG_COUNT*8];
in_tlp_error_reg[i*TLP_SEG_COUNT*4 +: TLP_SEG_COUNT*4] <= in_tlp_error[i*TLP_SEG_COUNT*4 +: TLP_SEG_COUNT*4];
@ -203,25 +203,25 @@ always @(posedge clk) begin
end
// output datapath logic
reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] out_tlp_data_reg = 0;
reg [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] out_tlp_strb_reg = 0;
reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] out_tlp_hdr_reg = 0;
reg [TLP_SEG_COUNT*3-1:0] out_tlp_bar_id_reg = 0;
reg [TLP_SEG_COUNT*8-1:0] out_tlp_func_num_reg = 0;
reg [TLP_SEG_COUNT*4-1:0] out_tlp_error_reg = 0;
reg [TLP_SEG_COUNT-1:0] out_tlp_valid_reg = 0, out_tlp_valid_next;
reg [TLP_SEG_COUNT-1:0] out_tlp_sop_reg = 0;
reg [TLP_SEG_COUNT-1:0] out_tlp_eop_reg = 0;
reg [TLP_DATA_WIDTH-1:0] out_tlp_data_reg = 0;
reg [TLP_STRB_WIDTH-1:0] out_tlp_strb_reg = 0;
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] out_tlp_hdr_reg = 0;
reg [TLP_SEG_COUNT*3-1:0] out_tlp_bar_id_reg = 0;
reg [TLP_SEG_COUNT*8-1:0] out_tlp_func_num_reg = 0;
reg [TLP_SEG_COUNT*4-1:0] out_tlp_error_reg = 0;
reg [TLP_SEG_COUNT-1:0] out_tlp_valid_reg = 0, out_tlp_valid_next;
reg [TLP_SEG_COUNT-1:0] out_tlp_sop_reg = 0;
reg [TLP_SEG_COUNT-1:0] out_tlp_eop_reg = 0;
reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] temp_out_tlp_data_reg = 0;
reg [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] temp_out_tlp_strb_reg = 0;
reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] temp_out_tlp_hdr_reg = 0;
reg [TLP_SEG_COUNT*3-1:0] temp_out_tlp_bar_id_reg = 0;
reg [TLP_SEG_COUNT*8-1:0] temp_out_tlp_func_num_reg = 0;
reg [TLP_SEG_COUNT*4-1:0] temp_out_tlp_error_reg = 0;
reg [TLP_SEG_COUNT-1:0] temp_out_tlp_valid_reg = 0, temp_out_tlp_valid_next;
reg [TLP_SEG_COUNT-1:0] temp_out_tlp_sop_reg = 0;
reg [TLP_SEG_COUNT-1:0] temp_out_tlp_eop_reg = 0;
reg [TLP_DATA_WIDTH-1:0] temp_out_tlp_data_reg = 0;
reg [TLP_STRB_WIDTH-1:0] temp_out_tlp_strb_reg = 0;
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] temp_out_tlp_hdr_reg = 0;
reg [TLP_SEG_COUNT*3-1:0] temp_out_tlp_bar_id_reg = 0;
reg [TLP_SEG_COUNT*8-1:0] temp_out_tlp_func_num_reg = 0;
reg [TLP_SEG_COUNT*4-1:0] temp_out_tlp_error_reg = 0;
reg [TLP_SEG_COUNT-1:0] temp_out_tlp_valid_reg = 0, temp_out_tlp_valid_next;
reg [TLP_SEG_COUNT-1:0] temp_out_tlp_sop_reg = 0;
reg [TLP_SEG_COUNT-1:0] temp_out_tlp_eop_reg = 0;
// datapath control
reg store_axis_int_to_output;

70
fpga/lib/pcie/rtl/pcie_us_if.v
View File

@ -47,14 +47,14 @@ module pcie_us_if #
parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
// RQ sequence number width
parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
// TLP data width
parameter TLP_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH,
// TLP strobe width
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
// TLP header width
parameter TLP_HDR_WIDTH = 128,
// TLP segment count
parameter TLP_SEG_COUNT = 1,
// TLP segment data width
parameter TLP_SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH/TLP_SEG_COUNT,
// TLP segment strobe width
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32,
// TLP segment header width
parameter TLP_SEG_HDR_WIDTH = 128,
// TX sequence number count
parameter TX_SEQ_NUM_COUNT = AXIS_PCIE_DATA_WIDTH < 512 ? 1 : 2,
// TX sequence number width
@ -188,8 +188,8 @@ module pcie_us_if #
/*
* TLP output (request to BAR)
*/
output wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] rx_req_tlp_data,
output wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] rx_req_tlp_hdr,
output wire [TLP_DATA_WIDTH-1:0] rx_req_tlp_data,
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_req_tlp_hdr,
output wire [TLP_SEG_COUNT*3-1:0] rx_req_tlp_bar_id,
output wire [TLP_SEG_COUNT*8-1:0] rx_req_tlp_func_num,
output wire [TLP_SEG_COUNT-1:0] rx_req_tlp_valid,
@ -200,8 +200,8 @@ module pcie_us_if #
/*
* TLP output (completion to DMA)
*/
output wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] rx_cpl_tlp_data,
output wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] rx_cpl_tlp_hdr,
output wire [TLP_DATA_WIDTH-1:0] rx_cpl_tlp_data,
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_cpl_tlp_hdr,
output wire [TLP_SEG_COUNT*4-1:0] rx_cpl_tlp_error,
output wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_sop,
@ -211,7 +211,7 @@ module pcie_us_if #
/*
* TLP input (read request from DMA)
*/
input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_rd_req_tlp_hdr,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_rd_req_tlp_hdr,
input wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_rd_req_tlp_seq,
input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_sop,
@ -227,9 +227,9 @@ module pcie_us_if #
/*
* TLP input (write request from DMA)
*/
input wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] tx_wr_req_tlp_data,
input wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] tx_wr_req_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr,
input wire [TLP_DATA_WIDTH-1:0] tx_wr_req_tlp_data,
input wire [TLP_STRB_WIDTH-1:0] tx_wr_req_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr,
input wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_wr_req_tlp_seq,
input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_sop,
@ -245,9 +245,9 @@ module pcie_us_if #
/*
* TLP input (completion from BAR)
*/
input wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] tx_cpl_tlp_data,
input wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] tx_cpl_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_cpl_tlp_hdr,
input wire [TLP_DATA_WIDTH-1:0] tx_cpl_tlp_data,
input wire [TLP_STRB_WIDTH-1:0] tx_cpl_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_cpl_tlp_hdr,
input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop,
@ -256,9 +256,9 @@ module pcie_us_if #
/*
* TLP input (write request from MSI-X)
*/
input wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] tx_msix_wr_req_tlp_data,
input wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] tx_msix_wr_req_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_msix_wr_req_tlp_hdr,
input wire [TLP_DATA_WIDTH-1:0] tx_msix_wr_req_tlp_data,
input wire [TLP_STRB_WIDTH-1:0] tx_msix_wr_req_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_msix_wr_req_tlp_hdr,
input wire [TLP_SEG_COUNT-1:0] tx_msix_wr_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_msix_wr_req_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] tx_msix_wr_req_tlp_eop,
@ -293,10 +293,10 @@ pcie_us_if_rc #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH)
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT)
)
pcie_us_if_rc_inst
(
@ -330,10 +330,10 @@ pcie_us_if_rq #(
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH),
.TX_SEQ_NUM_COUNT(TX_SEQ_NUM_COUNT),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH)
)
@ -399,10 +399,10 @@ pcie_us_if_cq #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH)
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT)
)
pcie_us_if_cq_inst
(
@ -436,10 +436,10 @@ pcie_us_if_cc #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT),
.TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),
.TLP_SEG_STRB_WIDTH(TLP_SEG_STRB_WIDTH),
.TLP_SEG_HDR_WIDTH(TLP_SEG_HDR_WIDTH)
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
.TLP_SEG_COUNT(TLP_SEG_COUNT)
)
pcie_us_if_cc_inst
(

54
fpga/lib/pcie/rtl/pcie_us_if_cc.v
View File

@ -39,43 +39,41 @@ module pcie_us_if_cc #
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32),
// PCIe AXI stream CC tuser signal width
parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
// TLP data width
parameter TLP_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH,
// TLP strobe width
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
// TLP header width
parameter TLP_HDR_WIDTH = 128,
// TLP segment count
parameter TLP_SEG_COUNT = 1,
// TLP segment data width
parameter TLP_SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH/TLP_SEG_COUNT,
// TLP segment strobe width
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32,
// TLP segment header width
parameter TLP_SEG_HDR_WIDTH = 128
parameter TLP_SEG_COUNT = 1
)
(
input wire clk,
input wire rst,
input wire clk,
input wire rst,
/*
* AXI output (CC)
*/
output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata,
output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep,
output wire m_axis_cc_tvalid,
input wire m_axis_cc_tready,
output wire m_axis_cc_tlast,
output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser,
output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata,
output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep,
output wire m_axis_cc_tvalid,
input wire m_axis_cc_tready,
output wire m_axis_cc_tlast,
output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser,
/*
* TLP input (completion from BAR)
*/
input wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] tx_cpl_tlp_data,
input wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] tx_cpl_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_cpl_tlp_hdr,
input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop,
output wire tx_cpl_tlp_ready
input wire [TLP_DATA_WIDTH-1:0] tx_cpl_tlp_data,
input wire [TLP_STRB_WIDTH-1:0] tx_cpl_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_cpl_tlp_hdr,
input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop,
input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop,
output wire tx_cpl_tlp_ready
);
parameter TLP_DATA_WIDTH = TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH;
parameter TLP_STRB_WIDTH = TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH;
parameter TLP_DATA_WIDTH_BYTES = TLP_DATA_WIDTH/8;
parameter TLP_DATA_WIDTH_DWORDS = TLP_DATA_WIDTH/32;
@ -110,12 +108,12 @@ initial begin
$finish;
end
if (TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH != AXIS_PCIE_DATA_WIDTH) begin
if (TLP_DATA_WIDTH != AXIS_PCIE_DATA_WIDTH) begin
$error("Error: Interface widths must match (instance %m)");
$finish;
end
if (TLP_SEG_HDR_WIDTH != 128) begin
if (TLP_HDR_WIDTH != 128) begin
$error("Error: TLP segment header width must be 128 (instance %m)");
$finish;
end
@ -146,8 +144,8 @@ localparam [1:0]
reg [1:0] tlp_output_state_reg = TLP_OUTPUT_STATE_IDLE, tlp_output_state_next;
reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] out_tlp_data_reg = 0, out_tlp_data_next;
reg [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] out_tlp_strb_reg = 0, out_tlp_strb_next;
reg [TLP_DATA_WIDTH-1:0] out_tlp_data_reg = 0, out_tlp_data_next;
reg [TLP_STRB_WIDTH-1:0] out_tlp_strb_reg = 0, out_tlp_strb_next;
reg [TLP_SEG_COUNT-1:0] out_tlp_eop_reg = 0, out_tlp_eop_next;
reg [2:0] tx_cpl_tlp_hdr_fmt;

28
fpga/lib/pcie/rtl/pcie_us_if_cq.v
View File

@ -39,14 +39,14 @@ module pcie_us_if_cq #
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32),
// PCIe AXI stream CQ tuser signal width
parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
// TLP data width
parameter TLP_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH,
// TLP strobe width
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
// TLP header width
parameter TLP_HDR_WIDTH = 128,
// TLP segment count
parameter TLP_SEG_COUNT = 1,
// TLP segment data width
parameter TLP_SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH/TLP_SEG_COUNT,
// TLP segment strobe width
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32,
// TLP segment header width
parameter TLP_SEG_HDR_WIDTH = 128
parameter TLP_SEG_COUNT = 1
)
(
input wire clk,
@ -65,8 +65,8 @@ module pcie_us_if_cq #
/*
* TLP output (request to BAR)
*/
output wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] rx_req_tlp_data,
output wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] rx_req_tlp_hdr,
output wire [TLP_DATA_WIDTH-1:0] rx_req_tlp_data,
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_req_tlp_hdr,
output wire [TLP_SEG_COUNT*3-1:0] rx_req_tlp_bar_id,
output wire [TLP_SEG_COUNT*8-1:0] rx_req_tlp_func_num,
output wire [TLP_SEG_COUNT-1:0] rx_req_tlp_valid,
@ -75,8 +75,6 @@ module pcie_us_if_cq #
input wire rx_req_tlp_ready
);
parameter TLP_DATA_WIDTH = TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH;
parameter TLP_STRB_WIDTH = TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH;
parameter TLP_DATA_WIDTH_BYTES = TLP_DATA_WIDTH/8;
parameter TLP_DATA_WIDTH_DWORDS = TLP_DATA_WIDTH/32;
@ -111,12 +109,12 @@ initial begin
$finish;
end
if (TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH != AXIS_PCIE_DATA_WIDTH) begin
if (TLP_DATA_WIDTH != AXIS_PCIE_DATA_WIDTH) begin
$error("Error: Interface widths must match (instance %m)");
$finish;
end
if (TLP_SEG_HDR_WIDTH != 128) begin
if (TLP_HDR_WIDTH != 128) begin
$error("Error: TLP segment header width must be 128 (instance %m)");
$finish;
end
@ -146,8 +144,8 @@ localparam [3:0]
REQ_MSG_VENDOR = 4'b1101,
REQ_MSG_ATS = 4'b1110;
reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] rx_req_tlp_data_reg = 0, rx_req_tlp_data_next;
reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] rx_req_tlp_hdr_reg = 0, rx_req_tlp_hdr_next;
reg [TLP_DATA_WIDTH-1:0] rx_req_tlp_data_reg = 0, rx_req_tlp_data_next;
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_req_tlp_hdr_reg = 0, rx_req_tlp_hdr_next;
reg [TLP_SEG_COUNT*3-1:0] rx_req_tlp_bar_id_reg = 0, rx_req_tlp_bar_id_next;
reg [TLP_SEG_COUNT*7-1:0] rx_req_tlp_func_num_reg = 0, rx_req_tlp_func_num_next;
reg [TLP_SEG_COUNT-1:0] rx_req_tlp_valid_reg = 0, rx_req_tlp_valid_next;

54
fpga/lib/pcie/rtl/pcie_us_if_rc.v
View File

@ -41,43 +41,41 @@ module pcie_us_if_rc #
parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161,
// PCIe AXI stream RQ tuser signal width
parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 60 : 137,
// TLP data width
parameter TLP_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH,
// TLP strobe width
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
// TLP header width
parameter TLP_HDR_WIDTH = 128,
// TLP segment count
parameter TLP_SEG_COUNT = 1,
// TLP segment data width
parameter TLP_SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH/TLP_SEG_COUNT,
// TLP segment strobe width
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32,
// TLP segment header width
parameter TLP_SEG_HDR_WIDTH = 128
parameter TLP_SEG_COUNT = 1
)
(
input wire clk,
input wire rst,
input wire clk,
input wire rst,
/*
* AXI input (RC)
*/
input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata,
input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep,
input wire s_axis_rc_tvalid,
output wire s_axis_rc_tready,
input wire s_axis_rc_tlast,
input wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser,
input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata,
input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep,
input wire s_axis_rc_tvalid,
output wire s_axis_rc_tready,
input wire s_axis_rc_tlast,
input wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser,
/*
* TLP output (completion to DMA)
*/
output wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] rx_cpl_tlp_data,
output wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] rx_cpl_tlp_hdr,
output wire [TLP_SEG_COUNT*4-1:0] rx_cpl_tlp_error,
output wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_sop,
output wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_eop,
input wire rx_cpl_tlp_ready
output wire [TLP_DATA_WIDTH-1:0] rx_cpl_tlp_data,
output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_cpl_tlp_hdr,
output wire [TLP_SEG_COUNT*4-1:0] rx_cpl_tlp_error,
output wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_valid,
output wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_sop,
output wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_eop,
input wire rx_cpl_tlp_ready
);
parameter TLP_DATA_WIDTH = TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH;
parameter TLP_STRB_WIDTH = TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH;
parameter TLP_DATA_WIDTH_BYTES = TLP_DATA_WIDTH/8;
parameter TLP_DATA_WIDTH_DWORDS = TLP_DATA_WIDTH/32;
@ -112,12 +110,12 @@ initial begin
$finish;
end
if (TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH != AXIS_PCIE_DATA_WIDTH) begin
if (TLP_DATA_WIDTH != AXIS_PCIE_DATA_WIDTH) begin
$error("Error: Interface widths must match (instance %m)");
$finish;
end
if (TLP_SEG_HDR_WIDTH != 128) begin
if (TLP_HDR_WIDTH != 128) begin
$error("Error: TLP segment header width must be 128 (instance %m)");
$finish;
end
@ -158,8 +156,8 @@ localparam [3:0]
PCIE_ERROR_FLR = 4'd8,
PCIE_ERROR_TIMEOUT = 4'd15;
reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] rx_cpl_tlp_data_reg = 0, rx_cpl_tlp_data_next;
reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] rx_cpl_tlp_hdr_reg = 0, rx_cpl_tlp_hdr_next;
reg [TLP_DATA_WIDTH-1:0] rx_cpl_tlp_data_reg = 0, rx_cpl_tlp_data_next;
reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_cpl_tlp_hdr_reg = 0, rx_cpl_tlp_hdr_next;
reg [TLP_SEG_COUNT*4-1:0] rx_cpl_tlp_error_reg = 0, rx_cpl_tlp_error_next;
reg [TLP_SEG_COUNT-1:0] rx_cpl_tlp_valid_reg = 0, rx_cpl_tlp_valid_next;
reg [TLP_SEG_COUNT-1:0] rx_cpl_tlp_sop_reg = 0, rx_cpl_tlp_sop_next;

30
fpga/lib/pcie/rtl/pcie_us_if_rq.v
View File

@ -41,14 +41,14 @@ module pcie_us_if_rq #
parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 60 : 137,
// RQ sequence number width
parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
// TLP data width
parameter TLP_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH,
// TLP strobe width
parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
// TLP header width
parameter TLP_HDR_WIDTH = 128,
// TLP segment count
parameter TLP_SEG_COUNT = 1,
// TLP segment data width
parameter TLP_SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH/TLP_SEG_COUNT,
// TLP segment strobe width
parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32,
// TLP segment header width
parameter TLP_SEG_HDR_WIDTH = 128,
// TX sequence number count
parameter TX_SEQ_NUM_COUNT = AXIS_PCIE_DATA_WIDTH < 512 ? 1 : 2,
// TX sequence number width
@ -79,7 +79,7 @@ module pcie_us_if_rq #
/*
* TLP input (read request from DMA)
*/
input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_rd_req_tlp_hdr,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_rd_req_tlp_hdr,
input wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_rd_req_tlp_seq,
input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_sop,
@ -95,9 +95,9 @@ module pcie_us_if_rq #
/*
* TLP input (write request from DMA)
*/
input wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] tx_wr_req_tlp_data,
input wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] tx_wr_req_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr,
input wire [TLP_DATA_WIDTH-1:0] tx_wr_req_tlp_data,
input wire [TLP_STRB_WIDTH-1:0] tx_wr_req_tlp_strb,
input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr,
input wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_wr_req_tlp_seq,
input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_valid,
input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_sop,
@ -111,8 +111,6 @@ module pcie_us_if_rq #
output wire [TX_SEQ_NUM_COUNT-1:0] m_axis_wr_req_tx_seq_num_valid
);
parameter TLP_DATA_WIDTH = TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH;
parameter TLP_STRB_WIDTH = TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH;
parameter TLP_DATA_WIDTH_BYTES = TLP_DATA_WIDTH/8;
parameter TLP_DATA_WIDTH_DWORDS = TLP_DATA_WIDTH/32;
@ -172,12 +170,12 @@ initial begin
$finish;
end
if (TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH != AXIS_PCIE_DATA_WIDTH) begin
if (TLP_DATA_WIDTH != AXIS_PCIE_DATA_WIDTH) begin
$error("Error: Interface widths must match (instance %m)");
$finish;
end
if (TLP_SEG_HDR_WIDTH != 128) begin
if (TLP_HDR_WIDTH != 128) begin
$error("Error: TLP segment header width must be 128 (instance %m)");
$finish;
end
@ -245,8 +243,8 @@ localparam [1:0]
reg [1:0] tlp_output_state_reg = TLP_OUTPUT_STATE_IDLE, tlp_output_state_next;
reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] out_tlp_data_reg = 0, out_tlp_data_next;
reg [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] out_tlp_strb_reg = 0, out_tlp_strb_next;
reg [TLP_DATA_WIDTH-1:0] out_tlp_data_reg = 0, out_tlp_data_next;
reg [TLP_STRB_WIDTH-1:0] out_tlp_strb_reg = 0, out_tlp_strb_next;
reg [TLP_SEG_COUNT-1:0] out_tlp_eop_reg = 0, out_tlp_eop_next;
reg [127:0] tlp_header_data_rd;

21
fpga/lib/pcie/tb/dma_client_axis_sink/test_dma_client_axis_sink.py
View File

@ -190,21 +190,14 @@ def test_dma_client_axis_sink(request, ram_data_width, axis_data_width):
parameters = {}
# segmented interface parameters
ram_addr_width = 16
seg_count = max(2, ram_data_width // 128)
seg_data_width = ram_data_width // seg_count
seg_be_width = seg_data_width // 8
seg_addr_width = ram_addr_width - (seg_count*seg_be_width-1).bit_length()
parameters['RAM_ADDR_WIDTH'] = ram_addr_width
parameters['SEG_COUNT'] = seg_count
parameters['SEG_DATA_WIDTH'] = seg_data_width
parameters['SEG_BE_WIDTH'] = seg_be_width
parameters['SEG_ADDR_WIDTH'] = seg_addr_width
parameters['RAM_ADDR_WIDTH'] = 16
parameters['SEG_COUNT'] = max(2, parameters['RAM_ADDR_WIDTH'] // 128)
parameters['SEG_DATA_WIDTH'] = ram_data_width // parameters['SEG_COUNT']
parameters['SEG_BE_WIDTH'] = parameters['SEG_DATA_WIDTH'] // 8
parameters['SEG_ADDR_WIDTH'] = parameters['RAM_ADDR_WIDTH'] - (parameters['SEG_COUNT']*parameters['SEG_BE_WIDTH']-1).bit_length()
parameters['AXIS_DATA_WIDTH'] = axis_data_width
parameters['AXIS_KEEP_ENABLE'] = int(axis_data_width > 8)
parameters['AXIS_KEEP_WIDTH'] = axis_data_width // 8
parameters['AXIS_KEEP_ENABLE'] = int(parameters['AXIS_DATA_WIDTH'] > 8)
parameters['AXIS_KEEP_WIDTH'] = parameters['AXIS_DATA_WIDTH'] // 8
parameters['AXIS_LAST_ENABLE'] = 1
parameters['AXIS_ID_ENABLE'] = 1
parameters['AXIS_ID_WIDTH'] = 8

21
fpga/lib/pcie/tb/dma_client_axis_source/test_dma_client_axis_source.py
View File

@ -181,21 +181,14 @@ def test_dma_client_axis_source(request, ram_data_width, axis_data_width):
parameters = {}
# segmented interface parameters
ram_addr_width = 16
seg_count = max(2, ram_data_width // 128)
seg_data_width = ram_data_width // seg_count
seg_be_width = seg_data_width // 8
seg_addr_width = ram_addr_width - (seg_count*seg_be_width-1).bit_length()
parameters['RAM_ADDR_WIDTH'] = ram_addr_width
parameters['SEG_COUNT'] = seg_count
parameters['SEG_DATA_WIDTH'] = seg_data_width
parameters['SEG_BE_WIDTH'] = seg_be_width
parameters['SEG_ADDR_WIDTH'] = seg_addr_width
parameters['RAM_ADDR_WIDTH'] = 16
parameters['SEG_COUNT'] = max(2, parameters['RAM_ADDR_WIDTH'] // 128)
parameters['SEG_DATA_WIDTH'] = ram_data_width // parameters['SEG_COUNT']
parameters['SEG_BE_WIDTH'] = parameters['SEG_DATA_WIDTH'] // 8
parameters['SEG_ADDR_WIDTH'] = parameters['RAM_ADDR_WIDTH'] - (parameters['SEG_COUNT']*parameters['SEG_BE_WIDTH']-1).bit_length()
parameters['AXIS_DATA_WIDTH'] = axis_data_width
parameters['AXIS_KEEP_ENABLE'] = int(axis_data_width > 8)
parameters['AXIS_KEEP_WIDTH'] = axis_data_width // 8
parameters['AXIS_KEEP_ENABLE'] = int(parameters['AXIS_DATA_WIDTH'] > 8)
parameters['AXIS_KEEP_WIDTH'] = parameters['AXIS_DATA_WIDTH'] // 8
parameters['AXIS_LAST_ENABLE'] = 1
parameters['AXIS_ID_ENABLE'] = 1
parameters['AXIS_ID_WIDTH'] = 8

6
fpga/lib/pcie/tb/dma_if_axi/Makefile
View File

@ -44,6 +44,8 @@ export PARAM_RAM_SEG_COUNT ?= 2
export PARAM_RAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) \* 2 / $(PARAM_RAM_SEG_COUNT) )
export PARAM_RAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_RAM_SEG_DATA_WIDTH) / 8 )
export PARAM_RAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())")
export PARAM_IMM_ENABLE ?= 1
export PARAM_IMM_WIDTH ?= $(PARAM_AXI_DATA_WIDTH)
export PARAM_LEN_WIDTH ?= 16
export PARAM_TAG_WIDTH ?= 8
export PARAM_READ_OP_TABLE_SIZE ?= $(shell python -c "print(2**$(PARAM_AXI_ID_WIDTH))")
@ -64,6 +66,8 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_DATA_WIDTH=$(PARAM_RAM_SEG_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_BE_WIDTH=$(PARAM_RAM_SEG_BE_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).RAM_SEG_ADDR_WIDTH=$(PARAM_RAM_SEG_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).IMM_ENABLE=$(PARAM_IMM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).IMM_WIDTH=$(PARAM_IMM_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).LEN_WIDTH=$(PARAM_LEN_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TAG_WIDTH=$(PARAM_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).READ_OP_TABLE_SIZE=$(PARAM_READ_OP_TABLE_SIZE)
@ -88,6 +92,8 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GRAM_SEG_DATA_WIDTH=$(PARAM_RAM_SEG_DATA_WIDTH)
COMPILE_ARGS += -GRAM_SEG_BE_WIDTH=$(PARAM_RAM_SEG_BE_WIDTH)
COMPILE_ARGS += -GRAM_SEG_ADDR_WIDTH=$(PARAM_RAM_SEG_ADDR_WIDTH)
COMPILE_ARGS += -GIMM_WIDTH=$(PARAM_IMM_WIDTH)
COMPILE_ARGS += -GIMM_ENABLE=$(PARAM_IMM_ENABLE)
COMPILE_ARGS += -GLEN_WIDTH=$(PARAM_LEN_WIDTH)
COMPILE_ARGS += -GTAG_WIDTH=$(PARAM_TAG_WIDTH)
COMPILE_ARGS += -GREAD_OP_TABLE_SIZE=$(PARAM_READ_OP_TABLE_SIZE)

75
fpga/lib/pcie/tb/dma_if_axi/test_dma_if_axi.py
View File

@ -50,7 +50,8 @@ except ImportError:
del sys.path[0]
DescBus, DescTransaction, DescSource, DescSink, DescMonitor = define_stream("Desc",
signals=["axi_addr", "ram_addr", "ram_sel", "len", "tag", "valid", "ready"]
signals=["axi_addr", "ram_addr", "ram_sel", "len", "tag", "valid", "ready"],
optional_signals=["imm", "imm_en"]
)
DescStatusBus, DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream("DescStatus",
@ -126,7 +127,6 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
tb.dut.write_enable.value = 1
for length in list(range(1, ram_byte_lanes+3))+list(range(128-4, 128+4))+[1024]:
# for axi_offset in axi_offsets:
for axi_offset in list(range(axi_byte_lanes+1))+list(range(4096-axi_byte_lanes, 4096)):
for ram_offset in range(1):
tb.log.info("length %d, axi_offset %d, ram_offset %d", length, axi_offset, ram_offset)
@ -211,13 +211,60 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None):
await RisingEdge(dut.clk)
async def run_test_write_imm(dut, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
axi_byte_lanes = tb.axi_ram.write_if.byte_lanes
tag_count = 2**len(tb.write_desc_source.bus.tag)
cur_tag = 1
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
await tb.cycle_reset()
tb.dut.write_enable.value = 1
for length in list(range(1, len(dut.s_axis_write_desc_imm) // 8)):
for axi_offset in list(range(axi_byte_lanes+1))+list(range(4096-axi_byte_lanes, 4096)):
tb.log.info("length %d, axi_offset %d", length, axi_offset)
axi_addr = axi_offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
imm = int.from_bytes(test_data, 'little')
tb.axi_ram.write(axi_addr-128, b'\xaa'*(len(test_data)+256))
tb.log.debug("Immediate: 0x%x", imm)
desc = DescTransaction(axi_addr=axi_addr, ram_addr=0, ram_sel=0, imm=imm, imm_en=1, len=len(test_data), tag=cur_tag)
await tb.write_desc_source.send(desc)
status = await tb.write_desc_status_sink.recv()
tb.log.info("status: %s", status)
assert int(status.tag) == cur_tag
assert int(status.error) == 0
tb.log.debug("%s", tb.axi_ram.hexdump_str((axi_addr & ~0xf)-16, (((axi_addr & 0xf)+length-1) & ~0xf)+48, prefix="AXI "))
assert tb.axi_ram.read(axi_addr-1, len(test_data)+2) == b'\xaa'+test_data+b'\xaa'
cur_tag = (cur_tag + 1) % tag_count
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
def cycle_pause():
return itertools.cycle([1, 1, 1, 0])
if cocotb.SIM_NAME:
for test in [run_test_write, run_test_read]:
for test in [run_test_write, run_test_read, run_test_write_imm]:
factory = TestFactory(test)
factory.add_option("idle_inserter", [None, cycle_pause])
@ -245,24 +292,18 @@ def test_dma_if_axi(request, axi_data_width):
parameters = {}
# segmented interface parameters
ram_sel_width = 2
ram_addr_width = 16
ram_seg_count = 2
ram_seg_data_width = axi_data_width*2 // ram_seg_count
ram_seg_be_width = ram_seg_data_width // 8
ram_seg_addr_width = ram_addr_width - (ram_seg_count*ram_seg_be_width-1).bit_length()
parameters['AXI_DATA_WIDTH'] = axi_data_width
parameters['AXI_ADDR_WIDTH'] = 16
parameters['AXI_STRB_WIDTH'] = parameters['AXI_DATA_WIDTH'] // 8
parameters['AXI_ID_WIDTH'] = 8
parameters['RAM_SEL_WIDTH'] = ram_sel_width
parameters['RAM_ADDR_WIDTH'] = ram_addr_width
parameters['RAM_SEG_COUNT'] = ram_seg_count
parameters['RAM_SEG_DATA_WIDTH'] = ram_seg_data_width
parameters['RAM_SEG_BE_WIDTH'] = ram_seg_be_width
parameters['RAM_SEG_ADDR_WIDTH'] = ram_seg_addr_width
parameters['RAM_SEL_WIDTH'] = 2
parameters['RAM_ADDR_WIDTH'] = 16
parameters['RAM_SEG_COUNT'] = 2
parameters['RAM_SEG_DATA_WIDTH'] = parameters['AXI_DATA_WIDTH']*2 // parameters['RAM_SEG_COUNT']
parameters['RAM_SEG_BE_WIDTH'] = parameters['RAM_SEG_DATA_WIDTH'] // 8
parameters['RAM_SEG_ADDR_WIDTH'] = parameters['RAM_ADDR_WIDTH'] - (parameters['RAM_SEG_COUNT']*parameters['RAM_SEG_BE_WIDTH']-1).bit_length()
parameters['IMM_ENABLE'] = 1
parameters['IMM_WIDTH'] = parameters['AXI_DATA_WIDTH']
parameters['LEN_WIDTH'] = 16
parameters['TAG_WIDTH'] = 8
parameters['READ_OP_TABLE_SIZE'] = 2**parameters['AXI_ID_WIDTH']

23
fpga/lib/pcie/tb/dma_if_axi_rd/test_dma_if_axi_rd.py
View File

@ -50,7 +50,8 @@ except ImportError:
del sys.path[0]
DescBus, DescTransaction, DescSource, DescSink, DescMonitor = define_stream("Desc",
signals=["axi_addr", "ram_addr", "ram_sel", "len", "tag", "valid", "ready"]
signals=["axi_addr", "ram_addr", "ram_sel", "len", "tag", "valid", "ready"],
optional_signals=["imm", "imm_en"]
)
DescStatusBus, DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream("DescStatus",
@ -181,24 +182,16 @@ def test_dma_if_axi_rd(request, axi_data_width):
parameters = {}
# segmented interface parameters
ram_sel_width = 2
ram_addr_width = 16
ram_seg_count = 2
ram_seg_data_width = axi_data_width*2 // ram_seg_count
ram_seg_be_width = ram_seg_data_width // 8
ram_seg_addr_width = ram_addr_width - (ram_seg_count*ram_seg_be_width-1).bit_length()
parameters['AXI_DATA_WIDTH'] = axi_data_width
parameters['AXI_ADDR_WIDTH'] = 16
parameters['AXI_STRB_WIDTH'] = parameters['AXI_DATA_WIDTH'] // 8
parameters['AXI_ID_WIDTH'] = 8
parameters['RAM_SEL_WIDTH'] = ram_sel_width
parameters['RAM_ADDR_WIDTH'] = ram_addr_width
parameters['RAM_SEG_COUNT'] = ram_seg_count
parameters['RAM_SEG_DATA_WIDTH'] = ram_seg_data_width
parameters['RAM_SEG_BE_WIDTH'] = ram_seg_be_width
parameters['RAM_SEG_ADDR_WIDTH'] = ram_seg_addr_width
parameters['RAM_SEL_WIDTH'] = 2
parameters['RAM_ADDR_WIDTH'] = 16
parameters['RAM_SEG_COUNT'] = 2
parameters['RAM_SEG_DATA_WIDTH'] = parameters['AXI_DATA_WIDTH']*2 // parameters['RAM_SEG_COUNT']
parameters['RAM_SEG_BE_WIDTH'] = parameters['RAM_SEG_DATA_WIDTH'] // 8
parameters['RAM_SEG_ADDR_WIDTH'] = parameters['RAM_ADDR_WIDTH'] - (parameters['RAM_SEG_COUNT']*parameters['RAM_SEG_BE_WIDTH']-1).bit_length()
parameters['LEN_WIDTH'] = 16
parameters['TAG_WIDTH'] = 8
parameters['OP_TABLE_SIZE'] = 2**parameters['AXI_ID_WIDTH']

38
fpga/lib/pcie/tb/dma_if_axi_wr/test_dma_if_axi_wr.py
View File

@ -50,7 +50,8 @@ except ImportError:
del sys.path[0]
DescBus, DescTransaction, DescSource, DescSink, DescMonitor = define_stream("Desc",
signals=["axi_addr", "ram_addr", "ram_sel", "imm", "imm_en", "len", "tag", "valid", "ready"]
signals=["axi_addr", "ram_addr", "ram_sel", "len", "tag", "valid", "ready"],
optional_signals=["imm", "imm_en"]
)
DescStatusBus, DescStatusTransaction, DescStatusSource, DescStatusSink, DescStatusMonitor = define_stream("DescStatus",
@ -119,7 +120,6 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None):
tb.dut.enable.value = 1
for length in list(range(0, ram_byte_lanes+3))+list(range(128-4, 128+4))+[1024]:
# for axi_offset in axi_offsets:
for axi_offset in list(range(axi_byte_lanes+1))+list(range(4096-axi_byte_lanes, 4096)):
for ram_offset in range(ram_byte_lanes+1):
tb.log.info("length %d, axi_offset %d, ram_offset %d", length, axi_offset, ram_offset)
@ -170,7 +170,6 @@ async def run_test_write_imm(dut, idle_inserter=None, backpressure_inserter=None
tb.dut.enable.value = 1
for length in list(range(1, len(dut.s_axis_write_desc_imm) // 8)):
# for axi_offset in axi_offsets:
for axi_offset in list(range(axi_byte_lanes+1))+list(range(4096-axi_byte_lanes, 4096)):
tb.log.info("length %d, axi_offset %d", length, axi_offset)
axi_addr = axi_offset+0x1000
@ -207,15 +206,12 @@ def cycle_pause():
if cocotb.SIM_NAME:
factory = TestFactory(run_test_write)
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
for test in [run_test_write, run_test_write_imm]:
factory = TestFactory(run_test_write_imm)
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
factory = TestFactory(test)
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
# cocotb-test
@ -236,24 +232,16 @@ def test_dma_if_axi_wr(request, axi_data_width):
parameters = {}
# segmented interface parameters
ram_sel_width = 2
ram_addr_width = 16
ram_seg_count = 2
ram_seg_data_width = axi_data_width*2 // ram_seg_count
ram_seg_be_width = ram_seg_data_width // 8
ram_seg_addr_width = ram_addr_width - (ram_seg_count*ram_seg_be_width-1).bit_length()
parameters['AXI_DATA_WIDTH'] = axi_data_width
parameters['AXI_ADDR_WIDTH'] = 16
parameters['AXI_STRB_WIDTH'] = parameters['AXI_DATA_WIDTH'] // 8
parameters['AXI_ID_WIDTH'] = 8
parameters['RAM_SEL_WIDTH'] = ram_sel_width
parameters['RAM_ADDR_WIDTH'] = ram_addr_width
parameters['RAM_SEG_COUNT'] = ram_seg_count
parameters['RAM_SEG_DATA_WIDTH'] = ram_seg_data_width
parameters['RAM_SEG_BE_WIDTH'] = ram_seg_be_width
parameters['RAM_SEG_ADDR_WIDTH'] = ram_seg_addr_width
parameters['RAM_SEL_WIDTH'] = 2
parameters['RAM_ADDR_WIDTH'] = 16
parameters['RAM_SEG_COUNT'] = 2
parameters['RAM_SEG_DATA_WIDTH'] = parameters['AXI_DATA_WIDTH']*2 // parameters['RAM_SEG_COUNT']
parameters['RAM_SEG_BE_WIDTH'] = parameters['RAM_SEG_DATA_WIDTH'] // 8
parameters['RAM_SEG_ADDR_WIDTH'] = parameters['RAM_ADDR_WIDTH'] - (parameters['RAM_SEG_COUNT']*parameters['RAM_SEG_BE_WIDTH']-1).bit_length()
parameters['IMM_ENABLE'] = 1
parameters['IMM_WIDTH'] = parameters['AXI_DATA_WIDTH']
parameters['LEN_WIDTH'] = 16

14
fpga/lib/pcie/tb/dma_if_pcie_rd/Makefile
View File

@ -32,16 +32,16 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_TLP_DATA_WIDTH ?= 64
export PARAM_TLP_HDR_WIDTH ?= 128
export PARAM_TLP_SEG_COUNT ?= 1
export PARAM_TLP_SEG_DATA_WIDTH ?= 64
export PARAM_TLP_SEG_HDR_WIDTH ?= 128
export PARAM_TX_SEQ_NUM_COUNT ?= 1
export PARAM_TX_SEQ_NUM_WIDTH ?= 6
export PARAM_TX_SEQ_NUM_ENABLE ?= 1
export PARAM_RAM_SEL_WIDTH ?= 2
export PARAM_RAM_ADDR_WIDTH ?= 16
export PARAM_RAM_SEG_COUNT ?= $(shell expr $(PARAM_TLP_SEG_COUNT) \* 2 )
export PARAM_RAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_TLP_SEG_COUNT) \* $(PARAM_TLP_SEG_DATA_WIDTH) \* 2 / $(PARAM_RAM_SEG_COUNT) )
export PARAM_RAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) \* 2 / $(PARAM_RAM_SEG_COUNT) )
export PARAM_RAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_RAM_SEG_DATA_WIDTH) / 8 )
export PARAM_RAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())")
export PARAM_PCIE_ADDR_WIDTH ?= 64
@ -57,9 +57,9 @@ export PARAM_CHECK_BUS_NUMBER ?= 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += -P $(TOPLEVEL).TLP_DATA_WIDTH=$(PARAM_TLP_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_HDR_WIDTH=$(PARAM_TLP_HDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_COUNT=$(PARAM_TLP_SEG_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_DATA_WIDTH=$(PARAM_TLP_SEG_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_HDR_WIDTH=$(PARAM_TLP_SEG_HDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SEQ_NUM_COUNT=$(PARAM_TX_SEQ_NUM_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SEQ_NUM_WIDTH=$(PARAM_TX_SEQ_NUM_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SEQ_NUM_ENABLE=$(PARAM_TX_SEQ_NUM_ENABLE)
@ -86,9 +86,9 @@ ifeq ($(SIM), icarus)
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
COMPILE_ARGS += -GTLP_DATA_WIDTH=$(PARAM_TLP_DATA_WIDTH)
COMPILE_ARGS += -GTLP_HDR_WIDTH=$(PARAM_TLP_HDR_WIDTH)
COMPILE_ARGS += -GTLP_SEG_COUNT=$(PARAM_TLP_SEG_COUNT)
COMPILE_ARGS += -GTLP_SEG_DATA_WIDTH=$(PARAM_TLP_SEG_DATA_WIDTH)
COMPILE_ARGS += -GTLP_SEG_HDR_WIDTH=$(PARAM_TLP_SEG_HDR_WIDTH)
COMPILE_ARGS += -GTX_SEQ_NUM_COUNT=$(PARAM_TX_SEQ_NUM_COUNT)
COMPILE_ARGS += -GTX_SEQ_NUM_WIDTH=$(PARAM_TX_SEQ_NUM_WIDTH)
COMPILE_ARGS += -GTX_SEQ_NUM_ENABLE=$(PARAM_TX_SEQ_NUM_ENABLE)

29
fpga/lib/pcie/tb/dma_if_pcie_rd/test_dma_if_pcie_rd.py
View File

@ -314,29 +314,18 @@ def test_dma_if_pcie_rd(request, pcie_data_width, pcie_offset):
parameters = {}
# segmented interface parameters
tlp_seg_count = 1
tlp_seg_data_width = pcie_data_width // tlp_seg_count
ram_sel_width = 2
ram_addr_width = 16
ram_seg_count = tlp_seg_count*2
ram_seg_data_width = (tlp_seg_count*tlp_seg_data_width)*2 // ram_seg_count
ram_seg_be_width = ram_seg_data_width // 8
ram_seg_addr_width = ram_addr_width - (ram_seg_count*ram_seg_be_width-1).bit_length()
parameters['TLP_SEG_COUNT'] = tlp_seg_count
parameters['TLP_SEG_DATA_WIDTH'] = tlp_seg_data_width
parameters['TLP_SEG_HDR_WIDTH'] = 128
parameters['TLP_DATA_WIDTH'] = pcie_data_width
parameters['TLP_HDR_WIDTH'] = 128
parameters['TLP_SEG_COUNT'] = 1
parameters['TX_SEQ_NUM_COUNT'] = 1
parameters['TX_SEQ_NUM_WIDTH'] = 6
parameters['TX_SEQ_NUM_ENABLE'] = 1
parameters['RAM_SEL_WIDTH'] = ram_sel_width
parameters['RAM_ADDR_WIDTH'] = ram_addr_width
parameters['RAM_SEG_COUNT'] = ram_seg_count
parameters['RAM_SEG_DATA_WIDTH'] = ram_seg_data_width
parameters['RAM_SEG_BE_WIDTH'] = ram_seg_be_width
parameters['RAM_SEG_ADDR_WIDTH'] = ram_seg_addr_width
parameters['RAM_SEL_WIDTH'] = 2
parameters['RAM_ADDR_WIDTH'] = 16
parameters['RAM_SEG_COUNT'] = parameters['TLP_SEG_COUNT']*2
parameters['RAM_SEG_DATA_WIDTH'] = parameters['TLP_DATA_WIDTH']*2 // parameters['RAM_SEG_COUNT']
parameters['RAM_SEG_BE_WIDTH'] = parameters['RAM_SEG_DATA_WIDTH'] // 8
parameters['RAM_SEG_ADDR_WIDTH'] = parameters['RAM_ADDR_WIDTH'] - (parameters['RAM_SEG_COUNT']*parameters['RAM_SEG_BE_WIDTH']-1).bit_length()
parameters['PCIE_ADDR_WIDTH'] = 64
parameters['PCIE_TAG_COUNT'] = 256
parameters['LEN_WIDTH'] = 20

26
fpga/lib/pcie/tb/dma_if_pcie_us/test_dma_if_pcie_us.py
View File

@ -77,8 +77,10 @@ class TB(object):
# pcie_link_width=2,
# user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
cq_straddle=False,
cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False,
pf_count=1,
max_payload_size=1024,
@ -423,26 +425,18 @@ def test_dma_if_pcie_us(request, axis_pcie_data_width):
parameters = {}
# segmented interface parameters
ram_sel_width = 2
ram_addr_width = 16
seg_count = max(2, axis_pcie_data_width*2 // 128)
seg_data_width = axis_pcie_data_width*2 // seg_count
seg_be_width = seg_data_width // 8
seg_addr_width = ram_addr_width - (seg_count*seg_be_width-1).bit_length()
parameters['AXIS_PCIE_DATA_WIDTH'] = axis_pcie_data_width
parameters['AXIS_PCIE_KEEP_WIDTH'] = parameters['AXIS_PCIE_DATA_WIDTH'] // 32
parameters['AXIS_PCIE_RQ_USER_WIDTH'] = 62 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 137
parameters['AXIS_PCIE_RC_USER_WIDTH'] = 75 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 161
parameters['RQ_SEQ_NUM_WIDTH'] = 4 if parameters['AXIS_PCIE_RQ_USER_WIDTH'] == 60 else 6
parameters['RQ_SEQ_NUM_ENABLE'] = 1
parameters['RAM_SEL_WIDTH'] = ram_sel_width
parameters['RAM_ADDR_WIDTH'] = ram_addr_width
parameters['SEG_COUNT'] = seg_count
parameters['SEG_DATA_WIDTH'] = seg_data_width
parameters['SEG_BE_WIDTH'] = seg_be_width
parameters['SEG_ADDR_WIDTH'] = seg_addr_width
parameters['RAM_SEL_WIDTH'] = 2
parameters['RAM_ADDR_WIDTH'] = 16
parameters['SEG_COUNT'] = max(2, parameters['AXIS_PCIE_DATA_WIDTH']*2 // 128)
parameters['SEG_DATA_WIDTH'] = parameters['AXIS_PCIE_DATA_WIDTH']*2 // parameters['SEG_COUNT']
parameters['SEG_BE_WIDTH'] = parameters['SEG_DATA_WIDTH'] // 8
parameters['SEG_ADDR_WIDTH'] = parameters['RAM_ADDR_WIDTH'] - (parameters['SEG_COUNT']*parameters['SEG_BE_WIDTH']-1).bit_length()
parameters['PCIE_ADDR_WIDTH'] = 64
parameters['PCIE_TAG_COUNT'] = 64 if parameters['AXIS_PCIE_RQ_USER_WIDTH'] == 60 else 256
parameters['LEN_WIDTH'] = 20

26
fpga/lib/pcie/tb/dma_if_pcie_us_rd/test_dma_if_pcie_us_rd.py
View File

@ -76,8 +76,10 @@ class TB(object):
# pcie_link_width=2,
# user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
cq_straddle=False,
cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False,
pf_count=1,
max_payload_size=1024,
@ -355,26 +357,18 @@ def test_dma_if_pcie_us_rd(request, axis_pcie_data_width, pcie_offset):
parameters = {}
# segmented interface parameters
ram_sel_width = 2
ram_addr_width = 16
seg_count = max(2, axis_pcie_data_width*2 // 128)
seg_data_width = axis_pcie_data_width*2 // seg_count
seg_be_width = seg_data_width // 8
seg_addr_width = ram_addr_width - (seg_count*seg_be_width-1).bit_length()
parameters['AXIS_PCIE_DATA_WIDTH'] = axis_pcie_data_width
parameters['AXIS_PCIE_KEEP_WIDTH'] = parameters['AXIS_PCIE_DATA_WIDTH'] // 32
parameters['AXIS_PCIE_RQ_USER_WIDTH'] = 62 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 137
parameters['AXIS_PCIE_RC_USER_WIDTH'] = 75 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 161
parameters['RQ_SEQ_NUM_WIDTH'] = 4 if parameters['AXIS_PCIE_RQ_USER_WIDTH'] == 60 else 6
parameters['RQ_SEQ_NUM_ENABLE'] = 1
parameters['RAM_SEL_WIDTH'] = ram_sel_width
parameters['RAM_ADDR_WIDTH'] = ram_addr_width
parameters['SEG_COUNT'] = seg_count
parameters['SEG_DATA_WIDTH'] = seg_data_width
parameters['SEG_BE_WIDTH'] = seg_be_width
parameters['SEG_ADDR_WIDTH'] = seg_addr_width
parameters['RAM_SEL_WIDTH'] = 2
parameters['RAM_ADDR_WIDTH'] = 16
parameters['SEG_COUNT'] = max(2, parameters['AXIS_PCIE_DATA_WIDTH']*2 // 128)
parameters['SEG_DATA_WIDTH'] = parameters['AXIS_PCIE_DATA_WIDTH']*2 // parameters['SEG_COUNT']
parameters['SEG_BE_WIDTH'] = parameters['SEG_DATA_WIDTH'] // 8
parameters['SEG_ADDR_WIDTH'] = parameters['RAM_ADDR_WIDTH'] - (parameters['SEG_COUNT']*parameters['SEG_BE_WIDTH']-1).bit_length()
parameters['PCIE_ADDR_WIDTH'] = 64
parameters['PCIE_TAG_COUNT'] = 64 if parameters['AXIS_PCIE_RQ_USER_WIDTH'] == 60 else 256
parameters['LEN_WIDTH'] = 20

26
fpga/lib/pcie/tb/dma_if_pcie_us_wr/test_dma_if_pcie_us_wr.py
View File

@ -76,8 +76,10 @@ class TB(object):
# pcie_link_width=2,
# user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
cq_straddle=False,
cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False,
pf_count=1,
max_payload_size=1024,
@ -269,25 +271,17 @@ def test_dma_if_pcie_us_wr(request, axis_pcie_data_width, pcie_offset):
parameters = {}
# segmented interface parameters
ram_sel_width = 2
ram_addr_width = 16
seg_count = max(2, axis_pcie_data_width*2 // 128)
seg_data_width = axis_pcie_data_width*2 // seg_count
seg_be_width = seg_data_width // 8
seg_addr_width = ram_addr_width - (seg_count*seg_be_width-1).bit_length()
parameters['AXIS_PCIE_DATA_WIDTH'] = axis_pcie_data_width
parameters['AXIS_PCIE_KEEP_WIDTH'] = parameters['AXIS_PCIE_DATA_WIDTH'] // 32
parameters['AXIS_PCIE_RQ_USER_WIDTH'] = 62 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 137
parameters['RQ_SEQ_NUM_WIDTH'] = 4 if parameters['AXIS_PCIE_RQ_USER_WIDTH'] == 60 else 6
parameters['RQ_SEQ_NUM_ENABLE'] = 1
parameters['RAM_SEL_WIDTH'] = ram_sel_width
parameters['RAM_ADDR_WIDTH'] = ram_addr_width
parameters['SEG_COUNT'] = seg_count
parameters['SEG_DATA_WIDTH'] = seg_data_width
parameters['SEG_BE_WIDTH'] = seg_be_width
parameters['SEG_ADDR_WIDTH'] = seg_addr_width
parameters['RAM_SEL_WIDTH'] = 2
parameters['RAM_ADDR_WIDTH'] = 16
parameters['SEG_COUNT'] = max(2, parameters['AXIS_PCIE_DATA_WIDTH']*2 // 128)
parameters['SEG_DATA_WIDTH'] = parameters['AXIS_PCIE_DATA_WIDTH']*2 // parameters['SEG_COUNT']
parameters['SEG_BE_WIDTH'] = parameters['SEG_DATA_WIDTH'] // 8
parameters['SEG_ADDR_WIDTH'] = parameters['RAM_ADDR_WIDTH'] - (parameters['SEG_COUNT']*parameters['SEG_BE_WIDTH']-1).bit_length()
parameters['PCIE_ADDR_WIDTH'] = 64
parameters['LEN_WIDTH'] = 20
parameters['TAG_WIDTH'] = 8

22
fpga/lib/pcie/tb/dma_if_pcie_wr/Makefile
View File

@ -32,22 +32,22 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_TLP_DATA_WIDTH ?= 64
export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
export PARAM_TLP_HDR_WIDTH ?= 128
export PARAM_TLP_SEG_COUNT ?= 1
export PARAM_TLP_SEG_DATA_WIDTH ?= 64
export PARAM_TLP_SEG_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_SEG_DATA_WIDTH) / 32 )
export PARAM_TLP_SEG_HDR_WIDTH ?= 128
export PARAM_TX_SEQ_NUM_COUNT ?= 1
export PARAM_TX_SEQ_NUM_WIDTH ?= 6
export PARAM_TX_SEQ_NUM_ENABLE ?= 1
export PARAM_RAM_SEL_WIDTH ?= 2
export PARAM_RAM_ADDR_WIDTH ?= 16
export PARAM_RAM_SEG_COUNT ?= $(shell expr $(PARAM_TLP_SEG_COUNT) \* 2 )
export PARAM_RAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_TLP_SEG_COUNT) \* $(PARAM_TLP_SEG_DATA_WIDTH) \* 2 / $(PARAM_RAM_SEG_COUNT) )
export PARAM_RAM_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) \* 2 / $(PARAM_RAM_SEG_COUNT) )
export PARAM_RAM_SEG_BE_WIDTH ?= $(shell expr $(PARAM_RAM_SEG_DATA_WIDTH) / 8 )
export PARAM_RAM_SEG_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_ADDR_WIDTH) - ($(PARAM_RAM_SEG_COUNT)*$(PARAM_RAM_SEG_BE_WIDTH)-1).bit_length())")
export PARAM_PCIE_ADDR_WIDTH ?= 64
export PARAM_IMM_ENABLE ?= 1
export PARAM_IMM_WIDTH ?= $(shell expr $(PARAM_TLP_SEG_COUNT) \* $(PARAM_TLP_SEG_DATA_WIDTH) )
export PARAM_IMM_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) )
export PARAM_LEN_WIDTH ?= 20
export PARAM_TAG_WIDTH ?= 8
export PARAM_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << ($(PARAM_TX_SEQ_NUM_WIDTH)-1) ))" )
@ -58,10 +58,10 @@ export PARAM_TLP_FORCE_64_BIT_ADDR ?= 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += -P $(TOPLEVEL).TLP_DATA_WIDTH=$(PARAM_TLP_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_STRB_WIDTH=$(PARAM_TLP_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_HDR_WIDTH=$(PARAM_TLP_HDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_COUNT=$(PARAM_TLP_SEG_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_DATA_WIDTH=$(PARAM_TLP_SEG_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_STRB_WIDTH=$(PARAM_TLP_SEG_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_HDR_WIDTH=$(PARAM_TLP_SEG_HDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SEQ_NUM_COUNT=$(PARAM_TX_SEQ_NUM_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SEQ_NUM_WIDTH=$(PARAM_TX_SEQ_NUM_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SEQ_NUM_ENABLE=$(PARAM_TX_SEQ_NUM_ENABLE)
@ -88,10 +88,10 @@ ifeq ($(SIM), icarus)
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
COMPILE_ARGS += -GTLP_DATA_WIDTH=$(PARAM_TLP_DATA_WIDTH)
COMPILE_ARGS += -GTLP_STRB_WIDTH=$(PARAM_TLP_STRB_WIDTH)
COMPILE_ARGS += -GTLP_HDR_WIDTH=$(PARAM_TLP_HDR_WIDTH)
COMPILE_ARGS += -GTLP_SEG_COUNT=$(PARAM_TLP_SEG_COUNT)
COMPILE_ARGS += -GTLP_SEG_DATA_WIDTH=$(PARAM_TLP_SEG_DATA_WIDTH)
COMPILE_ARGS += -GTLP_SEG_STRB_WIDTH=$(PARAM_TLP_SEG_STRB_WIDTH)
COMPILE_ARGS += -GTLP_SEG_HDR_WIDTH=$(PARAM_TLP_SEG_HDR_WIDTH)
COMPILE_ARGS += -GTX_SEQ_NUM_COUNT=$(PARAM_TX_SEQ_NUM_COUNT)
COMPILE_ARGS += -GTX_SEQ_NUM_WIDTH=$(PARAM_TX_SEQ_NUM_WIDTH)
COMPILE_ARGS += -GTX_SEQ_NUM_ENABLE=$(PARAM_TX_SEQ_NUM_ENABLE)

34
fpga/lib/pcie/tb/dma_if_pcie_wr/test_dma_if_pcie_wr.py
View File

@ -285,34 +285,22 @@ def test_dma_if_pcie_wr(request, pcie_data_width, pcie_offset):
parameters = {}
# segmented interface parameters
tlp_seg_count = 1
tlp_seg_data_width = pcie_data_width // tlp_seg_count
tlp_seg_strb_width = tlp_seg_data_width // 32
ram_sel_width = 2
ram_addr_width = 16
ram_seg_count = tlp_seg_count*2
ram_seg_data_width = (tlp_seg_count*tlp_seg_data_width)*2 // ram_seg_count
ram_seg_be_width = ram_seg_data_width // 8
ram_seg_addr_width = ram_addr_width - (ram_seg_count*ram_seg_be_width-1).bit_length()
parameters['TLP_SEG_COUNT'] = tlp_seg_count
parameters['TLP_SEG_DATA_WIDTH'] = tlp_seg_data_width
parameters['TLP_SEG_STRB_WIDTH'] = tlp_seg_strb_width
parameters['TLP_SEG_HDR_WIDTH'] = 128
parameters['TLP_DATA_WIDTH'] = pcie_data_width
parameters['TLP_STRB_WIDTH'] = parameters['TLP_DATA_WIDTH'] // 32
parameters['TLP_HDR_WIDTH'] = 128
parameters['TLP_SEG_COUNT'] = 1
parameters['TX_SEQ_NUM_COUNT'] = 1
parameters['TX_SEQ_NUM_WIDTH'] = 6
parameters['TX_SEQ_NUM_ENABLE'] = 1
parameters['RAM_SEL_WIDTH'] = ram_sel_width
parameters['RAM_ADDR_WIDTH'] = ram_addr_width
parameters['RAM_SEG_COUNT'] = ram_seg_count
parameters['RAM_SEG_DATA_WIDTH'] = ram_seg_data_width
parameters['RAM_SEG_BE_WIDTH'] = ram_seg_be_width
parameters['RAM_SEG_ADDR_WIDTH'] = ram_seg_addr_width
parameters['RAM_SEL_WIDTH'] = 2
parameters['RAM_ADDR_WIDTH'] = 16
parameters['RAM_SEG_COUNT'] = parameters['TLP_SEG_COUNT']*2
parameters['RAM_SEG_DATA_WIDTH'] = parameters['TLP_DATA_WIDTH']*2 // parameters['RAM_SEG_COUNT']
parameters['RAM_SEG_BE_WIDTH'] = parameters['RAM_SEG_DATA_WIDTH'] // 8
parameters['RAM_SEG_ADDR_WIDTH'] = parameters['RAM_ADDR_WIDTH'] - (parameters['RAM_SEG_COUNT']*parameters['RAM_SEG_BE_WIDTH']-1).bit_length()
parameters['PCIE_ADDR_WIDTH'] = 64
parameters['IMM_ENABLE'] = 1
parameters['IMM_WIDTH'] = parameters['TLP_SEG_COUNT'] * parameters['TLP_SEG_DATA_WIDTH']
parameters['IMM_WIDTH'] = parameters['TLP_DATA_WIDTH']
parameters['LEN_WIDTH'] = 20
parameters['TAG_WIDTH'] = 8
parameters['OP_TABLE_SIZE'] = 2**(parameters['TX_SEQ_NUM_WIDTH']-1)

20
fpga/lib/pcie/tb/pcie_axi_master/Makefile
View File

@ -37,11 +37,11 @@ VERILOG_SOURCES += ../../rtl/pcie_tlp_demux.v
VERILOG_SOURCES += ../../rtl/pulse_merge.v
# module parameters
export PARAM_TLP_DATA_WIDTH ?= 64
export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
export PARAM_TLP_HDR_WIDTH ?= 128
export PARAM_TLP_SEG_COUNT ?= 1
export PARAM_TLP_SEG_DATA_WIDTH ?= 64
export PARAM_TLP_SEG_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_SEG_DATA_WIDTH) / 32 )
export PARAM_TLP_SEG_HDR_WIDTH ?= 128
export PARAM_AXI_DATA_WIDTH ?= $(shell expr $(PARAM_TLP_SEG_COUNT) \* $(PARAM_TLP_SEG_DATA_WIDTH) )
export PARAM_AXI_DATA_WIDTH ?= $(PARAM_TLP_DATA_WIDTH)
export PARAM_AXI_ADDR_WIDTH ?= 64
export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 )
export PARAM_AXI_ID_WIDTH ?= 8
@ -51,10 +51,10 @@ export PARAM_TLP_FORCE_64_BIT_ADDR ?= 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += -P $(TOPLEVEL).TLP_DATA_WIDTH=$(PARAM_TLP_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_STRB_WIDTH=$(PARAM_TLP_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_HDR_WIDTH=$(PARAM_TLP_HDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_COUNT=$(PARAM_TLP_SEG_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_DATA_WIDTH=$(PARAM_TLP_SEG_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_STRB_WIDTH=$(PARAM_TLP_SEG_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_HDR_WIDTH=$(PARAM_TLP_SEG_HDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_DATA_WIDTH=$(PARAM_AXI_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_ADDR_WIDTH=$(PARAM_AXI_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_STRB_WIDTH=$(PARAM_AXI_STRB_WIDTH)
@ -69,10 +69,10 @@ ifeq ($(SIM), icarus)
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH -Wno-CASEINCOMPLETE -Wno-UNOPT
COMPILE_ARGS += -GTLP_DATA_WIDTH=$(PARAM_TLP_DATA_WIDTH)
COMPILE_ARGS += -GTLP_STRB_WIDTH=$(PARAM_TLP_STRB_WIDTH)
COMPILE_ARGS += -GTLP_HDR_WIDTH=$(PARAM_TLP_HDR_WIDTH)
COMPILE_ARGS += -GTLP_SEG_COUNT=$(PARAM_TLP_SEG_COUNT)
COMPILE_ARGS += -GTLP_SEG_DATA_WIDTH=$(PARAM_TLP_SEG_DATA_WIDTH)
COMPILE_ARGS += -GTLP_SEG_STRB_WIDTH=$(PARAM_TLP_SEG_STRB_WIDTH)
COMPILE_ARGS += -GTLP_SEG_HDR_WIDTH=$(PARAM_TLP_SEG_HDR_WIDTH)
COMPILE_ARGS += -GAXI_DATA_WIDTH=$(PARAM_AXI_DATA_WIDTH)
COMPILE_ARGS += -GAXI_ADDR_WIDTH=$(PARAM_AXI_ADDR_WIDTH)
COMPILE_ARGS += -GAXI_STRB_WIDTH=$(PARAM_AXI_STRB_WIDTH)

15
fpga/lib/pcie/tb/pcie_axi_master/test_pcie_axi_master.py
View File

@ -330,16 +330,11 @@ def test_pcie_axi_master(request, pcie_data_width):
parameters = {}
# segmented interface parameters
tlp_seg_count = 1
tlp_seg_data_width = pcie_data_width // tlp_seg_count
tlp_seg_strb_width = tlp_seg_data_width // 32
parameters['TLP_SEG_COUNT'] = tlp_seg_count
parameters['TLP_SEG_DATA_WIDTH'] = tlp_seg_data_width
parameters['TLP_SEG_STRB_WIDTH'] = tlp_seg_strb_width
parameters['TLP_SEG_HDR_WIDTH'] = 128
parameters['AXI_DATA_WIDTH'] = parameters['TLP_SEG_COUNT'] * parameters['TLP_SEG_DATA_WIDTH']
parameters['TLP_DATA_WIDTH'] = pcie_data_width
parameters['TLP_STRB_WIDTH'] = parameters['TLP_DATA_WIDTH'] // 32
parameters['TLP_HDR_WIDTH'] = 128
parameters['TLP_SEG_COUNT'] = 1
parameters['AXI_DATA_WIDTH'] = parameters['TLP_DATA_WIDTH']
parameters['AXI_ADDR_WIDTH'] = 64
parameters['AXI_STRB_WIDTH'] = parameters['AXI_DATA_WIDTH'] // 8
parameters['AXI_ID_WIDTH'] = 8

20
fpga/lib/pcie/tb/pcie_axi_master_rd/Makefile
View File

@ -33,11 +33,11 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_TLP_DATA_WIDTH ?= 64
export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
export PARAM_TLP_HDR_WIDTH ?= 128
export PARAM_TLP_SEG_COUNT ?= 1
export PARAM_TLP_SEG_DATA_WIDTH ?= 64
export PARAM_TLP_SEG_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_SEG_DATA_WIDTH) / 32 )
export PARAM_TLP_SEG_HDR_WIDTH ?= 128
export PARAM_AXI_DATA_WIDTH ?= $(shell expr $(PARAM_TLP_SEG_COUNT) \* $(PARAM_TLP_SEG_DATA_WIDTH) )
export PARAM_AXI_DATA_WIDTH ?= $(PARAM_TLP_DATA_WIDTH)
export PARAM_AXI_ADDR_WIDTH ?= 64
export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 )
export PARAM_AXI_ID_WIDTH ?= 8
@ -47,10 +47,10 @@ export PARAM_TLP_FORCE_64_BIT_ADDR ?= 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += -P $(TOPLEVEL).TLP_DATA_WIDTH=$(PARAM_TLP_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_STRB_WIDTH=$(PARAM_TLP_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_HDR_WIDTH=$(PARAM_TLP_HDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_COUNT=$(PARAM_TLP_SEG_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_DATA_WIDTH=$(PARAM_TLP_SEG_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_STRB_WIDTH=$(PARAM_TLP_SEG_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_HDR_WIDTH=$(PARAM_TLP_SEG_HDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_DATA_WIDTH=$(PARAM_AXI_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_ADDR_WIDTH=$(PARAM_AXI_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_STRB_WIDTH=$(PARAM_AXI_STRB_WIDTH)
@ -65,10 +65,10 @@ ifeq ($(SIM), icarus)
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH -Wno-CASEINCOMPLETE -Wno-UNOPT
COMPILE_ARGS += -GTLP_DATA_WIDTH=$(PARAM_TLP_DATA_WIDTH)
COMPILE_ARGS += -GTLP_STRB_WIDTH=$(PARAM_TLP_STRB_WIDTH)
COMPILE_ARGS += -GTLP_HDR_WIDTH=$(PARAM_TLP_HDR_WIDTH)
COMPILE_ARGS += -GTLP_SEG_COUNT=$(PARAM_TLP_SEG_COUNT)
COMPILE_ARGS += -GTLP_SEG_DATA_WIDTH=$(PARAM_TLP_SEG_DATA_WIDTH)
COMPILE_ARGS += -GTLP_SEG_STRB_WIDTH=$(PARAM_TLP_SEG_STRB_WIDTH)
COMPILE_ARGS += -GTLP_SEG_HDR_WIDTH=$(PARAM_TLP_SEG_HDR_WIDTH)
COMPILE_ARGS += -GAXI_DATA_WIDTH=$(PARAM_AXI_DATA_WIDTH)
COMPILE_ARGS += -GAXI_ADDR_WIDTH=$(PARAM_AXI_ADDR_WIDTH)
COMPILE_ARGS += -GAXI_STRB_WIDTH=$(PARAM_AXI_STRB_WIDTH)

15
fpga/lib/pcie/tb/pcie_axi_master_rd/test_pcie_axi_master_rd.py
View File

@ -304,16 +304,11 @@ def test_pcie_axi_master_rd(request, pcie_data_width):
parameters = {}
# segmented interface parameters
tlp_seg_count = 1
tlp_seg_data_width = pcie_data_width // tlp_seg_count
tlp_seg_strb_width = tlp_seg_data_width // 32
parameters['TLP_SEG_COUNT'] = tlp_seg_count
parameters['TLP_SEG_DATA_WIDTH'] = tlp_seg_data_width
parameters['TLP_SEG_STRB_WIDTH'] = tlp_seg_strb_width
parameters['TLP_SEG_HDR_WIDTH'] = 128
parameters['AXI_DATA_WIDTH'] = parameters['TLP_SEG_COUNT'] * parameters['TLP_SEG_DATA_WIDTH']
parameters['TLP_DATA_WIDTH'] = pcie_data_width
parameters['TLP_STRB_WIDTH'] = parameters['TLP_DATA_WIDTH'] // 32
parameters['TLP_HDR_WIDTH'] = 128
parameters['TLP_SEG_COUNT'] = 1
parameters['AXI_DATA_WIDTH'] = parameters['TLP_DATA_WIDTH']
parameters['AXI_ADDR_WIDTH'] = 64
parameters['AXI_STRB_WIDTH'] = parameters['AXI_DATA_WIDTH'] // 8
parameters['AXI_ID_WIDTH'] = 8

14
fpga/lib/pcie/tb/pcie_axi_master_wr/Makefile
View File

@ -33,10 +33,10 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
# module parameters
export PARAM_TLP_DATA_WIDTH ?= 64
export PARAM_TLP_HDR_WIDTH ?= 128
export PARAM_TLP_SEG_COUNT ?= 1
export PARAM_TLP_SEG_DATA_WIDTH ?= 64
export PARAM_TLP_SEG_HDR_WIDTH ?= 128
export PARAM_AXI_DATA_WIDTH ?= $(shell expr $(PARAM_TLP_SEG_COUNT) \* $(PARAM_TLP_SEG_DATA_WIDTH) )
export PARAM_AXI_DATA_WIDTH ?= $(PARAM_TLP_DATA_WIDTH)
export PARAM_AXI_ADDR_WIDTH ?= 64
export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 )
export PARAM_AXI_ID_WIDTH ?= 8
@ -46,9 +46,9 @@ export PARAM_TLP_FORCE_64_BIT_ADDR ?= 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += -P $(TOPLEVEL).TLP_DATA_WIDTH=$(PARAM_TLP_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_HDR_WIDTH=$(PARAM_TLP_HDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_COUNT=$(PARAM_TLP_SEG_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_DATA_WIDTH=$(PARAM_TLP_SEG_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_HDR_WIDTH=$(PARAM_TLP_SEG_HDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_DATA_WIDTH=$(PARAM_AXI_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_ADDR_WIDTH=$(PARAM_AXI_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_STRB_WIDTH=$(PARAM_AXI_STRB_WIDTH)
@ -63,9 +63,9 @@ ifeq ($(SIM), icarus)
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH -Wno-CASEINCOMPLETE -Wno-UNOPT
COMPILE_ARGS += -GTLP_DATA_WIDTH=$(PARAM_TLP_DATA_WIDTH)
COMPILE_ARGS += -GTLP_HDR_WIDTH=$(PARAM_TLP_HDR_WIDTH)
COMPILE_ARGS += -GTLP_SEG_COUNT=$(PARAM_TLP_SEG_COUNT)
COMPILE_ARGS += -GTLP_SEG_DATA_WIDTH=$(PARAM_TLP_SEG_DATA_WIDTH)
COMPILE_ARGS += -GTLP_SEG_HDR_WIDTH=$(PARAM_TLP_SEG_HDR_WIDTH)
COMPILE_ARGS += -GAXI_DATA_WIDTH=$(PARAM_AXI_DATA_WIDTH)
COMPILE_ARGS += -GAXI_ADDR_WIDTH=$(PARAM_AXI_ADDR_WIDTH)
COMPILE_ARGS += -GAXI_STRB_WIDTH=$(PARAM_AXI_STRB_WIDTH)

12
fpga/lib/pcie/tb/pcie_axi_master_wr/test_pcie_axi_master_wr.py
View File

@ -277,14 +277,10 @@ def test_pcie_axi_master_wr(request, pcie_data_width):
parameters = {}
# segmented interface parameters
tlp_seg_count = 1
tlp_seg_data_width = pcie_data_width // tlp_seg_count
parameters['TLP_SEG_COUNT'] = tlp_seg_count
parameters['TLP_SEG_DATA_WIDTH'] = tlp_seg_data_width
parameters['TLP_SEG_HDR_WIDTH'] = 128
parameters['AXI_DATA_WIDTH'] = parameters['TLP_SEG_COUNT'] * parameters['TLP_SEG_DATA_WIDTH']
parameters['TLP_DATA_WIDTH'] = pcie_data_width
parameters['TLP_HDR_WIDTH'] = 128
parameters['TLP_SEG_COUNT'] = 1
parameters['AXI_DATA_WIDTH'] = parameters['TLP_DATA_WIDTH']
parameters['AXI_ADDR_WIDTH'] = 64
parameters['AXI_STRB_WIDTH'] = parameters['AXI_DATA_WIDTH'] // 8
parameters['AXI_ID_WIDTH'] = 8

18
fpga/lib/pcie/tb/pcie_axil_master/Makefile
View File

@ -33,10 +33,10 @@ MODULE = test_$(DUT)
VERILOG_SOURCES = ../../rtl/$(DUT).v
# module parameters
export PARAM_TLP_DATA_WIDTH ?= 64
export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
export PARAM_TLP_HDR_WIDTH ?= 128
export PARAM_TLP_SEG_COUNT ?= 1
export PARAM_TLP_SEG_DATA_WIDTH ?= 64
export PARAM_TLP_SEG_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_SEG_DATA_WIDTH) / 32 )
export PARAM_TLP_SEG_HDR_WIDTH ?= 128
export PARAM_AXIL_DATA_WIDTH ?= 32
export PARAM_AXIL_ADDR_WIDTH ?= 64
export PARAM_AXIL_STRB_WIDTH ?= $(shell expr $(PARAM_AXIL_DATA_WIDTH) / 8 )
@ -45,10 +45,10 @@ export PARAM_TLP_FORCE_64_BIT_ADDR ?= 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += -P $(TOPLEVEL).TLP_DATA_WIDTH=$(PARAM_TLP_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_STRB_WIDTH=$(PARAM_TLP_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_HDR_WIDTH=$(PARAM_TLP_HDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_COUNT=$(PARAM_TLP_SEG_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_DATA_WIDTH=$(PARAM_TLP_SEG_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_STRB_WIDTH=$(PARAM_TLP_SEG_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_HDR_WIDTH=$(PARAM_TLP_SEG_HDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_DATA_WIDTH=$(PARAM_AXIL_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_ADDR_WIDTH=$(PARAM_AXIL_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_STRB_WIDTH=$(PARAM_AXIL_STRB_WIDTH)
@ -61,10 +61,10 @@ ifeq ($(SIM), icarus)
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
COMPILE_ARGS += -GTLP_DATA_WIDTH=$(PARAM_TLP_DATA_WIDTH)
COMPILE_ARGS += -GTLP_STRB_WIDTH=$(PARAM_TLP_STRB_WIDTH)
COMPILE_ARGS += -GTLP_HDR_WIDTH=$(PARAM_TLP_HDR_WIDTH)
COMPILE_ARGS += -GTLP_SEG_COUNT=$(PARAM_TLP_SEG_COUNT)
COMPILE_ARGS += -GTLP_SEG_DATA_WIDTH=$(PARAM_TLP_SEG_DATA_WIDTH)
COMPILE_ARGS += -GTLP_SEG_STRB_WIDTH=$(PARAM_TLP_SEG_STRB_WIDTH)
COMPILE_ARGS += -GTLP_SEG_HDR_WIDTH=$(PARAM_TLP_SEG_HDR_WIDTH)
COMPILE_ARGS += -GAXIL_DATA_WIDTH=$(PARAM_AXIL_DATA_WIDTH)
COMPILE_ARGS += -GAXIL_ADDR_WIDTH=$(PARAM_AXIL_ADDR_WIDTH)
COMPILE_ARGS += -GAXIL_STRB_WIDTH=$(PARAM_AXIL_STRB_WIDTH)

13
fpga/lib/pcie/tb/pcie_axil_master/test_pcie_axil_master.py
View File

@ -332,15 +332,10 @@ def test_pcie_axil_master(request, pcie_data_width, axil_data_width):
parameters = {}
# segmented interface parameters
tlp_seg_count = 1
tlp_seg_data_width = pcie_data_width // tlp_seg_count
tlp_seg_strb_width = tlp_seg_data_width // 32
parameters['TLP_SEG_COUNT'] = tlp_seg_count
parameters['TLP_SEG_DATA_WIDTH'] = tlp_seg_data_width
parameters['TLP_SEG_STRB_WIDTH'] = tlp_seg_strb_width
parameters['TLP_SEG_HDR_WIDTH'] = 128
parameters['TLP_DATA_WIDTH'] = pcie_data_width
parameters['TLP_STRB_WIDTH'] = parameters['TLP_DATA_WIDTH'] // 32
parameters['TLP_HDR_WIDTH'] = 128
parameters['TLP_SEG_COUNT'] = 1
parameters['AXIL_DATA_WIDTH'] = axil_data_width
parameters['AXIL_ADDR_WIDTH'] = 64
parameters['AXIL_STRB_WIDTH'] = (axil_data_width // 8)

18
fpga/lib/pcie/tb/pcie_axil_master_minimal/Makefile
View File

@ -33,10 +33,10 @@ MODULE = test_$(DUT)
VERILOG_SOURCES = ../../rtl/$(DUT).v
# module parameters
export PARAM_TLP_DATA_WIDTH ?= 64
export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
export PARAM_TLP_HDR_WIDTH ?= 128
export PARAM_TLP_SEG_COUNT ?= 1
export PARAM_TLP_SEG_DATA_WIDTH ?= 64
export PARAM_TLP_SEG_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_SEG_DATA_WIDTH) / 32 )
export PARAM_TLP_SEG_HDR_WIDTH ?= 128
export PARAM_AXIL_DATA_WIDTH ?= 32
export PARAM_AXIL_ADDR_WIDTH ?= 64
export PARAM_AXIL_STRB_WIDTH ?= $(shell expr $(PARAM_AXIL_DATA_WIDTH) / 8 )
@ -45,10 +45,10 @@ export PARAM_TLP_FORCE_64_BIT_ADDR ?= 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += -P $(TOPLEVEL).TLP_DATA_WIDTH=$(PARAM_TLP_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_STRB_WIDTH=$(PARAM_TLP_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_HDR_WIDTH=$(PARAM_TLP_HDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_COUNT=$(PARAM_TLP_SEG_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_DATA_WIDTH=$(PARAM_TLP_SEG_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_STRB_WIDTH=$(PARAM_TLP_SEG_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_HDR_WIDTH=$(PARAM_TLP_SEG_HDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_DATA_WIDTH=$(PARAM_AXIL_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_ADDR_WIDTH=$(PARAM_AXIL_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_STRB_WIDTH=$(PARAM_AXIL_STRB_WIDTH)
@ -61,10 +61,10 @@ ifeq ($(SIM), icarus)
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
COMPILE_ARGS += -GTLP_DATA_WIDTH=$(PARAM_TLP_DATA_WIDTH)
COMPILE_ARGS += -GTLP_STRB_WIDTH=$(PARAM_TLP_STRB_WIDTH)
COMPILE_ARGS += -GTLP_HDR_WIDTH=$(PARAM_TLP_HDR_WIDTH)
COMPILE_ARGS += -GTLP_SEG_COUNT=$(PARAM_TLP_SEG_COUNT)
COMPILE_ARGS += -GTLP_SEG_DATA_WIDTH=$(PARAM_TLP_SEG_DATA_WIDTH)
COMPILE_ARGS += -GTLP_SEG_STRB_WIDTH=$(PARAM_TLP_SEG_STRB_WIDTH)
COMPILE_ARGS += -GTLP_SEG_HDR_WIDTH=$(PARAM_TLP_SEG_HDR_WIDTH)
COMPILE_ARGS += -GAXIL_DATA_WIDTH=$(PARAM_AXIL_DATA_WIDTH)
COMPILE_ARGS += -GAXIL_ADDR_WIDTH=$(PARAM_AXIL_ADDR_WIDTH)
COMPILE_ARGS += -GAXIL_STRB_WIDTH=$(PARAM_AXIL_STRB_WIDTH)

13
fpga/lib/pcie/tb/pcie_axil_master_minimal/test_pcie_axil_master_minimal.py
View File

@ -368,15 +368,10 @@ def test_pcie_axil_master_minimal(request, pcie_data_width, axil_data_width):
parameters = {}
# segmented interface parameters
tlp_seg_count = 1
tlp_seg_data_width = pcie_data_width // tlp_seg_count
tlp_seg_strb_width = tlp_seg_data_width // 32
parameters['TLP_SEG_COUNT'] = tlp_seg_count
parameters['TLP_SEG_DATA_WIDTH'] = tlp_seg_data_width
parameters['TLP_SEG_STRB_WIDTH'] = tlp_seg_strb_width
parameters['TLP_SEG_HDR_WIDTH'] = 128
parameters['TLP_DATA_WIDTH'] = pcie_data_width
parameters['TLP_STRB_WIDTH'] = parameters['TLP_DATA_WIDTH'] // 32
parameters['TLP_HDR_WIDTH'] = 128
parameters['TLP_SEG_COUNT'] = 1
parameters['AXIL_DATA_WIDTH'] = axil_data_width
parameters['AXIL_ADDR_WIDTH'] = 64
parameters['AXIL_STRB_WIDTH'] = (axil_data_width // 8)

34
fpga/lib/pcie/tb/pcie_if.py
View File

@ -1465,6 +1465,10 @@ class PcieIfTestDevice:
async def dma_io_write(self, addr, data, timeout=0, timeout_unit='ns'):
n = 0
zero_len = len(data) == 0
if zero_len:
data = b'\x00'
while True:
tlp = Tlp()
tlp.fmt_type = TlpType.IO_WRITE
@ -1474,6 +1478,9 @@ class PcieIfTestDevice:
byte_length = min(len(data)-n, 4-first_pad)
tlp.set_addr_be_data(addr, data[n:n+byte_length])
if zero_len:
tlp.first_be = 0
tlp.tag = await self.alloc_tag()
await self.tx_wr_req_tlp_source.send(PcieIfFrame.from_tlp(tlp, self.force_64bit_addr))
@ -1497,6 +1504,10 @@ class PcieIfTestDevice:
data = b''
n = 0
zero_len = length <= 0
if zero_len:
length = 1
while True:
tlp = Tlp()
tlp.fmt_type = TlpType.IO_READ
@ -1506,6 +1517,9 @@ class PcieIfTestDevice:
byte_length = min(length-n, 4-first_pad)
tlp.set_addr_be(addr, byte_length)
if zero_len:
tlp.first_be = 0
tlp.tag = await self.alloc_tag()
await self.tx_rd_req_tlp_source.send(PcieIfFrame.from_tlp(tlp, self.force_64bit_addr))
@ -1529,11 +1543,18 @@ class PcieIfTestDevice:
if n >= length:
break
if zero_len:
return b''
return data[:length]
async def dma_mem_write(self, addr, data, timeout=0, timeout_unit='ns'):
n = 0
zero_len = len(data) == 0
if zero_len:
data = b'\x00'
while True:
tlp = Tlp()
if addr > 0xffffffff:
@ -1550,6 +1571,9 @@ class PcieIfTestDevice:
byte_length = min(byte_length, 0x1000 - (addr & 0xfff))
tlp.set_addr_be_data(addr, data[n:n+byte_length])
if zero_len:
tlp.first_be = 0
await self.tx_wr_req_tlp_source.send(PcieIfFrame.from_tlp(tlp, self.force_64bit_addr))
n += byte_length
@ -1562,6 +1586,10 @@ class PcieIfTestDevice:
data = b''
n = 0
zero_len = length <= 0
if zero_len:
length = 1
while True:
tlp = Tlp()
if addr > 0xffffffff:
@ -1578,6 +1606,9 @@ class PcieIfTestDevice:
byte_length = min(byte_length, 0x1000 - (addr & 0xfff))
tlp.set_addr_be(addr, byte_length)
if zero_len:
tlp.first_be = 0
tlp.tag = await self.alloc_tag()
await self.tx_rd_req_tlp_source.send(PcieIfFrame.from_tlp(tlp, self.force_64bit_addr))
@ -1614,6 +1645,9 @@ class PcieIfTestDevice:
if n >= length:
break
if zero_len:
return b''
return data[:length]
async def issue_msi_interrupt(self, addr, data):

18
fpga/lib/pcie/tb/pcie_msix/Makefile
View File

@ -36,10 +36,10 @@ export PARAM_IRQ_INDEX_WIDTH ?= 11
export PARAM_AXIL_DATA_WIDTH ?= 32
export PARAM_AXIL_ADDR_WIDTH ?= $(shell expr $(PARAM_IRQ_INDEX_WIDTH) + 5 )
export PARAM_AXIL_STRB_WIDTH ?= $(shell expr $(PARAM_AXIL_DATA_WIDTH) / 8 )
export PARAM_TLP_DATA_WIDTH ?= 64
export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
export PARAM_TLP_HDR_WIDTH ?= 128
export PARAM_TLP_SEG_COUNT ?= 1
export PARAM_TLP_SEG_DATA_WIDTH ?= 64
export PARAM_TLP_SEG_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_SEG_DATA_WIDTH) / 32 )
export PARAM_TLP_SEG_HDR_WIDTH ?= 128
export PARAM_TLP_FORCE_64_BIT_ADDR ?= 0
ifeq ($(SIM), icarus)
@ -49,10 +49,10 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_DATA_WIDTH=$(PARAM_AXIL_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_ADDR_WIDTH=$(PARAM_AXIL_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_STRB_WIDTH=$(PARAM_AXIL_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_DATA_WIDTH=$(PARAM_TLP_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_STRB_WIDTH=$(PARAM_TLP_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_HDR_WIDTH=$(PARAM_TLP_HDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_COUNT=$(PARAM_TLP_SEG_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_DATA_WIDTH=$(PARAM_TLP_SEG_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_STRB_WIDTH=$(PARAM_TLP_SEG_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_HDR_WIDTH=$(PARAM_TLP_SEG_HDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_FORCE_64_BIT_ADDR=$(PARAM_TLP_FORCE_64_BIT_ADDR)
ifeq ($(WAVES), 1)
@ -66,10 +66,10 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GAXIL_DATA_WIDTH=$(PARAM_AXIL_DATA_WIDTH)
COMPILE_ARGS += -GAXIL_ADDR_WIDTH=$(PARAM_AXIL_ADDR_WIDTH)
COMPILE_ARGS += -GAXIL_STRB_WIDTH=$(PARAM_AXIL_STRB_WIDTH)
COMPILE_ARGS += -GTLP_DATA_WIDTH=$(PARAM_TLP_DATA_WIDTH)
COMPILE_ARGS += -GTLP_STRB_WIDTH=$(PARAM_TLP_STRB_WIDTH)
COMPILE_ARGS += -GTLP_HDR_WIDTH=$(PARAM_TLP_HDR_WIDTH)
COMPILE_ARGS += -GTLP_SEG_COUNT=$(PARAM_TLP_SEG_COUNT)
COMPILE_ARGS += -GTLP_SEG_DATA_WIDTH=$(PARAM_TLP_SEG_DATA_WIDTH)
COMPILE_ARGS += -GTLP_SEG_STRB_WIDTH=$(PARAM_TLP_SEG_STRB_WIDTH)
COMPILE_ARGS += -GTLP_SEG_HDR_WIDTH=$(PARAM_TLP_SEG_HDR_WIDTH)
COMPILE_ARGS += -GTLP_FORCE_64_BIT_ADDR=$(PARAM_TLP_FORCE_64_BIT_ADDR)
ifeq ($(WAVES), 1)

13
fpga/lib/pcie/tb/pcie_msix/test_pcie_msix.py
View File

@ -331,19 +331,14 @@ def test_pcie_msix(request, pcie_data_width, axil_data_width):
parameters = {}
# segmented interface parameters
tlp_seg_count = 1
tlp_seg_data_width = pcie_data_width // tlp_seg_count
tlp_seg_strb_width = tlp_seg_data_width // 32
parameters['IRQ_INDEX_WIDTH'] = 11
parameters['AXIL_DATA_WIDTH'] = axil_data_width
parameters['AXIL_ADDR_WIDTH'] = parameters['IRQ_INDEX_WIDTH']+5
parameters['AXIL_STRB_WIDTH'] = (axil_data_width // 8)
parameters['TLP_SEG_COUNT'] = tlp_seg_count
parameters['TLP_SEG_DATA_WIDTH'] = tlp_seg_data_width
parameters['TLP_SEG_STRB_WIDTH'] = tlp_seg_strb_width
parameters['TLP_SEG_HDR_WIDTH'] = 128
parameters['TLP_DATA_WIDTH'] = pcie_data_width
parameters['TLP_STRB_WIDTH'] = pcie_data_width // 32
parameters['TLP_HDR_WIDTH'] = 128
parameters['TLP_SEG_COUNT'] = 1
parameters['TLP_FORCE_64_BIT_ADDR'] = 0
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}

18
fpga/lib/pcie/tb/pcie_s10_if/Makefile
View File

@ -41,10 +41,10 @@ VERILOG_SOURCES += ../../rtl/priority_encoder.v
export PARAM_SEG_COUNT ?= 1
export PARAM_SEG_DATA_WIDTH ?= 256
export PARAM_SEG_EMPTY_WIDTH ?= $(shell python -c "print((($(PARAM_SEG_DATA_WIDTH)//32)-1).bit_length())" )
export PARAM_TLP_DATA_WIDTH ?= $(shell expr $(PARAM_SEG_COUNT) \* $(PARAM_SEG_DATA_WIDTH) )
export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
export PARAM_TLP_HDR_WIDTH ?= 128
export PARAM_TLP_SEG_COUNT ?= 1
export PARAM_TLP_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_SEG_COUNT) \* $(PARAM_SEG_DATA_WIDTH) / $(PARAM_TLP_SEG_COUNT) )
export PARAM_TLP_SEG_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_SEG_DATA_WIDTH) / 32 )
export PARAM_TLP_SEG_HDR_WIDTH ?= 128
export PARAM_TX_SEQ_NUM_WIDTH ?= 6
export PARAM_L_TILE ?= 0
export PARAM_PF_COUNT ?= 1
@ -60,10 +60,10 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).SEG_COUNT=$(PARAM_SEG_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).SEG_DATA_WIDTH=$(PARAM_SEG_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).SEG_EMPTY_WIDTH=$(PARAM_SEG_EMPTY_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_DATA_WIDTH=$(PARAM_TLP_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_STRB_WIDTH=$(PARAM_TLP_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_HDR_WIDTH=$(PARAM_TLP_HDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_COUNT=$(PARAM_TLP_SEG_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_DATA_WIDTH=$(PARAM_TLP_SEG_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_STRB_WIDTH=$(PARAM_TLP_SEG_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_HDR_WIDTH=$(PARAM_TLP_SEG_HDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SEQ_NUM_WIDTH=$(PARAM_TX_SEQ_NUM_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).L_TILE=$(PARAM_L_TILE)
COMPILE_ARGS += -P $(TOPLEVEL).PF_COUNT=$(PARAM_PF_COUNT)
@ -83,10 +83,10 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GSEG_COUNT=$(PARAM_SEG_COUNT)
COMPILE_ARGS += -GSEG_DATA_WIDTH=$(PARAM_SEG_DATA_WIDTH)
COMPILE_ARGS += -GSEG_EMPTY_WIDTH=$(PARAM_SEG_EMPTY_WIDTH)
COMPILE_ARGS += -GTLP_DATA_WIDTH=$(PARAM_TLP_DATA_WIDTH)
COMPILE_ARGS += -GTLP_STRB_WIDTH=$(PARAM_TLP_STRB_WIDTH)
COMPILE_ARGS += -GTLP_HDR_WIDTH=$(PARAM_TLP_HDR_WIDTH)
COMPILE_ARGS += -GTLP_SEG_COUNT=$(PARAM_TLP_SEG_COUNT)
COMPILE_ARGS += -GTLP_SEG_DATA_WIDTH=$(PARAM_TLP_SEG_DATA_WIDTH)
COMPILE_ARGS += -GTLP_SEG_STRB_WIDTH=$(PARAM_TLP_SEG_STRB_WIDTH)
COMPILE_ARGS += -GTLP_SEG_HDR_WIDTH=$(PARAM_TLP_SEG_HDR_WIDTH)
COMPILE_ARGS += -GTX_SEQ_NUM_WIDTH=$(PARAM_TX_SEQ_NUM_WIDTH)
COMPILE_ARGS += -GL_TILE=$(PARAM_L_TILE)
COMPILE_ARGS += -GPF_COUNT=$(PARAM_PF_COUNT)

13
fpga/lib/pcie/tb/pcie_s10_if/test_pcie_s10_if.py
View File

@ -571,18 +571,13 @@ def test_pcie_s10_if(request, data_width, l_tile):
parameters = {}
# segmented interface parameters
tlp_seg_count = 1
tlp_seg_data_width = data_width // tlp_seg_count
tlp_seg_strb_width = tlp_seg_data_width // 32
parameters['SEG_COUNT'] = 2 if data_width == 512 else 1
parameters['SEG_DATA_WIDTH'] = data_width // parameters['SEG_COUNT']
parameters['SEG_EMPTY_WIDTH'] = ((parameters['SEG_DATA_WIDTH'] // 32) - 1).bit_length()
parameters['TLP_SEG_COUNT'] = tlp_seg_count
parameters['TLP_SEG_DATA_WIDTH'] = tlp_seg_data_width
parameters['TLP_SEG_STRB_WIDTH'] = tlp_seg_strb_width
parameters['TLP_SEG_HDR_WIDTH'] = 128
parameters['TLP_DATA_WIDTH'] = data_width
parameters['TLP_STRB_WIDTH'] = parameters['TLP_DATA_WIDTH'] // 32
parameters['TLP_HDR_WIDTH'] = 128
parameters['TLP_SEG_COUNT'] = 1
parameters['TX_SEQ_NUM_WIDTH'] = 6
parameters['L_TILE'] = l_tile
parameters['PF_COUNT'] = 1

6
fpga/lib/pcie/tb/pcie_us_axi_dma/test_pcie_us_axi_dma.py
View File

@ -66,8 +66,10 @@ class TB(object):
# pcie_link_width=2,
# user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
cq_straddle=False,
cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False,
pf_count=1,
max_payload_size=1024,

6
fpga/lib/pcie/tb/pcie_us_axi_dma_rd/test_pcie_us_axi_dma_rd.py
View File

@ -66,8 +66,10 @@ class TB(object):
# pcie_link_width=2,
# user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
cq_straddle=False,
cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False,
pf_count=1,
max_payload_size=1024,

6
fpga/lib/pcie/tb/pcie_us_axi_dma_wr/test_pcie_us_axi_dma_wr.py
View File

@ -66,8 +66,10 @@ class TB(object):
# pcie_link_width=2,
# user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
cq_straddle=False,
cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False,
pf_count=1,
max_payload_size=1024,

6
fpga/lib/pcie/tb/pcie_us_axi_master/test_pcie_us_axi_master.py
View File

@ -71,8 +71,10 @@ class TB(object):
# pcie_link_width=2,
# user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
cq_straddle=False,
cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False,
pf_count=1,
max_payload_size=1024,

6
fpga/lib/pcie/tb/pcie_us_axi_master_rd/test_pcie_us_axi_master_rd.py
View File

@ -71,8 +71,10 @@ class TB(object):
# pcie_link_width=2,
# user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
cq_straddle=False,
cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False,
pf_count=1,
max_payload_size=1024,

6
fpga/lib/pcie/tb/pcie_us_axi_master_wr/test_pcie_us_axi_master_wr.py
View File

@ -71,8 +71,10 @@ class TB(object):
# pcie_link_width=2,
# user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
cq_straddle=False,
cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False,
pf_count=1,
max_payload_size=1024,

6
fpga/lib/pcie/tb/pcie_us_axil_master/test_pcie_us_axil_master.py
View File

@ -71,8 +71,10 @@ class TB(object):
# pcie_link_width=2,
# user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
cq_straddle=False,
cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False,
pf_count=1,
max_payload_size=1024,

18
fpga/lib/pcie/tb/pcie_us_if/Makefile
View File

@ -47,10 +47,10 @@ export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_
export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81)
export PARAM_RQ_SEQ_NUM_WIDTH ?= $(if $(filter-out 60,$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)),6,4)
export PARAM_TLP_DATA_WIDTH ?= $(PARAM_AXIS_PCIE_DATA_WIDTH)
export PARAM_TLP_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_DATA_WIDTH) / 32 )
export PARAM_TLP_HDR_WIDTH ?= 128
export PARAM_TLP_SEG_COUNT ?= 1
export PARAM_TLP_SEG_DATA_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / $(PARAM_TLP_SEG_COUNT) )
export PARAM_TLP_SEG_STRB_WIDTH ?= $(shell expr $(PARAM_TLP_SEG_DATA_WIDTH) / 32 )
export PARAM_TLP_SEG_HDR_WIDTH ?= 128
export PARAM_TX_SEQ_NUM_COUNT ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),1,2)
export PARAM_TX_SEQ_NUM_WIDTH ?= $(shell expr $(PARAM_RQ_SEQ_NUM_WIDTH) - 1 )
export PARAM_PF_COUNT ?= 1
@ -73,10 +73,10 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_CQ_USER_WIDTH=$(PARAM_AXIS_PCIE_CQ_USER_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_CC_USER_WIDTH=$(PARAM_AXIS_PCIE_CC_USER_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).RQ_SEQ_NUM_WIDTH=$(PARAM_RQ_SEQ_NUM_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_DATA_WIDTH=$(PARAM_TLP_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_STRB_WIDTH=$(PARAM_TLP_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_HDR_WIDTH=$(PARAM_TLP_HDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_COUNT=$(PARAM_TLP_SEG_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_DATA_WIDTH=$(PARAM_TLP_SEG_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_STRB_WIDTH=$(PARAM_TLP_SEG_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TLP_SEG_HDR_WIDTH=$(PARAM_TLP_SEG_HDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SEQ_NUM_COUNT=$(PARAM_TX_SEQ_NUM_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SEQ_NUM_WIDTH=$(PARAM_TX_SEQ_NUM_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).PF_COUNT=$(PARAM_PF_COUNT)
@ -103,10 +103,10 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GAXIS_PCIE_CQ_USER_WIDTH=$(PARAM_AXIS_PCIE_CQ_USER_WIDTH)
COMPILE_ARGS += -GAXIS_PCIE_CC_USER_WIDTH=$(PARAM_AXIS_PCIE_CC_USER_WIDTH)
COMPILE_ARGS += -GRQ_SEQ_NUM_WIDTH=$(PARAM_RQ_SEQ_NUM_WIDTH)
COMPILE_ARGS += -GTLP_DATA_WIDTH=$(PARAM_TLP_DATA_WIDTH)
COMPILE_ARGS += -GTLP_STRB_WIDTH=$(PARAM_TLP_STRB_WIDTH)
COMPILE_ARGS += -GTLP_HDR_WIDTH=$(PARAM_TLP_HDR_WIDTH)
COMPILE_ARGS += -GTLP_SEG_COUNT=$(PARAM_TLP_SEG_COUNT)
COMPILE_ARGS += -GTLP_SEG_DATA_WIDTH=$(PARAM_TLP_SEG_DATA_WIDTH)
COMPILE_ARGS += -GTLP_SEG_STRB_WIDTH=$(PARAM_TLP_SEG_STRB_WIDTH)
COMPILE_ARGS += -GTLP_SEG_HDR_WIDTH=$(PARAM_TLP_SEG_HDR_WIDTH)
COMPILE_ARGS += -GTX_SEQ_NUM_COUNT=$(PARAM_TX_SEQ_NUM_COUNT)
COMPILE_ARGS += -GTX_SEQ_NUM_WIDTH=$(PARAM_TX_SEQ_NUM_WIDTH)
COMPILE_ARGS += -GPF_COUNT=$(PARAM_PF_COUNT)

19
fpga/lib/pcie/tb/pcie_us_if/test_pcie_us_if.py
View File

@ -66,8 +66,10 @@ class TB(object):
# pcie_link_width=2,
# user_clk_frequency=250e6,
alignment="dword",
cq_cc_straddle=False,
rq_rc_straddle=False,
cq_straddle=False,
cc_straddle=False,
rq_straddle=False,
rc_straddle=False,
rc_4tlp_straddle=False,
pf_count=1,
max_payload_size=1024,
@ -610,11 +612,6 @@ def test_pcie_us_if(request, axis_pcie_data_width):
parameters = {}
# segmented interface parameters
tlp_seg_count = 1
tlp_seg_data_width = axis_pcie_data_width // tlp_seg_count
tlp_seg_strb_width = tlp_seg_data_width // 32
parameters['AXIS_PCIE_DATA_WIDTH'] = axis_pcie_data_width
parameters['AXIS_PCIE_KEEP_WIDTH'] = parameters['AXIS_PCIE_DATA_WIDTH'] // 32
parameters['AXIS_PCIE_RQ_USER_WIDTH'] = 62 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 137
@ -622,10 +619,10 @@ def test_pcie_us_if(request, axis_pcie_data_width):
parameters['AXIS_PCIE_CQ_USER_WIDTH'] = 88 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 183
parameters['AXIS_PCIE_CC_USER_WIDTH'] = 33 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 81
parameters['RQ_SEQ_NUM_WIDTH'] = 4 if parameters['AXIS_PCIE_RQ_USER_WIDTH'] == 60 else 6
parameters['TLP_SEG_COUNT'] = tlp_seg_count
parameters['TLP_SEG_DATA_WIDTH'] = tlp_seg_data_width
parameters['TLP_SEG_STRB_WIDTH'] = tlp_seg_strb_width
parameters['TLP_SEG_HDR_WIDTH'] = 128
parameters['TLP_DATA_WIDTH'] = axis_pcie_data_width
parameters['TLP_STRB_WIDTH'] = parameters['TLP_DATA_WIDTH'] // 32
parameters['TLP_HDR_WIDTH'] = 128
parameters['TLP_SEG_COUNT'] = 1
parameters['TX_SEQ_NUM_COUNT'] = 1 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 2
parameters['TX_SEQ_NUM_WIDTH'] = parameters['RQ_SEQ_NUM_WIDTH']-1
parameters['PF_COUNT'] = 1

2
fpga/lib/pcie/tox.ini
View File

@ -17,7 +17,7 @@ deps =
cocotb == 1.6.1
cocotb-test == 0.2.1
cocotbext-axi == 0.1.16
cocotbext-pcie == 0.2.0
cocotbext-pcie == 0.2.2
commands =
pytest -n auto {posargs}