diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga.sdc b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga.sdc
index 2099441fa..96fd3c457 100644
--- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga.sdc
+++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga.sdc
@@ -65,20 +65,3 @@ constrain_sync_reset_inst "ptp_rst_reset_sync_inst"
 
 # PCIe clock
 set_clock_groups -asynchronous -group [ get_clocks "pcie_hip_inst|intel_pcie_ptile_ast_0|inst|inst|maib_and_tile|xcvr_hip_native|rx_ch15" ]
-
-# E-Tile MACs
-proc constrain_etile_mac_dual { inst } {
-    puts "Inserting timing constraints for MAC dual $inst"
-
-    foreach mac {mac_02_inst mac_13_inst} {
-        set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|E100GX4_FEC_PTP_PR.nphy_ptp0|alt_ehipc3_fm_nphy_elane_ptp|tx_clkout|ch0" ]
-        set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|E100GX4_FEC_PTP_PR.nphy_ptp1|alt_ehipc3_fm_nphy_elane_ptp|tx_clkout|ch0" ]
-    }
-
-    for {set i 0} {$i < 2} {incr i} {
-        constrain_sync_reset_inst "$inst|mac_ch[$i].mac_reset_sync_inst"
-    }
-}
-
-constrain_etile_mac_dual "qsfpdd0_mac_inst"
-constrain_etile_mac_dual "qsfpdd1_mac_inst"
diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g/Makefile
index d0a9eba6e..54324b6c6 100644
--- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g/Makefile
+++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g/Makefile
@@ -126,7 +126,8 @@ IP_TCL_FILES += ip/mac_13.tcl
 QSF_FILES = fpga.qsf
 
 # SDC files
-SDC_FILES = fpga.sdc
+SDC_FILES += fpga.sdc
+SDC_FILES += mac_100g.sdc
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl
diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g_24AR0/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g_24AR0/Makefile
index c9d53b6d5..592f6a130 100644
--- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g_24AR0/Makefile
+++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g_24AR0/Makefile
@@ -126,7 +126,8 @@ IP_TCL_FILES += ip/mac_13.tcl
 QSF_FILES = fpga.qsf
 
 # SDC files
-SDC_FILES = fpga.sdc
+SDC_FILES += fpga.sdc
+SDC_FILES += mac_100g.sdc
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl
diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g_app_dma_bench/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g_app_dma_bench/Makefile
index e095779e0..b61a113ae 100644
--- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g_app_dma_bench/Makefile
+++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g_app_dma_bench/Makefile
@@ -128,7 +128,8 @@ IP_TCL_FILES += ip/mac_13.tcl
 QSF_FILES = fpga.qsf
 
 # SDC files
-SDC_FILES = fpga.sdc
+SDC_FILES += fpga.sdc
+SDC_FILES += mac_100g.sdc
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl
diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g_app_dma_bench_24AR0/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g_app_dma_bench_24AR0/Makefile
index ff92a0d2d..3557a60b2 100644
--- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g_app_dma_bench_24AR0/Makefile
+++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g_app_dma_bench_24AR0/Makefile
@@ -128,7 +128,8 @@ IP_TCL_FILES += ip/mac_13.tcl
 QSF_FILES = fpga.qsf
 
 # SDC files
-SDC_FILES = fpga.sdc
+SDC_FILES += fpga.sdc
+SDC_FILES += mac_100g.sdc
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl
diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_10g/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_10g/Makefile
index 3b3110145..85f017b92 100644
--- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_10g/Makefile
+++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_10g/Makefile
@@ -127,7 +127,8 @@ IP_TCL_FILES += ip/iopll_etile_ptp.tcl
 QSF_FILES = fpga.qsf
 
 # SDC files
-SDC_FILES = fpga.sdc
+SDC_FILES += fpga.sdc
+SDC_FILES += mac_25g.sdc
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl
diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_10g_24AR0/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_10g_24AR0/Makefile
index 17adc6057..1d2972807 100644
--- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_10g_24AR0/Makefile
+++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_10g_24AR0/Makefile
@@ -127,7 +127,8 @@ IP_TCL_FILES += ip/iopll_etile_ptp.tcl
 QSF_FILES = fpga.qsf
 
 # SDC files
-SDC_FILES = fpga.sdc
+SDC_FILES += fpga.sdc
+SDC_FILES += mac_25g.sdc
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl
diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g/Makefile
index d47ee38ab..6d27231b9 100644
--- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g/Makefile
+++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g/Makefile
@@ -127,7 +127,8 @@ IP_TCL_FILES += ip/iopll_etile_ptp.tcl
 QSF_FILES = fpga.qsf
 
 # SDC files
-SDC_FILES = fpga.sdc
+SDC_FILES += fpga.sdc
+SDC_FILES += mac_25g.sdc
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl
diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g_24AR0/Makefile b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g_24AR0/Makefile
index fd39a4824..e29413cf6 100644
--- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g_24AR0/Makefile
+++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g_24AR0/Makefile
@@ -127,7 +127,8 @@ IP_TCL_FILES += ip/iopll_etile_ptp.tcl
 QSF_FILES = fpga.qsf
 
 # SDC files
-SDC_FILES = fpga.sdc
+SDC_FILES += fpga.sdc
+SDC_FILES += mac_25g.sdc
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl
diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/mac_100g.sdc b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/mac_100g.sdc
new file mode 100644
index 000000000..1497ea1b8
--- /dev/null
+++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/mac_100g.sdc
@@ -0,0 +1,16 @@
+# E-Tile MACs
+proc constrain_etile_mac_dual { inst } {
+    puts "Inserting timing constraints for MAC dual $inst"
+
+    foreach mac {mac_02_inst mac_13_inst} {
+        set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|E100GX4_FEC_PTP_PR.nphy_ptp0|alt_ehipc3_fm_nphy_elane_ptp|tx_clkout|ch0" ]
+        set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|E100GX4_FEC_PTP_PR.nphy_ptp1|alt_ehipc3_fm_nphy_elane_ptp|tx_clkout|ch0" ]
+    }
+
+    for {set i 0} {$i < 2} {incr i} {
+        constrain_sync_reset_inst "$inst|mac_ch[$i].mac_reset_sync_inst"
+    }
+}
+
+constrain_etile_mac_dual "qsfpdd0_mac_inst"
+constrain_etile_mac_dual "qsfpdd1_mac_inst"
diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/mac_25g.sdc b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/mac_25g.sdc
new file mode 100644
index 000000000..013d8682a
--- /dev/null
+++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/mac_25g.sdc
@@ -0,0 +1,33 @@
+# E-Tile MACs
+set_clock_groups -asynchronous -group [ get_clocks "iopll_etile_ptp_inst|iopll_0_refclk" ]
+set_clock_groups -asynchronous -group [ get_clocks "iopll_etile_ptp_inst|iopll_0_outclk0" ]
+
+proc constrain_etile_mac_dual_quad { inst } {
+    puts "Inserting timing constraints for MAC quad $inst"
+
+    foreach mac {mac_02_inst mac_13_inst} {
+        for {set i 0} {$i < 4} {incr i} {
+            set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|rx_clkout2|ch${i}" ]
+            set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|rx_clkout|ch${i}" ]
+            set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|tx_clkout2|ch${i}" ]
+            set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|tx_clkout|ch${i}" ]
+            set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY_RSFEC.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|rx_clkout2|ch${i}" ]
+            set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY_RSFEC.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|rx_clkout|ch${i}" ]
+            set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY_RSFEC.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|tx_clkout2|ch${i}" ]
+            set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY_RSFEC.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|tx_clkout|ch${i}" ]
+        }
+
+        set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_PTP_NPHY_CHPLL.nphy_ptp0|alt_ehipc3_fm_nphy_elane_ptp|tx_clkout|ch0" ]
+        set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_PTP_NPHY_CHPLL.nphy_ptp1|alt_ehipc3_fm_nphy_elane_ptp|tx_clkout|ch0" ]
+        set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_PTP_NPHY_CHPLL.nphy_ptp1|alt_ehipc3_fm_nphy_elane_ptp_plloff|tx_transfer_clk|ch0" ]
+    }
+
+    for {set i 0} {$i < 8} {incr i} {
+        constrain_sync_reset_inst "$inst|mac_ch[$i].mac_tx_reset_sync_inst"
+        constrain_sync_reset_inst "$inst|mac_ch[$i].mac_tx_ptp_reset_sync_inst"
+        constrain_sync_reset_inst "$inst|mac_ch[$i].mac_rx_ptp_reset_sync_inst"
+    }
+}
+
+constrain_etile_mac_dual_quad "qsfpdd0_mac_inst"
+constrain_etile_mac_dual_quad "qsfpdd1_mac_inst"