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fpga/mqnic/DK_DEV_AGF014EA: Fix MAC timing constraints for DK-DEV-AGF014EA

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-11-14 18:13:25 -08:00
parent 184b7242e9
commit 55c5ea335f
11 changed files with 65 additions and 25 deletions
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17
fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga.sdc
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@ -65,20 +65,3 @@ constrain_sync_reset_inst "ptp_rst_reset_sync_inst"
# PCIe clock # PCIe clock
set_clock_groups -asynchronous -group [ get_clocks "pcie_hip_inst|intel_pcie_ptile_ast_0|inst|inst|maib_and_tile|xcvr_hip_native|rx_ch15" ] set_clock_groups -asynchronous -group [ get_clocks "pcie_hip_inst|intel_pcie_ptile_ast_0|inst|inst|maib_and_tile|xcvr_hip_native|rx_ch15" ]
# E-Tile MACs
proc constrain_etile_mac_dual { inst } {
puts "Inserting timing constraints for MAC dual $inst"
foreach mac {mac_02_inst mac_13_inst} {
set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|E100GX4_FEC_PTP_PR.nphy_ptp0|alt_ehipc3_fm_nphy_elane_ptp|tx_clkout|ch0" ]
set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|E100GX4_FEC_PTP_PR.nphy_ptp1|alt_ehipc3_fm_nphy_elane_ptp|tx_clkout|ch0" ]
}
for {set i 0} {$i < 2} {incr i} {
constrain_sync_reset_inst "$inst|mac_ch[$i].mac_reset_sync_inst"
}
}
constrain_etile_mac_dual "qsfpdd0_mac_inst"
constrain_etile_mac_dual "qsfpdd1_mac_inst"

3
fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g/Makefile
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@ -126,7 +126,8 @@ IP_TCL_FILES += ip/mac_13.tcl
QSF_FILES = fpga.qsf QSF_FILES = fpga.qsf
# SDC files # SDC files
SDC_FILES = fpga.sdc SDC_FILES += fpga.sdc
SDC_FILES += mac_100g.sdc
# Configuration # Configuration
CONFIG_TCL_FILES = ./config.tcl CONFIG_TCL_FILES = ./config.tcl

3
fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g_24AR0/Makefile
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@ -126,7 +126,8 @@ IP_TCL_FILES += ip/mac_13.tcl
QSF_FILES = fpga.qsf QSF_FILES = fpga.qsf
# SDC files # SDC files
SDC_FILES = fpga.sdc SDC_FILES += fpga.sdc
SDC_FILES += mac_100g.sdc
# Configuration # Configuration
CONFIG_TCL_FILES = ./config.tcl CONFIG_TCL_FILES = ./config.tcl

3
fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g_app_dma_bench/Makefile
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@ -128,7 +128,8 @@ IP_TCL_FILES += ip/mac_13.tcl
QSF_FILES = fpga.qsf QSF_FILES = fpga.qsf
# SDC files # SDC files
SDC_FILES = fpga.sdc SDC_FILES += fpga.sdc
SDC_FILES += mac_100g.sdc
# Configuration # Configuration
CONFIG_TCL_FILES = ./config.tcl CONFIG_TCL_FILES = ./config.tcl

3
fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_100g_app_dma_bench_24AR0/Makefile
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@ -128,7 +128,8 @@ IP_TCL_FILES += ip/mac_13.tcl
QSF_FILES = fpga.qsf QSF_FILES = fpga.qsf
# SDC files # SDC files
SDC_FILES = fpga.sdc SDC_FILES += fpga.sdc
SDC_FILES += mac_100g.sdc
# Configuration # Configuration
CONFIG_TCL_FILES = ./config.tcl CONFIG_TCL_FILES = ./config.tcl

3
fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_10g/Makefile
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@ -127,7 +127,8 @@ IP_TCL_FILES += ip/iopll_etile_ptp.tcl
QSF_FILES = fpga.qsf QSF_FILES = fpga.qsf
# SDC files # SDC files
SDC_FILES = fpga.sdc SDC_FILES += fpga.sdc
SDC_FILES += mac_25g.sdc
# Configuration # Configuration
CONFIG_TCL_FILES = ./config.tcl CONFIG_TCL_FILES = ./config.tcl

3
fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_10g_24AR0/Makefile
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@ -127,7 +127,8 @@ IP_TCL_FILES += ip/iopll_etile_ptp.tcl
QSF_FILES = fpga.qsf QSF_FILES = fpga.qsf
# SDC files # SDC files
SDC_FILES = fpga.sdc SDC_FILES += fpga.sdc
SDC_FILES += mac_25g.sdc
# Configuration # Configuration
CONFIG_TCL_FILES = ./config.tcl CONFIG_TCL_FILES = ./config.tcl

3
fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g/Makefile
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@ -127,7 +127,8 @@ IP_TCL_FILES += ip/iopll_etile_ptp.tcl
QSF_FILES = fpga.qsf QSF_FILES = fpga.qsf
# SDC files # SDC files
SDC_FILES = fpga.sdc SDC_FILES += fpga.sdc
SDC_FILES += mac_25g.sdc
# Configuration # Configuration
CONFIG_TCL_FILES = ./config.tcl CONFIG_TCL_FILES = ./config.tcl

3
fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g_24AR0/Makefile
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@ -127,7 +127,8 @@ IP_TCL_FILES += ip/iopll_etile_ptp.tcl
QSF_FILES = fpga.qsf QSF_FILES = fpga.qsf
# SDC files # SDC files
SDC_FILES = fpga.sdc SDC_FILES += fpga.sdc
SDC_FILES += mac_25g.sdc
# Configuration # Configuration
CONFIG_TCL_FILES = ./config.tcl CONFIG_TCL_FILES = ./config.tcl

16
fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/mac_100g.sdc Normal file
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@ -0,0 +1,16 @@
# E-Tile MACs
proc constrain_etile_mac_dual { inst } {
puts "Inserting timing constraints for MAC dual $inst"
foreach mac {mac_02_inst mac_13_inst} {
set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|E100GX4_FEC_PTP_PR.nphy_ptp0|alt_ehipc3_fm_nphy_elane_ptp|tx_clkout|ch0" ]
set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|E100GX4_FEC_PTP_PR.nphy_ptp1|alt_ehipc3_fm_nphy_elane_ptp|tx_clkout|ch0" ]
}
for {set i 0} {$i < 2} {incr i} {
constrain_sync_reset_inst "$inst|mac_ch[$i].mac_reset_sync_inst"
}
}
constrain_etile_mac_dual "qsfpdd0_mac_inst"
constrain_etile_mac_dual "qsfpdd1_mac_inst"

33
fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/mac_25g.sdc Normal file
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@ -0,0 +1,33 @@
# E-Tile MACs
set_clock_groups -asynchronous -group [ get_clocks "iopll_etile_ptp_inst|iopll_0_refclk" ]
set_clock_groups -asynchronous -group [ get_clocks "iopll_etile_ptp_inst|iopll_0_outclk0" ]
proc constrain_etile_mac_dual_quad { inst } {
puts "Inserting timing constraints for MAC quad $inst"
foreach mac {mac_02_inst mac_13_inst} {
for {set i 0} {$i < 4} {incr i} {
set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|rx_clkout2|ch${i}" ]
set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|rx_clkout|ch${i}" ]
set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|tx_clkout2|ch${i}" ]
set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|tx_clkout|ch${i}" ]
set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY_RSFEC.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|rx_clkout2|ch${i}" ]
set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY_RSFEC.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|rx_clkout|ch${i}" ]
set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY_RSFEC.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|tx_clkout2|ch${i}" ]
set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_NPHY_RSFEC.altera_xcvr_native_inst|alt_ehipc3_fm_nphy_elane|tx_clkout|ch${i}" ]
}
set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_PTP_NPHY_CHPLL.nphy_ptp0|alt_ehipc3_fm_nphy_elane_ptp|tx_clkout|ch0" ]
set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_PTP_NPHY_CHPLL.nphy_ptp1|alt_ehipc3_fm_nphy_elane_ptp|tx_clkout|ch0" ]
set_clock_groups -asynchronous -group [ get_clocks "$inst|$mac|alt_ehipc3_fm_0|alt_ehipc3_fm_hard_inst|SL_PTP_NPHY_CHPLL.nphy_ptp1|alt_ehipc3_fm_nphy_elane_ptp_plloff|tx_transfer_clk|ch0" ]
}
for {set i 0} {$i < 8} {incr i} {
constrain_sync_reset_inst "$inst|mac_ch[$i].mac_tx_reset_sync_inst"
constrain_sync_reset_inst "$inst|mac_ch[$i].mac_tx_ptp_reset_sync_inst"
constrain_sync_reset_inst "$inst|mac_ch[$i].mac_rx_ptp_reset_sync_inst"
}
}
constrain_etile_mac_dual_quad "qsfpdd0_mac_inst"
constrain_etile_mac_dual_quad "qsfpdd1_mac_inst"