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synced 2025-01-30 08:32:52 +08:00
Pass EQ ring instead of index
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0418fe33a6
commit
56706beefc
@ -232,6 +232,7 @@ struct mqnic_cq_ring {
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struct mqnic_priv *priv;
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struct napi_struct napi;
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int index;
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struct mqnic_eq_ring *eq_ring;
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int eq_index;
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int active;
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@ -405,7 +406,7 @@ int mqnic_create_cq_ring(struct mqnic_priv *priv, struct mqnic_cq_ring **ring_pt
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void mqnic_destroy_cq_ring(struct mqnic_cq_ring **ring_ptr);
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int mqnic_alloc_cq_ring(struct mqnic_cq_ring *ring, int size, int stride);
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void mqnic_free_cq_ring(struct mqnic_cq_ring *ring);
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int mqnic_activate_cq_ring(struct mqnic_cq_ring *ring, int eq_index);
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int mqnic_activate_cq_ring(struct mqnic_cq_ring *ring, struct mqnic_eq_ring *eq_ring);
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void mqnic_deactivate_cq_ring(struct mqnic_cq_ring *ring);
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bool mqnic_is_cq_ring_empty(const struct mqnic_cq_ring *ring);
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bool mqnic_is_cq_ring_full(const struct mqnic_cq_ring *ring);
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@ -118,14 +118,15 @@ void mqnic_free_cq_ring(struct mqnic_cq_ring *ring)
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ring->buf_dma_addr = 0;
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}
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int mqnic_activate_cq_ring(struct mqnic_cq_ring *ring, int eq_index)
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int mqnic_activate_cq_ring(struct mqnic_cq_ring *ring, struct mqnic_eq_ring *eq_ring)
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{
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mqnic_deactivate_cq_ring(ring);
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if (!ring->buf)
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if (!ring->buf || !eq_ring)
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return -EINVAL;
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ring->eq_index = eq_index;
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ring->eq_ring = eq_ring;
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ring->eq_index = eq_ring->index;
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// deactivate queue
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iowrite32(0, ring->hw_addr + MQNIC_CPL_QUEUE_ACTIVE_LOG_SIZE_REG);
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@ -133,7 +134,7 @@ int mqnic_activate_cq_ring(struct mqnic_cq_ring *ring, int eq_index)
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iowrite32(ring->buf_dma_addr, ring->hw_addr + MQNIC_CPL_QUEUE_BASE_ADDR_REG + 0);
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iowrite32(ring->buf_dma_addr >> 32, ring->hw_addr + MQNIC_CPL_QUEUE_BASE_ADDR_REG + 4);
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// set interrupt index
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iowrite32(eq_index, ring->hw_addr + MQNIC_CPL_QUEUE_INTERRUPT_INDEX_REG);
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iowrite32(ring->eq_index, ring->hw_addr + MQNIC_CPL_QUEUE_INTERRUPT_INDEX_REG);
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// set pointers
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iowrite32(ring->head_ptr & ring->hw_ptr_mask, ring->hw_addr + MQNIC_CPL_QUEUE_HEAD_PTR_REG);
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iowrite32(ring->tail_ptr & ring->hw_ptr_mask, ring->hw_addr + MQNIC_CPL_QUEUE_TAIL_PTR_REG);
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@ -153,6 +154,8 @@ void mqnic_deactivate_cq_ring(struct mqnic_cq_ring *ring)
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// disarm queue
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iowrite32(ring->eq_index, ring->hw_addr + MQNIC_CPL_QUEUE_INTERRUPT_INDEX_REG);
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ring->eq_ring = NULL;
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ring->active = 0;
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}
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@ -178,6 +181,9 @@ void mqnic_cq_write_tail_ptr(struct mqnic_cq_ring *ring)
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void mqnic_arm_cq(struct mqnic_cq_ring *ring)
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{
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if (!ring->active)
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return;
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iowrite32(ring->eq_index | MQNIC_CPL_QUEUE_ARM_MASK,
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ring->hw_addr + MQNIC_CPL_QUEUE_INTERRUPT_INDEX_REG);
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}
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@ -52,7 +52,7 @@ static int mqnic_start_port(struct net_device *ndev)
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// set up RX completion queues
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for (k = 0; k < priv->rx_cpl_queue_count; k++) {
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mqnic_activate_cq_ring(priv->rx_cpl_ring[k],
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priv->event_ring[k % priv->event_queue_count]->index);
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priv->event_ring[k % priv->event_queue_count]);
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priv->rx_cpl_ring[k]->handler = mqnic_rx_irq;
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netif_napi_add(ndev, &priv->rx_cpl_ring[k]->napi,
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@ -76,7 +76,7 @@ static int mqnic_start_port(struct net_device *ndev)
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// set up TX completion queues
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for (k = 0; k < priv->tx_cpl_queue_count; k++) {
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mqnic_activate_cq_ring(priv->tx_cpl_ring[k],
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priv->event_ring[k % priv->event_queue_count]->index);
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priv->event_ring[k % priv->event_queue_count]);
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priv->tx_cpl_ring[k]->handler = mqnic_tx_irq;
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netif_tx_napi_add(ndev, &priv->tx_cpl_ring[k]->napi,
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