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lib/mqnic: Add more JTAG IDs for Xilinx devices
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
parent
3c33590ca7
commit
56df4cb677
@ -134,6 +134,7 @@ const struct fpga_id fpga_id_list[] =
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{FPGA_ID_XCVU47P, FPGA_ID_MASK_NOVER, "XCVU47P"},
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{FPGA_ID_XCVU57P, FPGA_ID_MASK_NOVER, "XCVU57P"},
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// Zynq UltraScale+
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{FPGA_ID_XCZU1, FPGA_ID_MASK_NOVER, "XCZU1"},
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{FPGA_ID_XCZU2, FPGA_ID_MASK_NOVER, "XCZU2"},
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{FPGA_ID_XCZU3, FPGA_ID_MASK_NOVER, "XCZU3"},
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{FPGA_ID_XCZU4, FPGA_ID_MASK_NOVER, "XCZU4"},
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@ -156,11 +157,53 @@ const struct fpga_id fpga_id_list[] =
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{FPGA_ID_XCZU47, FPGA_ID_MASK_NOVER, "XCZU47"},
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{FPGA_ID_XCZU48, FPGA_ID_MASK_NOVER, "XCZU48"},
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{FPGA_ID_XCZU49, FPGA_ID_MASK_NOVER, "XCZU49"},
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// Alveo
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{FPGA_ID_XCZU65, FPGA_ID_MASK_NOVER, "XCZU65"},
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{FPGA_ID_XCZU67, FPGA_ID_MASK_NOVER, "XCZU67"},
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// Kria SoM (Zynq UltraScale+)
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{FPGA_ID_XCK26, FPGA_ID_MASK_NOVER, "XCK26"},
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// Alveo (Virtex UltraScale+)
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{FPGA_ID_XCU50, FPGA_ID_MASK_NOVER, "XCU50"},
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{FPGA_ID_XCU200, FPGA_ID_MASK_NOVER, "XCU200"},
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{FPGA_ID_XCU250, FPGA_ID_MASK_NOVER, "XCU250"},
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{FPGA_ID_XCU280, FPGA_ID_MASK_NOVER, "XCU280"},
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// Versal AI Edge
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{FPGA_ID_XCVE1752, FPGA_ID_MASK_NOVER, "XCVE1752"},
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{FPGA_ID_XCVE2002, FPGA_ID_MASK_NOVER, "XCVE2002"},
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{FPGA_ID_XCVE2102, FPGA_ID_MASK_NOVER, "XCVE2102"},
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{FPGA_ID_XCVE2202, FPGA_ID_MASK_NOVER, "XCVE2202"},
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{FPGA_ID_XCVE2302, FPGA_ID_MASK_NOVER, "XCVE2302"},
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{FPGA_ID_XCVE2602, FPGA_ID_MASK_NOVER, "XCVE2602"},
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{FPGA_ID_XCVE2802, FPGA_ID_MASK_NOVER, "XCVE2802"},
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// Versal AI Core
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{FPGA_ID_XCVC1352, FPGA_ID_MASK_NOVER, "XCVC1352"},
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{FPGA_ID_XCVC1502, FPGA_ID_MASK_NOVER, "XCVC1502"},
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{FPGA_ID_XCVC1702, FPGA_ID_MASK_NOVER, "XCVC1702"},
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{FPGA_ID_XCVC1802, FPGA_ID_MASK_NOVER, "XCVC1802"},
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{FPGA_ID_XCVC1902, FPGA_ID_MASK_NOVER, "XCVC1902"},
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{FPGA_ID_XCVC2602, FPGA_ID_MASK_NOVER, "XCVC2602"},
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{FPGA_ID_XCVC2802, FPGA_ID_MASK_NOVER, "XCVC2802"},
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// Versal Prime
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{FPGA_ID_XCVM1102, FPGA_ID_MASK_NOVER, "XCVM1102"},
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{FPGA_ID_XCVM1302, FPGA_ID_MASK_NOVER, "XCVM1302"},
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{FPGA_ID_XCVM1402, FPGA_ID_MASK_NOVER, "XCVM1402"},
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{FPGA_ID_XCVM1502, FPGA_ID_MASK_NOVER, "XCVM1502"},
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{FPGA_ID_XCVM1802, FPGA_ID_MASK_NOVER, "XCVM1802"},
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{FPGA_ID_XCVM2202, FPGA_ID_MASK_NOVER, "XCVM2202"},
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{FPGA_ID_XCVM2302, FPGA_ID_MASK_NOVER, "XCVM2302"},
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{FPGA_ID_XCVM2502, FPGA_ID_MASK_NOVER, "XCVM2502"},
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{FPGA_ID_XCVM2902, FPGA_ID_MASK_NOVER, "XCVM2902"},
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// Versal Premium
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{FPGA_ID_XCVP1002, FPGA_ID_MASK_NOVER, "XCVP1002"},
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{FPGA_ID_XCVP1052, FPGA_ID_MASK_NOVER, "XCVP1052"},
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{FPGA_ID_XCVP1102, FPGA_ID_MASK_NOVER, "XCVP1102"},
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{FPGA_ID_XCVP1202, FPGA_ID_MASK_NOVER, "XCVP1202"},
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{FPGA_ID_XCVP1402, FPGA_ID_MASK_NOVER, "XCVP1402"},
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{FPGA_ID_XCVP1502, FPGA_ID_MASK_NOVER, "XCVP1502"},
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{FPGA_ID_XCVP1552, FPGA_ID_MASK_NOVER, "XCVP1552"},
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{FPGA_ID_XCVP1702, FPGA_ID_MASK_NOVER, "XCVP1702"},
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{FPGA_ID_XCVP1802, FPGA_ID_MASK_NOVER, "XCVP1802"},
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{FPGA_ID_XCVP2502, FPGA_ID_MASK_NOVER, "XCVP2502"},
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{FPGA_ID_XCVP2802, FPGA_ID_MASK_NOVER, "XCVP2802"},
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// Intel
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// Stratix 10
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@ -134,6 +134,7 @@ either expressed or implied, of The Regents of the University of California.
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#define FPGA_ID_XCVU47P 0x4B7B093
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#define FPGA_ID_XCVU57P 0x4B61093
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// Zynq UltraScale+
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#define FPGA_ID_XCZU1 0x4688093
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#define FPGA_ID_XCZU2 0x4711093
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#define FPGA_ID_XCZU3 0x4710093
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#define FPGA_ID_XCZU4 0x4721093
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@ -156,11 +157,53 @@ either expressed or implied, of The Regents of the University of California.
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#define FPGA_ID_XCZU47 0x47FF093
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#define FPGA_ID_XCZU48 0x47FB093
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#define FPGA_ID_XCZU49 0x47FE093
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// Alveo
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#define FPGA_ID_XCZU65 0x46D1093
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#define FPGA_ID_XCZU67 0x46D0093
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// Kria SoM (Zynq UltraScale+)
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#define FPGA_ID_XCK26 0x4A49093
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// Alveo (Virtex UltraScale+)
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#define FPGA_ID_XCU50 0x4B77093
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#define FPGA_ID_XCU200 0x4B37093
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#define FPGA_ID_XCU250 0x4B57093
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#define FPGA_ID_XCU280 0x4B7D093
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// Versal AI Edge
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#define FPGA_ID_XCVE1752 0x4C9A093
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#define FPGA_ID_XCVE2002 0x4CC1093
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#define FPGA_ID_XCVE2102 0x4CC0093
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#define FPGA_ID_XCVE2202 0x4CC9093
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#define FPGA_ID_XCVE2302 0x4CC8093
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#define FPGA_ID_XCVE2602 0x4CD3093
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#define FPGA_ID_XCVE2802 0x4CD1093
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// Versal AI Core
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#define FPGA_ID_XCVC1352 0x4C93093
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#define FPGA_ID_XCVC1502 0x4C9B093
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#define FPGA_ID_XCVC1702 0x4C98093
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#define FPGA_ID_XCVC1802 0x4CA9093
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#define FPGA_ID_XCVC1902 0x4CA8093
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#define FPGA_ID_XCVC2602 0x4CD2093
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#define FPGA_ID_XCVC2802 0x4CD0093
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// Versal Prime
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#define FPGA_ID_XCVM1102 0x4CCA093
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#define FPGA_ID_XCVM1302 0x4C09093
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#define FPGA_ID_XCVM1402 0x4C08093
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#define FPGA_ID_XCVM1502 0x4C99093
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#define FPGA_ID_XCVM1802 0x4CAA093
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#define FPGA_ID_XCVM2202 0x4CD4093
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#define FPGA_ID_XCVM2302 0x4C24093
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#define FPGA_ID_XCVM2502 0x4D01093
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#define FPGA_ID_XCVM2902 0x4C23093
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// Versal Premium
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#define FPGA_ID_XCVP1002 0x4C1B093
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#define FPGA_ID_XCVP1052 0x4C18093
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#define FPGA_ID_XCVP1102 0x4C22093
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#define FPGA_ID_XCVP1202 0x4D00093
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#define FPGA_ID_XCVP1402 0x4C20093
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#define FPGA_ID_XCVP1502 0x4D08093
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#define FPGA_ID_XCVP1552 0x4D34093
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#define FPGA_ID_XCVP1702 0x4D10093
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#define FPGA_ID_XCVP1802 0x4D14093
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#define FPGA_ID_XCVP2502 0x4D1C093
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#define FPGA_ID_XCVP2802 0x4D20093
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// Intel
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// Stratix 10
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