diff --git a/example/520N_MX/fpga_10g/tb/fpga_core/test_fpga_core.py b/example/520N_MX/fpga_10g/tb/fpga_core/test_fpga_core.py
index 8c0e0c856..ef7224c09 100644
--- a/example/520N_MX/fpga_10g/tb/fpga_core/test_fpga_core.py
+++ b/example/520N_MX/fpga_10g/tb/fpga_core/test_fpga_core.py
@@ -167,76 +167,76 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 1
-        self.dut.qsfp0_rx_rst_1 <= 1
-        self.dut.qsfp0_tx_rst_1 <= 1
-        self.dut.qsfp0_rx_rst_2 <= 1
-        self.dut.qsfp0_tx_rst_2 <= 1
-        self.dut.qsfp0_rx_rst_3 <= 1
-        self.dut.qsfp0_tx_rst_3 <= 1
-        self.dut.qsfp0_rx_rst_4 <= 1
-        self.dut.qsfp0_tx_rst_4 <= 1
-        self.dut.qsfp1_rx_rst_1 <= 1
-        self.dut.qsfp1_tx_rst_1 <= 1
-        self.dut.qsfp1_rx_rst_2 <= 1
-        self.dut.qsfp1_tx_rst_2 <= 1
-        self.dut.qsfp1_rx_rst_3 <= 1
-        self.dut.qsfp1_tx_rst_3 <= 1
-        self.dut.qsfp1_rx_rst_4 <= 1
-        self.dut.qsfp1_tx_rst_4 <= 1
-        self.dut.qsfp2_rx_rst_1 <= 1
-        self.dut.qsfp2_tx_rst_1 <= 1
-        self.dut.qsfp2_rx_rst_2 <= 1
-        self.dut.qsfp2_tx_rst_2 <= 1
-        self.dut.qsfp2_rx_rst_3 <= 1
-        self.dut.qsfp2_tx_rst_3 <= 1
-        self.dut.qsfp2_rx_rst_4 <= 1
-        self.dut.qsfp2_tx_rst_4 <= 1
-        self.dut.qsfp3_rx_rst_1 <= 1
-        self.dut.qsfp3_tx_rst_1 <= 1
-        self.dut.qsfp3_rx_rst_2 <= 1
-        self.dut.qsfp3_tx_rst_2 <= 1
-        self.dut.qsfp3_rx_rst_3 <= 1
-        self.dut.qsfp3_tx_rst_3 <= 1
-        self.dut.qsfp3_rx_rst_4 <= 1
-        self.dut.qsfp3_tx_rst_4 <= 1
+        self.dut.rst.value = 1
+        self.dut.qsfp0_rx_rst_1.value = 1
+        self.dut.qsfp0_tx_rst_1.value = 1
+        self.dut.qsfp0_rx_rst_2.value = 1
+        self.dut.qsfp0_tx_rst_2.value = 1
+        self.dut.qsfp0_rx_rst_3.value = 1
+        self.dut.qsfp0_tx_rst_3.value = 1
+        self.dut.qsfp0_rx_rst_4.value = 1
+        self.dut.qsfp0_tx_rst_4.value = 1
+        self.dut.qsfp1_rx_rst_1.value = 1
+        self.dut.qsfp1_tx_rst_1.value = 1
+        self.dut.qsfp1_rx_rst_2.value = 1
+        self.dut.qsfp1_tx_rst_2.value = 1
+        self.dut.qsfp1_rx_rst_3.value = 1
+        self.dut.qsfp1_tx_rst_3.value = 1
+        self.dut.qsfp1_rx_rst_4.value = 1
+        self.dut.qsfp1_tx_rst_4.value = 1
+        self.dut.qsfp2_rx_rst_1.value = 1
+        self.dut.qsfp2_tx_rst_1.value = 1
+        self.dut.qsfp2_rx_rst_2.value = 1
+        self.dut.qsfp2_tx_rst_2.value = 1
+        self.dut.qsfp2_rx_rst_3.value = 1
+        self.dut.qsfp2_tx_rst_3.value = 1
+        self.dut.qsfp2_rx_rst_4.value = 1
+        self.dut.qsfp2_tx_rst_4.value = 1
+        self.dut.qsfp3_rx_rst_1.value = 1
+        self.dut.qsfp3_tx_rst_1.value = 1
+        self.dut.qsfp3_rx_rst_2.value = 1
+        self.dut.qsfp3_tx_rst_2.value = 1
+        self.dut.qsfp3_rx_rst_3.value = 1
+        self.dut.qsfp3_tx_rst_3.value = 1
+        self.dut.qsfp3_rx_rst_4.value = 1
+        self.dut.qsfp3_tx_rst_4.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
-        self.dut.qsfp0_rx_rst_1 <= 0
-        self.dut.qsfp0_tx_rst_1 <= 0
-        self.dut.qsfp0_rx_rst_2 <= 0
-        self.dut.qsfp0_tx_rst_2 <= 0
-        self.dut.qsfp0_rx_rst_3 <= 0
-        self.dut.qsfp0_tx_rst_3 <= 0
-        self.dut.qsfp0_rx_rst_4 <= 0
-        self.dut.qsfp0_tx_rst_4 <= 0
-        self.dut.qsfp1_rx_rst_1 <= 0
-        self.dut.qsfp1_tx_rst_1 <= 0
-        self.dut.qsfp1_rx_rst_2 <= 0
-        self.dut.qsfp1_tx_rst_2 <= 0
-        self.dut.qsfp1_rx_rst_3 <= 0
-        self.dut.qsfp1_tx_rst_3 <= 0
-        self.dut.qsfp1_rx_rst_4 <= 0
-        self.dut.qsfp1_tx_rst_4 <= 0
-        self.dut.qsfp2_rx_rst_1 <= 0
-        self.dut.qsfp2_tx_rst_1 <= 0
-        self.dut.qsfp2_rx_rst_2 <= 0
-        self.dut.qsfp2_tx_rst_2 <= 0
-        self.dut.qsfp2_rx_rst_3 <= 0
-        self.dut.qsfp2_tx_rst_3 <= 0
-        self.dut.qsfp2_rx_rst_4 <= 0
-        self.dut.qsfp2_tx_rst_4 <= 0
-        self.dut.qsfp3_rx_rst_1 <= 0
-        self.dut.qsfp3_tx_rst_1 <= 0
-        self.dut.qsfp3_rx_rst_2 <= 0
-        self.dut.qsfp3_tx_rst_2 <= 0
-        self.dut.qsfp3_rx_rst_3 <= 0
-        self.dut.qsfp3_tx_rst_3 <= 0
-        self.dut.qsfp3_rx_rst_4 <= 0
-        self.dut.qsfp3_tx_rst_4 <= 0
+        self.dut.rst.value = 0
+        self.dut.qsfp0_rx_rst_1.value = 0
+        self.dut.qsfp0_tx_rst_1.value = 0
+        self.dut.qsfp0_rx_rst_2.value = 0
+        self.dut.qsfp0_tx_rst_2.value = 0
+        self.dut.qsfp0_rx_rst_3.value = 0
+        self.dut.qsfp0_tx_rst_3.value = 0
+        self.dut.qsfp0_rx_rst_4.value = 0
+        self.dut.qsfp0_tx_rst_4.value = 0
+        self.dut.qsfp1_rx_rst_1.value = 0
+        self.dut.qsfp1_tx_rst_1.value = 0
+        self.dut.qsfp1_rx_rst_2.value = 0
+        self.dut.qsfp1_tx_rst_2.value = 0
+        self.dut.qsfp1_rx_rst_3.value = 0
+        self.dut.qsfp1_tx_rst_3.value = 0
+        self.dut.qsfp1_rx_rst_4.value = 0
+        self.dut.qsfp1_tx_rst_4.value = 0
+        self.dut.qsfp2_rx_rst_1.value = 0
+        self.dut.qsfp2_tx_rst_1.value = 0
+        self.dut.qsfp2_rx_rst_2.value = 0
+        self.dut.qsfp2_tx_rst_2.value = 0
+        self.dut.qsfp2_rx_rst_3.value = 0
+        self.dut.qsfp2_tx_rst_3.value = 0
+        self.dut.qsfp2_rx_rst_4.value = 0
+        self.dut.qsfp2_tx_rst_4.value = 0
+        self.dut.qsfp3_rx_rst_1.value = 0
+        self.dut.qsfp3_tx_rst_1.value = 0
+        self.dut.qsfp3_rx_rst_2.value = 0
+        self.dut.qsfp3_tx_rst_2.value = 0
+        self.dut.qsfp3_rx_rst_3.value = 0
+        self.dut.qsfp3_tx_rst_3.value = 0
+        self.dut.qsfp3_rx_rst_4.value = 0
+        self.dut.qsfp3_tx_rst_4.value = 0
 
 
 @cocotb.test()
diff --git a/example/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/test_fpga_core.py b/example/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/test_fpga_core.py
index d65d197cf..6d907a8c7 100644
--- a/example/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/test_fpga_core.py
+++ b/example/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/test_fpga_core.py
@@ -113,44 +113,44 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 1
-        self.dut.qsfp_0_rx_rst_0 <= 1
-        self.dut.qsfp_0_tx_rst_0 <= 1
-        self.dut.qsfp_0_rx_rst_1 <= 1
-        self.dut.qsfp_0_tx_rst_1 <= 1
-        self.dut.qsfp_0_rx_rst_2 <= 1
-        self.dut.qsfp_0_tx_rst_2 <= 1
-        self.dut.qsfp_0_rx_rst_3 <= 1
-        self.dut.qsfp_0_tx_rst_3 <= 1
-        self.dut.qsfp_1_rx_rst_0 <= 1
-        self.dut.qsfp_1_tx_rst_0 <= 1
-        self.dut.qsfp_1_rx_rst_1 <= 1
-        self.dut.qsfp_1_tx_rst_1 <= 1
-        self.dut.qsfp_1_rx_rst_2 <= 1
-        self.dut.qsfp_1_tx_rst_2 <= 1
-        self.dut.qsfp_1_rx_rst_3 <= 1
-        self.dut.qsfp_1_tx_rst_3 <= 1
+        self.dut.rst.value = 1
+        self.dut.qsfp_0_rx_rst_0.value = 1
+        self.dut.qsfp_0_tx_rst_0.value = 1
+        self.dut.qsfp_0_rx_rst_1.value = 1
+        self.dut.qsfp_0_tx_rst_1.value = 1
+        self.dut.qsfp_0_rx_rst_2.value = 1
+        self.dut.qsfp_0_tx_rst_2.value = 1
+        self.dut.qsfp_0_rx_rst_3.value = 1
+        self.dut.qsfp_0_tx_rst_3.value = 1
+        self.dut.qsfp_1_rx_rst_0.value = 1
+        self.dut.qsfp_1_tx_rst_0.value = 1
+        self.dut.qsfp_1_rx_rst_1.value = 1
+        self.dut.qsfp_1_tx_rst_1.value = 1
+        self.dut.qsfp_1_rx_rst_2.value = 1
+        self.dut.qsfp_1_tx_rst_2.value = 1
+        self.dut.qsfp_1_rx_rst_3.value = 1
+        self.dut.qsfp_1_tx_rst_3.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
-        self.dut.qsfp_0_rx_rst_0 <= 0
-        self.dut.qsfp_0_tx_rst_0 <= 0
-        self.dut.qsfp_0_rx_rst_1 <= 0
-        self.dut.qsfp_0_tx_rst_1 <= 0
-        self.dut.qsfp_0_rx_rst_2 <= 0
-        self.dut.qsfp_0_tx_rst_2 <= 0
-        self.dut.qsfp_0_rx_rst_3 <= 0
-        self.dut.qsfp_0_tx_rst_3 <= 0
-        self.dut.qsfp_1_rx_rst_0 <= 0
-        self.dut.qsfp_1_tx_rst_0 <= 0
-        self.dut.qsfp_1_rx_rst_1 <= 0
-        self.dut.qsfp_1_tx_rst_1 <= 0
-        self.dut.qsfp_1_rx_rst_2 <= 0
-        self.dut.qsfp_1_tx_rst_2 <= 0
-        self.dut.qsfp_1_rx_rst_3 <= 0
-        self.dut.qsfp_1_tx_rst_3 <= 0
+        self.dut.rst.value = 0
+        self.dut.qsfp_0_rx_rst_0.value = 0
+        self.dut.qsfp_0_tx_rst_0.value = 0
+        self.dut.qsfp_0_rx_rst_1.value = 0
+        self.dut.qsfp_0_tx_rst_1.value = 0
+        self.dut.qsfp_0_rx_rst_2.value = 0
+        self.dut.qsfp_0_tx_rst_2.value = 0
+        self.dut.qsfp_0_rx_rst_3.value = 0
+        self.dut.qsfp_0_tx_rst_3.value = 0
+        self.dut.qsfp_1_rx_rst_0.value = 0
+        self.dut.qsfp_1_tx_rst_0.value = 0
+        self.dut.qsfp_1_rx_rst_1.value = 0
+        self.dut.qsfp_1_tx_rst_1.value = 0
+        self.dut.qsfp_1_rx_rst_2.value = 0
+        self.dut.qsfp_1_tx_rst_2.value = 0
+        self.dut.qsfp_1_rx_rst_3.value = 0
+        self.dut.qsfp_1_tx_rst_3.value = 0
 
 
 @cocotb.test()
diff --git a/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py b/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
index ec5c34f30..78e9eb932 100644
--- a/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -113,44 +113,44 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 1
-        self.dut.qsfp_0_rx_rst_0 <= 1
-        self.dut.qsfp_0_tx_rst_0 <= 1
-        self.dut.qsfp_0_rx_rst_1 <= 1
-        self.dut.qsfp_0_tx_rst_1 <= 1
-        self.dut.qsfp_0_rx_rst_2 <= 1
-        self.dut.qsfp_0_tx_rst_2 <= 1
-        self.dut.qsfp_0_rx_rst_3 <= 1
-        self.dut.qsfp_0_tx_rst_3 <= 1
-        self.dut.qsfp_1_rx_rst_0 <= 1
-        self.dut.qsfp_1_tx_rst_0 <= 1
-        self.dut.qsfp_1_rx_rst_1 <= 1
-        self.dut.qsfp_1_tx_rst_1 <= 1
-        self.dut.qsfp_1_rx_rst_2 <= 1
-        self.dut.qsfp_1_tx_rst_2 <= 1
-        self.dut.qsfp_1_rx_rst_3 <= 1
-        self.dut.qsfp_1_tx_rst_3 <= 1
+        self.dut.rst.value = 1
+        self.dut.qsfp_0_rx_rst_0.value = 1
+        self.dut.qsfp_0_tx_rst_0.value = 1
+        self.dut.qsfp_0_rx_rst_1.value = 1
+        self.dut.qsfp_0_tx_rst_1.value = 1
+        self.dut.qsfp_0_rx_rst_2.value = 1
+        self.dut.qsfp_0_tx_rst_2.value = 1
+        self.dut.qsfp_0_rx_rst_3.value = 1
+        self.dut.qsfp_0_tx_rst_3.value = 1
+        self.dut.qsfp_1_rx_rst_0.value = 1
+        self.dut.qsfp_1_tx_rst_0.value = 1
+        self.dut.qsfp_1_rx_rst_1.value = 1
+        self.dut.qsfp_1_tx_rst_1.value = 1
+        self.dut.qsfp_1_rx_rst_2.value = 1
+        self.dut.qsfp_1_tx_rst_2.value = 1
+        self.dut.qsfp_1_rx_rst_3.value = 1
+        self.dut.qsfp_1_tx_rst_3.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
-        self.dut.qsfp_0_rx_rst_0 <= 0
-        self.dut.qsfp_0_tx_rst_0 <= 0
-        self.dut.qsfp_0_rx_rst_1 <= 0
-        self.dut.qsfp_0_tx_rst_1 <= 0
-        self.dut.qsfp_0_rx_rst_2 <= 0
-        self.dut.qsfp_0_tx_rst_2 <= 0
-        self.dut.qsfp_0_rx_rst_3 <= 0
-        self.dut.qsfp_0_tx_rst_3 <= 0
-        self.dut.qsfp_1_rx_rst_0 <= 0
-        self.dut.qsfp_1_tx_rst_0 <= 0
-        self.dut.qsfp_1_rx_rst_1 <= 0
-        self.dut.qsfp_1_tx_rst_1 <= 0
-        self.dut.qsfp_1_rx_rst_2 <= 0
-        self.dut.qsfp_1_tx_rst_2 <= 0
-        self.dut.qsfp_1_rx_rst_3 <= 0
-        self.dut.qsfp_1_tx_rst_3 <= 0
+        self.dut.rst.value = 0
+        self.dut.qsfp_0_rx_rst_0.value = 0
+        self.dut.qsfp_0_tx_rst_0.value = 0
+        self.dut.qsfp_0_rx_rst_1.value = 0
+        self.dut.qsfp_0_tx_rst_1.value = 0
+        self.dut.qsfp_0_rx_rst_2.value = 0
+        self.dut.qsfp_0_tx_rst_2.value = 0
+        self.dut.qsfp_0_rx_rst_3.value = 0
+        self.dut.qsfp_0_tx_rst_3.value = 0
+        self.dut.qsfp_1_rx_rst_0.value = 0
+        self.dut.qsfp_1_tx_rst_0.value = 0
+        self.dut.qsfp_1_rx_rst_1.value = 0
+        self.dut.qsfp_1_tx_rst_1.value = 0
+        self.dut.qsfp_1_rx_rst_2.value = 0
+        self.dut.qsfp_1_tx_rst_2.value = 0
+        self.dut.qsfp_1_rx_rst_3.value = 0
+        self.dut.qsfp_1_tx_rst_3.value = 0
 
 
 @cocotb.test()
diff --git a/example/ATLYS/fpga/tb/fpga_core/test_fpga_core.py b/example/ATLYS/fpga/tb/fpga_core/test_fpga_core.py
index 47913a947..4dcffe3f7 100644
--- a/example/ATLYS/fpga/tb/fpga_core/test_fpga_core.py
+++ b/example/ATLYS/fpga/tb/fpga_core/test_fpga_core.py
@@ -66,12 +66,12 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
 
 
 @cocotb.test()
diff --git a/example/AU200/fpga_10g/tb/fpga_core/test_fpga_core.py b/example/AU200/fpga_10g/tb/fpga_core/test_fpga_core.py
index 37a47626b..6f609015c 100644
--- a/example/AU200/fpga_10g/tb/fpga_core/test_fpga_core.py
+++ b/example/AU200/fpga_10g/tb/fpga_core/test_fpga_core.py
@@ -113,44 +113,44 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 1
-        self.dut.qsfp0_rx_rst_1 <= 1
-        self.dut.qsfp0_tx_rst_1 <= 1
-        self.dut.qsfp0_rx_rst_2 <= 1
-        self.dut.qsfp0_tx_rst_2 <= 1
-        self.dut.qsfp0_rx_rst_3 <= 1
-        self.dut.qsfp0_tx_rst_3 <= 1
-        self.dut.qsfp0_rx_rst_4 <= 1
-        self.dut.qsfp0_tx_rst_4 <= 1
-        self.dut.qsfp1_rx_rst_1 <= 1
-        self.dut.qsfp1_tx_rst_1 <= 1
-        self.dut.qsfp1_rx_rst_2 <= 1
-        self.dut.qsfp1_tx_rst_2 <= 1
-        self.dut.qsfp1_rx_rst_3 <= 1
-        self.dut.qsfp1_tx_rst_3 <= 1
-        self.dut.qsfp1_rx_rst_4 <= 1
-        self.dut.qsfp1_tx_rst_4 <= 1
+        self.dut.rst.value = 1
+        self.dut.qsfp0_rx_rst_1.value = 1
+        self.dut.qsfp0_tx_rst_1.value = 1
+        self.dut.qsfp0_rx_rst_2.value = 1
+        self.dut.qsfp0_tx_rst_2.value = 1
+        self.dut.qsfp0_rx_rst_3.value = 1
+        self.dut.qsfp0_tx_rst_3.value = 1
+        self.dut.qsfp0_rx_rst_4.value = 1
+        self.dut.qsfp0_tx_rst_4.value = 1
+        self.dut.qsfp1_rx_rst_1.value = 1
+        self.dut.qsfp1_tx_rst_1.value = 1
+        self.dut.qsfp1_rx_rst_2.value = 1
+        self.dut.qsfp1_tx_rst_2.value = 1
+        self.dut.qsfp1_rx_rst_3.value = 1
+        self.dut.qsfp1_tx_rst_3.value = 1
+        self.dut.qsfp1_rx_rst_4.value = 1
+        self.dut.qsfp1_tx_rst_4.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
-        self.dut.qsfp0_rx_rst_1 <= 0
-        self.dut.qsfp0_tx_rst_1 <= 0
-        self.dut.qsfp0_rx_rst_2 <= 0
-        self.dut.qsfp0_tx_rst_2 <= 0
-        self.dut.qsfp0_rx_rst_3 <= 0
-        self.dut.qsfp0_tx_rst_3 <= 0
-        self.dut.qsfp0_rx_rst_4 <= 0
-        self.dut.qsfp0_tx_rst_4 <= 0
-        self.dut.qsfp1_rx_rst_1 <= 0
-        self.dut.qsfp1_tx_rst_1 <= 0
-        self.dut.qsfp1_rx_rst_2 <= 0
-        self.dut.qsfp1_tx_rst_2 <= 0
-        self.dut.qsfp1_rx_rst_3 <= 0
-        self.dut.qsfp1_tx_rst_3 <= 0
-        self.dut.qsfp1_rx_rst_4 <= 0
-        self.dut.qsfp1_tx_rst_4 <= 0
+        self.dut.rst.value = 0
+        self.dut.qsfp0_rx_rst_1.value = 0
+        self.dut.qsfp0_tx_rst_1.value = 0
+        self.dut.qsfp0_rx_rst_2.value = 0
+        self.dut.qsfp0_tx_rst_2.value = 0
+        self.dut.qsfp0_rx_rst_3.value = 0
+        self.dut.qsfp0_tx_rst_3.value = 0
+        self.dut.qsfp0_rx_rst_4.value = 0
+        self.dut.qsfp0_tx_rst_4.value = 0
+        self.dut.qsfp1_rx_rst_1.value = 0
+        self.dut.qsfp1_tx_rst_1.value = 0
+        self.dut.qsfp1_rx_rst_2.value = 0
+        self.dut.qsfp1_tx_rst_2.value = 0
+        self.dut.qsfp1_rx_rst_3.value = 0
+        self.dut.qsfp1_tx_rst_3.value = 0
+        self.dut.qsfp1_rx_rst_4.value = 0
+        self.dut.qsfp1_tx_rst_4.value = 0
 
 
 @cocotb.test()
diff --git a/example/AU250/fpga_10g/tb/fpga_core/test_fpga_core.py b/example/AU250/fpga_10g/tb/fpga_core/test_fpga_core.py
index 37a47626b..6f609015c 100644
--- a/example/AU250/fpga_10g/tb/fpga_core/test_fpga_core.py
+++ b/example/AU250/fpga_10g/tb/fpga_core/test_fpga_core.py
@@ -113,44 +113,44 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 1
-        self.dut.qsfp0_rx_rst_1 <= 1
-        self.dut.qsfp0_tx_rst_1 <= 1
-        self.dut.qsfp0_rx_rst_2 <= 1
-        self.dut.qsfp0_tx_rst_2 <= 1
-        self.dut.qsfp0_rx_rst_3 <= 1
-        self.dut.qsfp0_tx_rst_3 <= 1
-        self.dut.qsfp0_rx_rst_4 <= 1
-        self.dut.qsfp0_tx_rst_4 <= 1
-        self.dut.qsfp1_rx_rst_1 <= 1
-        self.dut.qsfp1_tx_rst_1 <= 1
-        self.dut.qsfp1_rx_rst_2 <= 1
-        self.dut.qsfp1_tx_rst_2 <= 1
-        self.dut.qsfp1_rx_rst_3 <= 1
-        self.dut.qsfp1_tx_rst_3 <= 1
-        self.dut.qsfp1_rx_rst_4 <= 1
-        self.dut.qsfp1_tx_rst_4 <= 1
+        self.dut.rst.value = 1
+        self.dut.qsfp0_rx_rst_1.value = 1
+        self.dut.qsfp0_tx_rst_1.value = 1
+        self.dut.qsfp0_rx_rst_2.value = 1
+        self.dut.qsfp0_tx_rst_2.value = 1
+        self.dut.qsfp0_rx_rst_3.value = 1
+        self.dut.qsfp0_tx_rst_3.value = 1
+        self.dut.qsfp0_rx_rst_4.value = 1
+        self.dut.qsfp0_tx_rst_4.value = 1
+        self.dut.qsfp1_rx_rst_1.value = 1
+        self.dut.qsfp1_tx_rst_1.value = 1
+        self.dut.qsfp1_rx_rst_2.value = 1
+        self.dut.qsfp1_tx_rst_2.value = 1
+        self.dut.qsfp1_rx_rst_3.value = 1
+        self.dut.qsfp1_tx_rst_3.value = 1
+        self.dut.qsfp1_rx_rst_4.value = 1
+        self.dut.qsfp1_tx_rst_4.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
-        self.dut.qsfp0_rx_rst_1 <= 0
-        self.dut.qsfp0_tx_rst_1 <= 0
-        self.dut.qsfp0_rx_rst_2 <= 0
-        self.dut.qsfp0_tx_rst_2 <= 0
-        self.dut.qsfp0_rx_rst_3 <= 0
-        self.dut.qsfp0_tx_rst_3 <= 0
-        self.dut.qsfp0_rx_rst_4 <= 0
-        self.dut.qsfp0_tx_rst_4 <= 0
-        self.dut.qsfp1_rx_rst_1 <= 0
-        self.dut.qsfp1_tx_rst_1 <= 0
-        self.dut.qsfp1_rx_rst_2 <= 0
-        self.dut.qsfp1_tx_rst_2 <= 0
-        self.dut.qsfp1_rx_rst_3 <= 0
-        self.dut.qsfp1_tx_rst_3 <= 0
-        self.dut.qsfp1_rx_rst_4 <= 0
-        self.dut.qsfp1_tx_rst_4 <= 0
+        self.dut.rst.value = 0
+        self.dut.qsfp0_rx_rst_1.value = 0
+        self.dut.qsfp0_tx_rst_1.value = 0
+        self.dut.qsfp0_rx_rst_2.value = 0
+        self.dut.qsfp0_tx_rst_2.value = 0
+        self.dut.qsfp0_rx_rst_3.value = 0
+        self.dut.qsfp0_tx_rst_3.value = 0
+        self.dut.qsfp0_rx_rst_4.value = 0
+        self.dut.qsfp0_tx_rst_4.value = 0
+        self.dut.qsfp1_rx_rst_1.value = 0
+        self.dut.qsfp1_tx_rst_1.value = 0
+        self.dut.qsfp1_rx_rst_2.value = 0
+        self.dut.qsfp1_tx_rst_2.value = 0
+        self.dut.qsfp1_rx_rst_3.value = 0
+        self.dut.qsfp1_tx_rst_3.value = 0
+        self.dut.qsfp1_rx_rst_4.value = 0
+        self.dut.qsfp1_tx_rst_4.value = 0
 
 
 @cocotb.test()
diff --git a/example/AU280/fpga_10g/tb/fpga_core/test_fpga_core.py b/example/AU280/fpga_10g/tb/fpga_core/test_fpga_core.py
index e989629b2..3884d768e 100644
--- a/example/AU280/fpga_10g/tb/fpga_core/test_fpga_core.py
+++ b/example/AU280/fpga_10g/tb/fpga_core/test_fpga_core.py
@@ -111,44 +111,44 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 1
-        self.dut.qsfp0_rx_rst_1 <= 1
-        self.dut.qsfp0_tx_rst_1 <= 1
-        self.dut.qsfp0_rx_rst_2 <= 1
-        self.dut.qsfp0_tx_rst_2 <= 1
-        self.dut.qsfp0_rx_rst_3 <= 1
-        self.dut.qsfp0_tx_rst_3 <= 1
-        self.dut.qsfp0_rx_rst_4 <= 1
-        self.dut.qsfp0_tx_rst_4 <= 1
-        self.dut.qsfp1_rx_rst_1 <= 1
-        self.dut.qsfp1_tx_rst_1 <= 1
-        self.dut.qsfp1_rx_rst_2 <= 1
-        self.dut.qsfp1_tx_rst_2 <= 1
-        self.dut.qsfp1_rx_rst_3 <= 1
-        self.dut.qsfp1_tx_rst_3 <= 1
-        self.dut.qsfp1_rx_rst_4 <= 1
-        self.dut.qsfp1_tx_rst_4 <= 1
+        self.dut.rst.value = 1
+        self.dut.qsfp0_rx_rst_1.value = 1
+        self.dut.qsfp0_tx_rst_1.value = 1
+        self.dut.qsfp0_rx_rst_2.value = 1
+        self.dut.qsfp0_tx_rst_2.value = 1
+        self.dut.qsfp0_rx_rst_3.value = 1
+        self.dut.qsfp0_tx_rst_3.value = 1
+        self.dut.qsfp0_rx_rst_4.value = 1
+        self.dut.qsfp0_tx_rst_4.value = 1
+        self.dut.qsfp1_rx_rst_1.value = 1
+        self.dut.qsfp1_tx_rst_1.value = 1
+        self.dut.qsfp1_rx_rst_2.value = 1
+        self.dut.qsfp1_tx_rst_2.value = 1
+        self.dut.qsfp1_rx_rst_3.value = 1
+        self.dut.qsfp1_tx_rst_3.value = 1
+        self.dut.qsfp1_rx_rst_4.value = 1
+        self.dut.qsfp1_tx_rst_4.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
-        self.dut.qsfp0_rx_rst_1 <= 0
-        self.dut.qsfp0_tx_rst_1 <= 0
-        self.dut.qsfp0_rx_rst_2 <= 0
-        self.dut.qsfp0_tx_rst_2 <= 0
-        self.dut.qsfp0_rx_rst_3 <= 0
-        self.dut.qsfp0_tx_rst_3 <= 0
-        self.dut.qsfp0_rx_rst_4 <= 0
-        self.dut.qsfp0_tx_rst_4 <= 0
-        self.dut.qsfp1_rx_rst_1 <= 0
-        self.dut.qsfp1_tx_rst_1 <= 0
-        self.dut.qsfp1_rx_rst_2 <= 0
-        self.dut.qsfp1_tx_rst_2 <= 0
-        self.dut.qsfp1_rx_rst_3 <= 0
-        self.dut.qsfp1_tx_rst_3 <= 0
-        self.dut.qsfp1_rx_rst_4 <= 0
-        self.dut.qsfp1_tx_rst_4 <= 0
+        self.dut.rst.value = 0
+        self.dut.qsfp0_rx_rst_1.value = 0
+        self.dut.qsfp0_tx_rst_1.value = 0
+        self.dut.qsfp0_rx_rst_2.value = 0
+        self.dut.qsfp0_tx_rst_2.value = 0
+        self.dut.qsfp0_rx_rst_3.value = 0
+        self.dut.qsfp0_tx_rst_3.value = 0
+        self.dut.qsfp0_rx_rst_4.value = 0
+        self.dut.qsfp0_tx_rst_4.value = 0
+        self.dut.qsfp1_rx_rst_1.value = 0
+        self.dut.qsfp1_tx_rst_1.value = 0
+        self.dut.qsfp1_rx_rst_2.value = 0
+        self.dut.qsfp1_tx_rst_2.value = 0
+        self.dut.qsfp1_rx_rst_3.value = 0
+        self.dut.qsfp1_tx_rst_3.value = 0
+        self.dut.qsfp1_rx_rst_4.value = 0
+        self.dut.qsfp1_tx_rst_4.value = 0
 
 
 @cocotb.test()
diff --git a/example/AU50/fpga_10g/tb/fpga_core/test_fpga_core.py b/example/AU50/fpga_10g/tb/fpga_core/test_fpga_core.py
index 8921956ea..95d86a84c 100644
--- a/example/AU50/fpga_10g/tb/fpga_core/test_fpga_core.py
+++ b/example/AU50/fpga_10g/tb/fpga_core/test_fpga_core.py
@@ -83,28 +83,28 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst.setimmediatevalue(1)
-        self.dut.qsfp_rx_rst_1 <= 1
-        self.dut.qsfp_tx_rst_1 <= 1
-        self.dut.qsfp_rx_rst_2 <= 1
-        self.dut.qsfp_tx_rst_2 <= 1
-        self.dut.qsfp_rx_rst_3 <= 1
-        self.dut.qsfp_tx_rst_3 <= 1
-        self.dut.qsfp_rx_rst_4 <= 1
-        self.dut.qsfp_tx_rst_4 <= 1
+        self.dut.rst.value = 1
+        self.dut.qsfp_rx_rst_1.value = 1
+        self.dut.qsfp_tx_rst_1.value = 1
+        self.dut.qsfp_rx_rst_2.value = 1
+        self.dut.qsfp_tx_rst_2.value = 1
+        self.dut.qsfp_rx_rst_3.value = 1
+        self.dut.qsfp_tx_rst_3.value = 1
+        self.dut.qsfp_rx_rst_4.value = 1
+        self.dut.qsfp_tx_rst_4.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
-        self.dut.qsfp_rx_rst_1 <= 0
-        self.dut.qsfp_tx_rst_1 <= 0
-        self.dut.qsfp_rx_rst_2 <= 0
-        self.dut.qsfp_tx_rst_2 <= 0
-        self.dut.qsfp_rx_rst_3 <= 0
-        self.dut.qsfp_tx_rst_3 <= 0
-        self.dut.qsfp_rx_rst_4 <= 0
-        self.dut.qsfp_tx_rst_4 <= 0
+        self.dut.rst.value = 0
+        self.dut.qsfp_rx_rst_1.value = 0
+        self.dut.qsfp_tx_rst_1.value = 0
+        self.dut.qsfp_rx_rst_2.value = 0
+        self.dut.qsfp_tx_rst_2.value = 0
+        self.dut.qsfp_rx_rst_3.value = 0
+        self.dut.qsfp_tx_rst_3.value = 0
+        self.dut.qsfp_rx_rst_4.value = 0
+        self.dut.qsfp_tx_rst_4.value = 0
 
 
 @cocotb.test()
diff --git a/example/Arty/fpga/tb/fpga_core/test_fpga_core.py b/example/Arty/fpga/tb/fpga_core/test_fpga_core.py
index f4a58a58d..34d8ba613 100644
--- a/example/Arty/fpga/tb/fpga_core/test_fpga_core.py
+++ b/example/Arty/fpga/tb/fpga_core/test_fpga_core.py
@@ -64,12 +64,12 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
 
 
 @cocotb.test()
diff --git a/example/C10LP/fpga/tb/fpga_core/test_fpga_core.py b/example/C10LP/fpga/tb/fpga_core/test_fpga_core.py
index 331c63817..40558f75a 100644
--- a/example/C10LP/fpga/tb/fpga_core/test_fpga_core.py
+++ b/example/C10LP/fpga/tb/fpga_core/test_fpga_core.py
@@ -64,23 +64,23 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
 
     async def _run_clk(self):
         t = Timer(2, 'ns')
         while True:
-            self.dut.clk <= 1
+            self.dut.clk.value = 1
             await t
-            self.dut.clk90 <= 1
+            self.dut.clk90.value = 1
             await t
-            self.dut.clk <= 0
+            self.dut.clk.value = 0
             await t
-            self.dut.clk90 <= 0
+            self.dut.clk90.value = 0
             await t
 
 
diff --git a/example/DE2-115/fpga/tb/fpga_core/test_fpga_core.py b/example/DE2-115/fpga/tb/fpga_core/test_fpga_core.py
index c24ab12e1..f2a2f5dfb 100644
--- a/example/DE2-115/fpga/tb/fpga_core/test_fpga_core.py
+++ b/example/DE2-115/fpga/tb/fpga_core/test_fpga_core.py
@@ -68,23 +68,23 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
 
     async def _run_clk(self):
         t = Timer(2, 'ns')
         while True:
-            self.dut.clk <= 1
+            self.dut.clk.value = 1
             await t
-            self.dut.clk90 <= 1
+            self.dut.clk90.value = 1
             await t
-            self.dut.clk <= 0
+            self.dut.clk.value = 0
             await t
-            self.dut.clk90 <= 0
+            self.dut.clk90.value = 0
             await t
 
 
diff --git a/example/DE5-Net/fpga/tb/fpga_core/test_fpga_core.py b/example/DE5-Net/fpga/tb/fpga_core/test_fpga_core.py
index 89c239e2c..95b1238af 100644
--- a/example/DE5-Net/fpga/tb/fpga_core/test_fpga_core.py
+++ b/example/DE5-Net/fpga/tb/fpga_core/test_fpga_core.py
@@ -70,12 +70,12 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
 
 
 @cocotb.test()
diff --git a/example/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py b/example/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py
index 9907cad0b..d4370edac 100644
--- a/example/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py
+++ b/example/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py
@@ -69,20 +69,20 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 1
-        self.dut.sfp_1_rx_rst <= 1
-        self.dut.sfp_1_tx_rst <= 1
-        self.dut.sfp_2_rx_rst <= 1
-        self.dut.sfp_2_tx_rst <= 1
+        self.dut.rst.value = 1
+        self.dut.sfp_1_rx_rst.value = 1
+        self.dut.sfp_1_tx_rst.value = 1
+        self.dut.sfp_2_rx_rst.value = 1
+        self.dut.sfp_2_tx_rst.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
-        self.dut.sfp_1_rx_rst <= 0
-        self.dut.sfp_1_tx_rst <= 0
-        self.dut.sfp_2_rx_rst <= 0
-        self.dut.sfp_2_tx_rst <= 0
+        self.dut.rst.value = 0
+        self.dut.sfp_1_rx_rst.value = 0
+        self.dut.sfp_1_tx_rst.value = 0
+        self.dut.sfp_2_rx_rst.value = 0
+        self.dut.sfp_2_tx_rst.value = 0
 
 
 @cocotb.test()
diff --git a/example/ExaNIC_X25/fpga_10g/tb/fpga_core/test_fpga_core.py b/example/ExaNIC_X25/fpga_10g/tb/fpga_core/test_fpga_core.py
index 9907cad0b..d4370edac 100644
--- a/example/ExaNIC_X25/fpga_10g/tb/fpga_core/test_fpga_core.py
+++ b/example/ExaNIC_X25/fpga_10g/tb/fpga_core/test_fpga_core.py
@@ -69,20 +69,20 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 1
-        self.dut.sfp_1_rx_rst <= 1
-        self.dut.sfp_1_tx_rst <= 1
-        self.dut.sfp_2_rx_rst <= 1
-        self.dut.sfp_2_tx_rst <= 1
+        self.dut.rst.value = 1
+        self.dut.sfp_1_rx_rst.value = 1
+        self.dut.sfp_1_tx_rst.value = 1
+        self.dut.sfp_2_rx_rst.value = 1
+        self.dut.sfp_2_tx_rst.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
-        self.dut.sfp_1_rx_rst <= 0
-        self.dut.sfp_1_tx_rst <= 0
-        self.dut.sfp_2_rx_rst <= 0
-        self.dut.sfp_2_tx_rst <= 0
+        self.dut.rst.value = 0
+        self.dut.sfp_1_rx_rst.value = 0
+        self.dut.sfp_1_tx_rst.value = 0
+        self.dut.sfp_2_rx_rst.value = 0
+        self.dut.sfp_2_tx_rst.value = 0
 
 
 @cocotb.test()
diff --git a/example/HTG9200/fpga_10g/tb/fpga_core/test_fpga_core.py b/example/HTG9200/fpga_10g/tb/fpga_core/test_fpga_core.py
index e1eb8dea9..0a109c8be 100644
--- a/example/HTG9200/fpga_10g/tb/fpga_core/test_fpga_core.py
+++ b/example/HTG9200/fpga_10g/tb/fpga_core/test_fpga_core.py
@@ -313,156 +313,156 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 1
-        self.dut.qsfp_1_rx_rst_1 <= 1
-        self.dut.qsfp_1_tx_rst_1 <= 1
-        self.dut.qsfp_1_rx_rst_2 <= 1
-        self.dut.qsfp_1_tx_rst_2 <= 1
-        self.dut.qsfp_1_rx_rst_3 <= 1
-        self.dut.qsfp_1_tx_rst_3 <= 1
-        self.dut.qsfp_1_rx_rst_4 <= 1
-        self.dut.qsfp_1_tx_rst_4 <= 1
-        self.dut.qsfp_2_rx_rst_1 <= 1
-        self.dut.qsfp_2_tx_rst_1 <= 1
-        self.dut.qsfp_2_rx_rst_2 <= 1
-        self.dut.qsfp_2_tx_rst_2 <= 1
-        self.dut.qsfp_2_rx_rst_3 <= 1
-        self.dut.qsfp_2_tx_rst_3 <= 1
-        self.dut.qsfp_2_rx_rst_4 <= 1
-        self.dut.qsfp_2_tx_rst_4 <= 1
-        self.dut.qsfp_3_rx_rst_1 <= 1
-        self.dut.qsfp_3_tx_rst_1 <= 1
-        self.dut.qsfp_3_rx_rst_2 <= 1
-        self.dut.qsfp_3_tx_rst_2 <= 1
-        self.dut.qsfp_3_rx_rst_3 <= 1
-        self.dut.qsfp_3_tx_rst_3 <= 1
-        self.dut.qsfp_3_rx_rst_4 <= 1
-        self.dut.qsfp_3_tx_rst_4 <= 1
-        self.dut.qsfp_4_rx_rst_1 <= 1
-        self.dut.qsfp_4_tx_rst_1 <= 1
-        self.dut.qsfp_4_rx_rst_2 <= 1
-        self.dut.qsfp_4_tx_rst_2 <= 1
-        self.dut.qsfp_4_rx_rst_3 <= 1
-        self.dut.qsfp_4_tx_rst_3 <= 1
-        self.dut.qsfp_4_rx_rst_4 <= 1
-        self.dut.qsfp_4_tx_rst_4 <= 1
-        self.dut.qsfp_5_rx_rst_1 <= 1
-        self.dut.qsfp_5_tx_rst_1 <= 1
-        self.dut.qsfp_5_rx_rst_2 <= 1
-        self.dut.qsfp_5_tx_rst_2 <= 1
-        self.dut.qsfp_5_rx_rst_3 <= 1
-        self.dut.qsfp_5_tx_rst_3 <= 1
-        self.dut.qsfp_5_rx_rst_4 <= 1
-        self.dut.qsfp_5_tx_rst_4 <= 1
-        self.dut.qsfp_6_rx_rst_1 <= 1
-        self.dut.qsfp_6_tx_rst_1 <= 1
-        self.dut.qsfp_6_rx_rst_2 <= 1
-        self.dut.qsfp_6_tx_rst_2 <= 1
-        self.dut.qsfp_6_rx_rst_3 <= 1
-        self.dut.qsfp_6_tx_rst_3 <= 1
-        self.dut.qsfp_6_rx_rst_4 <= 1
-        self.dut.qsfp_6_tx_rst_4 <= 1
-        self.dut.qsfp_7_rx_rst_1 <= 1
-        self.dut.qsfp_7_tx_rst_1 <= 1
-        self.dut.qsfp_7_rx_rst_2 <= 1
-        self.dut.qsfp_7_tx_rst_2 <= 1
-        self.dut.qsfp_7_rx_rst_3 <= 1
-        self.dut.qsfp_7_tx_rst_3 <= 1
-        self.dut.qsfp_7_rx_rst_4 <= 1
-        self.dut.qsfp_7_tx_rst_4 <= 1
-        self.dut.qsfp_8_rx_rst_1 <= 1
-        self.dut.qsfp_8_tx_rst_1 <= 1
-        self.dut.qsfp_8_rx_rst_2 <= 1
-        self.dut.qsfp_8_tx_rst_2 <= 1
-        self.dut.qsfp_8_rx_rst_3 <= 1
-        self.dut.qsfp_8_tx_rst_3 <= 1
-        self.dut.qsfp_8_rx_rst_4 <= 1
-        self.dut.qsfp_8_tx_rst_4 <= 1
-        self.dut.qsfp_9_rx_rst_1 <= 1
-        self.dut.qsfp_9_tx_rst_1 <= 1
-        self.dut.qsfp_9_rx_rst_2 <= 1
-        self.dut.qsfp_9_tx_rst_2 <= 1
-        self.dut.qsfp_9_rx_rst_3 <= 1
-        self.dut.qsfp_9_tx_rst_3 <= 1
-        self.dut.qsfp_9_rx_rst_4 <= 1
-        self.dut.qsfp_9_tx_rst_4 <= 1
+        self.dut.rst.value = 1
+        self.dut.qsfp_1_rx_rst_1.value = 1
+        self.dut.qsfp_1_tx_rst_1.value = 1
+        self.dut.qsfp_1_rx_rst_2.value = 1
+        self.dut.qsfp_1_tx_rst_2.value = 1
+        self.dut.qsfp_1_rx_rst_3.value = 1
+        self.dut.qsfp_1_tx_rst_3.value = 1
+        self.dut.qsfp_1_rx_rst_4.value = 1
+        self.dut.qsfp_1_tx_rst_4.value = 1
+        self.dut.qsfp_2_rx_rst_1.value = 1
+        self.dut.qsfp_2_tx_rst_1.value = 1
+        self.dut.qsfp_2_rx_rst_2.value = 1
+        self.dut.qsfp_2_tx_rst_2.value = 1
+        self.dut.qsfp_2_rx_rst_3.value = 1
+        self.dut.qsfp_2_tx_rst_3.value = 1
+        self.dut.qsfp_2_rx_rst_4.value = 1
+        self.dut.qsfp_2_tx_rst_4.value = 1
+        self.dut.qsfp_3_rx_rst_1.value = 1
+        self.dut.qsfp_3_tx_rst_1.value = 1
+        self.dut.qsfp_3_rx_rst_2.value = 1
+        self.dut.qsfp_3_tx_rst_2.value = 1
+        self.dut.qsfp_3_rx_rst_3.value = 1
+        self.dut.qsfp_3_tx_rst_3.value = 1
+        self.dut.qsfp_3_rx_rst_4.value = 1
+        self.dut.qsfp_3_tx_rst_4.value = 1
+        self.dut.qsfp_4_rx_rst_1.value = 1
+        self.dut.qsfp_4_tx_rst_1.value = 1
+        self.dut.qsfp_4_rx_rst_2.value = 1
+        self.dut.qsfp_4_tx_rst_2.value = 1
+        self.dut.qsfp_4_rx_rst_3.value = 1
+        self.dut.qsfp_4_tx_rst_3.value = 1
+        self.dut.qsfp_4_rx_rst_4.value = 1
+        self.dut.qsfp_4_tx_rst_4.value = 1
+        self.dut.qsfp_5_rx_rst_1.value = 1
+        self.dut.qsfp_5_tx_rst_1.value = 1
+        self.dut.qsfp_5_rx_rst_2.value = 1
+        self.dut.qsfp_5_tx_rst_2.value = 1
+        self.dut.qsfp_5_rx_rst_3.value = 1
+        self.dut.qsfp_5_tx_rst_3.value = 1
+        self.dut.qsfp_5_rx_rst_4.value = 1
+        self.dut.qsfp_5_tx_rst_4.value = 1
+        self.dut.qsfp_6_rx_rst_1.value = 1
+        self.dut.qsfp_6_tx_rst_1.value = 1
+        self.dut.qsfp_6_rx_rst_2.value = 1
+        self.dut.qsfp_6_tx_rst_2.value = 1
+        self.dut.qsfp_6_rx_rst_3.value = 1
+        self.dut.qsfp_6_tx_rst_3.value = 1
+        self.dut.qsfp_6_rx_rst_4.value = 1
+        self.dut.qsfp_6_tx_rst_4.value = 1
+        self.dut.qsfp_7_rx_rst_1.value = 1
+        self.dut.qsfp_7_tx_rst_1.value = 1
+        self.dut.qsfp_7_rx_rst_2.value = 1
+        self.dut.qsfp_7_tx_rst_2.value = 1
+        self.dut.qsfp_7_rx_rst_3.value = 1
+        self.dut.qsfp_7_tx_rst_3.value = 1
+        self.dut.qsfp_7_rx_rst_4.value = 1
+        self.dut.qsfp_7_tx_rst_4.value = 1
+        self.dut.qsfp_8_rx_rst_1.value = 1
+        self.dut.qsfp_8_tx_rst_1.value = 1
+        self.dut.qsfp_8_rx_rst_2.value = 1
+        self.dut.qsfp_8_tx_rst_2.value = 1
+        self.dut.qsfp_8_rx_rst_3.value = 1
+        self.dut.qsfp_8_tx_rst_3.value = 1
+        self.dut.qsfp_8_rx_rst_4.value = 1
+        self.dut.qsfp_8_tx_rst_4.value = 1
+        self.dut.qsfp_9_rx_rst_1.value = 1
+        self.dut.qsfp_9_tx_rst_1.value = 1
+        self.dut.qsfp_9_rx_rst_2.value = 1
+        self.dut.qsfp_9_tx_rst_2.value = 1
+        self.dut.qsfp_9_rx_rst_3.value = 1
+        self.dut.qsfp_9_tx_rst_3.value = 1
+        self.dut.qsfp_9_rx_rst_4.value = 1
+        self.dut.qsfp_9_tx_rst_4.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
-        self.dut.qsfp_1_rx_rst_1 <= 0
-        self.dut.qsfp_1_tx_rst_1 <= 0
-        self.dut.qsfp_1_rx_rst_2 <= 0
-        self.dut.qsfp_1_tx_rst_2 <= 0
-        self.dut.qsfp_1_rx_rst_3 <= 0
-        self.dut.qsfp_1_tx_rst_3 <= 0
-        self.dut.qsfp_1_rx_rst_4 <= 0
-        self.dut.qsfp_1_tx_rst_4 <= 0
-        self.dut.qsfp_2_rx_rst_1 <= 0
-        self.dut.qsfp_2_tx_rst_1 <= 0
-        self.dut.qsfp_2_rx_rst_2 <= 0
-        self.dut.qsfp_2_tx_rst_2 <= 0
-        self.dut.qsfp_2_rx_rst_3 <= 0
-        self.dut.qsfp_2_tx_rst_3 <= 0
-        self.dut.qsfp_2_rx_rst_4 <= 0
-        self.dut.qsfp_2_tx_rst_4 <= 0
-        self.dut.qsfp_3_rx_rst_1 <= 0
-        self.dut.qsfp_3_tx_rst_1 <= 0
-        self.dut.qsfp_3_rx_rst_2 <= 0
-        self.dut.qsfp_3_tx_rst_2 <= 0
-        self.dut.qsfp_3_rx_rst_3 <= 0
-        self.dut.qsfp_3_tx_rst_3 <= 0
-        self.dut.qsfp_3_rx_rst_4 <= 0
-        self.dut.qsfp_3_tx_rst_4 <= 0
-        self.dut.qsfp_4_rx_rst_1 <= 0
-        self.dut.qsfp_4_tx_rst_1 <= 0
-        self.dut.qsfp_4_rx_rst_2 <= 0
-        self.dut.qsfp_4_tx_rst_2 <= 0
-        self.dut.qsfp_4_rx_rst_3 <= 0
-        self.dut.qsfp_4_tx_rst_3 <= 0
-        self.dut.qsfp_4_rx_rst_4 <= 0
-        self.dut.qsfp_4_tx_rst_4 <= 0
-        self.dut.qsfp_5_rx_rst_1 <= 0
-        self.dut.qsfp_5_tx_rst_1 <= 0
-        self.dut.qsfp_5_rx_rst_2 <= 0
-        self.dut.qsfp_5_tx_rst_2 <= 0
-        self.dut.qsfp_5_rx_rst_3 <= 0
-        self.dut.qsfp_5_tx_rst_3 <= 0
-        self.dut.qsfp_5_rx_rst_4 <= 0
-        self.dut.qsfp_5_tx_rst_4 <= 0
-        self.dut.qsfp_6_rx_rst_1 <= 0
-        self.dut.qsfp_6_tx_rst_1 <= 0
-        self.dut.qsfp_6_rx_rst_2 <= 0
-        self.dut.qsfp_6_tx_rst_2 <= 0
-        self.dut.qsfp_6_rx_rst_3 <= 0
-        self.dut.qsfp_6_tx_rst_3 <= 0
-        self.dut.qsfp_6_rx_rst_4 <= 0
-        self.dut.qsfp_6_tx_rst_4 <= 0
-        self.dut.qsfp_7_rx_rst_1 <= 0
-        self.dut.qsfp_7_tx_rst_1 <= 0
-        self.dut.qsfp_7_rx_rst_2 <= 0
-        self.dut.qsfp_7_tx_rst_2 <= 0
-        self.dut.qsfp_7_rx_rst_3 <= 0
-        self.dut.qsfp_7_tx_rst_3 <= 0
-        self.dut.qsfp_7_rx_rst_4 <= 0
-        self.dut.qsfp_7_tx_rst_4 <= 0
-        self.dut.qsfp_8_rx_rst_1 <= 0
-        self.dut.qsfp_8_tx_rst_1 <= 0
-        self.dut.qsfp_8_rx_rst_2 <= 0
-        self.dut.qsfp_8_tx_rst_2 <= 0
-        self.dut.qsfp_8_rx_rst_3 <= 0
-        self.dut.qsfp_8_tx_rst_3 <= 0
-        self.dut.qsfp_8_rx_rst_4 <= 0
-        self.dut.qsfp_8_tx_rst_4 <= 0
-        self.dut.qsfp_9_rx_rst_1 <= 0
-        self.dut.qsfp_9_tx_rst_1 <= 0
-        self.dut.qsfp_9_rx_rst_2 <= 0
-        self.dut.qsfp_9_tx_rst_2 <= 0
-        self.dut.qsfp_9_rx_rst_3 <= 0
-        self.dut.qsfp_9_tx_rst_3 <= 0
-        self.dut.qsfp_9_rx_rst_4 <= 0
-        self.dut.qsfp_9_tx_rst_4 <= 0
+        self.dut.rst.value = 0
+        self.dut.qsfp_1_rx_rst_1.value = 0
+        self.dut.qsfp_1_tx_rst_1.value = 0
+        self.dut.qsfp_1_rx_rst_2.value = 0
+        self.dut.qsfp_1_tx_rst_2.value = 0
+        self.dut.qsfp_1_rx_rst_3.value = 0
+        self.dut.qsfp_1_tx_rst_3.value = 0
+        self.dut.qsfp_1_rx_rst_4.value = 0
+        self.dut.qsfp_1_tx_rst_4.value = 0
+        self.dut.qsfp_2_rx_rst_1.value = 0
+        self.dut.qsfp_2_tx_rst_1.value = 0
+        self.dut.qsfp_2_rx_rst_2.value = 0
+        self.dut.qsfp_2_tx_rst_2.value = 0
+        self.dut.qsfp_2_rx_rst_3.value = 0
+        self.dut.qsfp_2_tx_rst_3.value = 0
+        self.dut.qsfp_2_rx_rst_4.value = 0
+        self.dut.qsfp_2_tx_rst_4.value = 0
+        self.dut.qsfp_3_rx_rst_1.value = 0
+        self.dut.qsfp_3_tx_rst_1.value = 0
+        self.dut.qsfp_3_rx_rst_2.value = 0
+        self.dut.qsfp_3_tx_rst_2.value = 0
+        self.dut.qsfp_3_rx_rst_3.value = 0
+        self.dut.qsfp_3_tx_rst_3.value = 0
+        self.dut.qsfp_3_rx_rst_4.value = 0
+        self.dut.qsfp_3_tx_rst_4.value = 0
+        self.dut.qsfp_4_rx_rst_1.value = 0
+        self.dut.qsfp_4_tx_rst_1.value = 0
+        self.dut.qsfp_4_rx_rst_2.value = 0
+        self.dut.qsfp_4_tx_rst_2.value = 0
+        self.dut.qsfp_4_rx_rst_3.value = 0
+        self.dut.qsfp_4_tx_rst_3.value = 0
+        self.dut.qsfp_4_rx_rst_4.value = 0
+        self.dut.qsfp_4_tx_rst_4.value = 0
+        self.dut.qsfp_5_rx_rst_1.value = 0
+        self.dut.qsfp_5_tx_rst_1.value = 0
+        self.dut.qsfp_5_rx_rst_2.value = 0
+        self.dut.qsfp_5_tx_rst_2.value = 0
+        self.dut.qsfp_5_rx_rst_3.value = 0
+        self.dut.qsfp_5_tx_rst_3.value = 0
+        self.dut.qsfp_5_rx_rst_4.value = 0
+        self.dut.qsfp_5_tx_rst_4.value = 0
+        self.dut.qsfp_6_rx_rst_1.value = 0
+        self.dut.qsfp_6_tx_rst_1.value = 0
+        self.dut.qsfp_6_rx_rst_2.value = 0
+        self.dut.qsfp_6_tx_rst_2.value = 0
+        self.dut.qsfp_6_rx_rst_3.value = 0
+        self.dut.qsfp_6_tx_rst_3.value = 0
+        self.dut.qsfp_6_rx_rst_4.value = 0
+        self.dut.qsfp_6_tx_rst_4.value = 0
+        self.dut.qsfp_7_rx_rst_1.value = 0
+        self.dut.qsfp_7_tx_rst_1.value = 0
+        self.dut.qsfp_7_rx_rst_2.value = 0
+        self.dut.qsfp_7_tx_rst_2.value = 0
+        self.dut.qsfp_7_rx_rst_3.value = 0
+        self.dut.qsfp_7_tx_rst_3.value = 0
+        self.dut.qsfp_7_rx_rst_4.value = 0
+        self.dut.qsfp_7_tx_rst_4.value = 0
+        self.dut.qsfp_8_rx_rst_1.value = 0
+        self.dut.qsfp_8_tx_rst_1.value = 0
+        self.dut.qsfp_8_rx_rst_2.value = 0
+        self.dut.qsfp_8_tx_rst_2.value = 0
+        self.dut.qsfp_8_rx_rst_3.value = 0
+        self.dut.qsfp_8_tx_rst_3.value = 0
+        self.dut.qsfp_8_rx_rst_4.value = 0
+        self.dut.qsfp_8_tx_rst_4.value = 0
+        self.dut.qsfp_9_rx_rst_1.value = 0
+        self.dut.qsfp_9_tx_rst_1.value = 0
+        self.dut.qsfp_9_rx_rst_2.value = 0
+        self.dut.qsfp_9_tx_rst_2.value = 0
+        self.dut.qsfp_9_rx_rst_3.value = 0
+        self.dut.qsfp_9_tx_rst_3.value = 0
+        self.dut.qsfp_9_rx_rst_4.value = 0
+        self.dut.qsfp_9_tx_rst_4.value = 0
 
 
 @cocotb.test()
diff --git a/example/HXT100G/fpga/tb/fpga_core/test_fpga_core.py b/example/HXT100G/fpga/tb/fpga_core/test_fpga_core.py
index 7116db21e..a4698680d 100644
--- a/example/HXT100G/fpga/tb/fpga_core/test_fpga_core.py
+++ b/example/HXT100G/fpga/tb/fpga_core/test_fpga_core.py
@@ -136,12 +136,12 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
 
 
 @cocotb.test()
diff --git a/example/HXT100G/fpga_cxpt16/tb/fpga_core/test_fpga_core.py b/example/HXT100G/fpga_cxpt16/tb/fpga_core/test_fpga_core.py
index 0460b5326..7f3e94ed8 100644
--- a/example/HXT100G/fpga_cxpt16/tb/fpga_core/test_fpga_core.py
+++ b/example/HXT100G/fpga_cxpt16/tb/fpga_core/test_fpga_core.py
@@ -135,12 +135,12 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
 
 
 @cocotb.test()
diff --git a/example/KC705/fpga_gmii/tb/fpga_core/test_fpga_core.py b/example/KC705/fpga_gmii/tb/fpga_core/test_fpga_core.py
index f324b2205..589e2c8a5 100644
--- a/example/KC705/fpga_gmii/tb/fpga_core/test_fpga_core.py
+++ b/example/KC705/fpga_gmii/tb/fpga_core/test_fpga_core.py
@@ -67,12 +67,12 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
 
 
 @cocotb.test()
diff --git a/example/KC705/fpga_rgmii/tb/fpga_core/test_fpga_core.py b/example/KC705/fpga_rgmii/tb/fpga_core/test_fpga_core.py
index c66d04590..e2a4b09f6 100644
--- a/example/KC705/fpga_rgmii/tb/fpga_core/test_fpga_core.py
+++ b/example/KC705/fpga_rgmii/tb/fpga_core/test_fpga_core.py
@@ -68,23 +68,23 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
 
     async def _run_clk(self):
         t = Timer(2, 'ns')
         while True:
-            self.dut.clk <= 1
+            self.dut.clk.value = 1
             await t
-            self.dut.clk90 <= 1
+            self.dut.clk90.value = 1
             await t
-            self.dut.clk <= 0
+            self.dut.clk.value = 0
             await t
-            self.dut.clk90 <= 0
+            self.dut.clk90.value = 0
             await t
 
 
diff --git a/example/KC705/fpga_sgmii/tb/fpga_core/test_fpga_core.py b/example/KC705/fpga_sgmii/tb/fpga_core/test_fpga_core.py
index 6a4cf4c28..318f92fe8 100644
--- a/example/KC705/fpga_sgmii/tb/fpga_core/test_fpga_core.py
+++ b/example/KC705/fpga_sgmii/tb/fpga_core/test_fpga_core.py
@@ -72,14 +72,14 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 1
-        self.dut.phy_gmii_rst <= 1
+        self.dut.rst.value = 1
+        self.dut.phy_gmii_rst.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
-        self.dut.phy_gmii_rst <= 0
+        self.dut.rst.value = 0
+        self.dut.phy_gmii_rst.value = 0
 
 
 @cocotb.test()
diff --git a/example/ML605/fpga_gmii/tb/fpga_core/test_fpga_core.py b/example/ML605/fpga_gmii/tb/fpga_core/test_fpga_core.py
index a37da8504..733a7f3c0 100644
--- a/example/ML605/fpga_gmii/tb/fpga_core/test_fpga_core.py
+++ b/example/ML605/fpga_gmii/tb/fpga_core/test_fpga_core.py
@@ -67,12 +67,12 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk_125mhz)
 
-        self.dut.rst_125mhz <= 1
+        self.dut.rst_125mhz.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk_125mhz)
 
-        self.dut.rst_125mhz <= 0
+        self.dut.rst_125mhz.value = 0
 
 
 @cocotb.test()
diff --git a/example/ML605/fpga_rgmii/tb/fpga_core/test_fpga_core.py b/example/ML605/fpga_rgmii/tb/fpga_core/test_fpga_core.py
index bdab9452e..c9125bdc2 100644
--- a/example/ML605/fpga_rgmii/tb/fpga_core/test_fpga_core.py
+++ b/example/ML605/fpga_rgmii/tb/fpga_core/test_fpga_core.py
@@ -68,23 +68,23 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk_125mhz)
 
-        self.dut.rst_125mhz <= 1
+        self.dut.rst_125mhz.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk_125mhz)
 
-        self.dut.rst_125mhz <= 0
+        self.dut.rst_125mhz.value = 0
 
     async def _run_clk_125mhz(self):
         t = Timer(2, 'ns')
         while True:
-            self.dut.clk_125mhz <= 1
+            self.dut.clk_125mhz.value = 1
             await t
-            self.dut.clk90_125mhz <= 1
+            self.dut.clk90_125mhz.value = 1
             await t
-            self.dut.clk_125mhz <= 0
+            self.dut.clk_125mhz.value = 0
             await t
-            self.dut.clk90_125mhz <= 0
+            self.dut.clk90_125mhz.value = 0
             await t
 
 
diff --git a/example/ML605/fpga_sgmii/tb/fpga_core/test_fpga_core.py b/example/ML605/fpga_sgmii/tb/fpga_core/test_fpga_core.py
index 1268b0025..6061778ed 100644
--- a/example/ML605/fpga_sgmii/tb/fpga_core/test_fpga_core.py
+++ b/example/ML605/fpga_sgmii/tb/fpga_core/test_fpga_core.py
@@ -72,14 +72,14 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk_125mhz)
 
-        self.dut.rst_125mhz <= 1
-        self.dut.phy_gmii_rst <= 1
+        self.dut.rst_125mhz.value = 1
+        self.dut.phy_gmii_rst.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk_125mhz)
 
-        self.dut.rst_125mhz <= 0
-        self.dut.phy_gmii_rst <= 0
+        self.dut.rst_125mhz.value = 0
+        self.dut.phy_gmii_rst.value = 0
 
 
 @cocotb.test()
diff --git a/example/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py b/example/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py
index 5f8296d10..4a25a06c1 100644
--- a/example/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py
+++ b/example/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py
@@ -85,28 +85,28 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 1
-        self.dut.sfp_1_rx_rst <= 1
-        self.dut.sfp_1_tx_rst <= 1
-        self.dut.sfp_2_rx_rst <= 1
-        self.dut.sfp_2_tx_rst <= 1
-        self.dut.sfp_3_rx_rst <= 1
-        self.dut.sfp_3_tx_rst <= 1
-        self.dut.sfp_4_rx_rst <= 1
-        self.dut.sfp_4_tx_rst <= 1
+        self.dut.rst.value = 1
+        self.dut.sfp_1_rx_rst.value = 1
+        self.dut.sfp_1_tx_rst.value = 1
+        self.dut.sfp_2_rx_rst.value = 1
+        self.dut.sfp_2_tx_rst.value = 1
+        self.dut.sfp_3_rx_rst.value = 1
+        self.dut.sfp_3_tx_rst.value = 1
+        self.dut.sfp_4_rx_rst.value = 1
+        self.dut.sfp_4_tx_rst.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
-        self.dut.sfp_1_rx_rst <= 0
-        self.dut.sfp_1_tx_rst <= 0
-        self.dut.sfp_2_rx_rst <= 0
-        self.dut.sfp_2_tx_rst <= 0
-        self.dut.sfp_3_rx_rst <= 0
-        self.dut.sfp_3_tx_rst <= 0
-        self.dut.sfp_4_rx_rst <= 0
-        self.dut.sfp_4_tx_rst <= 0
+        self.dut.rst.value = 0
+        self.dut.sfp_1_rx_rst.value = 0
+        self.dut.sfp_1_tx_rst.value = 0
+        self.dut.sfp_2_rx_rst.value = 0
+        self.dut.sfp_2_tx_rst.value = 0
+        self.dut.sfp_3_rx_rst.value = 0
+        self.dut.sfp_3_tx_rst.value = 0
+        self.dut.sfp_4_rx_rst.value = 0
+        self.dut.sfp_4_tx_rst.value = 0
 
 
 @cocotb.test()
diff --git a/example/NexysVideo/fpga/tb/fpga_core/test_fpga_core.py b/example/NexysVideo/fpga/tb/fpga_core/test_fpga_core.py
index e34c42ee6..042262ec0 100644
--- a/example/NexysVideo/fpga/tb/fpga_core/test_fpga_core.py
+++ b/example/NexysVideo/fpga/tb/fpga_core/test_fpga_core.py
@@ -70,23 +70,23 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
 
     async def _run_clk(self):
         t = Timer(2, 'ns')
         while True:
-            self.dut.clk <= 1
+            self.dut.clk.value = 1
             await t
-            self.dut.clk90 <= 1
+            self.dut.clk90.value = 1
             await t
-            self.dut.clk <= 0
+            self.dut.clk.value = 0
             await t
-            self.dut.clk90 <= 0
+            self.dut.clk90.value = 0
             await t
 
 
diff --git a/example/S10DX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py b/example/S10DX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py
index d1c4fc17d..72d03bd32 100644
--- a/example/S10DX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py
+++ b/example/S10DX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py
@@ -178,44 +178,44 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 1
-        self.dut.qsfp1_mac_1_rx_rst <= 1
-        self.dut.qsfp1_mac_1_tx_rst <= 1
-        self.dut.qsfp1_mac_2_rx_rst <= 1
-        self.dut.qsfp1_mac_2_tx_rst <= 1
-        self.dut.qsfp1_mac_3_rx_rst <= 1
-        self.dut.qsfp1_mac_3_tx_rst <= 1
-        self.dut.qsfp1_mac_4_rx_rst <= 1
-        self.dut.qsfp1_mac_4_tx_rst <= 1
-        self.dut.qsfp2_mac_1_rx_rst <= 1
-        self.dut.qsfp2_mac_1_tx_rst <= 1
-        self.dut.qsfp2_mac_2_rx_rst <= 1
-        self.dut.qsfp2_mac_2_tx_rst <= 1
-        self.dut.qsfp2_mac_3_rx_rst <= 1
-        self.dut.qsfp2_mac_3_tx_rst <= 1
-        self.dut.qsfp2_mac_4_rx_rst <= 1
-        self.dut.qsfp2_mac_4_tx_rst <= 1
+        self.dut.rst.value = 1
+        self.dut.qsfp1_mac_1_rx_rst.value = 1
+        self.dut.qsfp1_mac_1_tx_rst.value = 1
+        self.dut.qsfp1_mac_2_rx_rst.value = 1
+        self.dut.qsfp1_mac_2_tx_rst.value = 1
+        self.dut.qsfp1_mac_3_rx_rst.value = 1
+        self.dut.qsfp1_mac_3_tx_rst.value = 1
+        self.dut.qsfp1_mac_4_rx_rst.value = 1
+        self.dut.qsfp1_mac_4_tx_rst.value = 1
+        self.dut.qsfp2_mac_1_rx_rst.value = 1
+        self.dut.qsfp2_mac_1_tx_rst.value = 1
+        self.dut.qsfp2_mac_2_rx_rst.value = 1
+        self.dut.qsfp2_mac_2_tx_rst.value = 1
+        self.dut.qsfp2_mac_3_rx_rst.value = 1
+        self.dut.qsfp2_mac_3_tx_rst.value = 1
+        self.dut.qsfp2_mac_4_rx_rst.value = 1
+        self.dut.qsfp2_mac_4_tx_rst.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
-        self.dut.qsfp1_mac_1_rx_rst <= 0
-        self.dut.qsfp1_mac_1_tx_rst <= 0
-        self.dut.qsfp1_mac_2_rx_rst <= 0
-        self.dut.qsfp1_mac_2_tx_rst <= 0
-        self.dut.qsfp1_mac_3_rx_rst <= 0
-        self.dut.qsfp1_mac_3_tx_rst <= 0
-        self.dut.qsfp1_mac_4_rx_rst <= 0
-        self.dut.qsfp1_mac_4_tx_rst <= 0
-        self.dut.qsfp2_mac_1_rx_rst <= 0
-        self.dut.qsfp2_mac_1_tx_rst <= 0
-        self.dut.qsfp2_mac_2_rx_rst <= 0
-        self.dut.qsfp2_mac_2_tx_rst <= 0
-        self.dut.qsfp2_mac_3_rx_rst <= 0
-        self.dut.qsfp2_mac_3_tx_rst <= 0
-        self.dut.qsfp2_mac_4_rx_rst <= 0
-        self.dut.qsfp2_mac_4_tx_rst <= 0
+        self.dut.rst.value = 0
+        self.dut.qsfp1_mac_1_rx_rst.value = 0
+        self.dut.qsfp1_mac_1_tx_rst.value = 0
+        self.dut.qsfp1_mac_2_rx_rst.value = 0
+        self.dut.qsfp1_mac_2_tx_rst.value = 0
+        self.dut.qsfp1_mac_3_rx_rst.value = 0
+        self.dut.qsfp1_mac_3_tx_rst.value = 0
+        self.dut.qsfp1_mac_4_rx_rst.value = 0
+        self.dut.qsfp1_mac_4_tx_rst.value = 0
+        self.dut.qsfp2_mac_1_rx_rst.value = 0
+        self.dut.qsfp2_mac_1_tx_rst.value = 0
+        self.dut.qsfp2_mac_2_rx_rst.value = 0
+        self.dut.qsfp2_mac_2_tx_rst.value = 0
+        self.dut.qsfp2_mac_3_rx_rst.value = 0
+        self.dut.qsfp2_mac_3_tx_rst.value = 0
+        self.dut.qsfp2_mac_4_rx_rst.value = 0
+        self.dut.qsfp2_mac_4_tx_rst.value = 0
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
diff --git a/example/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py b/example/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py
index 4c378adc0..934d967e9 100644
--- a/example/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py
+++ b/example/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py
@@ -111,44 +111,44 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 1
-        self.dut.qsfp0_rx_rst_1 <= 1
-        self.dut.qsfp0_tx_rst_1 <= 1
-        self.dut.qsfp0_rx_rst_2 <= 1
-        self.dut.qsfp0_tx_rst_2 <= 1
-        self.dut.qsfp0_rx_rst_3 <= 1
-        self.dut.qsfp0_tx_rst_3 <= 1
-        self.dut.qsfp0_rx_rst_4 <= 1
-        self.dut.qsfp0_tx_rst_4 <= 1
-        self.dut.qsfp1_rx_rst_1 <= 1
-        self.dut.qsfp1_tx_rst_1 <= 1
-        self.dut.qsfp1_rx_rst_2 <= 1
-        self.dut.qsfp1_tx_rst_2 <= 1
-        self.dut.qsfp1_rx_rst_3 <= 1
-        self.dut.qsfp1_tx_rst_3 <= 1
-        self.dut.qsfp1_rx_rst_4 <= 1
-        self.dut.qsfp1_tx_rst_4 <= 1
+        self.dut.rst.value = 1
+        self.dut.qsfp0_rx_rst_1.value = 1
+        self.dut.qsfp0_tx_rst_1.value = 1
+        self.dut.qsfp0_rx_rst_2.value = 1
+        self.dut.qsfp0_tx_rst_2.value = 1
+        self.dut.qsfp0_rx_rst_3.value = 1
+        self.dut.qsfp0_tx_rst_3.value = 1
+        self.dut.qsfp0_rx_rst_4.value = 1
+        self.dut.qsfp0_tx_rst_4.value = 1
+        self.dut.qsfp1_rx_rst_1.value = 1
+        self.dut.qsfp1_tx_rst_1.value = 1
+        self.dut.qsfp1_rx_rst_2.value = 1
+        self.dut.qsfp1_tx_rst_2.value = 1
+        self.dut.qsfp1_rx_rst_3.value = 1
+        self.dut.qsfp1_tx_rst_3.value = 1
+        self.dut.qsfp1_rx_rst_4.value = 1
+        self.dut.qsfp1_tx_rst_4.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
-        self.dut.qsfp0_rx_rst_1 <= 0
-        self.dut.qsfp0_tx_rst_1 <= 0
-        self.dut.qsfp0_rx_rst_2 <= 0
-        self.dut.qsfp0_tx_rst_2 <= 0
-        self.dut.qsfp0_rx_rst_3 <= 0
-        self.dut.qsfp0_tx_rst_3 <= 0
-        self.dut.qsfp0_rx_rst_4 <= 0
-        self.dut.qsfp0_tx_rst_4 <= 0
-        self.dut.qsfp1_rx_rst_1 <= 0
-        self.dut.qsfp1_tx_rst_1 <= 0
-        self.dut.qsfp1_rx_rst_2 <= 0
-        self.dut.qsfp1_tx_rst_2 <= 0
-        self.dut.qsfp1_rx_rst_3 <= 0
-        self.dut.qsfp1_tx_rst_3 <= 0
-        self.dut.qsfp1_rx_rst_4 <= 0
-        self.dut.qsfp1_tx_rst_4 <= 0
+        self.dut.rst.value = 0
+        self.dut.qsfp0_rx_rst_1.value = 0
+        self.dut.qsfp0_tx_rst_1.value = 0
+        self.dut.qsfp0_rx_rst_2.value = 0
+        self.dut.qsfp0_tx_rst_2.value = 0
+        self.dut.qsfp0_rx_rst_3.value = 0
+        self.dut.qsfp0_tx_rst_3.value = 0
+        self.dut.qsfp0_rx_rst_4.value = 0
+        self.dut.qsfp0_tx_rst_4.value = 0
+        self.dut.qsfp1_rx_rst_1.value = 0
+        self.dut.qsfp1_tx_rst_1.value = 0
+        self.dut.qsfp1_rx_rst_2.value = 0
+        self.dut.qsfp1_tx_rst_2.value = 0
+        self.dut.qsfp1_rx_rst_3.value = 0
+        self.dut.qsfp1_tx_rst_3.value = 0
+        self.dut.qsfp1_rx_rst_4.value = 0
+        self.dut.qsfp1_tx_rst_4.value = 0
 
 
 @cocotb.test()
diff --git a/example/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py b/example/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py
index ee8ff7acb..4ec069372 100644
--- a/example/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py
+++ b/example/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py
@@ -103,30 +103,30 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 1
-        self.dut.phy_gmii_rst <= 1
-        self.dut.qsfp_rx_rst_1 <= 1
-        self.dut.qsfp_tx_rst_1 <= 1
-        self.dut.qsfp_rx_rst_2 <= 1
-        self.dut.qsfp_tx_rst_2 <= 1
-        self.dut.qsfp_rx_rst_3 <= 1
-        self.dut.qsfp_tx_rst_3 <= 1
-        self.dut.qsfp_rx_rst_4 <= 1
-        self.dut.qsfp_tx_rst_4 <= 1
+        self.dut.rst.value = 1
+        self.dut.phy_gmii_rst.value = 1
+        self.dut.qsfp_rx_rst_1.value = 1
+        self.dut.qsfp_tx_rst_1.value = 1
+        self.dut.qsfp_rx_rst_2.value = 1
+        self.dut.qsfp_tx_rst_2.value = 1
+        self.dut.qsfp_rx_rst_3.value = 1
+        self.dut.qsfp_tx_rst_3.value = 1
+        self.dut.qsfp_rx_rst_4.value = 1
+        self.dut.qsfp_tx_rst_4.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
-        self.dut.phy_gmii_rst <= 0
-        self.dut.qsfp_rx_rst_1 <= 0
-        self.dut.qsfp_tx_rst_1 <= 0
-        self.dut.qsfp_rx_rst_2 <= 0
-        self.dut.qsfp_tx_rst_2 <= 0
-        self.dut.qsfp_rx_rst_3 <= 0
-        self.dut.qsfp_tx_rst_3 <= 0
-        self.dut.qsfp_rx_rst_4 <= 0
-        self.dut.qsfp_tx_rst_4 <= 0
+        self.dut.rst.value = 0
+        self.dut.phy_gmii_rst.value = 0
+        self.dut.qsfp_rx_rst_1.value = 0
+        self.dut.qsfp_tx_rst_1.value = 0
+        self.dut.qsfp_rx_rst_2.value = 0
+        self.dut.qsfp_tx_rst_2.value = 0
+        self.dut.qsfp_rx_rst_3.value = 0
+        self.dut.qsfp_tx_rst_3.value = 0
+        self.dut.qsfp_rx_rst_4.value = 0
+        self.dut.qsfp_tx_rst_4.value = 0
 
 
 @cocotb.test()
@@ -200,7 +200,7 @@ async def run_test(dut):
 
     # insert tap
     await RisingEdge(dut.clk)
-    dut.sw <= 0x8
+    dut.sw.value = 0x8
     await RisingEdge(dut.clk)
 
     payload = bytes([x % 256 for x in range(256)])
@@ -243,7 +243,7 @@ async def run_test(dut):
 
     # insert tap
     await RisingEdge(dut.clk)
-    dut.sw <= 0xC
+    dut.sw.value = 0xC
     await RisingEdge(dut.clk)
 
     payload = bytes([x % 256 for x in range(256)])
diff --git a/example/VCU108/fpga_1g/tb/fpga_core/test_fpga_core.py b/example/VCU108/fpga_1g/tb/fpga_core/test_fpga_core.py
index fd8946828..07c66f794 100644
--- a/example/VCU108/fpga_1g/tb/fpga_core/test_fpga_core.py
+++ b/example/VCU108/fpga_1g/tb/fpga_core/test_fpga_core.py
@@ -72,14 +72,14 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 1
-        self.dut.phy_gmii_rst <= 1
+        self.dut.rst.value = 1
+        self.dut.phy_gmii_rst.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
-        self.dut.phy_gmii_rst <= 0
+        self.dut.rst.value = 0
+        self.dut.phy_gmii_rst.value = 0
 
 
 @cocotb.test()
diff --git a/example/VCU118/fpga_10g/tb/fpga_core/test_fpga_core.py b/example/VCU118/fpga_10g/tb/fpga_core/test_fpga_core.py
index 656c80ae4..2ada7550b 100644
--- a/example/VCU118/fpga_10g/tb/fpga_core/test_fpga_core.py
+++ b/example/VCU118/fpga_10g/tb/fpga_core/test_fpga_core.py
@@ -131,46 +131,46 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 1
-        self.dut.phy_gmii_rst <= 1
-        self.dut.qsfp1_rx_rst_1 <= 1
-        self.dut.qsfp1_tx_rst_1 <= 1
-        self.dut.qsfp1_rx_rst_2 <= 1
-        self.dut.qsfp1_tx_rst_2 <= 1
-        self.dut.qsfp1_rx_rst_3 <= 1
-        self.dut.qsfp1_tx_rst_3 <= 1
-        self.dut.qsfp1_rx_rst_4 <= 1
-        self.dut.qsfp1_tx_rst_4 <= 1
-        self.dut.qsfp2_rx_rst_1 <= 1
-        self.dut.qsfp2_tx_rst_1 <= 1
-        self.dut.qsfp2_rx_rst_2 <= 1
-        self.dut.qsfp2_tx_rst_2 <= 1
-        self.dut.qsfp2_rx_rst_3 <= 1
-        self.dut.qsfp2_tx_rst_3 <= 1
-        self.dut.qsfp2_rx_rst_4 <= 1
-        self.dut.qsfp2_tx_rst_4 <= 1
+        self.dut.rst.value = 1
+        self.dut.phy_gmii_rst.value = 1
+        self.dut.qsfp1_rx_rst_1.value = 1
+        self.dut.qsfp1_tx_rst_1.value = 1
+        self.dut.qsfp1_rx_rst_2.value = 1
+        self.dut.qsfp1_tx_rst_2.value = 1
+        self.dut.qsfp1_rx_rst_3.value = 1
+        self.dut.qsfp1_tx_rst_3.value = 1
+        self.dut.qsfp1_rx_rst_4.value = 1
+        self.dut.qsfp1_tx_rst_4.value = 1
+        self.dut.qsfp2_rx_rst_1.value = 1
+        self.dut.qsfp2_tx_rst_1.value = 1
+        self.dut.qsfp2_rx_rst_2.value = 1
+        self.dut.qsfp2_tx_rst_2.value = 1
+        self.dut.qsfp2_rx_rst_3.value = 1
+        self.dut.qsfp2_tx_rst_3.value = 1
+        self.dut.qsfp2_rx_rst_4.value = 1
+        self.dut.qsfp2_tx_rst_4.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
-        self.dut.phy_gmii_rst <= 0
-        self.dut.qsfp1_rx_rst_1 <= 0
-        self.dut.qsfp1_tx_rst_1 <= 0
-        self.dut.qsfp1_rx_rst_2 <= 0
-        self.dut.qsfp1_tx_rst_2 <= 0
-        self.dut.qsfp1_rx_rst_3 <= 0
-        self.dut.qsfp1_tx_rst_3 <= 0
-        self.dut.qsfp1_rx_rst_4 <= 0
-        self.dut.qsfp1_tx_rst_4 <= 0
-        self.dut.qsfp2_rx_rst_1 <= 0
-        self.dut.qsfp2_tx_rst_1 <= 0
-        self.dut.qsfp2_rx_rst_2 <= 0
-        self.dut.qsfp2_tx_rst_2 <= 0
-        self.dut.qsfp2_rx_rst_3 <= 0
-        self.dut.qsfp2_tx_rst_3 <= 0
-        self.dut.qsfp2_rx_rst_4 <= 0
-        self.dut.qsfp2_tx_rst_4 <= 0
+        self.dut.rst.value = 0
+        self.dut.phy_gmii_rst.value = 0
+        self.dut.qsfp1_rx_rst_1.value = 0
+        self.dut.qsfp1_tx_rst_1.value = 0
+        self.dut.qsfp1_rx_rst_2.value = 0
+        self.dut.qsfp1_tx_rst_2.value = 0
+        self.dut.qsfp1_rx_rst_3.value = 0
+        self.dut.qsfp1_tx_rst_3.value = 0
+        self.dut.qsfp1_rx_rst_4.value = 0
+        self.dut.qsfp1_tx_rst_4.value = 0
+        self.dut.qsfp2_rx_rst_1.value = 0
+        self.dut.qsfp2_tx_rst_1.value = 0
+        self.dut.qsfp2_rx_rst_2.value = 0
+        self.dut.qsfp2_tx_rst_2.value = 0
+        self.dut.qsfp2_rx_rst_3.value = 0
+        self.dut.qsfp2_tx_rst_3.value = 0
+        self.dut.qsfp2_rx_rst_4.value = 0
+        self.dut.qsfp2_tx_rst_4.value = 0
 
 
 @cocotb.test()
@@ -244,7 +244,7 @@ async def run_test(dut):
 
     # insert tap
     await RisingEdge(dut.clk)
-    dut.sw <= 0x8
+    dut.sw.value = 0x8
     await RisingEdge(dut.clk)
 
     payload = bytes([x % 256 for x in range(256)])
@@ -287,7 +287,7 @@ async def run_test(dut):
 
     # insert tap
     await RisingEdge(dut.clk)
-    dut.sw <= 0xC
+    dut.sw.value = 0xC
     await RisingEdge(dut.clk)
 
     payload = bytes([x % 256 for x in range(256)])
diff --git a/example/VCU118/fpga_1g/tb/fpga_core/test_fpga_core.py b/example/VCU118/fpga_1g/tb/fpga_core/test_fpga_core.py
index fd8946828..07c66f794 100644
--- a/example/VCU118/fpga_1g/tb/fpga_core/test_fpga_core.py
+++ b/example/VCU118/fpga_1g/tb/fpga_core/test_fpga_core.py
@@ -72,14 +72,14 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 1
-        self.dut.phy_gmii_rst <= 1
+        self.dut.rst.value = 1
+        self.dut.phy_gmii_rst.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
-        self.dut.phy_gmii_rst <= 0
+        self.dut.rst.value = 0
+        self.dut.phy_gmii_rst.value = 0
 
 
 @cocotb.test()
diff --git a/example/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py b/example/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py
index f5028aed3..0b751835f 100644
--- a/example/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py
+++ b/example/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -131,46 +131,46 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 1
-        self.dut.phy_gmii_rst <= 1
-        self.dut.qsfp1_rx_rst_1 <= 1
-        self.dut.qsfp1_tx_rst_1 <= 1
-        self.dut.qsfp1_rx_rst_2 <= 1
-        self.dut.qsfp1_tx_rst_2 <= 1
-        self.dut.qsfp1_rx_rst_3 <= 1
-        self.dut.qsfp1_tx_rst_3 <= 1
-        self.dut.qsfp1_rx_rst_4 <= 1
-        self.dut.qsfp1_tx_rst_4 <= 1
-        self.dut.qsfp2_rx_rst_1 <= 1
-        self.dut.qsfp2_tx_rst_1 <= 1
-        self.dut.qsfp2_rx_rst_2 <= 1
-        self.dut.qsfp2_tx_rst_2 <= 1
-        self.dut.qsfp2_rx_rst_3 <= 1
-        self.dut.qsfp2_tx_rst_3 <= 1
-        self.dut.qsfp2_rx_rst_4 <= 1
-        self.dut.qsfp2_tx_rst_4 <= 1
+        self.dut.rst.value = 1
+        self.dut.phy_gmii_rst.value = 1
+        self.dut.qsfp1_rx_rst_1.value = 1
+        self.dut.qsfp1_tx_rst_1.value = 1
+        self.dut.qsfp1_rx_rst_2.value = 1
+        self.dut.qsfp1_tx_rst_2.value = 1
+        self.dut.qsfp1_rx_rst_3.value = 1
+        self.dut.qsfp1_tx_rst_3.value = 1
+        self.dut.qsfp1_rx_rst_4.value = 1
+        self.dut.qsfp1_tx_rst_4.value = 1
+        self.dut.qsfp2_rx_rst_1.value = 1
+        self.dut.qsfp2_tx_rst_1.value = 1
+        self.dut.qsfp2_rx_rst_2.value = 1
+        self.dut.qsfp2_tx_rst_2.value = 1
+        self.dut.qsfp2_rx_rst_3.value = 1
+        self.dut.qsfp2_tx_rst_3.value = 1
+        self.dut.qsfp2_rx_rst_4.value = 1
+        self.dut.qsfp2_tx_rst_4.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
-        self.dut.phy_gmii_rst <= 0
-        self.dut.qsfp1_rx_rst_1 <= 0
-        self.dut.qsfp1_tx_rst_1 <= 0
-        self.dut.qsfp1_rx_rst_2 <= 0
-        self.dut.qsfp1_tx_rst_2 <= 0
-        self.dut.qsfp1_rx_rst_3 <= 0
-        self.dut.qsfp1_tx_rst_3 <= 0
-        self.dut.qsfp1_rx_rst_4 <= 0
-        self.dut.qsfp1_tx_rst_4 <= 0
-        self.dut.qsfp2_rx_rst_1 <= 0
-        self.dut.qsfp2_tx_rst_1 <= 0
-        self.dut.qsfp2_rx_rst_2 <= 0
-        self.dut.qsfp2_tx_rst_2 <= 0
-        self.dut.qsfp2_rx_rst_3 <= 0
-        self.dut.qsfp2_tx_rst_3 <= 0
-        self.dut.qsfp2_rx_rst_4 <= 0
-        self.dut.qsfp2_tx_rst_4 <= 0
+        self.dut.rst.value = 0
+        self.dut.phy_gmii_rst.value = 0
+        self.dut.qsfp1_rx_rst_1.value = 0
+        self.dut.qsfp1_tx_rst_1.value = 0
+        self.dut.qsfp1_rx_rst_2.value = 0
+        self.dut.qsfp1_tx_rst_2.value = 0
+        self.dut.qsfp1_rx_rst_3.value = 0
+        self.dut.qsfp1_tx_rst_3.value = 0
+        self.dut.qsfp1_rx_rst_4.value = 0
+        self.dut.qsfp1_tx_rst_4.value = 0
+        self.dut.qsfp2_rx_rst_1.value = 0
+        self.dut.qsfp2_tx_rst_1.value = 0
+        self.dut.qsfp2_rx_rst_2.value = 0
+        self.dut.qsfp2_tx_rst_2.value = 0
+        self.dut.qsfp2_rx_rst_3.value = 0
+        self.dut.qsfp2_tx_rst_3.value = 0
+        self.dut.qsfp2_rx_rst_4.value = 0
+        self.dut.qsfp2_tx_rst_4.value = 0
 
 
 @cocotb.test()
@@ -244,7 +244,7 @@ async def run_test(dut):
 
     # insert tap
     await RisingEdge(dut.clk)
-    dut.sw <= 0x8
+    dut.sw.value = 0x8
     await RisingEdge(dut.clk)
 
     payload = bytes([x % 256 for x in range(256)])
@@ -287,7 +287,7 @@ async def run_test(dut):
 
     # insert tap
     await RisingEdge(dut.clk)
-    dut.sw <= 0xC
+    dut.sw.value = 0xC
     await RisingEdge(dut.clk)
 
     payload = bytes([x % 256 for x in range(256)])
diff --git a/example/VCU1525/fpga_10g/tb/fpga_core/test_fpga_core.py b/example/VCU1525/fpga_10g/tb/fpga_core/test_fpga_core.py
index 37a47626b..6f609015c 100644
--- a/example/VCU1525/fpga_10g/tb/fpga_core/test_fpga_core.py
+++ b/example/VCU1525/fpga_10g/tb/fpga_core/test_fpga_core.py
@@ -113,44 +113,44 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 1
-        self.dut.qsfp0_rx_rst_1 <= 1
-        self.dut.qsfp0_tx_rst_1 <= 1
-        self.dut.qsfp0_rx_rst_2 <= 1
-        self.dut.qsfp0_tx_rst_2 <= 1
-        self.dut.qsfp0_rx_rst_3 <= 1
-        self.dut.qsfp0_tx_rst_3 <= 1
-        self.dut.qsfp0_rx_rst_4 <= 1
-        self.dut.qsfp0_tx_rst_4 <= 1
-        self.dut.qsfp1_rx_rst_1 <= 1
-        self.dut.qsfp1_tx_rst_1 <= 1
-        self.dut.qsfp1_rx_rst_2 <= 1
-        self.dut.qsfp1_tx_rst_2 <= 1
-        self.dut.qsfp1_rx_rst_3 <= 1
-        self.dut.qsfp1_tx_rst_3 <= 1
-        self.dut.qsfp1_rx_rst_4 <= 1
-        self.dut.qsfp1_tx_rst_4 <= 1
+        self.dut.rst.value = 1
+        self.dut.qsfp0_rx_rst_1.value = 1
+        self.dut.qsfp0_tx_rst_1.value = 1
+        self.dut.qsfp0_rx_rst_2.value = 1
+        self.dut.qsfp0_tx_rst_2.value = 1
+        self.dut.qsfp0_rx_rst_3.value = 1
+        self.dut.qsfp0_tx_rst_3.value = 1
+        self.dut.qsfp0_rx_rst_4.value = 1
+        self.dut.qsfp0_tx_rst_4.value = 1
+        self.dut.qsfp1_rx_rst_1.value = 1
+        self.dut.qsfp1_tx_rst_1.value = 1
+        self.dut.qsfp1_rx_rst_2.value = 1
+        self.dut.qsfp1_tx_rst_2.value = 1
+        self.dut.qsfp1_rx_rst_3.value = 1
+        self.dut.qsfp1_tx_rst_3.value = 1
+        self.dut.qsfp1_rx_rst_4.value = 1
+        self.dut.qsfp1_tx_rst_4.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
-        self.dut.qsfp0_rx_rst_1 <= 0
-        self.dut.qsfp0_tx_rst_1 <= 0
-        self.dut.qsfp0_rx_rst_2 <= 0
-        self.dut.qsfp0_tx_rst_2 <= 0
-        self.dut.qsfp0_rx_rst_3 <= 0
-        self.dut.qsfp0_tx_rst_3 <= 0
-        self.dut.qsfp0_rx_rst_4 <= 0
-        self.dut.qsfp0_tx_rst_4 <= 0
-        self.dut.qsfp1_rx_rst_1 <= 0
-        self.dut.qsfp1_tx_rst_1 <= 0
-        self.dut.qsfp1_rx_rst_2 <= 0
-        self.dut.qsfp1_tx_rst_2 <= 0
-        self.dut.qsfp1_rx_rst_3 <= 0
-        self.dut.qsfp1_tx_rst_3 <= 0
-        self.dut.qsfp1_rx_rst_4 <= 0
-        self.dut.qsfp1_tx_rst_4 <= 0
+        self.dut.rst.value = 0
+        self.dut.qsfp0_rx_rst_1.value = 0
+        self.dut.qsfp0_tx_rst_1.value = 0
+        self.dut.qsfp0_rx_rst_2.value = 0
+        self.dut.qsfp0_tx_rst_2.value = 0
+        self.dut.qsfp0_rx_rst_3.value = 0
+        self.dut.qsfp0_tx_rst_3.value = 0
+        self.dut.qsfp0_rx_rst_4.value = 0
+        self.dut.qsfp0_tx_rst_4.value = 0
+        self.dut.qsfp1_rx_rst_1.value = 0
+        self.dut.qsfp1_tx_rst_1.value = 0
+        self.dut.qsfp1_rx_rst_2.value = 0
+        self.dut.qsfp1_tx_rst_2.value = 0
+        self.dut.qsfp1_rx_rst_3.value = 0
+        self.dut.qsfp1_tx_rst_3.value = 0
+        self.dut.qsfp1_rx_rst_4.value = 0
+        self.dut.qsfp1_tx_rst_4.value = 0
 
 
 @cocotb.test()
diff --git a/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py b/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py
index 5e47a3c22..78aca5d74 100644
--- a/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py
+++ b/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py
@@ -92,28 +92,28 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 1
-        self.dut.sfp0_rx_rst <= 1
-        self.dut.sfp0_tx_rst <= 1
-        self.dut.sfp1_rx_rst <= 1
-        self.dut.sfp1_tx_rst <= 1
-        self.dut.sfp2_rx_rst <= 1
-        self.dut.sfp2_tx_rst <= 1
-        self.dut.sfp3_rx_rst <= 1
-        self.dut.sfp3_tx_rst <= 1
+        self.dut.rst.value = 1
+        self.dut.sfp0_rx_rst.value = 1
+        self.dut.sfp0_tx_rst.value = 1
+        self.dut.sfp1_rx_rst.value = 1
+        self.dut.sfp1_tx_rst.value = 1
+        self.dut.sfp2_rx_rst.value = 1
+        self.dut.sfp2_tx_rst.value = 1
+        self.dut.sfp3_rx_rst.value = 1
+        self.dut.sfp3_tx_rst.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
-        self.dut.sfp0_rx_rst <= 0
-        self.dut.sfp0_tx_rst <= 0
-        self.dut.sfp1_rx_rst <= 0
-        self.dut.sfp1_tx_rst <= 0
-        self.dut.sfp2_rx_rst <= 0
-        self.dut.sfp2_tx_rst <= 0
-        self.dut.sfp3_rx_rst <= 0
-        self.dut.sfp3_tx_rst <= 0
+        self.dut.rst.value = 0
+        self.dut.sfp0_rx_rst.value = 0
+        self.dut.sfp0_tx_rst.value = 0
+        self.dut.sfp1_rx_rst.value = 0
+        self.dut.sfp1_tx_rst.value = 0
+        self.dut.sfp2_rx_rst.value = 0
+        self.dut.sfp2_tx_rst.value = 0
+        self.dut.sfp3_rx_rst.value = 0
+        self.dut.sfp3_tx_rst.value = 0
 
 
 @cocotb.test()
diff --git a/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py b/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py
index 7de8d6e9f..14a213b12 100644
--- a/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py
+++ b/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py
@@ -78,20 +78,20 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 1
-        self.dut.sfp0_rx_rst <= 1
-        self.dut.sfp0_tx_rst <= 1
-        self.dut.sfp1_rx_rst <= 1
-        self.dut.sfp1_tx_rst <= 1
+        self.dut.rst.value = 1
+        self.dut.sfp0_rx_rst.value = 1
+        self.dut.sfp0_tx_rst.value = 1
+        self.dut.sfp1_rx_rst.value = 1
+        self.dut.sfp1_tx_rst.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
-        self.dut.sfp0_rx_rst <= 0
-        self.dut.sfp0_tx_rst <= 0
-        self.dut.sfp1_rx_rst <= 0
-        self.dut.sfp1_tx_rst <= 0
+        self.dut.rst.value = 0
+        self.dut.sfp0_rx_rst.value = 0
+        self.dut.sfp0_tx_rst.value = 0
+        self.dut.sfp1_rx_rst.value = 0
+        self.dut.sfp1_tx_rst.value = 0
 
 
 @cocotb.test()
diff --git a/example/fb2CG/fpga_10g/tb/fpga_core/test_fpga_core.py b/example/fb2CG/fpga_10g/tb/fpga_core/test_fpga_core.py
index 181fdbf0d..9dcbf1323 100644
--- a/example/fb2CG/fpga_10g/tb/fpga_core/test_fpga_core.py
+++ b/example/fb2CG/fpga_10g/tb/fpga_core/test_fpga_core.py
@@ -111,44 +111,44 @@ class TB:
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 1
-        self.dut.qsfp_0_rx_rst_0 <= 1
-        self.dut.qsfp_0_tx_rst_0 <= 1
-        self.dut.qsfp_0_rx_rst_1 <= 1
-        self.dut.qsfp_0_tx_rst_1 <= 1
-        self.dut.qsfp_0_rx_rst_2 <= 1
-        self.dut.qsfp_0_tx_rst_2 <= 1
-        self.dut.qsfp_0_rx_rst_3 <= 1
-        self.dut.qsfp_0_tx_rst_3 <= 1
-        self.dut.qsfp_1_rx_rst_0 <= 1
-        self.dut.qsfp_1_tx_rst_0 <= 1
-        self.dut.qsfp_1_rx_rst_1 <= 1
-        self.dut.qsfp_1_tx_rst_1 <= 1
-        self.dut.qsfp_1_rx_rst_2 <= 1
-        self.dut.qsfp_1_tx_rst_2 <= 1
-        self.dut.qsfp_1_rx_rst_3 <= 1
-        self.dut.qsfp_1_tx_rst_3 <= 1
+        self.dut.rst.value = 1
+        self.dut.qsfp_0_rx_rst_0.value = 1
+        self.dut.qsfp_0_tx_rst_0.value = 1
+        self.dut.qsfp_0_rx_rst_1.value = 1
+        self.dut.qsfp_0_tx_rst_1.value = 1
+        self.dut.qsfp_0_rx_rst_2.value = 1
+        self.dut.qsfp_0_tx_rst_2.value = 1
+        self.dut.qsfp_0_rx_rst_3.value = 1
+        self.dut.qsfp_0_tx_rst_3.value = 1
+        self.dut.qsfp_1_rx_rst_0.value = 1
+        self.dut.qsfp_1_tx_rst_0.value = 1
+        self.dut.qsfp_1_rx_rst_1.value = 1
+        self.dut.qsfp_1_tx_rst_1.value = 1
+        self.dut.qsfp_1_rx_rst_2.value = 1
+        self.dut.qsfp_1_tx_rst_2.value = 1
+        self.dut.qsfp_1_rx_rst_3.value = 1
+        self.dut.qsfp_1_tx_rst_3.value = 1
 
         for k in range(10):
             await RisingEdge(self.dut.clk)
 
-        self.dut.rst <= 0
-        self.dut.qsfp_0_rx_rst_0 <= 0
-        self.dut.qsfp_0_tx_rst_0 <= 0
-        self.dut.qsfp_0_rx_rst_1 <= 0
-        self.dut.qsfp_0_tx_rst_1 <= 0
-        self.dut.qsfp_0_rx_rst_2 <= 0
-        self.dut.qsfp_0_tx_rst_2 <= 0
-        self.dut.qsfp_0_rx_rst_3 <= 0
-        self.dut.qsfp_0_tx_rst_3 <= 0
-        self.dut.qsfp_1_rx_rst_0 <= 0
-        self.dut.qsfp_1_tx_rst_0 <= 0
-        self.dut.qsfp_1_rx_rst_1 <= 0
-        self.dut.qsfp_1_tx_rst_1 <= 0
-        self.dut.qsfp_1_rx_rst_2 <= 0
-        self.dut.qsfp_1_tx_rst_2 <= 0
-        self.dut.qsfp_1_rx_rst_3 <= 0
-        self.dut.qsfp_1_tx_rst_3 <= 0
+        self.dut.rst.value = 0
+        self.dut.qsfp_0_rx_rst_0.value = 0
+        self.dut.qsfp_0_tx_rst_0.value = 0
+        self.dut.qsfp_0_rx_rst_1.value = 0
+        self.dut.qsfp_0_tx_rst_1.value = 0
+        self.dut.qsfp_0_rx_rst_2.value = 0
+        self.dut.qsfp_0_tx_rst_2.value = 0
+        self.dut.qsfp_0_rx_rst_3.value = 0
+        self.dut.qsfp_0_tx_rst_3.value = 0
+        self.dut.qsfp_1_rx_rst_0.value = 0
+        self.dut.qsfp_1_tx_rst_0.value = 0
+        self.dut.qsfp_1_rx_rst_1.value = 0
+        self.dut.qsfp_1_tx_rst_1.value = 0
+        self.dut.qsfp_1_rx_rst_2.value = 0
+        self.dut.qsfp_1_tx_rst_2.value = 0
+        self.dut.qsfp_1_rx_rst_3.value = 0
+        self.dut.qsfp_1_tx_rst_3.value = 0
 
 
 @cocotb.test()