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fpga/mqnic/ZCU106/fpga_zynqmp: Rewrite zynq PS TCL script, rework PS clock settings, switch to 300 MHz PL clock

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-04-11 12:25:51 -07:00
parent e9b62594c0
commit 57905a5ef9
8 changed files with 352 additions and 1164 deletions
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2
fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile
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@ -106,7 +106,7 @@ XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
# IP
IP_TCL_FILES = ip/bd_zynq.tcl
IP_TCL_FILES = ip/zynq_ps.tcl
IP_TCL_FILES += ip/eth_xcvr_gth.tcl
# Configuration

29
fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl
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@ -143,11 +143,12 @@ dict set params APP_AXIS_IF_ENABLE "1"
dict set params APP_STAT_ENABLE "1"
# AXI DMA interface configuration
open_bd_design [get_files bd_zynq.bd]
set s_axi_mm [get_bd_intf_ports -of_objects [get_bd_designs bd_zynq] -filter {NAME == s_axi_mm}]
dict set params AXI_DATA_WIDTH [get_property CONFIG.DATA_WIDTH $s_axi_mm]
dict set params AXI_ADDR_WIDTH [get_property CONFIG.ADDR_WIDTH $s_axi_mm]
dict set params AXI_ID_WIDTH [get_property CONFIG.ID_WIDTH $s_axi_mm]
open_bd_design [get_files zynq_ps.bd]
set s_axi_dma [get_bd_intf_ports s_axi_dma]
dict set params AXI_DATA_WIDTH [get_property CONFIG.DATA_WIDTH $s_axi_dma]
# dict set params AXI_ADDR_WIDTH [get_property CONFIG.ADDR_WIDTH $s_axi_dma]
dict set params AXI_ADDR_WIDTH 64
dict set params AXI_ID_WIDTH [get_property CONFIG.ID_WIDTH $s_axi_dma]
# DMA interface configuration
dict set params DMA_LEN_WIDTH "16"
@ -157,23 +158,23 @@ dict set params RAM_PIPELINE "2"
# NOTE: Querying the BD top-level interface port (or even the ZynqMP's interface
# pin) yields 256 for the maximum burst length, instead of 16, which is
# the actually supported length (due to ZynqMP using AXI3 internally).
#dict set params AXI_DMA_MAX_BURST_LEN [get_property CONFIG.MAX_BURST_LENGTH $s_axi_mm]
#dict set params AXI_DMA_MAX_BURST_LEN [get_property CONFIG.MAX_BURST_LENGTH $s_axi_dma]
dict set params AXI_DMA_MAX_BURST_LEN "16"
# AXI lite interface configuration (control)
set m_axil_0 [get_bd_intf_pins /axi_protocol_convert_0/M_AXI]
dict set params AXIL_CTRL_DATA_WIDTH [get_property CONFIG.DATA_WIDTH $m_axil_0]
dict set params AXIL_CTRL_ADDR_WIDTH [get_property CONFIG.ADDR_WIDTH $m_axil_0]
set m_axil_ctrl [get_bd_intf_ports m_axil_ctrl]
dict set params AXIL_CTRL_DATA_WIDTH [get_property CONFIG.DATA_WIDTH $m_axil_ctrl]
dict set params AXIL_CTRL_ADDR_WIDTH 24
# AXI lite interface configuration (application control)
set m_axil_1 [get_bd_intf_pins /axi_protocol_convert_1/M_AXI]
dict set params AXIL_APP_CTRL_DATA_WIDTH [get_property CONFIG.DATA_WIDTH $m_axil_1]
dict set params AXIL_APP_CTRL_ADDR_WIDTH [get_property CONFIG.ADDR_WIDTH $m_axil_1]
set m_axil_app_ctrl [get_bd_intf_ports m_axil_app_ctrl]
dict set params AXIL_APP_CTRL_DATA_WIDTH [get_property CONFIG.DATA_WIDTH $m_axil_app_ctrl]
dict set params AXIL_APP_CTRL_ADDR_WIDTH 24
# Interrupt configuration
set irq [get_bd_ports -of_objects [get_bd_designs bd_zynq] -filter {NAME == irq}]
set irq [get_bd_ports pl_ps_irq0]
dict set params IRQ_COUNT [get_property CONFIG.PortWidth $irq]
close_bd_design [get_bd_designs bd_zynq]
close_bd_design [get_bd_designs zynq_ps]
dict set params IRQ_STRETCH "10"
# Ethernet interface configuration

1025
fpga/mqnic/ZCU106/fpga_zynqmp/ip/bd_zynq.tcl
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212
fpga/mqnic/ZCU106/fpga_zynqmp/ip/zynq_ps.tcl Normal file
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@ -0,0 +1,212 @@
# Copyright 2022, The Regents of the University of California.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
# OF SUCH DAMAGE.
#
# The views and conclusions contained in the software and documentation are those
# of the authors and should not be interpreted as representing official policies,
# either expressed or implied, of The Regents of the University of California.
# create block design
create_bd_design "zynq_ps"
# Create blocks
# Zynq PS
set zynq_ultra_ps [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e zynq_ultra_ps ]
set_property -dict [list \
CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS33} \
CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN 1 \
CONFIG.PSU__DDRC__COMPONENTS {UDIMM} \
CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \
CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \
CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \
CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__PMU__GPI0__ENABLE {1} \
CONFIG.PSU__PMU__GPI1__ENABLE {0} \
CONFIG.PSU__PMU__GPI2__ENABLE {0} \
CONFIG.PSU__PMU__GPI3__ENABLE {0} \
CONFIG.PSU__PMU__GPI4__ENABLE {0} \
CONFIG.PSU__PMU__GPI5__ENABLE {0} \
CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel} \
CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \
CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \
CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 14 .. 15} \
CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \
CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \
CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \
CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \
CONFIG.PSU__SD1__GRP_POW__ENABLE {1} \
CONFIG.PSU__SD1__GRP_WP__ENABLE {1} \
CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \
CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__USE__M_AXI_GP0 {1} \
CONFIG.PSU__MAXIGP0__DATA_WIDTH {32} \
CONFIG.PSU__USE__M_AXI_GP1 {0} \
CONFIG.PSU__USE__M_AXI_GP2 {0} \
CONFIG.PSU__USE__S_AXI_GP0 {1} \
CONFIG.PSU__USE__IRQ0 {1} \
CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {667} \
CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {667} \
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {DPLL} \
CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {DPLL} \
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {DPLL} \
CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {DPLL} \
CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {DPLL} \
CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {300} \
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
] $zynq_ultra_ps
# control AXI interconnect
set axi_interconnect_ctrl [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_interconnect_ctrl ]
# reset
set proc_sys_reset [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset proc_sys_reset ]
# Create connections
# Clock
set pl_clk0 [get_bd_pins $zynq_ultra_ps/pl_clk0]
make_bd_pins_external $pl_clk0
set_property name pl_clk0 [get_bd_ports -of_objects [get_bd_nets -of_objects $pl_clk0]]
set pl_clk0_port [get_bd_ports -of_objects [get_bd_nets -of_objects $pl_clk0]]
connect_bd_net $pl_clk0 [get_bd_pins $zynq_ultra_ps/maxihpm0_fpd_aclk]
connect_bd_net $pl_clk0 [get_bd_pins $zynq_ultra_ps/saxihpc0_fpd_aclk]
connect_bd_net $pl_clk0 [get_bd_pins $proc_sys_reset/slowest_sync_clk]
connect_bd_net $pl_clk0 [get_bd_pins $axi_interconnect_ctrl/ACLK]
connect_bd_net $pl_clk0 [get_bd_pins $axi_interconnect_ctrl/S00_ACLK]
connect_bd_net $pl_clk0 [get_bd_pins $axi_interconnect_ctrl/M00_ACLK]
connect_bd_net $pl_clk0 [get_bd_pins $axi_interconnect_ctrl/M01_ACLK]
set pl_clk0_busif [list]
# Reset
set pl_resetn0 [get_bd_pins $zynq_ultra_ps/pl_resetn0]
connect_bd_net $pl_resetn0 [get_bd_pins $proc_sys_reset/ext_reset_in]
set pl_reset [get_bd_pins $proc_sys_reset/peripheral_reset]
make_bd_pins_external $pl_reset
set_property name pl_reset [get_bd_ports -of_objects [get_bd_nets -of_objects $pl_reset]]
set interconnect_aresetn [get_bd_pins $proc_sys_reset/interconnect_aresetn]
connect_bd_net $interconnect_aresetn [get_bd_pins $axi_interconnect_ctrl/ARESETN]
connect_bd_net $interconnect_aresetn [get_bd_pins $axi_interconnect_ctrl/S00_ARESETN]
connect_bd_net $interconnect_aresetn [get_bd_pins $axi_interconnect_ctrl/M00_ARESETN]
connect_bd_net $interconnect_aresetn [get_bd_pins $axi_interconnect_ctrl/M01_ARESETN]
# MMIO
connect_bd_intf_net [get_bd_intf_pins $zynq_ultra_ps/M_AXI_HPM0_FPD] [get_bd_intf_pins $axi_interconnect_ctrl/S00_AXI]
# Control interface
set m_axil_ctrl_pin [get_bd_intf_pins $axi_interconnect_ctrl/M00_AXI]
make_bd_intf_pins_external $m_axil_ctrl_pin
set_property name m_axil_ctrl [get_bd_intf_ports -of_objects [get_bd_intf_nets -of_objects $m_axil_ctrl_pin]]
set m_axil_ctrl_port [get_bd_intf_ports -of_objects [get_bd_intf_nets -of_objects $m_axil_ctrl_pin]]
set_property -dict [list \
CONFIG.PROTOCOL AXI4LITE \
CONFIG.DATA_WIDTH 32 \
CONFIG.ADDR_WIDTH 24 \
] $m_axil_ctrl_port
lappend pl_clk0_busif $m_axil_ctrl_port
# Application control interface
set m_axil_app_ctrl_pin [get_bd_intf_pins $axi_interconnect_ctrl/M01_AXI]
make_bd_intf_pins_external $m_axil_app_ctrl_pin
set_property name m_axil_app_ctrl [get_bd_intf_ports -of_objects [get_bd_intf_nets -of_objects $m_axil_app_ctrl_pin]]
set m_axil_app_ctrl_port [get_bd_intf_ports -of_objects [get_bd_intf_nets -of_objects $m_axil_app_ctrl_pin]]
set_property -dict [list \
CONFIG.PROTOCOL AXI4LITE \
CONFIG.DATA_WIDTH 32 \
CONFIG.ADDR_WIDTH 24 \
] $m_axil_app_ctrl_port
lappend pl_clk0_busif $m_axil_app_ctrl_port
# DMA interface
set s_axi_dma_pin [get_bd_intf_pins $zynq_ultra_ps/S_AXI_HPC0_FPD]
make_bd_intf_pins_external $s_axi_dma_pin
set_property name s_axi_dma [get_bd_intf_ports -of_objects [get_bd_intf_nets -of_objects $s_axi_dma_pin]]
set s_axi_dma_port [get_bd_intf_ports -of_objects [get_bd_intf_nets -of_objects $s_axi_dma_pin]]
lappend pl_clk0_busif $s_axi_dma_port
# IRQ
set pl_ps_irq0 [get_bd_pins $zynq_ultra_ps/pl_ps_irq0]
make_bd_pins_external $pl_ps_irq0
set_property name pl_ps_irq0 [get_bd_ports -of_objects [get_bd_nets -of_objects $pl_ps_irq0]]
set pl_ps_irq0_port [get_bd_ports -of_objects [get_bd_nets -of_objects $pl_ps_irq0]]
set_property -dict [list \
CONFIG.PortWidth 8 \
] $pl_ps_irq0_port
# Port clock associations
set lst [list]
foreach port $pl_clk0_busif {
lappend lst [get_property name $port]
}
set_property CONFIG.ASSOCIATED_BUSIF [join $lst ":"] $pl_clk0_port
# Assign addresses
assign_bd_address -target_address_space /s_axi_dma [get_bd_addr_segs $zynq_ultra_ps/SAXIGP0/HPC0_DDR_HIGH] -force
assign_bd_address -target_address_space /s_axi_dma [get_bd_addr_segs $zynq_ultra_ps/SAXIGP0/HPC0_QSPI] -force
assign_bd_address -target_address_space /s_axi_dma [get_bd_addr_segs $zynq_ultra_ps/SAXIGP0/HPC0_DDR_LOW] -force
assign_bd_address -target_address_space /s_axi_dma [get_bd_addr_segs $zynq_ultra_ps/SAXIGP0/HPC0_LPS_OCM] -force
assign_bd_address -offset 0xA000_0000 -range 16M -target_address_space $zynq_ultra_ps/Data [get_bd_addr_segs $m_axil_ctrl_port/Reg] -force
assign_bd_address -offset 0xA800_0000 -range 16M -target_address_space $zynq_ultra_ps/Data [get_bd_addr_segs $m_axil_app_ctrl_port/Reg] -force
validate_bd_design
# Save block design
save_bd_design [current_bd_design]
close_bd_design [current_bd_design]

6
fpga/mqnic/ZCU106/fpga_zynqmp/ps/petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi
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@ -1,13 +1,13 @@
/include/ "system-conf.dtsi"
/ {
/delete-node/ m_axil_0@a0000000;
/delete-node/ m_axil_1@b0000000;
/delete-node/ m_axil_ctrl@a0000000;
/delete-node/ m_axil_app_ctrl@a8000000;
mqnic0: ethernet@a0000000 {
compatible = "corundum,mqnic";
reg = <0x0 0xa0000000 0x0 0x1000000>,
<0x0 0xb0000000 0x0 0x1000000>;
<0x0 0xa8000000 0x0 0x1000000>;
reg-names = "csr", "app";
interrupt-parent = <&gic>;
interrupts = <0x0 0x59 0x1>, <0x0 0x5a 0x1>, <0x0 0x5b 0x1>,

186
fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v
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@ -196,8 +196,8 @@ parameter PTP_TAG_WIDTH = 16;
parameter PTP_PERIOD_NS_WIDTH = 4;
parameter PTP_OFFSET_NS_WIDTH = 32;
parameter PTP_FNS_WIDTH = 32;
parameter PTP_PERIOD_NS = 4'd4;
parameter PTP_PERIOD_FNS = 32'd0;
parameter PTP_PERIOD_NS = 4'h3;
parameter PTP_PERIOD_FNS = 32'h55555555;
parameter PTP_USE_SAMPLE_CLOCK = 0;
parameter IF_PTP_PERIOD_NS = 6'h6;
parameter IF_PTP_PERIOD_FNS = 16'h6666;
@ -212,8 +212,8 @@ parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1;
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;
// Clock and reset
wire zynq_user_clk;
wire zynq_user_reset;
wire zynq_pl_clk;
wire zynq_pl_reset;
wire clk_125mhz_ibufg;
wire clk_125mhz_mmcm_out;
@ -222,7 +222,7 @@ wire clk_125mhz_mmcm_out;
wire clk_125mhz_int;
wire rst_125mhz_int;
wire mmcm_rst = zynq_user_reset;
wire mmcm_rst = zynq_pl_reset;
wire mmcm_locked;
wire mmcm_clkfb;
@ -327,8 +327,8 @@ debounce_switch #(
.RATE(250000)
)
debounce_switch_inst (
.clk(zynq_user_clk),
.rst(zynq_user_reset),
.clk(zynq_pl_clk),
.rst(zynq_pl_reset),
.in({btnu,
btnl,
btnd,
@ -424,8 +424,8 @@ wire axil_app_ctrl_rvalid;
wire axil_app_ctrl_rready;
reg [(IRQ_COUNT*IRQ_STRETCH)-1:0] irq_stretch = {(IRQ_COUNT*IRQ_STRETCH){1'b0}};
always @(posedge zynq_user_clk) begin
if (zynq_user_reset) begin
always @(posedge zynq_pl_clk) begin
if (zynq_pl_reset) begin
irq_stretch <= {(IRQ_COUNT*IRQ_STRETCH){1'b0}};
end else begin
/* IRQ shift vector */
@ -444,91 +444,91 @@ always @* begin
end
end
bd_zynq bd_zynq_inst (
.clk(zynq_user_clk),
.rst(zynq_user_reset),
zynq_ps zynq_ps_inst (
.pl_clk0(zynq_pl_clk),
.pl_reset(zynq_pl_reset),
.irq(zynq_irq),
.pl_ps_irq0(zynq_irq),
.m_axil_0_araddr(axil_ctrl_araddr),
.m_axil_0_arprot(axil_ctrl_arprot),
.m_axil_0_arready(axil_ctrl_arready),
.m_axil_0_arvalid(axil_ctrl_arvalid),
.m_axil_0_awaddr(axil_ctrl_awaddr),
.m_axil_0_awprot(axil_ctrl_awprot),
.m_axil_0_awready(axil_ctrl_awready),
.m_axil_0_awvalid(axil_ctrl_awvalid),
.m_axil_0_bready(axil_ctrl_bready),
.m_axil_0_bresp(axil_ctrl_bresp),
.m_axil_0_bvalid(axil_ctrl_bvalid),
.m_axil_0_rdata(axil_ctrl_rdata),
.m_axil_0_rready(axil_ctrl_rready),
.m_axil_0_rresp(axil_ctrl_rresp),
.m_axil_0_rvalid(axil_ctrl_rvalid),
.m_axil_0_wdata(axil_ctrl_wdata),
.m_axil_0_wready(axil_ctrl_wready),
.m_axil_0_wstrb(axil_ctrl_wstrb),
.m_axil_0_wvalid(axil_ctrl_wvalid),
.m_axil_ctrl_araddr(axil_ctrl_araddr),
.m_axil_ctrl_arprot(axil_ctrl_arprot),
.m_axil_ctrl_arready(axil_ctrl_arready),
.m_axil_ctrl_arvalid(axil_ctrl_arvalid),
.m_axil_ctrl_awaddr(axil_ctrl_awaddr),
.m_axil_ctrl_awprot(axil_ctrl_awprot),
.m_axil_ctrl_awready(axil_ctrl_awready),
.m_axil_ctrl_awvalid(axil_ctrl_awvalid),
.m_axil_ctrl_bready(axil_ctrl_bready),
.m_axil_ctrl_bresp(axil_ctrl_bresp),
.m_axil_ctrl_bvalid(axil_ctrl_bvalid),
.m_axil_ctrl_rdata(axil_ctrl_rdata),
.m_axil_ctrl_rready(axil_ctrl_rready),
.m_axil_ctrl_rresp(axil_ctrl_rresp),
.m_axil_ctrl_rvalid(axil_ctrl_rvalid),
.m_axil_ctrl_wdata(axil_ctrl_wdata),
.m_axil_ctrl_wready(axil_ctrl_wready),
.m_axil_ctrl_wstrb(axil_ctrl_wstrb),
.m_axil_ctrl_wvalid(axil_ctrl_wvalid),
.m_axil_1_araddr(axil_app_ctrl_araddr),
.m_axil_1_arprot(axil_app_ctrl_arprot),
.m_axil_1_arready(axil_app_ctrl_arready),
.m_axil_1_arvalid(axil_app_ctrl_arvalid),
.m_axil_1_awaddr(axil_app_ctrl_awaddr),
.m_axil_1_awprot(axil_app_ctrl_awprot),
.m_axil_1_awready(axil_app_ctrl_awready),
.m_axil_1_awvalid(axil_app_ctrl_awvalid),
.m_axil_1_bready(axil_app_ctrl_bready),
.m_axil_1_bresp(axil_app_ctrl_bresp),
.m_axil_1_bvalid(axil_app_ctrl_bvalid),
.m_axil_1_rdata(axil_app_ctrl_rdata),
.m_axil_1_rready(axil_app_ctrl_rready),
.m_axil_1_rresp(axil_app_ctrl_rresp),
.m_axil_1_rvalid(axil_app_ctrl_rvalid),
.m_axil_1_wdata(axil_app_ctrl_wdata),
.m_axil_1_wready(axil_app_ctrl_wready),
.m_axil_1_wstrb(axil_app_ctrl_wstrb),
.m_axil_1_wvalid(axil_app_ctrl_wvalid),
.m_axil_app_ctrl_araddr(axil_app_ctrl_araddr),
.m_axil_app_ctrl_arprot(axil_app_ctrl_arprot),
.m_axil_app_ctrl_arready(axil_app_ctrl_arready),
.m_axil_app_ctrl_arvalid(axil_app_ctrl_arvalid),
.m_axil_app_ctrl_awaddr(axil_app_ctrl_awaddr),
.m_axil_app_ctrl_awprot(axil_app_ctrl_awprot),
.m_axil_app_ctrl_awready(axil_app_ctrl_awready),
.m_axil_app_ctrl_awvalid(axil_app_ctrl_awvalid),
.m_axil_app_ctrl_bready(axil_app_ctrl_bready),
.m_axil_app_ctrl_bresp(axil_app_ctrl_bresp),
.m_axil_app_ctrl_bvalid(axil_app_ctrl_bvalid),
.m_axil_app_ctrl_rdata(axil_app_ctrl_rdata),
.m_axil_app_ctrl_rready(axil_app_ctrl_rready),
.m_axil_app_ctrl_rresp(axil_app_ctrl_rresp),
.m_axil_app_ctrl_rvalid(axil_app_ctrl_rvalid),
.m_axil_app_ctrl_wdata(axil_app_ctrl_wdata),
.m_axil_app_ctrl_wready(axil_app_ctrl_wready),
.m_axil_app_ctrl_wstrb(axil_app_ctrl_wstrb),
.m_axil_app_ctrl_wvalid(axil_app_ctrl_wvalid),
.s_axi_mm_araddr(axi_araddr),
.s_axi_mm_arburst(axi_arburst),
.s_axi_mm_arcache(axi_arcache),
.s_axi_mm_arid(axi_arid),
.s_axi_mm_arlen(axi_arlen),
.s_axi_mm_arlock(axi_arlock),
.s_axi_mm_arprot(axi_arprot),
.s_axi_mm_arqos({4{1'b0}}),
.s_axi_mm_arready(axi_arready),
.s_axi_mm_arsize(axi_arsize),
.s_axi_mm_aruser(1'b0),
.s_axi_mm_arvalid(axi_arvalid),
.s_axi_mm_awaddr(axi_awaddr),
.s_axi_mm_awburst(axi_awburst),
.s_axi_mm_awcache(axi_awcache),
.s_axi_mm_awid(axi_awid),
.s_axi_mm_awlen(axi_awlen),
.s_axi_mm_awlock(axi_awlock),
.s_axi_mm_awprot(axi_awprot),
.s_axi_mm_awqos({4{1'b0}}),
.s_axi_mm_awready(axi_awready),
.s_axi_mm_awsize(axi_awsize),
.s_axi_mm_awuser(1'b0),
.s_axi_mm_awvalid(axi_awvalid),
.s_axi_mm_bid(axi_bid),
.s_axi_mm_bready(axi_bready),
.s_axi_mm_bresp(axi_bresp),
.s_axi_mm_bvalid(axi_bvalid),
.s_axi_mm_rdata(axi_rdata),
.s_axi_mm_rid(axi_rid),
.s_axi_mm_rlast(axi_rlast),
.s_axi_mm_rready(axi_rready),
.s_axi_mm_rresp(axi_rresp),
.s_axi_mm_rvalid(axi_rvalid),
.s_axi_mm_wdata(axi_wdata),
.s_axi_mm_wlast(axi_wlast),
.s_axi_mm_wready(axi_wready),
.s_axi_mm_wstrb(axi_wstrb),
.s_axi_mm_wvalid(axi_wvalid)
.s_axi_dma_araddr(axi_araddr),
.s_axi_dma_arburst(axi_arburst),
.s_axi_dma_arcache(axi_arcache),
.s_axi_dma_arid(axi_arid),
.s_axi_dma_arlen(axi_arlen),
.s_axi_dma_arlock(axi_arlock),
.s_axi_dma_arprot(axi_arprot),
.s_axi_dma_arqos({4{1'b0}}),
.s_axi_dma_arready(axi_arready),
.s_axi_dma_arsize(axi_arsize),
.s_axi_dma_aruser(1'b0),
.s_axi_dma_arvalid(axi_arvalid),
.s_axi_dma_awaddr(axi_awaddr),
.s_axi_dma_awburst(axi_awburst),
.s_axi_dma_awcache(axi_awcache),
.s_axi_dma_awid(axi_awid),
.s_axi_dma_awlen(axi_awlen),
.s_axi_dma_awlock(axi_awlock),
.s_axi_dma_awprot(axi_awprot),
.s_axi_dma_awqos({4{1'b0}}),
.s_axi_dma_awready(axi_awready),
.s_axi_dma_awsize(axi_awsize),
.s_axi_dma_awuser(1'b0),
.s_axi_dma_awvalid(axi_awvalid),
.s_axi_dma_bid(axi_bid),
.s_axi_dma_bready(axi_bready),
.s_axi_dma_bresp(axi_bresp),
.s_axi_dma_bvalid(axi_bvalid),
.s_axi_dma_rdata(axi_rdata),
.s_axi_dma_rid(axi_rid),
.s_axi_dma_rlast(axi_rlast),
.s_axi_dma_rready(axi_rready),
.s_axi_dma_rresp(axi_rresp),
.s_axi_dma_rvalid(axi_rvalid),
.s_axi_dma_wdata(axi_wdata),
.s_axi_dma_wlast(axi_wlast),
.s_axi_dma_wready(axi_wready),
.s_axi_dma_wstrb(axi_wstrb),
.s_axi_dma_wvalid(axi_wvalid)
);
// XGMII 10G PHY
@ -804,11 +804,11 @@ fpga_core #(
)
core_inst (
/*
* Clock: 250 MHz
* Clock: 300 MHz
* Synchronous reset
*/
.clk_250mhz(zynq_user_clk),
.rst_250mhz(zynq_user_reset),
.clk_300mhz(zynq_pl_clk),
.rst_300mhz(zynq_pl_reset),
/*
* GPIO

30
fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v
View File

@ -63,8 +63,8 @@ module fpga_core #
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
parameter PTP_PERIOD_NS = 4'd4,
parameter PTP_PERIOD_FNS = 32'd0,
parameter PTP_PERIOD_NS = 4'd3,
parameter PTP_PERIOD_FNS = 32'h55555555,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
@ -176,11 +176,11 @@ module fpga_core #
)
(
/*
* Clock: 250 MHz
* Clock: 300 MHz
* Synchronous reset
*/
input wire clk_250mhz,
input wire rst_250mhz,
input wire clk_300mhz,
input wire rst_300mhz,
/*
* GPIO
@ -404,7 +404,7 @@ assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg | sfp_drp_reg_rd_ack;
assign sfp0_tx_disable_b = !sfp0_tx_disable_reg;
assign sfp1_tx_disable_b = !sfp1_tx_disable_reg;
always @(posedge clk_250mhz) begin
always @(posedge clk_300mhz) begin
ctrl_reg_wr_ack_reg <= 1'b0;
ctrl_reg_rd_data_reg <= {AXIL_CTRL_DATA_WIDTH{1'b0}};
ctrl_reg_rd_ack_reg <= 1'b0;
@ -444,7 +444,7 @@ always @(posedge clk_250mhz) begin
endcase
end
if (rst_250mhz) begin
if (rst_300mhz) begin
ctrl_reg_wr_ack_reg <= 1'b0;
ctrl_reg_rd_ack_reg <= 1'b0;
@ -464,8 +464,8 @@ rb_drp #(
.RB_NEXT_PTR(0)
)
sfp_rb_drp_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.clk(clk_300mhz),
.rst(rst_300mhz),
/*
* Register interface
@ -498,7 +498,7 @@ sfp_rb_drp_inst (
reg [26:0] pps_led_counter_reg = 0;
reg pps_led_reg = 0;
always @(posedge clk_250mhz) begin
always @(posedge clk_300mhz) begin
if (ptp_pps) begin
pps_led_counter_reg <= 125000000;
end else if (pps_led_counter_reg > 0) begin
@ -526,8 +526,8 @@ tdma_ber #(
.ACTIVE_PERIOD_NS(90000)
)
tdma_ber_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.clk(clk_300mhz),
.rst(rst_300mhz),
.phy_tx_clk({sfp1_tx_clk, sfp0_tx_clk}),
.phy_rx_clk({sfp1_rx_clk, sfp0_rx_clk}),
.phy_rx_error_count({sfp1_rx_error_count, sfp0_rx_error_count}),
@ -843,8 +843,8 @@ mqnic_core_axi #(
.STAT_ID_WIDTH(STAT_ID_WIDTH)
)
core_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
.clk(clk_300mhz),
.rst(rst_300mhz),
/*
* Interrupt outputs
@ -977,7 +977,7 @@ core_inst (
/*
* PTP clock
*/
.ptp_sample_clk(clk_250mhz),
.ptp_sample_clk(clk_300mhz),
.ptp_pps(ptp_pps),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),

26
fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py
View File

@ -69,17 +69,17 @@ class TB(object):
self.log = SimLog("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.clk_250mhz, 4, units="ns").start())
cocotb.start_soon(Clock(dut.clk_300mhz, 3332, units="ps").start())
# AXI
self.address_space = AddressSpace()
self.pool = self.address_space.create_pool(0, 0x8000_0000)
self.axil_master = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axil_ctrl"), dut.clk_250mhz, dut.rst_250mhz)
self.axil_master = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axil_ctrl"), dut.clk_300mhz, dut.rst_300mhz)
self.address_space.register_region(self.axil_master, 0x10_0000_0000)
self.hw_regs = self.address_space.create_window(0x10_0000_0000, self.axil_master.size)
self.axi_slave = AxiSlave(AxiBus.from_prefix(dut, "m_axi"), dut.clk_250mhz, dut.rst_250mhz, self.address_space)
self.axi_slave = AxiSlave(AxiBus.from_prefix(dut, "m_axi"), dut.clk_300mhz, dut.rst_300mhz, self.address_space)
self.driver = mqnic.Driver()
@ -114,25 +114,25 @@ class TB(object):
async def init(self):
self.dut.rst_250mhz.setimmediatevalue(0)
self.dut.rst_300mhz.setimmediatevalue(0)
self.dut.sfp0_rx_rst.setimmediatevalue(0)
self.dut.sfp0_tx_rst.setimmediatevalue(0)
self.dut.sfp1_rx_rst.setimmediatevalue(0)
self.dut.sfp1_tx_rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk_250mhz)
await RisingEdge(self.dut.clk_250mhz)
await RisingEdge(self.dut.clk_300mhz)
await RisingEdge(self.dut.clk_300mhz)
self.dut.rst_250mhz.value = 1
self.dut.rst_300mhz.value = 1
self.dut.sfp0_rx_rst.setimmediatevalue(1)
self.dut.sfp0_tx_rst.setimmediatevalue(1)
self.dut.sfp1_rx_rst.setimmediatevalue(1)
self.dut.sfp1_tx_rst.setimmediatevalue(1)
await RisingEdge(self.dut.clk_250mhz)
await RisingEdge(self.dut.clk_250mhz)
await RisingEdge(self.dut.clk_300mhz)
await RisingEdge(self.dut.clk_300mhz)
self.dut.rst_250mhz.value = 0
self.dut.rst_300mhz.value = 0
self.dut.sfp0_rx_rst.setimmediatevalue(0)
self.dut.sfp0_tx_rst.setimmediatevalue(0)
self.dut.sfp1_rx_rst.setimmediatevalue(0)
@ -140,7 +140,7 @@ class TB(object):
async def _run_loopback(self):
while True:
await RisingEdge(self.dut.clk_250mhz)
await RisingEdge(self.dut.clk_300mhz)
if self.loopback_enable:
if not self.sfp0_sink.empty():
@ -263,8 +263,8 @@ async def run_test_nic(dut):
tb.loopback_enable = False
await RisingEdge(dut.clk_250mhz)
await RisingEdge(dut.clk_250mhz)
await RisingEdge(dut.clk_300mhz)
await RisingEdge(dut.clk_300mhz)
# cocotb-test