From 57905a5ef9eb6a08ea9561b5a26bbdb3a9ab3dfe Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Mon, 11 Apr 2022 12:25:51 -0700 Subject: [PATCH] fpga/mqnic/ZCU106/fpga_zynqmp: Rewrite zynq PS TCL script, rework PS clock settings, switch to 300 MHz PL clock Signed-off-by: Alex Forencich --- fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile | 2 +- fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl | 29 +- fpga/mqnic/ZCU106/fpga_zynqmp/ip/bd_zynq.tcl | 1025 ----------------- fpga/mqnic/ZCU106/fpga_zynqmp/ip/zynq_ps.tcl | 212 ++++ .../device-tree/files/system-user.dtsi | 6 +- fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v | 186 +-- fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v | 30 +- .../tb/fpga_core/test_fpga_core.py | 26 +- 8 files changed, 352 insertions(+), 1164 deletions(-) delete mode 100644 fpga/mqnic/ZCU106/fpga_zynqmp/ip/bd_zynq.tcl create mode 100644 fpga/mqnic/ZCU106/fpga_zynqmp/ip/zynq_ps.tcl diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile index 1d66637ec..d2f80bf42 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile @@ -106,7 +106,7 @@ XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP -IP_TCL_FILES = ip/bd_zynq.tcl +IP_TCL_FILES = ip/zynq_ps.tcl IP_TCL_FILES += ip/eth_xcvr_gth.tcl # Configuration diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl index b155b840d..7e21c51da 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl @@ -143,11 +143,12 @@ dict set params APP_AXIS_IF_ENABLE "1" dict set params APP_STAT_ENABLE "1" # AXI DMA interface configuration -open_bd_design [get_files bd_zynq.bd] -set s_axi_mm [get_bd_intf_ports -of_objects [get_bd_designs bd_zynq] -filter {NAME == s_axi_mm}] -dict set params AXI_DATA_WIDTH [get_property CONFIG.DATA_WIDTH $s_axi_mm] -dict set params AXI_ADDR_WIDTH [get_property CONFIG.ADDR_WIDTH $s_axi_mm] -dict set params AXI_ID_WIDTH [get_property CONFIG.ID_WIDTH $s_axi_mm] +open_bd_design [get_files zynq_ps.bd] +set s_axi_dma [get_bd_intf_ports s_axi_dma] +dict set params AXI_DATA_WIDTH [get_property CONFIG.DATA_WIDTH $s_axi_dma] +# dict set params AXI_ADDR_WIDTH [get_property CONFIG.ADDR_WIDTH $s_axi_dma] +dict set params AXI_ADDR_WIDTH 64 +dict set params AXI_ID_WIDTH [get_property CONFIG.ID_WIDTH $s_axi_dma] # DMA interface configuration dict set params DMA_LEN_WIDTH "16" @@ -157,23 +158,23 @@ dict set params RAM_PIPELINE "2" # NOTE: Querying the BD top-level interface port (or even the ZynqMP's interface # pin) yields 256 for the maximum burst length, instead of 16, which is # the actually supported length (due to ZynqMP using AXI3 internally). -#dict set params AXI_DMA_MAX_BURST_LEN [get_property CONFIG.MAX_BURST_LENGTH $s_axi_mm] +#dict set params AXI_DMA_MAX_BURST_LEN [get_property CONFIG.MAX_BURST_LENGTH $s_axi_dma] dict set params AXI_DMA_MAX_BURST_LEN "16" # AXI lite interface configuration (control) -set m_axil_0 [get_bd_intf_pins /axi_protocol_convert_0/M_AXI] -dict set params AXIL_CTRL_DATA_WIDTH [get_property CONFIG.DATA_WIDTH $m_axil_0] -dict set params AXIL_CTRL_ADDR_WIDTH [get_property CONFIG.ADDR_WIDTH $m_axil_0] +set m_axil_ctrl [get_bd_intf_ports m_axil_ctrl] +dict set params AXIL_CTRL_DATA_WIDTH [get_property CONFIG.DATA_WIDTH $m_axil_ctrl] +dict set params AXIL_CTRL_ADDR_WIDTH 24 # AXI lite interface configuration (application control) -set m_axil_1 [get_bd_intf_pins /axi_protocol_convert_1/M_AXI] -dict set params AXIL_APP_CTRL_DATA_WIDTH [get_property CONFIG.DATA_WIDTH $m_axil_1] -dict set params AXIL_APP_CTRL_ADDR_WIDTH [get_property CONFIG.ADDR_WIDTH $m_axil_1] +set m_axil_app_ctrl [get_bd_intf_ports m_axil_app_ctrl] +dict set params AXIL_APP_CTRL_DATA_WIDTH [get_property CONFIG.DATA_WIDTH $m_axil_app_ctrl] +dict set params AXIL_APP_CTRL_ADDR_WIDTH 24 # Interrupt configuration -set irq [get_bd_ports -of_objects [get_bd_designs bd_zynq] -filter {NAME == irq}] +set irq [get_bd_ports pl_ps_irq0] dict set params IRQ_COUNT [get_property CONFIG.PortWidth $irq] -close_bd_design [get_bd_designs bd_zynq] +close_bd_design [get_bd_designs zynq_ps] dict set params IRQ_STRETCH "10" # Ethernet interface configuration diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/ip/bd_zynq.tcl b/fpga/mqnic/ZCU106/fpga_zynqmp/ip/bd_zynq.tcl deleted file mode 100644 index 1f8403967..000000000 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/ip/bd_zynq.tcl +++ /dev/null @@ -1,1025 +0,0 @@ - -################################################################ -# This is a generated script based on design: bd_zynq -# -# Though there are limitations about the generated script, -# the main purpose of this utility is to make learning -# IP Integrator Tcl commands easier. -################################################################ - -namespace eval _tcl { -proc get_script_folder {} { - set script_path [file normalize [info script]] - set script_folder [file dirname $script_path] - return $script_folder -} -} -variable script_folder -set script_folder [_tcl::get_script_folder] - -################################################################ -# Check if script is running in correct Vivado version. -################################################################ -set scripts_vivado_version 2021.1 -set current_vivado_version [version -short] - -if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { - puts "" - catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} - - return 1 -} - -################################################################ -# START -################################################################ - -# To test this script, run the following commands from Vivado Tcl console: -# source bd_zynq_script.tcl - -# If there is no project opened, this script will create a -# project, but make sure you do not have an existing project -# <./myproj/project_1.xpr> in the current working folder. - -set list_projs [get_projects -quiet] -if { $list_projs eq "" } { - create_project project_1 myproj -part xczu7ev-ffvc1156-2-e -} - - -# CHANGE DESIGN NAME HERE -variable design_name -set design_name bd_zynq - -# If you do not already have an existing IP Integrator design open, -# you can create a design using the following command: -# create_bd_design $design_name - -# Creating design if needed -set errMsg "" -set nRet 0 - -set cur_design [current_bd_design -quiet] -set list_cells [get_bd_cells -quiet] - -if { ${design_name} eq "" } { - # USE CASES: - # 1) Design_name not set - - set errMsg "Please set the variable to a non-empty value." - set nRet 1 - -} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { - # USE CASES: - # 2): Current design opened AND is empty AND names same. - # 3): Current design opened AND is empty AND names diff; design_name NOT in project. - # 4): Current design opened AND is empty AND names diff; design_name exists in project. - - if { $cur_design ne $design_name } { - common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." - set design_name [get_property NAME $cur_design] - } - common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." - -} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { - # USE CASES: - # 5) Current design opened AND has components AND same names. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 1 -} elseif { [get_files -quiet ${design_name}.bd] ne "" } { - # USE CASES: - # 6) Current opened design, has components, but diff names, design_name exists in project. - # 7) No opened design, design_name exists in project. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 2 - -} else { - # USE CASES: - # 8) No opened design, design_name not in project. - # 9) Current opened design, has components, but diff names, design_name not in project. - - common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." - - create_bd_design $design_name - - common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." - current_bd_design $design_name - -} - -common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." - -if { $nRet != 0 } { - catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} - return $nRet -} - -set bCheckIPsPassed 1 -################################################################## -# CHECK IPs -################################################################## -set bCheckIPs 1 -if { $bCheckIPs == 1 } { - set list_check_ips "\ -xilinx.com:ip:axi_protocol_converter:2.1\ -xilinx.com:ip:proc_sys_reset:5.0\ -xilinx.com:ip:xlconcat:2.1\ -xilinx.com:ip:xlconstant:1.1\ -xilinx.com:ip:zynq_ultra_ps_e:3.3\ -" - - set list_ips_missing "" - common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." - - foreach ip_vlnv $list_check_ips { - set ip_obj [get_ipdefs -all $ip_vlnv] - if { $ip_obj eq "" } { - lappend list_ips_missing $ip_vlnv - } - } - - if { $list_ips_missing ne "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } - set bCheckIPsPassed 0 - } - -} - -if { $bCheckIPsPassed != 1 } { - common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." - return 3 -} - -################################################################## -# DESIGN PROCs -################################################################## - - - -# Procedure to create entire design; Provide argument to make -# procedure reusable. If parentCell is "", will use root. -proc create_root_design { parentCell } { - - variable script_folder - variable design_name - - if { $parentCell eq "" } { - set parentCell [get_bd_cells /] - } - - # Get object for parentCell - set parentObj [get_bd_cells $parentCell] - if { $parentObj == "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} - return - } - - # Make sure parentObj is hier blk - set parentType [get_property TYPE $parentObj] - if { $parentType ne "hier" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} - return - } - - # Save current instance; Restore later - set oldCurInst [current_bd_instance .] - - # Set parent object as current - current_bd_instance $parentObj - - - # Create interface ports - set m_axil_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axil_0 ] - set_property -dict [ list \ - CONFIG.ADDR_WIDTH {24} \ - CONFIG.DATA_WIDTH {32} \ - CONFIG.FREQ_HZ {249975021} \ - CONFIG.HAS_BURST {0} \ - CONFIG.HAS_CACHE {0} \ - CONFIG.HAS_LOCK {0} \ - CONFIG.HAS_QOS {0} \ - CONFIG.HAS_REGION {0} \ - CONFIG.PROTOCOL {AXI4LITE} \ - ] $m_axil_0 - - set m_axil_1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axil_1 ] - set_property -dict [ list \ - CONFIG.ADDR_WIDTH {24} \ - CONFIG.DATA_WIDTH {32} \ - CONFIG.FREQ_HZ {249975021} \ - CONFIG.HAS_BURST {0} \ - CONFIG.HAS_CACHE {0} \ - CONFIG.HAS_LOCK {0} \ - CONFIG.HAS_QOS {0} \ - CONFIG.HAS_REGION {0} \ - CONFIG.PROTOCOL {AXI4LITE} \ - ] $m_axil_1 - - set s_axi_mm [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_mm ] - set_property -dict [ list \ - CONFIG.ADDR_WIDTH {64} \ - CONFIG.ARUSER_WIDTH {1} \ - CONFIG.AWUSER_WIDTH {1} \ - CONFIG.BUSER_WIDTH {0} \ - CONFIG.DATA_WIDTH {128} \ - CONFIG.FREQ_HZ {249975021} \ - CONFIG.HAS_BRESP {1} \ - CONFIG.HAS_BURST {1} \ - CONFIG.HAS_CACHE {1} \ - CONFIG.HAS_LOCK {1} \ - CONFIG.HAS_PROT {1} \ - CONFIG.HAS_QOS {0} \ - CONFIG.HAS_REGION {0} \ - CONFIG.HAS_RRESP {1} \ - CONFIG.HAS_WSTRB {1} \ - CONFIG.ID_WIDTH {6} \ - CONFIG.MAX_BURST_LENGTH {256} \ - CONFIG.NUM_READ_OUTSTANDING {16} \ - CONFIG.NUM_READ_THREADS {1} \ - CONFIG.NUM_WRITE_OUTSTANDING {16} \ - CONFIG.NUM_WRITE_THREADS {1} \ - CONFIG.PROTOCOL {AXI4} \ - CONFIG.READ_WRITE_MODE {READ_WRITE} \ - CONFIG.RUSER_BITS_PER_BYTE {0} \ - CONFIG.RUSER_WIDTH {0} \ - CONFIG.SUPPORTS_NARROW_BURST {1} \ - CONFIG.WUSER_BITS_PER_BYTE {0} \ - CONFIG.WUSER_WIDTH {0} \ - ] $s_axi_mm - - - # Create ports - set clk [ create_bd_port -dir O -type clk clk ] - set_property -dict [ list \ - CONFIG.ASSOCIATED_BUSIF {s_axi_mm:m_axil_0:m_axil_1} \ - CONFIG.FREQ_HZ {249975021} \ - ] $clk - set irq [ create_bd_port -dir I -from 3 -to 0 -type intr irq ] - set_property -dict [ list \ - CONFIG.PortWidth {4} \ - ] $irq - set rst [ create_bd_port -dir O -from 0 -to 0 -type rst rst ] - set_property -dict [ list \ - CONFIG.POLARITY {ACTIVE_HIGH} \ - ] $rst - - # Create instance: axi_protocol_convert_0, and set properties - set axi_protocol_convert_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_protocol_converter:2.1 axi_protocol_convert_0 ] - set_property -dict [ list \ - CONFIG.ADDR_WIDTH {24} \ - CONFIG.MI_PROTOCOL {AXI4LITE} \ - ] $axi_protocol_convert_0 - - # Create instance: axi_protocol_convert_1, and set properties - set axi_protocol_convert_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_protocol_converter:2.1 axi_protocol_convert_1 ] - set_property -dict [ list \ - CONFIG.ADDR_WIDTH {24} \ - CONFIG.MI_PROTOCOL {AXI4LITE} \ - ] $axi_protocol_convert_1 - - # Create instance: proc_sys_reset, and set properties - set proc_sys_reset [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset ] - - # Create instance: xlconcat_0, and set properties - set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] - - # Create instance: xlconstant_0, and set properties - set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {4} \ - ] $xlconstant_0 - - # Create instance: zynq_ultra_ps, and set properties - set zynq_ultra_ps [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps ] - set_property -dict [ list \ - CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_DDR_RAM_HIGHADDR {0xFFFFFFFF} \ - CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x800000000} \ - CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \ - CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {1} \ - CONFIG.PSU_MIO_0_DIRECTION {out} \ - CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_0_POLARITY {Default} \ - CONFIG.PSU_MIO_10_DIRECTION {inout} \ - CONFIG.PSU_MIO_10_POLARITY {Default} \ - CONFIG.PSU_MIO_11_DIRECTION {inout} \ - CONFIG.PSU_MIO_11_POLARITY {Default} \ - CONFIG.PSU_MIO_12_DIRECTION {out} \ - CONFIG.PSU_MIO_12_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_12_POLARITY {Default} \ - CONFIG.PSU_MIO_13_DIRECTION {inout} \ - CONFIG.PSU_MIO_13_POLARITY {Default} \ - CONFIG.PSU_MIO_14_DIRECTION {inout} \ - CONFIG.PSU_MIO_14_POLARITY {Default} \ - CONFIG.PSU_MIO_15_DIRECTION {inout} \ - CONFIG.PSU_MIO_15_POLARITY {Default} \ - CONFIG.PSU_MIO_16_DIRECTION {inout} \ - CONFIG.PSU_MIO_16_POLARITY {Default} \ - CONFIG.PSU_MIO_17_DIRECTION {inout} \ - CONFIG.PSU_MIO_17_POLARITY {Default} \ - CONFIG.PSU_MIO_18_DIRECTION {in} \ - CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_18_POLARITY {Default} \ - CONFIG.PSU_MIO_18_SLEW {fast} \ - CONFIG.PSU_MIO_19_DIRECTION {out} \ - CONFIG.PSU_MIO_19_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_19_POLARITY {Default} \ - CONFIG.PSU_MIO_1_DIRECTION {inout} \ - CONFIG.PSU_MIO_1_POLARITY {Default} \ - CONFIG.PSU_MIO_20_DIRECTION {out} \ - CONFIG.PSU_MIO_20_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_20_POLARITY {Default} \ - CONFIG.PSU_MIO_21_DIRECTION {in} \ - CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_21_POLARITY {Default} \ - CONFIG.PSU_MIO_21_SLEW {fast} \ - CONFIG.PSU_MIO_22_DIRECTION {inout} \ - CONFIG.PSU_MIO_22_POLARITY {Default} \ - CONFIG.PSU_MIO_23_DIRECTION {inout} \ - CONFIG.PSU_MIO_23_POLARITY {Default} \ - CONFIG.PSU_MIO_24_DIRECTION {inout} \ - CONFIG.PSU_MIO_24_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_24_POLARITY {Default} \ - CONFIG.PSU_MIO_25_DIRECTION {inout} \ - CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_25_POLARITY {Default} \ - CONFIG.PSU_MIO_25_SLEW {fast} \ - CONFIG.PSU_MIO_26_DIRECTION {inout} \ - CONFIG.PSU_MIO_26_POLARITY {Default} \ - CONFIG.PSU_MIO_27_DIRECTION {inout} \ - CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_27_POLARITY {Default} \ - CONFIG.PSU_MIO_28_DIRECTION {inout} \ - CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_28_POLARITY {Default} \ - CONFIG.PSU_MIO_28_SLEW {fast} \ - CONFIG.PSU_MIO_29_DIRECTION {inout} \ - CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_29_POLARITY {Default} \ - CONFIG.PSU_MIO_2_DIRECTION {inout} \ - CONFIG.PSU_MIO_2_POLARITY {Default} \ - CONFIG.PSU_MIO_30_DIRECTION {inout} \ - CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_30_POLARITY {Default} \ - CONFIG.PSU_MIO_30_SLEW {fast} \ - CONFIG.PSU_MIO_31_DIRECTION {inout} \ - CONFIG.PSU_MIO_31_POLARITY {Default} \ - CONFIG.PSU_MIO_32_DIRECTION {out} \ - CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_32_POLARITY {Default} \ - CONFIG.PSU_MIO_33_DIRECTION {out} \ - CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_33_POLARITY {Default} \ - CONFIG.PSU_MIO_34_DIRECTION {out} \ - CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_34_POLARITY {Default} \ - CONFIG.PSU_MIO_35_DIRECTION {out} \ - CONFIG.PSU_MIO_35_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_35_POLARITY {Default} \ - CONFIG.PSU_MIO_36_DIRECTION {out} \ - CONFIG.PSU_MIO_36_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_36_POLARITY {Default} \ - CONFIG.PSU_MIO_37_DIRECTION {out} \ - CONFIG.PSU_MIO_37_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_37_POLARITY {Default} \ - CONFIG.PSU_MIO_38_DIRECTION {inout} \ - CONFIG.PSU_MIO_38_POLARITY {Default} \ - CONFIG.PSU_MIO_39_DIRECTION {inout} \ - CONFIG.PSU_MIO_39_POLARITY {Default} \ - CONFIG.PSU_MIO_3_DIRECTION {inout} \ - CONFIG.PSU_MIO_3_POLARITY {Default} \ - CONFIG.PSU_MIO_40_DIRECTION {inout} \ - CONFIG.PSU_MIO_40_POLARITY {Default} \ - CONFIG.PSU_MIO_41_DIRECTION {inout} \ - CONFIG.PSU_MIO_41_POLARITY {Default} \ - CONFIG.PSU_MIO_42_DIRECTION {inout} \ - CONFIG.PSU_MIO_42_POLARITY {Default} \ - CONFIG.PSU_MIO_43_DIRECTION {out} \ - CONFIG.PSU_MIO_43_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_43_POLARITY {Default} \ - CONFIG.PSU_MIO_44_DIRECTION {in} \ - CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_44_POLARITY {Default} \ - CONFIG.PSU_MIO_44_SLEW {fast} \ - CONFIG.PSU_MIO_45_DIRECTION {in} \ - CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_45_POLARITY {Default} \ - CONFIG.PSU_MIO_45_SLEW {fast} \ - CONFIG.PSU_MIO_46_DIRECTION {inout} \ - CONFIG.PSU_MIO_46_POLARITY {Default} \ - CONFIG.PSU_MIO_47_DIRECTION {inout} \ - CONFIG.PSU_MIO_47_POLARITY {Default} \ - CONFIG.PSU_MIO_48_DIRECTION {inout} \ - CONFIG.PSU_MIO_48_POLARITY {Default} \ - CONFIG.PSU_MIO_49_DIRECTION {inout} \ - CONFIG.PSU_MIO_49_POLARITY {Default} \ - CONFIG.PSU_MIO_4_DIRECTION {inout} \ - CONFIG.PSU_MIO_4_POLARITY {Default} \ - CONFIG.PSU_MIO_50_DIRECTION {inout} \ - CONFIG.PSU_MIO_50_POLARITY {Default} \ - CONFIG.PSU_MIO_51_DIRECTION {out} \ - CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_51_POLARITY {Default} \ - CONFIG.PSU_MIO_52_DIRECTION {in} \ - CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_52_POLARITY {Default} \ - CONFIG.PSU_MIO_52_SLEW {fast} \ - CONFIG.PSU_MIO_53_DIRECTION {in} \ - CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_53_POLARITY {Default} \ - CONFIG.PSU_MIO_53_SLEW {fast} \ - CONFIG.PSU_MIO_54_DIRECTION {inout} \ - CONFIG.PSU_MIO_54_POLARITY {Default} \ - CONFIG.PSU_MIO_55_DIRECTION {in} \ - CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_55_POLARITY {Default} \ - CONFIG.PSU_MIO_55_SLEW {fast} \ - CONFIG.PSU_MIO_56_DIRECTION {inout} \ - CONFIG.PSU_MIO_56_POLARITY {Default} \ - CONFIG.PSU_MIO_57_DIRECTION {inout} \ - CONFIG.PSU_MIO_57_POLARITY {Default} \ - CONFIG.PSU_MIO_58_DIRECTION {out} \ - CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_58_POLARITY {Default} \ - CONFIG.PSU_MIO_59_DIRECTION {inout} \ - CONFIG.PSU_MIO_59_POLARITY {Default} \ - CONFIG.PSU_MIO_5_DIRECTION {out} \ - CONFIG.PSU_MIO_5_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_5_POLARITY {Default} \ - CONFIG.PSU_MIO_60_DIRECTION {inout} \ - CONFIG.PSU_MIO_60_POLARITY {Default} \ - CONFIG.PSU_MIO_61_DIRECTION {inout} \ - CONFIG.PSU_MIO_61_POLARITY {Default} \ - CONFIG.PSU_MIO_62_DIRECTION {inout} \ - CONFIG.PSU_MIO_62_POLARITY {Default} \ - CONFIG.PSU_MIO_63_DIRECTION {inout} \ - CONFIG.PSU_MIO_63_POLARITY {Default} \ - CONFIG.PSU_MIO_64_DIRECTION {out} \ - CONFIG.PSU_MIO_64_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_64_POLARITY {Default} \ - CONFIG.PSU_MIO_65_DIRECTION {out} \ - CONFIG.PSU_MIO_65_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_65_POLARITY {Default} \ - CONFIG.PSU_MIO_66_DIRECTION {out} \ - CONFIG.PSU_MIO_66_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_66_POLARITY {Default} \ - CONFIG.PSU_MIO_67_DIRECTION {out} \ - CONFIG.PSU_MIO_67_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_67_POLARITY {Default} \ - CONFIG.PSU_MIO_68_DIRECTION {out} \ - CONFIG.PSU_MIO_68_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_68_POLARITY {Default} \ - CONFIG.PSU_MIO_69_DIRECTION {out} \ - CONFIG.PSU_MIO_69_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_69_POLARITY {Default} \ - CONFIG.PSU_MIO_6_DIRECTION {out} \ - CONFIG.PSU_MIO_6_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_6_POLARITY {Default} \ - CONFIG.PSU_MIO_70_DIRECTION {in} \ - CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_70_POLARITY {Default} \ - CONFIG.PSU_MIO_70_SLEW {fast} \ - CONFIG.PSU_MIO_71_DIRECTION {in} \ - CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_71_POLARITY {Default} \ - CONFIG.PSU_MIO_71_SLEW {fast} \ - CONFIG.PSU_MIO_72_DIRECTION {in} \ - CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_72_POLARITY {Default} \ - CONFIG.PSU_MIO_72_SLEW {fast} \ - CONFIG.PSU_MIO_73_DIRECTION {in} \ - CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_73_POLARITY {Default} \ - CONFIG.PSU_MIO_73_SLEW {fast} \ - CONFIG.PSU_MIO_74_DIRECTION {in} \ - CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_74_POLARITY {Default} \ - CONFIG.PSU_MIO_74_SLEW {fast} \ - CONFIG.PSU_MIO_75_DIRECTION {in} \ - CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_75_POLARITY {Default} \ - CONFIG.PSU_MIO_75_SLEW {fast} \ - CONFIG.PSU_MIO_76_DIRECTION {out} \ - CONFIG.PSU_MIO_76_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_76_POLARITY {Default} \ - CONFIG.PSU_MIO_77_DIRECTION {inout} \ - CONFIG.PSU_MIO_77_POLARITY {Default} \ - CONFIG.PSU_MIO_7_DIRECTION {out} \ - CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \ - CONFIG.PSU_MIO_7_POLARITY {Default} \ - CONFIG.PSU_MIO_8_DIRECTION {inout} \ - CONFIG.PSU_MIO_8_POLARITY {Default} \ - CONFIG.PSU_MIO_9_DIRECTION {inout} \ - CONFIG.PSU_MIO_9_POLARITY {Default} \ - CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad\ -SPI Flash#Feedback Clk#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI\ -Flash#Quad SPI Flash#Quad SPI Flash#GPIO0 MIO#I2C 0#I2C 0#I2C 1#I2C 1#UART\ -0#UART 0#UART 1#UART 1#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO1 MIO#GPIO1\ -MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#PMU\ -GPO 3#PMU GPO 4#PMU GPO 5#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD\ -1#SD 1#SD 1#SD 1#SD 1#############Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem\ -3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3}\ - CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#txd#rxd#gpio0[22]#gpio0[23]#gpio0[24]#gpio0[25]#gpio1[26]#gpio1[27]#gpio1[28]#gpio1[29]#gpio1[30]#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpo[3]#gpo[4]#gpo[5]#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#sdio1_bus_pow#sdio1_wp#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#############rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out}\ - CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {8} \ - CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {0} \ - CONFIG.PSU__ACT_DDR_FREQ_MHZ {1066.560059} \ - CONFIG.PSU__AFI0_COHERENCY {0} \ - CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \ - CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__CAN1__PERIPHERAL__IO {} \ - CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {0} \ - CONFIG.PSU__DISPLAYPORT__LANE1__IO {} \ - CONFIG.PSU__DP__LANE_SEL {} \ - CONFIG.PSU__DP__REF_CLK_SEL {} \ - CONFIG.PSU__GT__PRE_EMPH_LVL_4 {} \ - CONFIG.PSU__GT__VLT_SWNG_LVL_4 {} \ - CONFIG.PSU__HIGH_ADDRESS__ENABLE {1} \ - CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 14 .. 15} \ - CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \ - CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \ - CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \ - CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \ - CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \ - CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \ - CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {99.990005} \ - CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {99.990005} \ - CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \ - CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \ - CONFIG.PSU__MAXIGP0__DATA_WIDTH {32} \ - CONFIG.PSU__MAXIGP1__DATA_WIDTH {32} \ - CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \ - CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \ - CONFIG.PSU__PL_CLK0_BUF {TRUE} \ - CONFIG.PSU__PMU_COHERENCY {0} \ - CONFIG.PSU__PMU__AIBACK__ENABLE {0} \ - CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \ - CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \ - CONFIG.PSU__PMU__GPI0__ENABLE {0} \ - CONFIG.PSU__PMU__GPI1__ENABLE {0} \ - CONFIG.PSU__PMU__GPI2__ENABLE {0} \ - CONFIG.PSU__PMU__GPI3__ENABLE {0} \ - CONFIG.PSU__PMU__GPI4__ENABLE {0} \ - CONFIG.PSU__PMU__GPI5__ENABLE {0} \ - CONFIG.PSU__PMU__GPO0__ENABLE {1} \ - CONFIG.PSU__PMU__GPO0__IO {MIO 32} \ - CONFIG.PSU__PMU__GPO1__ENABLE {1} \ - CONFIG.PSU__PMU__GPO1__IO {MIO 33} \ - CONFIG.PSU__PMU__GPO2__ENABLE {1} \ - CONFIG.PSU__PMU__GPO2__IO {MIO 34} \ - CONFIG.PSU__PMU__GPO2__POLARITY {low} \ - CONFIG.PSU__PMU__GPO3__ENABLE {1} \ - CONFIG.PSU__PMU__GPO3__IO {MIO 35} \ - CONFIG.PSU__PMU__GPO3__POLARITY {low} \ - CONFIG.PSU__PMU__GPO4__ENABLE {1} \ - CONFIG.PSU__PMU__GPO4__IO {MIO 36} \ - CONFIG.PSU__PMU__GPO4__POLARITY {low} \ - CONFIG.PSU__PMU__GPO5__ENABLE {1} \ - CONFIG.PSU__PMU__GPO5__IO {MIO 37} \ - CONFIG.PSU__PMU__GPO5__POLARITY {low} \ - CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__PMU__PLERROR__ENABLE {0} \ - CONFIG.PSU__PRESET_APPLIED {1} \ - CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;0|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;1|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;0|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1}\ - CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;0|LPD;USB3_0;FF9D0000;FF9DFFFF;0|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\ -Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1}\ - CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.330} \ - CONFIG.PSU__QSPI_COHERENCY {0} \ - CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \ - CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \ - CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \ - CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \ - CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 12} \ - CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel} \ - CONFIG.PSU__SATA__LANE0__ENABLE {0} \ - CONFIG.PSU__SATA__LANE1__ENABLE {0} \ - CONFIG.PSU__SATA__LANE1__IO {} \ - CONFIG.PSU__SATA__REF_CLK_SEL {} \ - CONFIG.PSU__USB0__REF_CLK_FREQ {} \ - CONFIG.PSU__USB0__RESET__ENABLE {0} \ - CONFIG.PSU__USB1__RESET__ENABLE {0} \ - CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \ - CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \ - CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__USB3_0__PERIPHERAL__IO {} \ - CONFIG.PSU__USB__RESET__POLARITY {