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fpga/mqnic/DK_DEV_1SDX_P_A: Add 100G mqnic design for DK-DEV-1SDX-P-A

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-04-22 22:07:32 -07:00
parent 3d8bbc4b1c
commit 587b4d5743
27 changed files with 9639 additions and 0 deletions
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# Corundum mqnic for DK-DEV-1SDX-P-A
## Introduction
This design targets the Intel DK-DEV-1SDX-P-A FPGA development board.
* FPGA: 1SD280PT2F55E1VG
* PHY: E-Tile
## How to build
Run make to build. Ensure that the Intel Quartus Prime Pro toolchain components are in PATH.
Run make to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled.
## How to test
Run make program to program the board with the Intel software. Then load the driver with insmod mqnic.ko. Check dmesg for output from driver initialization.

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fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/app Symbolic link
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../../../app/

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fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/common/quartus_pro.mk Normal file
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###################################################################
#
# Makefile for Intel Quartus Prime Pro
#
# Alex Forencich
#
###################################################################
#
# Parameters:
# FPGA_TOP - Top module name
# FPGA_FAMILY - FPGA family (e.g. Stratix 10 DX)
# FPGA_DEVICE - FPGA device (e.g. 1SD280PT2F55E1VG)
# SYN_FILES - space-separated list of source files
# IP_FILES - space-separated list of IP files
# IP_TCL_FILES - space-separated list of TCL files for qsys-script
# QSF_FILES - space-separated list of settings files
# SDC_FILES - space-separated list of timing constraint files
#
# Example:
#
# FPGA_TOP = fpga
# FPGA_FAMILY = "Stratix 10 DX"
# FPGA_DEVICE = 1SD280PT2F55E1VG
# SYN_FILES = rtl/fpga.v
# QSF_FILES = fpga.qsf
# SDC_FILES = fpga.sdc
# include ../common/quartus_pro.mk
#
###################################################################
# phony targets
.PHONY: clean fpga
# output files to hang on to
.PRECIOUS: %.sof %.ipregen.rpt %.syn.rpt %.fit.rpt %.asm.rpt %.sta.rpt
.SECONDARY:
# any project specific settings
CONFIG ?= config.mk
-include ../$(CONFIG)
SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p))
IP_FILES_REL = $(patsubst %, ../%, $(IP_FILES))
IP_FILES_INT = $(patsubst %, ip/%, $(notdir $(IP_FILES)))
IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES))
IP_TCL_FILES_INT = $(patsubst %, ip/%, $(notdir $(IP_TCL_FILES)))
IP_TCL_FILES_IP_INT = $(patsubst %.tcl, ip/%.ip, $(notdir $(IP_TCL_FILES)))
CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p))
ifdef QSF_FILES
QSF_FILES_REL = $(foreach p,$(QSF_FILES),$(if $(filter /% ./%,$p),$p,../$p))
else
QSF_FILES_REL = ../$(FPGA_TOP).qsf
endif
SDC_FILES_REL = $(foreach p,$(SDC_FILES),$(if $(filter /% ./%,$p),$p,../$p))
ASSIGNMENT_FILES = $(FPGA_TOP).qpf $(FPGA_TOP).qsf
###################################################################
# Main Targets
#
# all: build everything
# clean: remove output files and database
###################################################################
all: fpga
fpga: $(FPGA_TOP).sof
quartus: $(FPGA_TOP).qpf
quartus $(FPGA_TOP).qpf
tmpclean::
-rm -rf defines.v
-rm -rf *.rpt *.summary *.done *.smsg *.chg smart.log *.htm *.eqn *.pin *.qsf *.qpf *.sld *.txt *.qws *.stp
-rm -rf ip db qdb incremental_db reconfig_mif tmp-clearbox synth_dumps .qsys_edit
-rm -rf create_project.tcl update_config.tcl update_ip_*.tcl
clean:: tmpclean
-rm -rf *.sof *.pof *.jdi *.jic *.map
distclean:: clean
-rm -rf rev
syn: smart.log output_files/$(PROJECT).syn.rpt
fit: smart.log output_files/$(PROJECT).fit.rpt
asm: smart.log output_files/$(PROJECT).asm.rpt
sta: smart.log output_files/$(PROJECT).sta.rpt
smart: smart.log
###################################################################
# Executable Configuration
###################################################################
IP_ARGS = --run_default_mode_op
SYN_ARGS = --read_settings_files=on --write_settings_files=off
FIT_ARGS = --read_settings_files=on --write_settings_files=off
ASM_ARGS = --read_settings_files=on --write_settings_files=off
STA_ARGS =
###################################################################
# Target implementations
###################################################################
STAMP = echo done >
define COPY_IP_RULE
$(patsubst %, ip/%, $(notdir $(1))): $(1)
@mkdir -p ip
@cp -pv $(1) ip/
endef
$(foreach l,$(IP_FILES_REL) $(IP_TCL_FILES_REL),$(eval $(call COPY_IP_RULE,$(l))))
define TCL_IP_GEN_RULE
$(patsubst %.tcl,%.ip,$(1)): $(1)
cd ip && rm -f $(patsubst %.tcl,%,$(notdir $(1))).{qpf,qsf}
cd ip && qsys-script --script=$(notdir $(1))
endef
$(foreach l,$(IP_TCL_FILES_INT),$(eval $(call TCL_IP_GEN_RULE,$(l))))
%.ipregen.rpt: $(FPGA_TOP).qpf $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT)
quartus_ipgenerate $(IP_ARGS) $(FPGA_TOP)
%.syn.rpt: syn.chg %.ipregen.rpt $(SYN_FILES_REL)
quartus_syn $(SYN_ARGS) $(FPGA_TOP)
%.fit.rpt: fit.chg %.syn.rpt $(SDC_FILES_REL)
quartus_fit $(FIT_ARGS) $(FPGA_TOP)
%.sta.rpt: sta.chg %.fit.rpt
quartus_sta $(STA_ARGS) $(FPGA_TOP)
%.asm.rpt: asm.chg %.sta.rpt
quartus_asm $(ASM_ARGS) $(FPGA_TOP)
mkdir -p rev
EXT=sof; COUNT=100; \
while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
do let COUNT=COUNT+1; done; \
cp $*.$$EXT rev/$*_rev$$COUNT.$$EXT; \
echo "Output: rev/$*_rev$$COUNT.$$EXT";
%.sof: smart.log %.asm.rpt
smart.log: $(ASSIGNMENT_FILES)
quartus_sh --determine_smart_action $(FPGA_TOP) > smart.log
###################################################################
# Project initialization
###################################################################
create_project.tcl: Makefile $(QSF_FILES_REL) | $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT)
rm -f update_config.tcl
echo "project_new $(FPGA_TOP) -overwrite" > $@
echo "set_global_assignment -name FAMILY \"$(FPGA_FAMILY)\"" >> $@
echo "set_global_assignment -name DEVICE \"$(FPGA_DEVICE)\"" >> $@
for x in $(SYN_FILES_REL) $(IP_FILES_INT) $(IP_TCL_FILES_IP_INT); do \
case $${x##*.} in \
v|V) echo set_global_assignment -name VERILOG_FILE "$$x" >> $@ ;;\
vhd|VHD) echo set_global_assignment -name VHDL_FILE "$$x" >> $@ ;;\
qip|QIP) echo set_global_assignment -name QIP_FILE "$$x" >> $@ ;;\
ip|IP) echo set_global_assignment -name IP_FILE "$$x" >> $@ ;;\
*) echo set_global_assignment -name SOURCE_FILE "$$x" >> $@ ;;\
esac; \
done
for x in $(SDC_FILES_REL); do echo set_global_assignment -name SDC_FILE "$$x" >> $@; done
for x in $(QSF_FILES_REL); do echo source "$$x" >> $@; done
update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL)
echo "project_open $(FPGA_TOP)" > $@
for x in $(CONFIG_TCL_FILES_REL); do echo source "$$x" >> $@; done
$(ASSIGNMENT_FILES): create_project.tcl update_config.tcl
for x in $?; do quartus_sh -t "$$x"; done
touch -c $(ASSIGNMENT_FILES)
syn.chg:
$(STAMP) syn.chg
fit.chg:
$(STAMP) fit.chg
sta.chg:
$(STAMP) sta.chg
asm.chg:
$(STAMP) asm.chg

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# Timing constraints for the Intel Stratix 10 DX FPGA development board
set_time_format -unit ns -decimal_places 3
# Clock constraints
create_clock -period 7.519 -name "clk_133m_ddr4_1" [ get_ports "clk_133m_ddr4_1_p" ]
create_clock -period 7.519 -name "clk_133m_ddr4_0" [ get_ports "clk_133m_ddr4_0_p" ]
create_clock -period 7.519 -name "clk_133m_dimm_1" [ get_ports "clk_133m_dimm_1_p" ]
create_clock -period 7.519 -name "clk_133m_dimm_0" [ get_ports "clk_133m_dimm_0_p" ]
create_clock -period 10.000 -name "clk2_100m_fpga_2i" [ get_ports "clk2_100m_fpga_2i_p" ]
create_clock -period 10.000 -name "clk2_100m_fpga_2j_0" [ get_ports "clk2_100m_fpga_2j_0_p" ]
create_clock -period 10.000 -name "clk2_100m_fpga_2j_1" [ get_ports "clk2_100m_fpga_2j_1_p" ]
create_clock -period 10.000 -name "clk_100m_fpga_3h" [ get_ports "clk_100m_fpga_3h_p" ]
create_clock -period 10.000 -name "clk_100m_fpga_3l_0" [ get_ports "clk_100m_fpga_3l_0_p" ]
create_clock -period 10.000 -name "clk_100m_fpga_3l_1" [ get_ports "clk_100m_fpga_3l_1_p" ]
create_clock -period 20.000 -name "clk2_fpga_50m" [ get_ports "clk2_fpga_50m" ]
create_clock -period 10.000 -name "clk_100m_pcie_0" [ get_ports "clk_100m_pcie_0_p" ]
create_clock -period 10.000 -name "clk_100m_pcie_1" [ get_ports "clk_100m_pcie_1_p" ]
create_clock -period 10.000 -name "clk_100m_upi0_0" [ get_ports "clk_100m_upi0_0_p" ]
create_clock -period 10.000 -name "clk_100m_upi0_1" [ get_ports "clk_100m_upi0_1_p" ]
create_clock -period 10.000 -name "clk_100m_upi1_0" [ get_ports "clk_100m_upi1_0_p" ]
create_clock -period 10.000 -name "clk_100m_upi1_1" [ get_ports "clk_100m_upi1_1_p" ]
create_clock -period 10.000 -name "clk_100m_upi2_0" [ get_ports "clk_100m_upi2_0_p" ]
create_clock -period 10.000 -name "clk_100m_upi2_1" [ get_ports "clk_100m_upi2_1_p" ]
create_clock -period 3.2 -name "clk_312p5m_qsfp0" [ get_ports "clk_312p5m_qsfp0_p" ]
create_clock -period 6.4 -name "clk_156p25m_qsfp0" [ get_ports "clk_156p25m_qsfp0_p" ]
create_clock -period 3.2 -name "clk_312p5m_qsfp1" [ get_ports "clk_312p5m_qsfp1_p" ]
create_clock -period 6.4 -name "clk_156p25m_qsfp1" [ get_ports "clk_156p25m_qsfp1_p" ]
create_clock -period 3.2 -name "clk_312p5m_qsfp2" [ get_ports "clk_312p5m_qsfp2_p" ]
derive_clock_uncertainty
set_clock_groups -asynchronous -group [ get_clocks "clk_133m_ddr4_1" ]
set_clock_groups -asynchronous -group [ get_clocks "clk_133m_ddr4_0" ]
set_clock_groups -asynchronous -group [ get_clocks "clk_133m_dimm_1" ]
set_clock_groups -asynchronous -group [ get_clocks "clk_133m_dimm_0" ]
set_clock_groups -asynchronous -group [ get_clocks "clk2_100m_fpga_2i" ]
set_clock_groups -asynchronous -group [ get_clocks "clk2_100m_fpga_2j_0" ]
set_clock_groups -asynchronous -group [ get_clocks "clk2_100m_fpga_2j_1" ]
set_clock_groups -asynchronous -group [ get_clocks "clk_100m_fpga_3h" ]
set_clock_groups -asynchronous -group [ get_clocks "clk_100m_fpga_3l_0" ]
set_clock_groups -asynchronous -group [ get_clocks "clk_100m_fpga_3l_1" ]
set_clock_groups -asynchronous -group [ get_clocks "clk2_fpga_50m" ]
set_clock_groups -asynchronous -group [ get_clocks "clk_100m_pcie_0" ]
set_clock_groups -asynchronous -group [ get_clocks "clk_100m_pcie_1" ]
set_clock_groups -asynchronous -group [ get_clocks "clk_100m_upi0_0" ]
set_clock_groups -asynchronous -group [ get_clocks "clk_100m_upi0_1" ]
set_clock_groups -asynchronous -group [ get_clocks "clk_100m_upi1_0" ]
set_clock_groups -asynchronous -group [ get_clocks "clk_100m_upi1_1" ]
set_clock_groups -asynchronous -group [ get_clocks "clk_100m_upi2_0" ]
set_clock_groups -asynchronous -group [ get_clocks "clk_100m_upi2_1" ]
set_clock_groups -asynchronous -group [ get_clocks "clk_312p5m_qsfp0" ]
set_clock_groups -asynchronous -group [ get_clocks "clk_156p25m_qsfp0" ]
set_clock_groups -asynchronous -group [ get_clocks "clk_312p5m_qsfp1" ]
set_clock_groups -asynchronous -group [ get_clocks "clk_156p25m_qsfp1" ]
set_clock_groups -asynchronous -group [ get_clocks "clk_312p5m_qsfp2" ]
# JTAG constraints
create_clock -name "altera_reserved_tck" -period 40.800 "altera_reserved_tck"
set_clock_groups -asynchronous -group [get_clocks "altera_reserved_tck"]
# IO constraints
set_false_path -from "cpu_resetn"
set_false_path -to "user_led_g[*]"
set_false_path -from "pcie_rst_n"
source ../lib/eth/lib/axis/syn/quartus_pro/sync_reset.sdc
# clocking infrastructure
constrain_sync_reset_inst "sync_reset_100mhz_inst"
constrain_sync_reset_inst "ptp_rst_reset_sync_inst"
# PCIe clock
set_clock_groups -asynchronous -group [ get_clocks "pcie_hip_inst|intel_pcie_ptile_ast_0|inst|inst|maib_and_tile|rx_pcs_x2_clk|ch15" ]
# PTP ref clock
set_clock_groups -asynchronous -group [ get_clocks "ref_div_inst|stratix10_clkctrl_0|clkdiv_inst|clock_div2" ]
# E-Tile MACs
proc constrain_etile_mac { inst } {
puts "Inserting timing constraints for MAC $inst"
set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|E100GX4_FEC_PTP_PR.nphy_ptp0|alt_ehipc3_nphy_elane_ptp|tx_clkout|ch0" ]
set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|E100GX4_FEC_PTP_PR.nphy_ptp1|alt_ehipc3_nphy_elane_ptp|tx_clkout|ch0" ]
constrain_sync_reset_inst "$inst|.mac_reset_sync_inst"
}
constrain_etile_mac "qsfp1_mac_inst"
constrain_etile_mac "qsfp2_mac_inst"

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# FPGA settings
FPGA_TOP = fpga
FPGA_FAMILY = "Stratix 10 DX"
FPGA_DEVICE = 1SD280PT2F55E1VG
# Files for synthesis
SYN_FILES = rtl/fpga.v
SYN_FILES += rtl/fpga_core.v
SYN_FILES += rtl/sync_signal.v
SYN_FILES += rtl/avst2axis.v
SYN_FILES += rtl/axis2avst.v
SYN_FILES += rtl/eth_mac_wrapper.v
SYN_FILES += rtl/xcvr_ctrl.v
SYN_FILES += rtl/common/mqnic_core_pcie_ptile.v
SYN_FILES += rtl/common/mqnic_core_pcie.v
SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
SYN_FILES += rtl/common/desc_fetch.v
SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v
SYN_FILES += rtl/common/rx_fifo.v
SYN_FILES += rtl/common/tx_req_mux.v
SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v
SYN_FILES += rtl/common/rx_hash.v
SYN_FILES += rtl/common/rx_checksum.v
SYN_FILES += rtl/common/stats_counter.v
SYN_FILES += rtl/common/stats_collect.v
SYN_FILES += rtl/common/stats_pcie_if.v
SYN_FILES += rtl/common/stats_pcie_tlp.v
SYN_FILES += rtl/common/stats_dma_if_pcie.v
SYN_FILES += rtl/common/stats_dma_latency.v
SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
SYN_FILES += rtl/common/tx_scheduler_rr.v
SYN_FILES += rtl/common/tdma_scheduler.v
SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v
SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v
SYN_FILES += lib/axi/rtl/axil_crossbar_rd.v
SYN_FILES += lib/axi/rtl/axil_crossbar_wr.v
SYN_FILES += lib/axi/rtl/axil_reg_if.v
SYN_FILES += lib/axi/rtl/axil_reg_if_rd.v
SYN_FILES += lib/axi/rtl/axil_reg_if_wr.v
SYN_FILES += lib/axi/rtl/axil_register_rd.v
SYN_FILES += lib/axi/rtl/axil_register_wr.v
SYN_FILES += lib/axi/rtl/arbiter.v
SYN_FILES += lib/axi/rtl/priority_encoder.v
SYN_FILES += lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_demux.v
# Workaround for Quartus MLAB RAM read enable bug
# https://www.intel.com/content/www/us/en/support/programmable/articles/000093130.html
SYN_FILES += rtl/axis_fifo.v
# SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_fc_count.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v
SYN_FILES += lib/pcie/rtl/pcie_msix.v
SYN_FILES += lib/pcie/rtl/irq_rate_limit.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_desc_mux.v
SYN_FILES += lib/pcie/rtl/dma_ram_demux_rd.v
SYN_FILES += lib/pcie/rtl/dma_ram_demux_wr.v
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v
SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v
SYN_FILES += lib/pcie/rtl/pcie_ptile_if.v
SYN_FILES += lib/pcie/rtl/pcie_ptile_if_rx.v
SYN_FILES += lib/pcie/rtl/pcie_ptile_if_tx.v
SYN_FILES += lib/pcie/rtl/pcie_ptile_cfg.v
SYN_FILES += lib/pcie/rtl/pcie_ptile_fc_counter.v
SYN_FILES += lib/pcie/rtl/pulse_merge.v
# IP files
IP_TCL_FILES += ip/reset_release.tcl
IP_TCL_FILES += ip/pcie.tcl
IP_TCL_FILES += ip/mac.tcl
IP_TCL_FILES += ip/ref_div.tcl
# QSF files
QSF_FILES = fpga.qsf
# SDC files
SDC_FILES = fpga.sdc
# Configuration
CONFIG_TCL_FILES = ./config.tcl
include ../common/quartus_pro.mk
program: fpga
quartus_pgm --no_banner --mode=jtag -o "P;$(FPGA_TOP).sof@2"

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# Copyright 2022, The Regents of the University of California.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
# OF SUCH DAMAGE.
#
# The views and conclusions contained in the software and documentation are those
# of the authors and should not be interpreted as representing official policies,
# either expressed or implied, of The Regents of the University of California.
set params [dict create]
# collect build information
set build_date [clock seconds]
set git_hash 00000000
set git_tag ""
if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } {
puts "Error running git or project not under version control"
}
if { [catch {set git_tag [exec git describe --tags HEAD]}] } {
puts "Error running git, project not under version control, or no tag found"
}
puts "Build date: ${build_date}"
puts "Git hash: ${git_hash}"
puts "Git tag: ${git_tag}"
if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } {
puts "Failed to extract version from git tag"
set tag_ver 0.0.1
}
puts "Tag version: ${tag_ver}"
# FW and board IDs
set fpga_id [expr 0xC32450DD]
set fw_id [expr 0x00000000]
set fw_ver $tag_ver
set board_vendor_id [expr 0x1172]
set board_device_id [expr 0xA00D]
set board_ver 1.0
set release_info [expr 0x00000000]
# PCIe IDs
set pcie_vendor_id [expr 0x1234]
set pcie_device_id [expr 0x1001]
set pcie_class_code [expr 0x020000]
set pcie_revision_id [expr 0x00]
set pcie_subsystem_vendor_id $board_vendor_id
set pcie_subsystem_device_id $board_device_id
dict set params FPGA_ID [format "32'h%08x" $fpga_id]
dict set params FW_ID [format "32'h%08x" $fw_id]
dict set params FW_VER [format "32'h%02x%02x%02x%02x" {*}[split $fw_ver .-] 0 0 0 0]
dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id]
dict set params BOARD_VER [format "32'h%02x%02x%02x%02x" {*}[split $board_ver .-] 0 0 0 0]
dict set params BUILD_DATE "32'd${build_date}"
dict set params GIT_HASH "32'h${git_hash}"
dict set params RELEASE_INFO [format "32'h%08x" $release_info]
# Structural configuration
dict set params IF_COUNT "2"
dict set params PORTS_PER_IF "1"
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
dict set params PORT_MASK "0"
# Clock configuration
dict set params CLK_PERIOD_NS_NUM "4"
dict set params CLK_PERIOD_NS_DENOM "1"
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"
dict set params PTP_CLOCK_CDC_PIPELINE "0"
dict set params PTP_PORT_CDC_PIPELINE "1"
dict set params PTP_PEROUT_ENABLE "1"
dict set params PTP_PEROUT_COUNT "1"
# Queue manager configuration
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "10"
dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
dict set params EVENT_QUEUE_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
dict set params RX_DESC_TABLE_SIZE "32"
dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)]
# Scheduler configuration
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params TDMA_INDEX_WIDTH "6"
# Interface configuration
dict set params PTP_TS_ENABLE "0"
dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "131072"
dict set params MAX_TX_SIZE "9214"
dict set params MAX_RX_SIZE "9214"
dict set params TX_RAM_SIZE "131072"
dict set params RX_RAM_SIZE "131072"
# Application block configuration
dict set params APP_ID "32'h00000000"
dict set params APP_ENABLE "0"
dict set params APP_CTRL_ENABLE "1"
dict set params APP_DMA_ENABLE "1"
dict set params APP_AXIS_DIRECT_ENABLE "1"
dict set params APP_AXIS_SYNC_ENABLE "1"
dict set params APP_AXIS_IF_ENABLE "1"
dict set params APP_STAT_ENABLE "1"
# DMA interface configuration
dict set params DMA_IMM_ENABLE "0"
dict set params DMA_IMM_WIDTH "32"
dict set params DMA_LEN_WIDTH "16"
dict set params DMA_TAG_WIDTH "16"
dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
dict set params RAM_PIPELINE "2"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
# AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32"
dict set params AXIL_CTRL_ADDR_WIDTH "24"
# AXI lite interface configuration (application control)
dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
# Ethernet interface configuration
dict set params AXIS_ETH_TX_PIPELINE "0"
dict set params AXIS_ETH_TX_FIFO_PIPELINE "2"
dict set params AXIS_ETH_TX_TS_PIPELINE "0"
dict set params AXIS_ETH_RX_PIPELINE "0"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
# Statistics counter subsystem
dict set params STAT_ENABLE "1"
dict set params STAT_DMA_ENABLE "1"
dict set params STAT_PCIE_ENABLE "1"
dict set params STAT_INC_WIDTH "24"
dict set params STAT_ID_WIDTH "12"
# PCIe IP core settings
set pcie intel_pcie_ptile_ast_0
set pcie_ip pcie
set core core16
set fp [open "update_ip_${pcie_ip}.tcl" "w"]
puts $fp "package require qsys"
puts $fp "load_system ip/${pcie_ip}.ip"
# PCIe IDs
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_pci_type0_device_id_hwtcl} {$pcie_device_id}"
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_pci_type0_vendor_id_hwtcl} {$pcie_vendor_id}"
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_class_code_hwtcl} {$pcie_class_code}"
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_revision_id_hwtcl} {$pcie_revision_id}"
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_subsys_dev_id_hwtcl} {$pcie_subsystem_device_id}"
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_subsys_vendor_id_hwtcl} {$pcie_subsystem_vendor_id}"
# PCIe IP core configuration
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_pci_msix_table_size_hwtcl} {[expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]}"
# configure BAR settings
proc configure_bar {fp pcie core pf bar aperture} {
if {$aperture > 0} {
puts "PF${pf} BAR${bar}: aperture ${aperture} bits"
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf${pf}_bar${bar}_address_width_hwtcl} {${aperture}}"
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf${pf}_bar${bar}_type_hwtcl} {64-bit prefetchable memory}"
return
}
puts "PF${pf} BAR${bar}: disabled"
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf${pf}_bar${bar}_address_width_hwtcl} {0}"
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf${pf}_bar${bar}_type_hwtcl} {Disabled}"
}
# Control BAR (BAR 0)
configure_bar $fp $pcie $core 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH]
# Application BAR (BAR 2)
configure_bar $fp $pcie $core 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0]
puts $fp "save_system"
close $fp
# apply parameters to PCIe IP core
exec -ignorestderr qsys-script "--qpf=fpga.qpf" "--script=update_ip_${pcie_ip}.tcl"
# apply parameters to top-level
dict for {name value} $params {
set_parameter -name $name $value
}

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# FPGA settings
FPGA_TOP = fpga
FPGA_FAMILY = "Stratix 10 DX"
FPGA_DEVICE = 1SD280PT2F55E1VG
# Files for synthesis
SYN_FILES = rtl/fpga.v
SYN_FILES += rtl/fpga_core.v
SYN_FILES += rtl/sync_signal.v
SYN_FILES += rtl/avst2axis.v
SYN_FILES += rtl/axis2avst.v
SYN_FILES += rtl/eth_mac_wrapper.v
SYN_FILES += rtl/xcvr_ctrl.v
SYN_FILES += rtl/common/mqnic_core_pcie_ptile.v
SYN_FILES += rtl/common/mqnic_core_pcie.v
SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_port_tx.v
SYN_FILES += rtl/common/mqnic_port_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_l2_egress.v
SYN_FILES += rtl/common/mqnic_l2_ingress.v
SYN_FILES += rtl/common/mqnic_rx_queue_map.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
SYN_FILES += rtl/common/mqnic_rb_clk_info.v
SYN_FILES += rtl/common/mqnic_port_map_mac_axis.v
SYN_FILES += rtl/common/cpl_write.v
SYN_FILES += rtl/common/cpl_op_mux.v
SYN_FILES += rtl/common/desc_fetch.v
SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v
SYN_FILES += rtl/common/rx_fifo.v
SYN_FILES += rtl/common/tx_req_mux.v
SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v
SYN_FILES += rtl/common/rx_hash.v
SYN_FILES += rtl/common/rx_checksum.v
SYN_FILES += rtl/common/stats_counter.v
SYN_FILES += rtl/common/stats_collect.v
SYN_FILES += rtl/common/stats_pcie_if.v
SYN_FILES += rtl/common/stats_pcie_tlp.v
SYN_FILES += rtl/common/stats_dma_if_pcie.v
SYN_FILES += rtl/common/stats_dma_latency.v
SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
SYN_FILES += rtl/common/tx_scheduler_rr.v
SYN_FILES += rtl/common/tdma_scheduler.v
SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
SYN_FILES += app/dma_bench/rtl/dma_bench.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v
SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v
SYN_FILES += lib/axi/rtl/axil_crossbar_rd.v
SYN_FILES += lib/axi/rtl/axil_crossbar_wr.v
SYN_FILES += lib/axi/rtl/axil_reg_if.v
SYN_FILES += lib/axi/rtl/axil_reg_if_rd.v
SYN_FILES += lib/axi/rtl/axil_reg_if_wr.v
SYN_FILES += lib/axi/rtl/axil_register_rd.v
SYN_FILES += lib/axi/rtl/axil_register_wr.v
SYN_FILES += lib/axi/rtl/arbiter.v
SYN_FILES += lib/axi/rtl/priority_encoder.v
SYN_FILES += lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_demux.v
# Workaround for Quartus MLAB RAM read enable bug
# https://www.intel.com/content/www/us/en/support/programmable/articles/000093130.html
SYN_FILES += rtl/axis_fifo.v
# SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_fc_count.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v
SYN_FILES += lib/pcie/rtl/pcie_msix.v
SYN_FILES += lib/pcie/rtl/irq_rate_limit.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v
SYN_FILES += lib/pcie/rtl/dma_if_desc_mux.v
SYN_FILES += lib/pcie/rtl/dma_ram_demux_rd.v
SYN_FILES += lib/pcie/rtl/dma_ram_demux_wr.v
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v
SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v
SYN_FILES += lib/pcie/rtl/pcie_ptile_if.v
SYN_FILES += lib/pcie/rtl/pcie_ptile_if_rx.v
SYN_FILES += lib/pcie/rtl/pcie_ptile_if_tx.v
SYN_FILES += lib/pcie/rtl/pcie_ptile_cfg.v
SYN_FILES += lib/pcie/rtl/pcie_ptile_fc_counter.v
SYN_FILES += lib/pcie/rtl/pulse_merge.v
# IP files
IP_TCL_FILES += ip/reset_release.tcl
IP_TCL_FILES += ip/pcie.tcl
IP_TCL_FILES += ip/mac.tcl
IP_TCL_FILES += ip/ref_div.tcl
# QSF files
QSF_FILES = fpga.qsf
# SDC files
SDC_FILES = fpga.sdc
# Configuration
CONFIG_TCL_FILES = ./config.tcl
include ../common/quartus_pro.mk
program: fpga
quartus_pgm --no_banner --mode=jtag -o "P;$(FPGA_TOP).sof@2"

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# Copyright 2022, The Regents of the University of California.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
# OF SUCH DAMAGE.
#
# The views and conclusions contained in the software and documentation are those
# of the authors and should not be interpreted as representing official policies,
# either expressed or implied, of The Regents of the University of California.
set params [dict create]
# collect build information
set build_date [clock seconds]
set git_hash 00000000
set git_tag ""
if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } {
puts "Error running git or project not under version control"
}
if { [catch {set git_tag [exec git describe --tags HEAD]}] } {
puts "Error running git, project not under version control, or no tag found"
}
puts "Build date: ${build_date}"
puts "Git hash: ${git_hash}"
puts "Git tag: ${git_tag}"
if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } {
puts "Failed to extract version from git tag"
set tag_ver 0.0.1
}
puts "Tag version: ${tag_ver}"
# FW and board IDs
set fpga_id [expr 0xC32450DD]
set fw_id [expr 0x00000000]
set fw_ver $tag_ver
set board_vendor_id [expr 0x1172]
set board_device_id [expr 0xA00D]
set board_ver 1.0
set release_info [expr 0x00000000]
# PCIe IDs
set pcie_vendor_id [expr 0x1234]
set pcie_device_id [expr 0x1001]
set pcie_class_code [expr 0x020000]
set pcie_revision_id [expr 0x00]
set pcie_subsystem_vendor_id $board_vendor_id
set pcie_subsystem_device_id $board_device_id
dict set params FPGA_ID [format "32'h%08x" $fpga_id]
dict set params FW_ID [format "32'h%08x" $fw_id]
dict set params FW_VER [format "32'h%02x%02x%02x%02x" {*}[split $fw_ver .-] 0 0 0 0]
dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id]
dict set params BOARD_VER [format "32'h%02x%02x%02x%02x" {*}[split $board_ver .-] 0 0 0 0]
dict set params BUILD_DATE "32'd${build_date}"
dict set params GIT_HASH "32'h${git_hash}"
dict set params RELEASE_INFO [format "32'h%08x" $release_info]
# Structural configuration
dict set params IF_COUNT "2"
dict set params PORTS_PER_IF "1"
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
dict set params PORT_MASK "0"
# Clock configuration
dict set params CLK_PERIOD_NS_NUM "4"
dict set params CLK_PERIOD_NS_DENOM "1"
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"
dict set params PTP_CLOCK_CDC_PIPELINE "0"
dict set params PTP_PORT_CDC_PIPELINE "1"
dict set params PTP_PEROUT_ENABLE "1"
dict set params PTP_PEROUT_COUNT "1"
# Queue manager configuration
dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_QUEUE_OP_TABLE_SIZE "32"
dict set params RX_QUEUE_OP_TABLE_SIZE "32"
dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
dict set params EVENT_QUEUE_INDEX_WIDTH "6"
dict set params TX_QUEUE_INDEX_WIDTH "10"
dict set params RX_QUEUE_INDEX_WIDTH "8"
dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
dict set params EVENT_QUEUE_PIPELINE "3"
dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
# TX and RX engine configuration
dict set params TX_DESC_TABLE_SIZE "32"
dict set params RX_DESC_TABLE_SIZE "32"
dict set params RX_INDIR_TBL_ADDR_WIDTH [expr min([dict get $params RX_QUEUE_INDEX_WIDTH], 8)]
# Scheduler configuration
dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
dict set params TDMA_INDEX_WIDTH "6"
# Interface configuration
dict set params PTP_TS_ENABLE "0"
dict set params TX_CPL_FIFO_DEPTH "32"
dict set params TX_CHECKSUM_ENABLE "1"
dict set params RX_HASH_ENABLE "1"
dict set params RX_CHECKSUM_ENABLE "1"
dict set params TX_FIFO_DEPTH "32768"
dict set params RX_FIFO_DEPTH "131072"
dict set params MAX_TX_SIZE "9214"
dict set params MAX_RX_SIZE "9214"
dict set params TX_RAM_SIZE "131072"
dict set params RX_RAM_SIZE "131072"
# Application block configuration
dict set params APP_ID "32'h12348001"
dict set params APP_ENABLE "1"
dict set params APP_CTRL_ENABLE "1"
dict set params APP_DMA_ENABLE "1"
dict set params APP_AXIS_DIRECT_ENABLE "1"
dict set params APP_AXIS_SYNC_ENABLE "1"
dict set params APP_AXIS_IF_ENABLE "1"
dict set params APP_STAT_ENABLE "1"
# DMA interface configuration
dict set params DMA_IMM_ENABLE "0"
dict set params DMA_IMM_WIDTH "32"
dict set params DMA_LEN_WIDTH "16"
dict set params DMA_TAG_WIDTH "16"
dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
dict set params RAM_PIPELINE "2"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
# AXI lite interface configuration (control)
dict set params AXIL_CTRL_DATA_WIDTH "32"
dict set params AXIL_CTRL_ADDR_WIDTH "24"
# AXI lite interface configuration (application control)
dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
# Ethernet interface configuration
dict set params AXIS_ETH_TX_PIPELINE "0"
dict set params AXIS_ETH_TX_FIFO_PIPELINE "2"
dict set params AXIS_ETH_TX_TS_PIPELINE "0"
dict set params AXIS_ETH_RX_PIPELINE "0"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
# Statistics counter subsystem
dict set params STAT_ENABLE "1"
dict set params STAT_DMA_ENABLE "1"
dict set params STAT_PCIE_ENABLE "1"
dict set params STAT_INC_WIDTH "24"
dict set params STAT_ID_WIDTH "12"
# PCIe IP core settings
set pcie intel_pcie_ptile_ast_0
set pcie_ip pcie
set core core16
set fp [open "update_ip_${pcie_ip}.tcl" "w"]
puts $fp "package require qsys"
puts $fp "load_system ip/${pcie_ip}.ip"
# PCIe IDs
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_pci_type0_device_id_hwtcl} {$pcie_device_id}"
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_pci_type0_vendor_id_hwtcl} {$pcie_vendor_id}"
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_class_code_hwtcl} {$pcie_class_code}"
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_revision_id_hwtcl} {$pcie_revision_id}"
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_subsys_dev_id_hwtcl} {$pcie_subsystem_device_id}"
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_subsys_vendor_id_hwtcl} {$pcie_subsystem_vendor_id}"
# PCIe IP core configuration
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf0_pci_msix_table_size_hwtcl} {[expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]}"
# configure BAR settings
proc configure_bar {fp pcie core pf bar aperture} {
if {$aperture > 0} {
puts "PF${pf} BAR${bar}: aperture ${aperture} bits"
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf${pf}_bar${bar}_address_width_hwtcl} {${aperture}}"
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf${pf}_bar${bar}_type_hwtcl} {64-bit prefetchable memory}"
return
}
puts "PF${pf} BAR${bar}: disabled"
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf${pf}_bar${bar}_address_width_hwtcl} {0}"
puts $fp "set_instance_parameter_value ${pcie} {${core}_pf${pf}_bar${bar}_type_hwtcl} {Disabled}"
}
# Control BAR (BAR 0)
configure_bar $fp $pcie $core 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH]
# Application BAR (BAR 2)
configure_bar $fp $pcie $core 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0]
puts $fp "save_system"
close $fp
# apply parameters to PCIe IP core
exec -ignorestderr qsys-script "--qpf=fpga.qpf" "--script=update_ip_${pcie_ip}.tcl"
# apply parameters to top-level
dict for {name value} $params {
set_parameter -name $name $value
}

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package require -exact qsys 21.3
# create the system "iopll_etile_ptp"
proc do_create_iopll_etile_ptp {} {
# create the system
create_system iopll_etile_ptp
set_project_property DEVICE {1SD280PT2F55E1VG}
set_project_property DEVICE_FAMILY {Stratix 10}
set_project_property HIDE_FROM_IP_CATALOG {true}
set_use_testbench_naming_pattern 0 {}
# add HDL parameters
# add the components
add_instance iopll_0 altera_iopll
set_instance_parameter_value iopll_0 {gui_active_clk} {0}
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src0} {c_m_cnt_in_src_ph_mux_clk}
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src1} {c_m_cnt_in_src_ph_mux_clk}
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src2} {c_m_cnt_in_src_ph_mux_clk}
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src3} {c_m_cnt_in_src_ph_mux_clk}
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src4} {c_m_cnt_in_src_ph_mux_clk}
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src5} {c_m_cnt_in_src_ph_mux_clk}
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src6} {c_m_cnt_in_src_ph_mux_clk}
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src7} {c_m_cnt_in_src_ph_mux_clk}
set_instance_parameter_value iopll_0 {gui_c_cnt_in_src8} {c_m_cnt_in_src_ph_mux_clk}
set_instance_parameter_value iopll_0 {gui_cal_code_hex_file} {iossm.hex}
set_instance_parameter_value iopll_0 {gui_cal_converge} {0}
set_instance_parameter_value iopll_0 {gui_cal_error} {cal_clean}
set_instance_parameter_value iopll_0 {gui_cascade_counter0} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter1} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter10} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter11} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter12} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter13} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter14} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter15} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter16} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter17} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter2} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter3} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter4} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter5} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter6} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter7} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter8} {0}
set_instance_parameter_value iopll_0 {gui_cascade_counter9} {0}
set_instance_parameter_value iopll_0 {gui_cascade_outclk_index} {0}
set_instance_parameter_value iopll_0 {gui_clk_bad} {0}
set_instance_parameter_value iopll_0 {gui_clock_name_global} {0}
set_instance_parameter_value iopll_0 {gui_clock_name_string0} {outclk0}
set_instance_parameter_value iopll_0 {gui_clock_name_string1} {outclk1}
set_instance_parameter_value iopll_0 {gui_clock_name_string10} {outclk10}
set_instance_parameter_value iopll_0 {gui_clock_name_string11} {outclk11}
set_instance_parameter_value iopll_0 {gui_clock_name_string12} {outclk12}
set_instance_parameter_value iopll_0 {gui_clock_name_string13} {outclk13}
set_instance_parameter_value iopll_0 {gui_clock_name_string14} {outclk14}
set_instance_parameter_value iopll_0 {gui_clock_name_string15} {outclk15}
set_instance_parameter_value iopll_0 {gui_clock_name_string16} {outclk16}
set_instance_parameter_value iopll_0 {gui_clock_name_string17} {outclk17}
set_instance_parameter_value iopll_0 {gui_clock_name_string2} {outclk2}
set_instance_parameter_value iopll_0 {gui_clock_name_string3} {outclk3}
set_instance_parameter_value iopll_0 {gui_clock_name_string4} {outclk4}
set_instance_parameter_value iopll_0 {gui_clock_name_string5} {outclk5}
set_instance_parameter_value iopll_0 {gui_clock_name_string6} {outclk6}
set_instance_parameter_value iopll_0 {gui_clock_name_string7} {outclk7}
set_instance_parameter_value iopll_0 {gui_clock_name_string8} {outclk8}
set_instance_parameter_value iopll_0 {gui_clock_name_string9} {outclk9}
set_instance_parameter_value iopll_0 {gui_clock_to_compensate} {0}
set_instance_parameter_value iopll_0 {gui_debug_mode} {0}
set_instance_parameter_value iopll_0 {gui_divide_factor_c0} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c1} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c10} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c11} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c12} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c13} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c14} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c15} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c16} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c17} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c2} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c3} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c4} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c5} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c6} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c7} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c8} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_c9} {6}
set_instance_parameter_value iopll_0 {gui_divide_factor_n} {1}
set_instance_parameter_value iopll_0 {gui_dps_cntr} {C0}
set_instance_parameter_value iopll_0 {gui_dps_dir} {Positive}
set_instance_parameter_value iopll_0 {gui_dps_num} {1}
set_instance_parameter_value iopll_0 {gui_dsm_out_sel} {1st_order}
set_instance_parameter_value iopll_0 {gui_duty_cycle0} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle1} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle10} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle11} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle12} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle13} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle14} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle15} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle16} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle17} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle2} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle3} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle4} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle5} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle6} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle7} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle8} {50.0}
set_instance_parameter_value iopll_0 {gui_duty_cycle9} {50.0}
set_instance_parameter_value iopll_0 {gui_en_adv_params} {0}
set_instance_parameter_value iopll_0 {gui_en_dps_ports} {0}
set_instance_parameter_value iopll_0 {gui_en_extclkout_ports} {0}
set_instance_parameter_value iopll_0 {gui_en_iossm_reconf} {0}
set_instance_parameter_value iopll_0 {gui_en_lvds_ports} {Disabled}
set_instance_parameter_value iopll_0 {gui_en_periphery_ports} {0}
set_instance_parameter_value iopll_0 {gui_en_phout_ports} {0}
set_instance_parameter_value iopll_0 {gui_en_reconf} {0}
set_instance_parameter_value iopll_0 {gui_enable_cascade_in} {0}
set_instance_parameter_value iopll_0 {gui_enable_cascade_out} {0}
set_instance_parameter_value iopll_0 {gui_enable_mif_dps} {0}
set_instance_parameter_value iopll_0 {gui_enable_output_counter_cascading} {0}
set_instance_parameter_value iopll_0 {gui_enable_permit_cal} {0}
set_instance_parameter_value iopll_0 {gui_enable_upstream_out_clk} {0}
set_instance_parameter_value iopll_0 {gui_existing_mif_file_path} {~/pll.mif}
set_instance_parameter_value iopll_0 {gui_extclkout_0_source} {C0}
set_instance_parameter_value iopll_0 {gui_extclkout_1_source} {C0}
set_instance_parameter_value iopll_0 {gui_feedback_clock} {Global Clock}
set_instance_parameter_value iopll_0 {gui_fix_vco_frequency} {0}
set_instance_parameter_value iopll_0 {gui_fixed_vco_frequency} {600.0}
set_instance_parameter_value iopll_0 {gui_fixed_vco_frequency_ps} {1667.0}
set_instance_parameter_value iopll_0 {gui_frac_multiply_factor} {1.0}
set_instance_parameter_value iopll_0 {gui_fractional_cout} {32}
set_instance_parameter_value iopll_0 {gui_include_iossm} {0}
set_instance_parameter_value iopll_0 {gui_location_type} {I/O Bank}
set_instance_parameter_value iopll_0 {gui_lock_setting} {Low Lock Time}
set_instance_parameter_value iopll_0 {gui_mif_config_name} {unnamed}
set_instance_parameter_value iopll_0 {gui_mif_gen_options} {Generate New MIF File}
set_instance_parameter_value iopll_0 {gui_multiply_factor} {6}
set_instance_parameter_value iopll_0 {gui_new_mif_file_path} {~/pll.mif}
set_instance_parameter_value iopll_0 {gui_number_of_clocks} {1}
set_instance_parameter_value iopll_0 {gui_operation_mode} {direct}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency0} {114.285714}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency1} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency10} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency11} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency12} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency13} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency14} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency15} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency16} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency17} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency2} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency3} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency4} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency5} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency6} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency7} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency8} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency9} {100.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps0} {8750.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps1} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps10} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps11} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps12} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps13} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps14} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps15} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps16} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps17} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps2} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps3} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps4} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps5} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps6} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps7} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps8} {10000.0}
set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps9} {10000.0}
set_instance_parameter_value iopll_0 {gui_parameter_table_hex_file} {seq_params_sim.hex}
set_instance_parameter_value iopll_0 {gui_phase_shift0} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift1} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift10} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift11} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift12} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift13} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift14} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift15} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift16} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift17} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift2} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift3} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift4} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift5} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift6} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift7} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift8} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift9} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg0} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg1} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg10} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg11} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg12} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg13} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg14} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg15} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg16} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg17} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg2} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg3} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg4} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg5} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg6} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg7} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg8} {0.0}
set_instance_parameter_value iopll_0 {gui_phase_shift_deg9} {0.0}
set_instance_parameter_value iopll_0 {gui_phout_division} {1}
set_instance_parameter_value iopll_0 {gui_pll_auto_reset} {0}
set_instance_parameter_value iopll_0 {gui_pll_bandwidth_preset} {Low}
set_instance_parameter_value iopll_0 {gui_pll_cal_done} {0}
set_instance_parameter_value iopll_0 {gui_pll_cascading_mode} {adjpllin}
set_instance_parameter_value iopll_0 {gui_pll_freqcal_en} {1}
set_instance_parameter_value iopll_0 {gui_pll_freqcal_req_flag} {1}
set_instance_parameter_value iopll_0 {gui_pll_m_cnt_in_src} {c_m_cnt_in_src_ph_mux_clk}
set_instance_parameter_value iopll_0 {gui_pll_mode} {Integer-N PLL}
set_instance_parameter_value iopll_0 {gui_pll_tclk_mux_en} {0}
set_instance_parameter_value iopll_0 {gui_pll_tclk_sel} {pll_tclk_m_src}
set_instance_parameter_value iopll_0 {gui_pll_type} {S10_Simple}
set_instance_parameter_value iopll_0 {gui_pll_vco_freq_band_0} {pll_freq_clk0_band18}
set_instance_parameter_value iopll_0 {gui_pll_vco_freq_band_1} {pll_freq_clk1_band18}
set_instance_parameter_value iopll_0 {gui_prot_mode} {UNUSED}
set_instance_parameter_value iopll_0 {gui_ps_units0} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units1} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units10} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units11} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units12} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units13} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units14} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units15} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units16} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units17} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units2} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units3} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units4} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units5} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units6} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units7} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units8} {ps}
set_instance_parameter_value iopll_0 {gui_ps_units9} {ps}
set_instance_parameter_value iopll_0 {gui_refclk1_frequency} {100.0}
set_instance_parameter_value iopll_0 {gui_refclk_might_change} {0}
set_instance_parameter_value iopll_0 {gui_refclk_switch} {0}
set_instance_parameter_value iopll_0 {gui_reference_clock_frequency} {100.0}
set_instance_parameter_value iopll_0 {gui_reference_clock_frequency_ps} {10000.0}
set_instance_parameter_value iopll_0 {gui_simulation_type} {0}
set_instance_parameter_value iopll_0 {gui_skip_sdc_generation} {0}
set_instance_parameter_value iopll_0 {gui_switchover_delay} {0}
set_instance_parameter_value iopll_0 {gui_switchover_mode} {Automatic Switchover}
set_instance_parameter_value iopll_0 {gui_use_NDFB_modes} {0}
set_instance_parameter_value iopll_0 {gui_use_coreclk} {0}
set_instance_parameter_value iopll_0 {gui_use_locked} {1}
set_instance_parameter_value iopll_0 {gui_use_logical} {0}
set_instance_parameter_value iopll_0 {gui_usr_device_speed_grade} {1}
set_instance_parameter_value iopll_0 {gui_vco_frequency} {600.0}
set_instance_parameter_value iopll_0 {hp_qsys_scripting_mode} {0}
set_instance_parameter_value iopll_0 {system_info_device_iobank_rev} {}
set_instance_property iopll_0 AUTO_EXPORT true
# add wirelevel expressions
# preserve ports for debug
# add the exports
set_interface_property reset EXPORT_OF iopll_0.reset
set_interface_property refclk EXPORT_OF iopll_0.refclk
set_interface_property locked EXPORT_OF iopll_0.locked
set_interface_property outclk0 EXPORT_OF iopll_0.outclk0
# set values for exposed HDL parameters
# set the the module properties
set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
<bonusData>
<element __value="iopll_0">
<datum __value="_sortIndex" value="0" type="int" />
</element>
</bonusData>
}
set_module_property FILE {iopll_etile_ptp.ip}
set_module_property GENERATION_ID {0x00000000}
set_module_property NAME {iopll_etile_ptp}
# save the system
sync_sysinfo_parameters
save_system iopll_etile_ptp
}
proc do_set_exported_interface_sysinfo_parameters {} {
}
# create all the systems, from bottom up
do_create_iopll_etile_ptp
# set system info parameters on exported interface, from bottom up
do_set_exported_interface_sysinfo_parameters

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package require -exact qsys 21.3
# create the system "mac"
proc do_create_mac {} {
# create the system
create_system mac
set_project_property BOARD {Intel Stratix 10 DX FPGA Development Kit DK-DEV-1SDX-P-A}
set_project_property DEVICE {1SD280PT2F55E1VG}
set_project_property DEVICE_FAMILY {Stratix 10}
set_project_property HIDE_FROM_IP_CATALOG {true}
set_use_testbench_naming_pattern 0 {}
# add HDL parameters
# add the components
add_instance alt_ehipc3_0 alt_ehipc3
set_instance_parameter_value alt_ehipc3_0 {AIB_test_sl} {0}
set_instance_parameter_value alt_ehipc3_0 {AN_CHAN} {0}
set_instance_parameter_value alt_ehipc3_0 {AN_PAUSE_C0} {1}
set_instance_parameter_value alt_ehipc3_0 {AN_PAUSE_C1} {1}
set_instance_parameter_value alt_ehipc3_0 {AVMM_test} {0}
set_instance_parameter_value alt_ehipc3_0 {AVMM_test_sl} {0}
set_instance_parameter_value alt_ehipc3_0 {CR_MODE} {1}
set_instance_parameter_value alt_ehipc3_0 {DEV_BOARD} {0}
set_instance_parameter_value alt_ehipc3_0 {EHIP_LOCATION} {0}
set_instance_parameter_value alt_ehipc3_0 {ENABLE_ADME} {1}
set_instance_parameter_value alt_ehipc3_0 {ENABLE_ADME_PTP_CHANNEL} {0}
set_instance_parameter_value alt_ehipc3_0 {ENABLE_AN} {1}
set_instance_parameter_value alt_ehipc3_0 {ENABLE_ANLT} {0}
set_instance_parameter_value alt_ehipc3_0 {ENABLE_ASYNC_ADAPTERS} {0}
set_instance_parameter_value alt_ehipc3_0 {ENABLE_ASYNC_ADAPTERS_SL} {0}
set_instance_parameter_value alt_ehipc3_0 {ENABLE_JTAG_AVMM} {0}
set_instance_parameter_value alt_ehipc3_0 {ENABLE_LT} {1}
set_instance_parameter_value alt_ehipc3_0 {ENABLE_PPM_TODSYNC} {1}
set_instance_parameter_value alt_ehipc3_0 {ENABLE_PTP} {1}
set_instance_parameter_value alt_ehipc3_0 {ENABLE_PTP_PPM} {0}
set_instance_parameter_value alt_ehipc3_0 {ENABLE_PTP_RX_DESKEW} {1}
set_instance_parameter_value alt_ehipc3_0 {ENABLE_PTP_TOG} {0}
set_instance_parameter_value alt_ehipc3_0 {ENABLE_RSFEC} {1}
set_instance_parameter_value alt_ehipc3_0 {ENABLE_SYNCE} {0}
set_instance_parameter_value alt_ehipc3_0 {ENHANCED_PTP_ACCURACY} {0}
set_instance_parameter_value alt_ehipc3_0 {ENHANCED_PTP_DBG} {0}
set_instance_parameter_value alt_ehipc3_0 {EN_DYN_FEC} {0}
set_instance_parameter_value alt_ehipc3_0 {EXAMPLE_DESIGN} {1}
set_instance_parameter_value alt_ehipc3_0 {GEN_SIM} {1}
set_instance_parameter_value alt_ehipc3_0 {GEN_SYNTH} {1}
set_instance_parameter_value alt_ehipc3_0 {HDL_FORMAT} {1}
set_instance_parameter_value alt_ehipc3_0 {LINK_TIMER_KR} {504}
set_instance_parameter_value alt_ehipc3_0 {PHY_REFCLK} {156.250000}
set_instance_parameter_value alt_ehipc3_0 {PHY_REFCLK_sl_0} {156.250000}
set_instance_parameter_value alt_ehipc3_0 {PPM_VALUE_RX} {0}
set_instance_parameter_value alt_ehipc3_0 {PPM_VALUE_TX} {0}
set_instance_parameter_value alt_ehipc3_0 {RECONFIG_1025} {0}
set_instance_parameter_value alt_ehipc3_0 {REQUEST_RSFEC} {1}
set_instance_parameter_value alt_ehipc3_0 {RSFEC_CLOCKING_MODE} {ehip_common_clk}
set_instance_parameter_value alt_ehipc3_0 {RSFEC_FIRST_LANE_SEL} {first_lane0}
set_instance_parameter_value alt_ehipc3_0 {SL_OPT} {2}
set_instance_parameter_value alt_ehipc3_0 {STATUS_CLK_MHZ} {100.0}
set_instance_parameter_value alt_ehipc3_0 {USE_PTP_PLLCH} {1}
set_instance_parameter_value alt_ehipc3_0 {XCVR_test} {0}
set_instance_parameter_value alt_ehipc3_0 {active_channel} {1}
set_instance_parameter_value alt_ehipc3_0 {additional_ipg_removed} {0}
set_instance_parameter_value alt_ehipc3_0 {additional_ipg_removed_sl_0} {0}
set_instance_parameter_value alt_ehipc3_0 {adpt_multi_enable} {1}
set_instance_parameter_value alt_ehipc3_0 {adpt_recipe_cnt} {1}
set_instance_parameter_value alt_ehipc3_0 {adpt_recipe_data0} {ctle_lf_val_a 999 ctle_lf_val_ada_a adaptable ctle_lf_min_a 999 ctle_lf_max_a 3 ctle_hf_val_a 999 ctle_hf_val_ada_a adaptable ctle_hf_min_a 999 ctle_hf_max_a 999 rf_p2_val_a 999 rf_p2_val_ada_a fix rf_p2_min_a 999 rf_p2_max_a 999 rf_p1_val_a 999 rf_p1_val_ada_a adaptable rf_p1_min_a 999 rf_p1_max_a 6 rf_reserved0_a 999 rf_p0_val_a 999 rf_p0_val_ada_a adaptable rf_reserved1_a 999 rf_b0t_a 10 ctle_gs1_val_a 2 ctle_gs2_val_a 2 rf_b1_a 1 rf_b1_ada_a fix rf_b0_a 1 rf_b0_ada_a fix rf_a_a 130 ctle_lf_val_b 999 ctle_lf_val_ada_b fix ctle_lf_min_b 999 ctle_lf_max_b 3 ctle_hf_val_b 999 ctle_hf_val_ada_b adaptable ctle_hf_min_b 999 ctle_hf_max_b 999 rf_p2_val_b 999 rf_p2_val_ada_b fix rf_p2_min_b 999 rf_p2_max_b 999 rf_p1_val_b 999 rf_p1_val_ada_b adaptable rf_p1_min_b 999 rf_p1_max_b 6 rf_reserved0_b 999 rf_p0_val_b 999 rf_p0_val_ada_b adaptable rf_reserved1_b 999 rf_b0t_b 10 ctle_gs1_val_b 2 ctle_gs2_val_b 2 rf_b1_b 8 rf_b1_ada_b fix rf_b0_b 1 rf_b0_ada_b fix rf_a_b 130}
set_instance_parameter_value alt_ehipc3_0 {adpt_recipe_data1} {}
set_instance_parameter_value alt_ehipc3_0 {adpt_recipe_data2} {}
set_instance_parameter_value alt_ehipc3_0 {adpt_recipe_data3} {}
set_instance_parameter_value alt_ehipc3_0 {adpt_recipe_data4} {}
set_instance_parameter_value alt_ehipc3_0 {adpt_recipe_data5} {}
set_instance_parameter_value alt_ehipc3_0 {adpt_recipe_data6} {}
set_instance_parameter_value alt_ehipc3_0 {adpt_recipe_data7} {}
set_instance_parameter_value alt_ehipc3_0 {adpt_recipe_select} {0}
set_instance_parameter_value alt_ehipc3_0 {cal_recipe_sel} {NRZ_28Gbps_LR}
set_instance_parameter_value alt_ehipc3_0 {core_variant} {3}
set_instance_parameter_value alt_ehipc3_0 {cpri_PHY_REFCLK} {184.320000}
set_instance_parameter_value alt_ehipc3_0 {cpri_ehip_rate_gui} {2}
set_instance_parameter_value alt_ehipc3_0 {cpri_enable_custom_sl_0} {1}
set_instance_parameter_value alt_ehipc3_0 {cpri_include_alternate_ports} {0}
set_instance_parameter_value alt_ehipc3_0 {cpri_include_refclk_mux_sl_0} {0}
set_instance_parameter_value alt_ehipc3_0 {cpri_number_of_channel} {1}
set_instance_parameter_value alt_ehipc3_0 {ctle_gs1_val_a} {2}
set_instance_parameter_value alt_ehipc3_0 {ctle_gs1_val_b} {2}
set_instance_parameter_value alt_ehipc3_0 {ctle_gs2_val_a} {2}
set_instance_parameter_value alt_ehipc3_0 {ctle_gs2_val_b} {2}
set_instance_parameter_value alt_ehipc3_0 {ctle_hf_max_a} {999}
set_instance_parameter_value alt_ehipc3_0 {ctle_hf_max_b} {999}
set_instance_parameter_value alt_ehipc3_0 {ctle_hf_min_a} {999}
set_instance_parameter_value alt_ehipc3_0 {ctle_hf_min_b} {999}
set_instance_parameter_value alt_ehipc3_0 {ctle_hf_val_a} {999}
set_instance_parameter_value alt_ehipc3_0 {ctle_hf_val_ada_a} {adaptable}
set_instance_parameter_value alt_ehipc3_0 {ctle_hf_val_ada_b} {adaptable}
set_instance_parameter_value alt_ehipc3_0 {ctle_hf_val_b} {999}
set_instance_parameter_value alt_ehipc3_0 {ctle_lf_max_a} {3}
set_instance_parameter_value alt_ehipc3_0 {ctle_lf_max_b} {3}
set_instance_parameter_value alt_ehipc3_0 {ctle_lf_min_a} {999}
set_instance_parameter_value alt_ehipc3_0 {ctle_lf_min_b} {999}
set_instance_parameter_value alt_ehipc3_0 {ctle_lf_val_a} {999}
set_instance_parameter_value alt_ehipc3_0 {ctle_lf_val_ada_a} {adaptable}
set_instance_parameter_value alt_ehipc3_0 {ctle_lf_val_ada_b} {fix}
set_instance_parameter_value alt_ehipc3_0 {ctle_lf_val_b} {999}
set_instance_parameter_value alt_ehipc3_0 {custom_pcs_PHY_REFCLK} {250.000000}
set_instance_parameter_value alt_ehipc3_0 {custom_pcs_ehip_mode_gui} {PCS_Only}
set_instance_parameter_value alt_ehipc3_0 {custom_pcs_ehip_rate_gui} {25000}
set_instance_parameter_value alt_ehipc3_0 {custom_pcs_enable_custom} {1}
set_instance_parameter_value alt_ehipc3_0 {custom_pcs_fibre_channel_mode} {disable}
set_instance_parameter_value alt_ehipc3_0 {custom_pcs_include_alternate_ports} {0}
set_instance_parameter_value alt_ehipc3_0 {custom_pcs_modulation} {NRZ}
set_instance_parameter_value alt_ehipc3_0 {custom_pcs_number_of_channel} {1}
set_instance_parameter_value alt_ehipc3_0 {design_environment} {NATIVE}
set_instance_parameter_value alt_ehipc3_0 {dis_anlt_std_recipe} {0}
set_instance_parameter_value alt_ehipc3_0 {disable_internal_dr} {0}
set_instance_parameter_value alt_ehipc3_0 {dr_100g_nrz_pam4} {0}
set_instance_parameter_value alt_ehipc3_0 {dr_25g_cpri} {0}
set_instance_parameter_value alt_ehipc3_0 {duplex_mode} {enable}
set_instance_parameter_value alt_ehipc3_0 {ehip_mode_gui} {MAC+1588PTP+PCS+(528,514)RSFEC}
set_instance_parameter_value alt_ehipc3_0 {ehip_mode_gui_sl_0} {MAC+PTP+PCS+RSFEC}
set_instance_parameter_value alt_ehipc3_0 {ehip_rate_gui} {100G}
set_instance_parameter_value alt_ehipc3_0 {ehip_rate_gui_sl_0} {25G}
set_instance_parameter_value alt_ehipc3_0 {enable_aib_latency_adj_ena_ports} {0}
set_instance_parameter_value alt_ehipc3_0 {enable_custom_sl_0} {0}
set_instance_parameter_value alt_ehipc3_0 {enable_external_aib_clocking} {0}
set_instance_parameter_value alt_ehipc3_0 {enable_internal_options} {0}
set_instance_parameter_value alt_ehipc3_0 {enable_rsfec_rst_ports} {0}
set_instance_parameter_value alt_ehipc3_0 {enforce_max_frame_size_gui} {0}
set_instance_parameter_value alt_ehipc3_0 {enforce_max_frame_size_gui_sl_0} {0}
set_instance_parameter_value alt_ehipc3_0 {flow_control_gui} {No}
set_instance_parameter_value alt_ehipc3_0 {flow_control_gui_sl_0} {No}
set_instance_parameter_value alt_ehipc3_0 {forward_rx_pause_requests_gui} {0}
set_instance_parameter_value alt_ehipc3_0 {forward_rx_pause_requests_gui_sl_0} {0}
set_instance_parameter_value alt_ehipc3_0 {include_alternate_ports_sl_0} {0}
set_instance_parameter_value alt_ehipc3_0 {include_dlat_sl_0} {0}
set_instance_parameter_value alt_ehipc3_0 {include_refclk_mux_sl_0} {0}
set_instance_parameter_value alt_ehipc3_0 {link_fault_mode_gui} {OFF}
set_instance_parameter_value alt_ehipc3_0 {link_fault_mode_gui_sl_0} {OFF}
set_instance_parameter_value alt_ehipc3_0 {number_of_channel} {0}
set_instance_parameter_value alt_ehipc3_0 {preamble_passthrough_gui} {0}
set_instance_parameter_value alt_ehipc3_0 {preamble_passthrough_gui_sl_0} {0}
set_instance_parameter_value alt_ehipc3_0 {preserve_unused_xcvr_channels} {0}
set_instance_parameter_value alt_ehipc3_0 {rcp_load_enable} {1}
set_instance_parameter_value alt_ehipc3_0 {ready_latency} {0}
set_instance_parameter_value alt_ehipc3_0 {ready_latency_sl} {0}
set_instance_parameter_value alt_ehipc3_0 {rf_a_a} {130}
set_instance_parameter_value alt_ehipc3_0 {rf_a_b} {130}
set_instance_parameter_value alt_ehipc3_0 {rf_b0_a} {1}
set_instance_parameter_value alt_ehipc3_0 {rf_b0_ada_a} {fix}
set_instance_parameter_value alt_ehipc3_0 {rf_b0_ada_b} {fix}
set_instance_parameter_value alt_ehipc3_0 {rf_b0_b} {1}
set_instance_parameter_value alt_ehipc3_0 {rf_b0t_a} {10}
set_instance_parameter_value alt_ehipc3_0 {rf_b0t_b} {10}
set_instance_parameter_value alt_ehipc3_0 {rf_b1_a} {1}
set_instance_parameter_value alt_ehipc3_0 {rf_b1_ada_a} {fix}
set_instance_parameter_value alt_ehipc3_0 {rf_b1_ada_b} {fix}
set_instance_parameter_value alt_ehipc3_0 {rf_b1_b} {8}
set_instance_parameter_value alt_ehipc3_0 {rf_p0_val_a} {999}
set_instance_parameter_value alt_ehipc3_0 {rf_p0_val_ada_a} {adaptable}
set_instance_parameter_value alt_ehipc3_0 {rf_p0_val_ada_b} {adaptable}
set_instance_parameter_value alt_ehipc3_0 {rf_p0_val_b} {999}
set_instance_parameter_value alt_ehipc3_0 {rf_p1_max_a} {6}
set_instance_parameter_value alt_ehipc3_0 {rf_p1_max_b} {6}
set_instance_parameter_value alt_ehipc3_0 {rf_p1_min_a} {999}
set_instance_parameter_value alt_ehipc3_0 {rf_p1_min_b} {999}
set_instance_parameter_value alt_ehipc3_0 {rf_p1_val_a} {999}
set_instance_parameter_value alt_ehipc3_0 {rf_p1_val_ada_a} {adaptable}
set_instance_parameter_value alt_ehipc3_0 {rf_p1_val_ada_b} {adaptable}
set_instance_parameter_value alt_ehipc3_0 {rf_p1_val_b} {999}
set_instance_parameter_value alt_ehipc3_0 {rf_p2_max_a} {999}
set_instance_parameter_value alt_ehipc3_0 {rf_p2_max_b} {999}
set_instance_parameter_value alt_ehipc3_0 {rf_p2_min_a} {999}
set_instance_parameter_value alt_ehipc3_0 {rf_p2_min_b} {999}
set_instance_parameter_value alt_ehipc3_0 {rf_p2_val_a} {999}
set_instance_parameter_value alt_ehipc3_0 {rf_p2_val_ada_a} {fix}
set_instance_parameter_value alt_ehipc3_0 {rf_p2_val_ada_b} {fix}
set_instance_parameter_value alt_ehipc3_0 {rf_p2_val_b} {999}
set_instance_parameter_value alt_ehipc3_0 {rf_reserved0_a} {999}
set_instance_parameter_value alt_ehipc3_0 {rf_reserved0_b} {999}
set_instance_parameter_value alt_ehipc3_0 {rf_reserved1_a} {999}
set_instance_parameter_value alt_ehipc3_0 {rf_reserved1_b} {999}
set_instance_parameter_value alt_ehipc3_0 {rx_bytes_to_remove} {Remove CRC bytes}
set_instance_parameter_value alt_ehipc3_0 {rx_bytes_to_remove_sl_0} {Remove CRC bytes}
set_instance_parameter_value alt_ehipc3_0 {rx_max_frame_size_gui} {9214}
set_instance_parameter_value alt_ehipc3_0 {rx_max_frame_size_gui_sl_0} {9214}
set_instance_parameter_value alt_ehipc3_0 {rx_vlan_detection_gui} {1}
set_instance_parameter_value alt_ehipc3_0 {rx_vlan_detection_gui_sl_0} {1}
set_instance_parameter_value alt_ehipc3_0 {source_address_insertion_gui} {0}
set_instance_parameter_value alt_ehipc3_0 {source_address_insertion_gui_sl_0} {0}
set_instance_parameter_value alt_ehipc3_0 {strict_preamble_checking_gui} {0}
set_instance_parameter_value alt_ehipc3_0 {strict_preamble_checking_gui_sl_0} {0}
set_instance_parameter_value alt_ehipc3_0 {strict_sfd_checking_gui} {0}
set_instance_parameter_value alt_ehipc3_0 {strict_sfd_checking_gui_sl_0} {0}
set_instance_parameter_value alt_ehipc3_0 {tx_ipg_size_gui} {12}
set_instance_parameter_value alt_ehipc3_0 {tx_ipg_size_gui_sl_0} {12}
set_instance_parameter_value alt_ehipc3_0 {tx_max_frame_size_gui} {9214}
set_instance_parameter_value alt_ehipc3_0 {tx_max_frame_size_gui_sl_0} {9214}
set_instance_parameter_value alt_ehipc3_0 {tx_vlan_detection_gui} {1}
set_instance_parameter_value alt_ehipc3_0 {tx_vlan_detection_gui_sl_0} {1}
set_instance_parameter_value alt_ehipc3_0 {txmac_saddr_gui} {73588229205}
set_instance_parameter_value alt_ehipc3_0 {user_bti_refclk_freq_mhz} {125}
set_instance_property alt_ehipc3_0 AUTO_EXPORT true
# add wirelevel expressions
# preserve ports for debug
# add the exports
set_interface_property i_stats_snapshot EXPORT_OF alt_ehipc3_0.i_stats_snapshot
set_interface_property o_cdr_lock EXPORT_OF alt_ehipc3_0.o_cdr_lock
set_interface_property o_tx_pll_locked EXPORT_OF alt_ehipc3_0.o_tx_pll_locked
set_interface_property eth_reconfig EXPORT_OF alt_ehipc3_0.eth_reconfig
set_interface_property rsfec_reconfig EXPORT_OF alt_ehipc3_0.rsfec_reconfig
set_interface_property o_tx_lanes_stable EXPORT_OF alt_ehipc3_0.o_tx_lanes_stable
set_interface_property o_rx_pcs_ready EXPORT_OF alt_ehipc3_0.o_rx_pcs_ready
set_interface_property o_ehip_ready EXPORT_OF alt_ehipc3_0.o_ehip_ready
set_interface_property o_rx_block_lock EXPORT_OF alt_ehipc3_0.o_rx_block_lock
set_interface_property o_rx_am_lock EXPORT_OF alt_ehipc3_0.o_rx_am_lock
set_interface_property o_rx_hi_ber EXPORT_OF alt_ehipc3_0.o_rx_hi_ber
set_interface_property o_local_fault_status EXPORT_OF alt_ehipc3_0.o_local_fault_status
set_interface_property o_remote_fault_status EXPORT_OF alt_ehipc3_0.o_remote_fault_status
set_interface_property i_clk_tx EXPORT_OF alt_ehipc3_0.i_clk_tx
set_interface_property i_clk_rx EXPORT_OF alt_ehipc3_0.i_clk_rx
set_interface_property i_csr_rst_n EXPORT_OF alt_ehipc3_0.i_csr_rst_n
set_interface_property i_tx_rst_n EXPORT_OF alt_ehipc3_0.i_tx_rst_n
set_interface_property i_rx_rst_n EXPORT_OF alt_ehipc3_0.i_rx_rst_n
set_interface_property serial_p EXPORT_OF alt_ehipc3_0.serial_p
set_interface_property serial_n EXPORT_OF alt_ehipc3_0.serial_n
set_interface_property i_reconfig_clk EXPORT_OF alt_ehipc3_0.i_reconfig_clk
set_interface_property i_reconfig_reset EXPORT_OF alt_ehipc3_0.i_reconfig_reset
set_interface_property tx_streaming EXPORT_OF alt_ehipc3_0.tx_streaming
set_interface_property rx_streaming EXPORT_OF alt_ehipc3_0.rx_streaming
set_interface_property i_xcvr_reconfig_address EXPORT_OF alt_ehipc3_0.i_xcvr_reconfig_address
set_interface_property i_xcvr_reconfig_read EXPORT_OF alt_ehipc3_0.i_xcvr_reconfig_read
set_interface_property i_xcvr_reconfig_write EXPORT_OF alt_ehipc3_0.i_xcvr_reconfig_write
set_interface_property o_xcvr_reconfig_readdata EXPORT_OF alt_ehipc3_0.o_xcvr_reconfig_readdata
set_interface_property i_xcvr_reconfig_writedata EXPORT_OF alt_ehipc3_0.i_xcvr_reconfig_writedata
set_interface_property o_xcvr_reconfig_waitrequest EXPORT_OF alt_ehipc3_0.o_xcvr_reconfig_waitrequest
set_interface_property i_clk_ref EXPORT_OF alt_ehipc3_0.i_clk_ref
set_interface_property o_clk_pll_div64 EXPORT_OF alt_ehipc3_0.o_clk_pll_div64
set_interface_property o_clk_pll_div66 EXPORT_OF alt_ehipc3_0.o_clk_pll_div66
set_interface_property o_clk_rec_div64 EXPORT_OF alt_ehipc3_0.o_clk_rec_div64
set_interface_property o_clk_rec_div66 EXPORT_OF alt_ehipc3_0.o_clk_rec_div66
set_interface_property i_ptp_reconfig_address EXPORT_OF alt_ehipc3_0.i_ptp_reconfig_address
set_interface_property i_ptp_reconfig_read EXPORT_OF alt_ehipc3_0.i_ptp_reconfig_read
set_interface_property i_ptp_reconfig_write EXPORT_OF alt_ehipc3_0.i_ptp_reconfig_write
set_interface_property o_ptp_reconfig_readdata EXPORT_OF alt_ehipc3_0.o_ptp_reconfig_readdata
set_interface_property i_ptp_reconfig_writedata EXPORT_OF alt_ehipc3_0.i_ptp_reconfig_writedata
set_interface_property o_ptp_reconfig_waitrequest EXPORT_OF alt_ehipc3_0.o_ptp_reconfig_waitrequest
set_interface_property ptp_tod_ports EXPORT_OF alt_ehipc3_0.ptp_tod_ports
set_interface_property ptp_ports EXPORT_OF alt_ehipc3_0.ptp_ports
set_interface_property ptp_1step_ports EXPORT_OF alt_ehipc3_0.ptp_1step_ports
set_interface_property nonpcs_ports EXPORT_OF alt_ehipc3_0.nonpcs_ports
set_interface_property pfc_ports EXPORT_OF alt_ehipc3_0.pfc_ports
set_interface_property pause_ports EXPORT_OF alt_ehipc3_0.pause_ports
# set values for exposed HDL parameters
# set the the module properties
set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
<bonusData>
<element __value="alt_ehipc3_0">
<datum __value="_sortIndex" value="0" type="int" />
</element>
</bonusData>
}
set_module_property FILE {mac.ip}
set_module_property GENERATION_ID {0x00000000}
set_module_property NAME {mac}
# save the system
sync_sysinfo_parameters
save_system mac
}
proc do_set_exported_interface_sysinfo_parameters {} {
}
# create all the systems, from bottom up
do_create_mac
# set system info parameters on exported interface, from bottom up
do_set_exported_interface_sysinfo_parameters

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fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/ip/pcie.tcl Normal file
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package require -exact qsys 21.3
# create the system "ref_div"
proc do_create_ref_div {} {
# create the system
create_system ref_div
set_project_property DEVICE {1SD280PT2F55E1VG}
set_project_property DEVICE_FAMILY {Stratix 10}
set_project_property HIDE_FROM_IP_CATALOG {true}
set_use_testbench_naming_pattern 0 {}
# add HDL parameters
# add the components
add_instance stratix10_clkctrl_0 stratix10_clkctrl
set_instance_parameter_value stratix10_clkctrl_0 {CLOCK_DIVIDER} {1}
set_instance_parameter_value stratix10_clkctrl_0 {CLOCK_DIVIDER_OUTPUTS} {3}
set_instance_parameter_value stratix10_clkctrl_0 {ENABLE} {0}
set_instance_parameter_value stratix10_clkctrl_0 {ENABLE_REGISTER_TYPE} {1}
set_instance_parameter_value stratix10_clkctrl_0 {ENABLE_TYPE} {2}
set_instance_parameter_value stratix10_clkctrl_0 {GLITCH_FREE_SWITCHOVER} {0}
set_instance_parameter_value stratix10_clkctrl_0 {NUM_CLOCKS} {1}
set_instance_property stratix10_clkctrl_0 AUTO_EXPORT true
# add wirelevel expressions
# preserve ports for debug
# add the exports
set_interface_property inclk EXPORT_OF stratix10_clkctrl_0.inclk
set_interface_property clock_div1x EXPORT_OF stratix10_clkctrl_0.clock_div1x
set_interface_property clock_div2x EXPORT_OF stratix10_clkctrl_0.clock_div2x
set_interface_property clock_div4x EXPORT_OF stratix10_clkctrl_0.clock_div4x
# set values for exposed HDL parameters
# set the the module properties
set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
<bonusData>
<element __value="stratix10_clkctrl_0">
<datum __value="_sortIndex" value="0" type="int" />
</element>
</bonusData>
}
set_module_property FILE {ref_div.ip}
set_module_property GENERATION_ID {0x00000000}
set_module_property NAME {ref_div}
# save the system
sync_sysinfo_parameters
save_system ref_div
}
proc do_set_exported_interface_sysinfo_parameters {} {
}
# create all the systems, from bottom up
do_create_ref_div
# set system info parameters on exported interface, from bottom up
do_set_exported_interface_sysinfo_parameters

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package require -exact qsys 21.3
# create the system "reset_release"
proc do_create_reset_release {} {
# create the system
create_system reset_release
set_project_property DEVICE {1SD280PT2F55E1VG}
set_project_property DEVICE_FAMILY {Stratix 10}
set_project_property HIDE_FROM_IP_CATALOG {true}
set_use_testbench_naming_pattern 0 {}
# add HDL parameters
# add the components
add_instance s10_user_rst_clkgate_0 altera_s10_user_rst_clkgate
set_instance_parameter_value s10_user_rst_clkgate_0 {outputType} {Conduit Interface}
set_instance_property s10_user_rst_clkgate_0 AUTO_EXPORT true
# add wirelevel expressions
# preserve ports for debug
# add the exports
set_interface_property ninit_done EXPORT_OF s10_user_rst_clkgate_0.ninit_done
# set values for exposed HDL parameters
# set the the module properties
set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
<bonusData>
<element __value="s10_user_rst_clkgate_0">
<datum __value="_sortIndex" value="0" type="int" />
</element>
</bonusData>
}
set_module_property FILE {reset_release.ip}
set_module_property GENERATION_ID {0x00000000}
set_module_property NAME {reset_release}
# save the system
sync_sysinfo_parameters
save_system reset_release
}
proc do_set_exported_interface_sysinfo_parameters {} {
}
# create all the systems, from bottom up
do_create_reset_release
# set system info parameters on exported interface, from bottom up
do_set_exported_interface_sysinfo_parameters

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../../../lib/

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/*
Copyright (c) 2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Avalon-ST to AXI stream
*/
module avst2axis #(
parameter DATA_WIDTH = 8,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter EMPTY_WIDTH = $clog2(KEEP_WIDTH),
parameter BYTE_REVERSE = 0
)
(
input wire clk,
input wire rst,
output wire avst_ready,
input wire avst_valid,
input wire [DATA_WIDTH-1:0] avst_data,
input wire avst_startofpacket,
input wire avst_endofpacket,
input wire [EMPTY_WIDTH-1:0] avst_empty,
input wire avst_error,
output wire [DATA_WIDTH-1:0] axis_tdata,
output wire [KEEP_WIDTH-1:0] axis_tkeep,
output wire axis_tvalid,
input wire axis_tready,
output wire axis_tlast,
output wire axis_tuser
);
parameter BYTE_WIDTH = KEEP_ENABLE ? DATA_WIDTH / KEEP_WIDTH : DATA_WIDTH;
assign avst_ready = axis_tready;
generate
genvar n;
if (BYTE_REVERSE) begin : rev
for (n = 0; n < KEEP_WIDTH; n = n + 1) begin
assign axis_tdata[n*BYTE_WIDTH +: BYTE_WIDTH] = avst_data[(KEEP_WIDTH-n-1)*BYTE_WIDTH +: BYTE_WIDTH];
end
end else begin
assign axis_tdata = avst_data;
end
endgenerate
assign axis_tkeep = KEEP_ENABLE ? {KEEP_WIDTH{1'b1}} >> avst_empty : 0;
assign axis_tvalid = avst_valid;
assign axis_tlast = avst_endofpacket;
assign axis_tuser = avst_error;
endmodule
`resetall

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/*
Copyright (c) 2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI stream to Avalon-ST
*/
module axis2avst #(
parameter DATA_WIDTH = 8,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter EMPTY_WIDTH = $clog2(KEEP_WIDTH),
parameter BYTE_REVERSE = 0
)
(
input wire clk,
input wire rst,
input wire [DATA_WIDTH-1:0] axis_tdata,
input wire [KEEP_WIDTH-1:0] axis_tkeep,
input wire axis_tvalid,
output wire axis_tready,
input wire axis_tlast,
input wire axis_tuser,
input wire avst_ready,
output wire avst_valid,
output wire [DATA_WIDTH-1:0] avst_data,
output wire avst_startofpacket,
output wire avst_endofpacket,
output wire [EMPTY_WIDTH-1:0] avst_empty,
output wire avst_error
);
parameter BYTE_WIDTH = KEEP_ENABLE ? DATA_WIDTH / KEEP_WIDTH : DATA_WIDTH;
reg frame_reg = 1'b0;
generate
genvar n;
if (BYTE_REVERSE) begin : rev
for (n = 0; n < KEEP_WIDTH; n = n + 1) begin
assign avst_data[n*BYTE_WIDTH +: BYTE_WIDTH] = axis_tdata[(KEEP_WIDTH-n-1)*BYTE_WIDTH +: BYTE_WIDTH];
end
end else begin
assign avst_data = axis_tdata;
end
endgenerate
reg [EMPTY_WIDTH-1:0] empty;
assign avst_empty = empty;
integer k;
always @* begin
empty = KEEP_WIDTH-1;
for (k = 0; k < KEEP_WIDTH; k = k + 1) begin
if (axis_tkeep[k]) begin
empty = KEEP_WIDTH-1-k;
end
end
end
assign avst_valid = axis_tvalid;
assign avst_startofpacket = axis_tvalid & !frame_reg;
assign avst_endofpacket = axis_tlast;
assign avst_error = axis_tuser;
assign axis_tready = avst_ready;
always @(posedge clk) begin
if (axis_tvalid && axis_tready) begin
frame_reg <= !axis_tlast;
end
if (rst) begin
frame_reg <= 1'b0;
end
end
endmodule
`resetall

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/*
Copyright (c) 2013-2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream FIFO
*/
module axis_fifo #
(
// FIFO depth in words
// KEEP_WIDTH words per cycle if KEEP_ENABLE set
// Rounded up to nearest power of 2 cycles
parameter DEPTH = 4096,
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = ((DATA_WIDTH+7)/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
parameter ID_WIDTH = 8,
// Propagate tdest signal
parameter DEST_ENABLE = 0,
// tdest signal width
parameter DEST_WIDTH = 8,
// Propagate tuser signal
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1,
// number of RAM pipeline registers
parameter RAM_PIPELINE = 1,
// use output FIFO
// When set, the RAM read enable and pipeline clock enables are removed
parameter OUTPUT_FIFO_ENABLE = 0,
// Frame FIFO mode - operate on frames instead of cycles
// When set, m_axis_tvalid will not be deasserted within a frame
// Requires LAST_ENABLE set
parameter FRAME_FIFO = 0,
// tuser value for bad frame marker
parameter USER_BAD_FRAME_VALUE = 1'b1,
// tuser mask for bad frame marker
parameter USER_BAD_FRAME_MASK = 1'b1,
// Drop frames larger than FIFO
// Requires FRAME_FIFO set
parameter DROP_OVERSIZE_FRAME = FRAME_FIFO,
// Drop frames marked bad
// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
parameter DROP_BAD_FRAME = 0,
// Drop incoming frames when full
// When set, s_axis_tready is always asserted
// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
parameter DROP_WHEN_FULL = 0
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [ID_WIDTH-1:0] s_axis_tid,
input wire [DEST_WIDTH-1:0] s_axis_tdest,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [ID_WIDTH-1:0] m_axis_tid,
output wire [DEST_WIDTH-1:0] m_axis_tdest,
output wire [USER_WIDTH-1:0] m_axis_tuser,
/*
* Status
*/
output wire status_overflow,
output wire status_bad_frame,
output wire status_good_frame
);
parameter ADDR_WIDTH = (KEEP_ENABLE && KEEP_WIDTH > 1) ? $clog2(DEPTH/KEEP_WIDTH) : $clog2(DEPTH);
parameter OUTPUT_FIFO_ADDR_WIDTH = RAM_PIPELINE < 2 ? 3 : $clog2(RAM_PIPELINE*2+7);
// check configuration
initial begin
if (FRAME_FIFO && !LAST_ENABLE) begin
$error("Error: FRAME_FIFO set requires LAST_ENABLE set (instance %m)");
$finish;
end
if (DROP_OVERSIZE_FRAME && !FRAME_FIFO) begin
$error("Error: DROP_OVERSIZE_FRAME set requires FRAME_FIFO set (instance %m)");
$finish;
end
if (DROP_BAD_FRAME && !(FRAME_FIFO && DROP_OVERSIZE_FRAME)) begin
$error("Error: DROP_BAD_FRAME set requires FRAME_FIFO and DROP_OVERSIZE_FRAME set (instance %m)");
$finish;
end
if (DROP_WHEN_FULL && !(FRAME_FIFO && DROP_OVERSIZE_FRAME)) begin
$error("Error: DROP_WHEN_FULL set requires FRAME_FIFO and DROP_OVERSIZE_FRAME set (instance %m)");
$finish;
end
if (DROP_BAD_FRAME && (USER_BAD_FRAME_MASK & {USER_WIDTH{1'b1}}) == 0) begin
$error("Error: Invalid USER_BAD_FRAME_MASK value (instance %m)");
$finish;
end
end
localparam KEEP_OFFSET = DATA_WIDTH;
localparam LAST_OFFSET = KEEP_OFFSET + (KEEP_ENABLE ? KEEP_WIDTH : 0);
localparam ID_OFFSET = LAST_OFFSET + (LAST_ENABLE ? 1 : 0);
localparam DEST_OFFSET = ID_OFFSET + (ID_ENABLE ? ID_WIDTH : 0);
localparam USER_OFFSET = DEST_OFFSET + (DEST_ENABLE ? DEST_WIDTH : 0);
localparam WIDTH = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0);
reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}};
// (* ramstyle = "no_rw_check" *)
// Workaround for Quartus MLAB RAM read enable bug
// https://www.intel.com/content/www/us/en/support/programmable/articles/000093130.html
(* ramstyle = "no_rw_check, m20k" *)
reg [WIDTH-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg mem_read_data_valid_reg = 1'b0;
(* shreg_extract = "no" *)
reg [WIDTH-1:0] m_axis_pipe_reg[RAM_PIPELINE+1-1:0];
reg [RAM_PIPELINE+1-1:0] m_axis_tvalid_pipe_reg = 0;
// full when first MSB different but rest same
wire full = wr_ptr_reg == (rd_ptr_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}});
wire full_cur = wr_ptr_cur_reg == (rd_ptr_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}});
// empty when pointers match exactly
wire empty = wr_ptr_reg == rd_ptr_reg;
// overflow within packet
wire full_wr = wr_ptr_reg == (wr_ptr_cur_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}});
reg drop_frame_reg = 1'b0;
reg send_frame_reg = 1'b0;
reg overflow_reg = 1'b0;
reg bad_frame_reg = 1'b0;
reg good_frame_reg = 1'b0;
assign s_axis_tready = FRAME_FIFO ? (!full_cur || (full_wr && DROP_OVERSIZE_FRAME) || DROP_WHEN_FULL) : !full;
wire [WIDTH-1:0] s_axis;
generate
assign s_axis[DATA_WIDTH-1:0] = s_axis_tdata;
if (KEEP_ENABLE) assign s_axis[KEEP_OFFSET +: KEEP_WIDTH] = s_axis_tkeep;
if (LAST_ENABLE) assign s_axis[LAST_OFFSET] = s_axis_tlast;
if (ID_ENABLE) assign s_axis[ID_OFFSET +: ID_WIDTH] = s_axis_tid;
if (DEST_ENABLE) assign s_axis[DEST_OFFSET +: DEST_WIDTH] = s_axis_tdest;
if (USER_ENABLE) assign s_axis[USER_OFFSET +: USER_WIDTH] = s_axis_tuser;
endgenerate
wire [WIDTH-1:0] m_axis = m_axis_pipe_reg[RAM_PIPELINE+1-1];
wire m_axis_tvalid_pipe = m_axis_tvalid_pipe_reg[RAM_PIPELINE+1-1];
wire [DATA_WIDTH-1:0] m_axis_tdata_pipe = m_axis[DATA_WIDTH-1:0];
wire [KEEP_WIDTH-1:0] m_axis_tkeep_pipe = KEEP_ENABLE ? m_axis[KEEP_OFFSET +: KEEP_WIDTH] : {KEEP_WIDTH{1'b1}};
wire m_axis_tlast_pipe = LAST_ENABLE ? m_axis[LAST_OFFSET] : 1'b1;
wire [ID_WIDTH-1:0] m_axis_tid_pipe = ID_ENABLE ? m_axis[ID_OFFSET +: ID_WIDTH] : {ID_WIDTH{1'b0}};
wire [DEST_WIDTH-1:0] m_axis_tdest_pipe = DEST_ENABLE ? m_axis[DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}};
wire [USER_WIDTH-1:0] m_axis_tuser_pipe = USER_ENABLE ? m_axis[USER_OFFSET +: USER_WIDTH] : {USER_WIDTH{1'b0}};
wire pipe_ready;
assign status_overflow = overflow_reg;
assign status_bad_frame = bad_frame_reg;
assign status_good_frame = good_frame_reg;
// Write logic
always @(posedge clk) begin
overflow_reg <= 1'b0;
bad_frame_reg <= 1'b0;
good_frame_reg <= 1'b0;
if (s_axis_tready && s_axis_tvalid) begin
// transfer in
if (!FRAME_FIFO) begin
// normal FIFO mode
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis;
wr_ptr_reg <= wr_ptr_reg + 1;
end else if ((full_cur && DROP_WHEN_FULL) || (full_wr && DROP_OVERSIZE_FRAME) || drop_frame_reg) begin
// full, packet overflow, or currently dropping frame
// drop frame
drop_frame_reg <= 1'b1;
if (s_axis_tlast) begin
// end of frame, reset write pointer
wr_ptr_cur_reg <= wr_ptr_reg;
drop_frame_reg <= 1'b0;
overflow_reg <= 1'b1;
end
end else begin
// store it
mem[wr_ptr_cur_reg[ADDR_WIDTH-1:0]] <= s_axis;
wr_ptr_cur_reg <= wr_ptr_cur_reg + 1;
if (s_axis_tlast || (!DROP_OVERSIZE_FRAME && (full_wr || send_frame_reg))) begin
// end of frame or send frame
send_frame_reg <= !s_axis_tlast;
if (s_axis_tlast && DROP_BAD_FRAME && USER_BAD_FRAME_MASK & ~(s_axis_tuser ^ USER_BAD_FRAME_VALUE)) begin
// bad packet, reset write pointer
wr_ptr_cur_reg <= wr_ptr_reg;
bad_frame_reg <= 1'b1;
end else begin
// good packet or packet overflow, update write pointer
wr_ptr_reg <= wr_ptr_cur_reg + 1;
good_frame_reg <= s_axis_tlast;
end
end
end
end else if (s_axis_tvalid && full_wr && FRAME_FIFO && !DROP_OVERSIZE_FRAME) begin
// data valid with packet overflow
// update write pointer
send_frame_reg <= 1'b1;
wr_ptr_reg <= wr_ptr_cur_reg;
end
if (rst) begin
wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_cur_reg <= {ADDR_WIDTH+1{1'b0}};
drop_frame_reg <= 1'b0;
send_frame_reg <= 1'b0;
overflow_reg <= 1'b0;
bad_frame_reg <= 1'b0;
good_frame_reg <= 1'b0;
end
end
// Read logic
integer j;
always @(posedge clk) begin
if (OUTPUT_FIFO_ENABLE || m_axis_tready) begin
// output ready; invalidate stage
m_axis_tvalid_pipe_reg[RAM_PIPELINE+1-1] <= 1'b0;
end
for (j = RAM_PIPELINE+1-1; j > 0; j = j - 1) begin
if (OUTPUT_FIFO_ENABLE || m_axis_tready || ((~m_axis_tvalid_pipe_reg) >> j)) begin
// output ready or bubble in pipeline; transfer down pipeline
m_axis_tvalid_pipe_reg[j] <= m_axis_tvalid_pipe_reg[j-1];
m_axis_pipe_reg[j] <= m_axis_pipe_reg[j-1];
m_axis_tvalid_pipe_reg[j-1] <= 1'b0;
end
end
if (OUTPUT_FIFO_ENABLE || m_axis_tready || ~m_axis_tvalid_pipe_reg) begin
// output ready or bubble in pipeline; read new data from FIFO
m_axis_tvalid_pipe_reg[0] <= 1'b0;
m_axis_pipe_reg[0] <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
if (!empty && pipe_ready) begin
// not empty, increment pointer
m_axis_tvalid_pipe_reg[0] <= 1'b1;
rd_ptr_reg <= rd_ptr_reg + 1;
end
end
if (rst) begin
rd_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
m_axis_tvalid_pipe_reg <= 0;
end
end
generate
if (!OUTPUT_FIFO_ENABLE) begin
assign pipe_ready = 1'b1;
assign m_axis_tvalid = m_axis_tvalid_pipe;
assign m_axis_tdata = m_axis_tdata_pipe;
assign m_axis_tkeep = m_axis_tkeep_pipe;
assign m_axis_tlast = m_axis_tlast_pipe;
assign m_axis_tid = m_axis_tid_pipe;
assign m_axis_tdest = m_axis_tdest_pipe;
assign m_axis_tuser = m_axis_tuser_pipe;
end else begin
// output datapath logic
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg m_axis_tvalid_reg = 1'b0;
reg m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_wr_ptr_reg = 0;
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_rd_ptr_reg = 0;
reg out_fifo_half_full_reg = 1'b0;
wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_ADDR_WIDTH{1'b0}}});
wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg;
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [DATA_WIDTH-1:0] out_fifo_tdata[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [KEEP_WIDTH-1:0] out_fifo_tkeep[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg out_fifo_tlast[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [ID_WIDTH-1:0] out_fifo_tid[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [DEST_WIDTH-1:0] out_fifo_tdest[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [USER_WIDTH-1:0] out_fifo_tuser[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
assign pipe_ready = !out_fifo_half_full_reg;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tkeep = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = LAST_ENABLE ? m_axis_tlast_reg : 1'b1;
assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
always @(posedge clk) begin
m_axis_tvalid_reg <= m_axis_tvalid_reg && !m_axis_tready;
out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(OUTPUT_FIFO_ADDR_WIDTH-1);
if (!out_fifo_full && m_axis_tvalid_pipe) begin
out_fifo_tdata[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tdata_pipe;
out_fifo_tkeep[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tkeep_pipe;
out_fifo_tlast[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tlast_pipe;
out_fifo_tid[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tid_pipe;
out_fifo_tdest[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tdest_pipe;
out_fifo_tuser[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_tuser_pipe;
out_fifo_wr_ptr_reg <= out_fifo_wr_ptr_reg + 1;
end
if (!out_fifo_empty && (!m_axis_tvalid_reg || m_axis_tready)) begin
m_axis_tdata_reg <= out_fifo_tdata[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
m_axis_tkeep_reg <= out_fifo_tkeep[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
m_axis_tvalid_reg <= 1'b1;
m_axis_tlast_reg <= out_fifo_tlast[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
m_axis_tid_reg <= out_fifo_tid[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
m_axis_tdest_reg <= out_fifo_tdest[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
m_axis_tuser_reg <= out_fifo_tuser[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
out_fifo_rd_ptr_reg <= out_fifo_rd_ptr_reg + 1;
end
if (rst) begin
out_fifo_wr_ptr_reg <= 0;
out_fifo_rd_ptr_reg <= 0;
m_axis_tvalid_reg <= 1'b0;
end
end
end
endgenerate
endmodule
`resetall

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/*
Copyright (c) 2022 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Ethernet MAC wrapper
*/
module eth_mac_wrapper #
(
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_WIDTH = 8,
parameter DATA_WIDTH = 512,
parameter KEEP_WIDTH = DATA_WIDTH/8,
parameter TX_USER_WIDTH = PTP_TAG_WIDTH+1,
parameter RX_USER_WIDTH = PTP_TS_WIDTH+1
)
(
input wire ctrl_clk,
input wire ctrl_rst,
output wire [3:0] tx_serial_data_p,
output wire [3:0] tx_serial_data_n,
input wire [3:0] rx_serial_data_p,
input wire [3:0] rx_serial_data_n,
input wire ref_clk,
output wire mac_clk,
output wire mac_rst,
input wire [PTP_TS_WIDTH-1:0] mac_ptp_time,
output wire [PTP_TS_WIDTH-1:0] mac_tx_ptp_ts,
output wire [PTP_TAG_WIDTH-1:0] mac_tx_ptp_ts_tag,
output wire mac_tx_ptp_ts_valid,
input wire [DATA_WIDTH-1:0] mac_tx_axis_tdata,
input wire [KEEP_WIDTH-1:0] mac_tx_axis_tkeep,
input wire mac_tx_axis_tvalid,
output wire mac_tx_axis_tready,
input wire mac_tx_axis_tlast,
input wire [TX_USER_WIDTH-1:0] mac_tx_axis_tuser,
output wire [DATA_WIDTH-1:0] mac_rx_axis_tdata,
output wire [KEEP_WIDTH-1:0] mac_rx_axis_tkeep,
output wire mac_rx_axis_tvalid,
output wire mac_rx_axis_tlast,
output wire [RX_USER_WIDTH-1:0] mac_rx_axis_tuser,
output wire mac_rx_status
);
parameter XCVR_CH = 4;
wire [5:0] mac_pll_clk_d64;
wire [5:0] mac_pll_clk_d66;
wire [5:0] mac_rec_clk_d64;
wire [5:0] mac_rec_clk_d66;
wire mac_tx_pll_locked;
wire [XCVR_CH*19-1:0] xcvr_reconfig_address;
wire [XCVR_CH-1:0] xcvr_reconfig_read;
wire [XCVR_CH-1:0] xcvr_reconfig_write;
wire [XCVR_CH*8-1:0] xcvr_reconfig_readdata;
wire [XCVR_CH*8-1:0] xcvr_reconfig_writedata;
wire [XCVR_CH-1:0] xcvr_reconfig_waitrequest;
wire mac_tx_lanes_stable;
wire mac_rx_pcs_ready;
wire mac_ehip_ready;
wire [PTP_TS_WIDTH-1:0] mac_ptp_tod;
wire [PTP_TAG_WIDTH-1:0] mac_ptp_fp;
wire mac_ptp_ets_valid;
wire [PTP_TS_WIDTH-1:0] mac_ptp_ets;
wire [PTP_TAG_WIDTH-1:0] mac_ptp_ets_fp;
wire [PTP_TS_WIDTH-1:0] mac_ptp_rx_its;
wire mac_tx_ready;
wire mac_tx_ready_int;
wire mac_tx_valid;
wire [DATA_WIDTH-1:0] mac_tx_data;
wire mac_tx_error;
wire mac_tx_startofpacket;
wire mac_tx_endofpacket;
wire [5:0] mac_tx_empty;
wire mac_rx_valid;
wire [DATA_WIDTH-1:0] mac_rx_data;
wire mac_rx_startofpacket;
wire mac_rx_endofpacket;
wire [5:0] mac_rx_empty;
wire [5:0] mac_rx_error;
// register slice to work around E-Tile soft logic bug
// (PTP input signals must be directly driven by "hyperflex-friendly registers")
reg mac_tx_valid_reg = 0;
reg [DATA_WIDTH-1:0] mac_tx_data_reg = 0;
reg mac_tx_error_reg = 0;
reg mac_tx_startofpacket_reg = 0;
reg mac_tx_endofpacket_reg = 0;
reg [5:0] mac_tx_empty_reg = 0;
reg [PTP_TAG_WIDTH-1:0] mac_ptp_fp_reg = 0;
always @(posedge mac_clk) begin
if (mac_tx_ready_int || !mac_tx_valid_reg) begin
mac_tx_valid_reg <= mac_tx_valid;
mac_tx_data_reg <= mac_tx_data;
mac_tx_error_reg <= mac_tx_error;
mac_tx_startofpacket_reg <= mac_tx_startofpacket;
mac_tx_endofpacket_reg <= mac_tx_endofpacket;
mac_tx_empty_reg <= mac_tx_empty;
mac_ptp_fp_reg <= mac_ptp_fp;
end
if (mac_rst) begin
mac_tx_valid_reg <= 1'b0;
end
end
assign mac_tx_ready = mac_tx_ready_int || !mac_tx_valid_reg;
mac mac_inst (
.i_stats_snapshot (1'b0),
.o_cdr_lock (),
.o_tx_pll_locked (mac_tx_pll_locked),
.i_eth_reconfig_addr (21'd0),
.i_eth_reconfig_read (1'b0),
.i_eth_reconfig_write (1'b0),
.o_eth_reconfig_readdata (),
.o_eth_reconfig_readdata_valid (),
.i_eth_reconfig_writedata (32'd0),
.o_eth_reconfig_waitrequest (),
.i_rsfec_reconfig_addr (11'd0),
.i_rsfec_reconfig_read (1'b0),
.i_rsfec_reconfig_write (1'b0),
.o_rsfec_reconfig_readdata (),
.i_rsfec_reconfig_writedata (8'd0),
.o_rsfec_reconfig_waitrequest (),
.i_ptp_reconfig_address ({2{19'd0}}),
.i_ptp_reconfig_read ({2{1'b0}}),
.i_ptp_reconfig_write ({2{1'b0}}),
.o_ptp_reconfig_readdata (),
.i_ptp_reconfig_writedata ({2{8'd0}}),
.o_ptp_reconfig_waitrequest (),
.o_tx_lanes_stable (mac_tx_lanes_stable),
.o_rx_pcs_ready (mac_rx_pcs_ready),
.o_ehip_ready (mac_ehip_ready),
.o_rx_block_lock (),
.o_rx_am_lock (),
.o_rx_hi_ber (),
.o_local_fault_status (),
.o_remote_fault_status (),
.i_clk_ref (ref_clk),
.i_clk_tx (mac_clk),
.i_clk_rx (mac_clk),
.o_clk_pll_div64 (mac_pll_clk_d64),
.o_clk_pll_div66 (mac_pll_clk_d66),
.o_clk_rec_div64 (mac_rec_clk_d64),
.o_clk_rec_div66 (mac_rec_clk_d66),
.i_csr_rst_n (!ctrl_rst),
.i_tx_rst_n (mac_tx_pll_locked),
.i_rx_rst_n (mac_tx_pll_locked),
.o_tx_serial (tx_serial_data_p),
.i_rx_serial (rx_serial_data_p),
.o_tx_serial_n (tx_serial_data_n),
.i_rx_serial_n (rx_serial_data_n),
.i_reconfig_clk (ctrl_clk),
.i_reconfig_reset (ctrl_rst),
.i_xcvr_reconfig_address (xcvr_reconfig_address),
.i_xcvr_reconfig_read (xcvr_reconfig_read),
.i_xcvr_reconfig_write (xcvr_reconfig_write),
.o_xcvr_reconfig_readdata (xcvr_reconfig_readdata),
.i_xcvr_reconfig_writedata (xcvr_reconfig_writedata),
.o_xcvr_reconfig_waitrequest (xcvr_reconfig_waitrequest),
.i_ptp_tod (mac_ptp_time),
.i_ptp_ts_req (1'b1),
.i_ptp_fp (mac_ptp_fp_reg),
.o_ptp_ets_valid (mac_tx_ptp_ts_valid),
.o_ptp_ets (mac_tx_ptp_ts),
.o_ptp_ets_fp (mac_tx_ptp_ts_tag),
.o_ptp_rx_its (mac_ptp_rx_its),
.o_tx_ptp_ready (),
.o_rx_ptp_ready (),
.i_ptp_ins_ets (1'b0),
.i_ptp_ins_cf (1'b0),
.i_ptp_zero_csum (1'b0),
.i_ptp_update_eb (1'b0),
.i_ptp_ts_format (1'b0),
.i_ptp_ts_offset (16'd0),
.i_ptp_cf_offset (16'd0),
.i_ptp_csum_offset (16'd0),
.i_ptp_eb_offset (16'd0),
.i_ptp_tx_its (96'd0),
.o_tx_ready (mac_tx_ready_int),
.i_tx_valid (mac_tx_valid_reg),
.i_tx_data (mac_tx_data_reg),
.i_tx_error (mac_tx_error_reg),
.i_tx_startofpacket (mac_tx_startofpacket_reg),
.i_tx_endofpacket (mac_tx_endofpacket_reg),
.i_tx_empty (mac_tx_empty_reg),
.i_tx_skip_crc (1'b0),
.o_rx_valid (mac_rx_valid),
.o_rx_data (mac_rx_data),
.o_rx_startofpacket (mac_rx_startofpacket),
.o_rx_endofpacket (mac_rx_endofpacket),
.o_rx_empty (mac_rx_empty),
.o_rx_error (mac_rx_error),
.o_rxstatus_data (),
.o_rxstatus_valid (),
.i_tx_pfc (8'd0),
.o_rx_pfc (),
.i_tx_pause (1'b0),
.o_rx_pause ()
);
assign mac_clk = mac_pll_clk_d64[4];
assign mac_rx_status = mac_rx_pcs_ready;
sync_reset #(
.N(4)
)
mac_tx_reset_sync_inst (
.clk(mac_clk),
.rst(ctrl_rst || !mac_tx_lanes_stable || !mac_ehip_ready),
.out(mac_rst)
);
generate
genvar n;
for (n = 0; n < XCVR_CH; n = n + 1) begin : xcvr_ch
xcvr_ctrl xcvr_ctrl_inst (
.reconfig_clk(ctrl_clk),
.reconfig_rst(ctrl_rst),
.pll_locked_in(mac_tx_pll_locked),
.xcvr_reconfig_address(xcvr_reconfig_address[n*19 +: 19]),
.xcvr_reconfig_read(xcvr_reconfig_read[n]),
.xcvr_reconfig_write(xcvr_reconfig_write[n]),
.xcvr_reconfig_readdata(xcvr_reconfig_readdata[n*8 +: 8]),
.xcvr_reconfig_writedata(xcvr_reconfig_writedata[n*8 +: 8]),
.xcvr_reconfig_waitrequest(xcvr_reconfig_waitrequest[n])
);
end
endgenerate
axis2avst #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.KEEP_ENABLE(1),
.EMPTY_WIDTH(6),
.BYTE_REVERSE(1)
)
mac_tx_axis2avst (
.clk(mac_clk),
.rst(mac_rst),
.axis_tdata(mac_tx_axis_tdata),
.axis_tkeep(mac_tx_axis_tkeep),
.axis_tvalid(mac_tx_axis_tvalid),
.axis_tready(mac_tx_axis_tready),
.axis_tlast(mac_tx_axis_tlast),
.axis_tuser(mac_tx_axis_tuser[0]),
.avst_ready(mac_tx_ready),
.avst_valid(mac_tx_valid),
.avst_data(mac_tx_data),
.avst_startofpacket(mac_tx_startofpacket),
.avst_endofpacket(mac_tx_endofpacket),
.avst_empty(mac_tx_empty),
.avst_error(mac_tx_error)
);
assign mac_ptp_fp = mac_tx_axis_tuser[1 +: PTP_TAG_WIDTH];
wire [DATA_WIDTH-1:0] mac_rx_axis_tdata_int;
wire [KEEP_WIDTH-1:0] mac_rx_axis_tkeep_int;
wire mac_rx_axis_tvalid_int;
wire mac_rx_axis_tlast_int;
wire mac_rx_axis_tuser_int;
avst2axis #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.KEEP_ENABLE(1),
.EMPTY_WIDTH(6),
.BYTE_REVERSE(1)
)
mac_rx_avst2axis (
.clk(mac_clk),
.rst(mac_rst),
.avst_ready(),
.avst_valid(mac_rx_valid),
.avst_data(mac_rx_data),
.avst_startofpacket(mac_rx_startofpacket),
.avst_endofpacket(mac_rx_endofpacket),
.avst_empty(mac_rx_empty),
.avst_error(mac_rx_error != 0),
.axis_tdata(mac_rx_axis_tdata_int),
.axis_tkeep(mac_rx_axis_tkeep_int),
.axis_tvalid(mac_rx_axis_tvalid_int),
.axis_tready(1'b1),
.axis_tlast(mac_rx_axis_tlast_int),
.axis_tuser(mac_rx_axis_tuser_int)
);
mac_ts_insert #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.S_USER_WIDTH(1),
.M_USER_WIDTH(PTP_TS_WIDTH+1)
)
mac_ts_insert_inst (
.clk(mac_clk),
.rst(mac_rst),
/*
* PTP TS input
*/
.ptp_ts(mac_ptp_rx_its),
/*
* AXI input
*/
.s_axis_tdata(mac_rx_axis_tdata_int),
.s_axis_tkeep(mac_rx_axis_tkeep_int),
.s_axis_tvalid(mac_rx_axis_tvalid_int),
.s_axis_tready(),
.s_axis_tlast(mac_rx_axis_tlast_int),
.s_axis_tuser(mac_rx_axis_tuser_int),
/*
* AXI output
*/
.m_axis_tdata(mac_rx_axis_tdata),
.m_axis_tkeep(mac_rx_axis_tkeep),
.m_axis_tvalid(mac_rx_axis_tvalid),
.m_axis_tready(1'b1),
.m_axis_tlast(mac_rx_axis_tlast),
.m_axis_tuser(mac_rx_axis_tuser)
);
endmodule
`resetall

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/*
Copyright 2021, The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
The views and conclusions contained in the software and documentation are those
of the authors and should not be interpreted as representing official policies,
either expressed or implied, of The Regents of the University of California.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA top-level module
*/
module fpga #
(
// FW and board IDs
parameter FPGA_ID = 32'hC32450DD,
parameter FW_ID = 32'h00000000,
parameter FW_VER = 32'h00_00_01_00,
parameter BOARD_ID = 32'h1172_A00D,
parameter BOARD_VER = 32'h01_00_00_00,
parameter BUILD_DATE = 32'd1563227611,
parameter GIT_HASH = 32'hdce357bf,
parameter RELEASE_INFO = 32'h00000000,
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
parameter PORT_MASK = 0,
// Clock configuration
parameter CLK_PERIOD_NS_NUM = 4,
parameter CLK_PERIOD_NS_DENOM = 1,
// PTP configuration
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 1,
parameter PTP_PEROUT_COUNT = 1,
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE,
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE,
parameter EVENT_QUEUE_INDEX_WIDTH = 5,
parameter TX_QUEUE_INDEX_WIDTH = 10,
parameter RX_QUEUE_INDEX_WIDTH = 8,
parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
parameter EVENT_QUEUE_PIPELINE = 3,
parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0),
parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0),
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 131072,
parameter MAX_TX_SIZE = 9214,
parameter MAX_RX_SIZE = 9214,
parameter TX_RAM_SIZE = 131072,
parameter RX_RAM_SIZE = 131072,
// Application block configuration
parameter APP_ID = 32'h00000000,
parameter APP_ENABLE = 0,
parameter APP_CTRL_ENABLE = 1,
parameter APP_DMA_ENABLE = 1,
parameter APP_AXIS_DIRECT_ENABLE = 1,
parameter APP_AXIS_SYNC_ENABLE = 1,
parameter APP_AXIS_IF_ENABLE = 1,
parameter APP_STAT_ENABLE = 1,
// DMA interface configuration
parameter DMA_IMM_ENABLE = 0,
parameter DMA_IMM_WIDTH = 32,
parameter DMA_LEN_WIDTH = 16,
parameter DMA_TAG_WIDTH = 16,
parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
parameter RAM_PIPELINE = 2,
// PCIe interface configuration
parameter SEG_COUNT = 2,
parameter SEG_DATA_WIDTH = 256,
parameter SEG_EMPTY_WIDTH = $clog2(SEG_DATA_WIDTH/32),
parameter SEG_HDR_WIDTH = 128,
parameter SEG_PRFX_WIDTH = 32,
parameter TX_SEQ_NUM_WIDTH = 6,
parameter PF_COUNT = 1,
parameter VF_COUNT = 0,
parameter PCIE_TAG_COUNT = 256,
parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
parameter PCIE_DMA_READ_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 2**TX_SEQ_NUM_WIDTH,
parameter PCIE_DMA_WRITE_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
// AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32,
parameter AXIL_CTRL_ADDR_WIDTH = 24,
// AXI lite interface configuration (application control)
parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH,
parameter AXIL_APP_CTRL_ADDR_WIDTH = 24,
// Ethernet interface configuration
parameter AXIS_ETH_TX_PIPELINE = 0,
parameter AXIS_ETH_TX_FIFO_PIPELINE = 2,
parameter AXIS_ETH_TX_TS_PIPELINE = 0,
parameter AXIS_ETH_RX_PIPELINE = 0,
parameter AXIS_ETH_RX_FIFO_PIPELINE = 2,
// Statistics counter subsystem
parameter STAT_ENABLE = 1,
parameter STAT_DMA_ENABLE = 1,
parameter STAT_PCIE_ENABLE = 1,
parameter STAT_INC_WIDTH = 24,
parameter STAT_ID_WIDTH = 12
)
(
/*
* Clock: 100 MHz
* Reset: Push button, active low
*/
// input wire clk2_fpga_50m,
input wire clk2_100m_fpga_2i_p,
// input wire cpu_resetn,
/*
* GPIO
*/
input wire user_pb,
output wire [3:0] user_led_g,
/*
* I2C
*/
inout wire i2c2_scl,
inout wire i2c2_sda,
output wire bmc_i2c2_disable,
/*
* PCIe: gen 4 x16
*/
output wire [15:0] pcie_tx_p,
output wire [15:0] pcie_tx_n,
input wire [15:0] pcie_rx_p,
input wire [15:0] pcie_rx_n,
input wire clk_100m_pcie_0_p,
input wire clk_100m_pcie_1_p,
input wire pcie_rst_n,
/*
* Ethernet: QSFP28
*/
output wire [3:0] qsfp1_tx_p,
// output wire [3:0] qsfp1_tx_n,
input wire [3:0] qsfp1_rx_p,
// input wire [3:0] qsfp1_rx_n,
output wire [3:0] qsfp2_tx_p,
// output wire [3:0] qsfp2_tx_n,
input wire [3:0] qsfp2_rx_p,
// input wire [3:0] qsfp2_rx_n,
input wire clk_156p25m_qsfp0_p
// input wire clk_156p25m_qsfp1_p,
// input wire clk_312p5m_qsfp0_p,
// input wire clk_312p5m_qsfp1_p,
// input wire clk_312p5m_qsfp2_p
);
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 4096;
parameter PTP_CLK_PERIOD_NS_DENOM = 825;
parameter PTP_TS_WIDTH = 96;
parameter PTP_TAG_WIDTH = 8;
parameter PTP_USE_SAMPLE_CLOCK = 1;
// Interface configuration
parameter TX_TAG_WIDTH = PTP_TAG_WIDTH;
// Ethernet interface configuration
parameter AXIS_ETH_DATA_WIDTH = 512;
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8;
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH;
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1;
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;
// Clock and reset
wire ninit_done;
wire pcie_clk;
wire pcie_rst;
reset_release reset_release_inst (
.ninit_done (ninit_done)
);
wire clk_100mhz = clk2_100m_fpga_2i_p;
wire rst_100mhz;
sync_reset #(
.N(20)
)
sync_reset_100mhz_inst (
.clk(clk_100mhz),
.rst(pcie_rst),
.out(rst_100mhz)
);
// GPIO
wire i2c2_scl_i;
wire i2c2_scl_o;
wire i2c2_scl_t;
wire i2c2_sda_i;
wire i2c2_sda_o;
wire i2c2_sda_t;
reg i2c2_scl_o_reg;
reg i2c2_scl_t_reg;
reg i2c2_sda_o_reg;
reg i2c2_sda_t_reg;
always @(posedge pcie_clk) begin
i2c2_scl_o_reg <= i2c2_scl_o;
i2c2_scl_t_reg <= i2c2_scl_t;
i2c2_sda_o_reg <= i2c2_sda_o;
i2c2_sda_t_reg <= i2c2_sda_t;
end
sync_signal #(
.WIDTH(2),
.N(2)
)
sync_signal_inst (
.clk(pcie_clk),
.in({i2c2_scl, i2c2_sda}),
.out({i2c2_scl_i, i2c2_sda_i})
);
assign i2c2_scl = i2c2_scl_t_reg ? 1'bz : i2c2_scl_o_reg;
assign i2c2_sda = i2c2_sda_t_reg ? 1'bz : i2c2_sda_o_reg;
// PCIe
wire coreclkout_hip;
wire reset_status_n;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] rx_st_data;
wire [SEG_COUNT*SEG_EMPTY_WIDTH-1:0] rx_st_empty;
wire [SEG_COUNT-1:0] rx_st_sop;
wire [SEG_COUNT-1:0] rx_st_eop;
wire [SEG_COUNT-1:0] rx_st_valid;
wire rx_st_ready;
wire [SEG_COUNT*SEG_HDR_WIDTH-1:0] rx_st_hdr;
wire [SEG_COUNT*SEG_PRFX_WIDTH-1:0] rx_st_tlp_prfx;
wire [SEG_COUNT-1:0] rx_st_vf_active = 0;
wire [SEG_COUNT*3-1:0] rx_st_func_num = 0;
wire [SEG_COUNT*11-1:0] rx_st_vf_num = 0;
wire [SEG_COUNT*3-1:0] rx_st_bar_range;
wire [SEG_COUNT-1:0] rx_st_tlp_abort;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] tx_st_data;
wire [SEG_COUNT-1:0] tx_st_sop;
wire [SEG_COUNT-1:0] tx_st_eop;
wire [SEG_COUNT-1:0] tx_st_valid;
wire tx_st_ready;
wire [SEG_COUNT-1:0] tx_st_err;
wire [SEG_COUNT*SEG_HDR_WIDTH-1:0] tx_st_hdr;
wire [SEG_COUNT*SEG_PRFX_WIDTH-1:0] tx_st_tlp_prfx;
wire [11:0] rx_buffer_limit;
wire [1:0] rx_buffer_limit_tdm_idx;
wire [15:0] tx_cdts_limit;
wire [2:0] tx_cdts_limit_tdm_idx;
wire [15:0] tl_cfg_ctl;
wire [4:0] tl_cfg_add;
wire [2:0] tl_cfg_func;
assign pcie_clk = coreclkout_hip;
assign pcie_rst = !reset_status_n;
pcie pcie_hip_inst (
.p0_rx_st_ready_i(rx_st_ready),
.p0_rx_st_sop_o(rx_st_sop),
.p0_rx_st_eop_o(rx_st_eop),
.p0_rx_st_data_o(rx_st_data),
.p0_rx_st_valid_o(rx_st_valid),
.p0_rx_st_empty_o(rx_st_empty),
.p0_rx_st_hdr_o(rx_st_hdr),
.p0_rx_st_tlp_prfx_o(rx_st_tlp_prfx),
.p0_rx_st_bar_range_o(rx_st_bar_range),
.p0_rx_st_tlp_abort_o(rx_st_tlp_abort),
.p0_rx_par_err_o(),
.p0_tx_st_sop_i(tx_st_sop),
.p0_tx_st_eop_i(tx_st_eop),
.p0_tx_st_data_i(tx_st_data),
.p0_tx_st_valid_i(tx_st_valid),
.p0_tx_st_err_i(tx_st_err),
.p0_tx_st_ready_o(tx_st_ready),
.p0_tx_st_hdr_i(tx_st_hdr),
.p0_tx_st_tlp_prfx_i(tx_st_tlp_prfx),
.p0_tx_par_err_o(),
.p0_tx_cdts_limit_o(tx_cdts_limit),
.p0_tx_cdts_limit_tdm_idx_o(tx_cdts_limit_tdm_idx),
.p0_tl_cfg_func_o(tl_cfg_func),
.p0_tl_cfg_add_o(tl_cfg_add),
.p0_tl_cfg_ctl_o(tl_cfg_ctl),
.p0_dl_timer_update_o(),
.p0_reset_status_n(reset_status_n),
.p0_pin_perst_n(),
.p0_link_up_o(),
.p0_dl_up_o(),
.p0_surprise_down_err_o(),
.p0_ltssm_state_o(),
.rx_n_in0(pcie_rx_n[0]),
.rx_n_in1(pcie_rx_n[1]),
.rx_n_in2(pcie_rx_n[2]),
.rx_n_in3(pcie_rx_n[3]),
.rx_n_in4(pcie_rx_n[4]),
.rx_n_in5(pcie_rx_n[5]),
.rx_n_in6(pcie_rx_n[6]),
.rx_n_in7(pcie_rx_n[7]),
.rx_n_in8(pcie_rx_n[8]),
.rx_n_in9(pcie_rx_n[9]),
.rx_n_in10(pcie_rx_n[10]),
.rx_n_in11(pcie_rx_n[11]),
.rx_n_in12(pcie_rx_n[12]),
.rx_n_in13(pcie_rx_n[13]),
.rx_n_in14(pcie_rx_n[14]),
.rx_n_in15(pcie_rx_n[15]),
.rx_p_in0(pcie_rx_p[0]),
.rx_p_in1(pcie_rx_p[1]),
.rx_p_in2(pcie_rx_p[2]),
.rx_p_in3(pcie_rx_p[3]),
.rx_p_in4(pcie_rx_p[4]),
.rx_p_in5(pcie_rx_p[5]),
.rx_p_in6(pcie_rx_p[6]),
.rx_p_in7(pcie_rx_p[7]),
.rx_p_in8(pcie_rx_p[8]),
.rx_p_in9(pcie_rx_p[9]),
.rx_p_in10(pcie_rx_p[10]),
.rx_p_in11(pcie_rx_p[11]),
.rx_p_in12(pcie_rx_p[12]),
.rx_p_in13(pcie_rx_p[13]),
.rx_p_in14(pcie_rx_p[14]),
.rx_p_in15(pcie_rx_p[15]),
.tx_n_out0(pcie_tx_n[0]),
.tx_n_out1(pcie_tx_n[1]),
.tx_n_out2(pcie_tx_n[2]),
.tx_n_out3(pcie_tx_n[3]),
.tx_n_out4(pcie_tx_n[4]),
.tx_n_out5(pcie_tx_n[5]),
.tx_n_out6(pcie_tx_n[6]),
.tx_n_out7(pcie_tx_n[7]),
.tx_n_out8(pcie_tx_n[8]),
.tx_n_out9(pcie_tx_n[9]),
.tx_n_out10(pcie_tx_n[10]),
.tx_n_out11(pcie_tx_n[11]),
.tx_n_out12(pcie_tx_n[12]),
.tx_n_out13(pcie_tx_n[13]),
.tx_n_out14(pcie_tx_n[14]),
.tx_n_out15(pcie_tx_n[15]),
.tx_p_out0(pcie_tx_p[0]),
.tx_p_out1(pcie_tx_p[1]),
.tx_p_out2(pcie_tx_p[2]),
.tx_p_out3(pcie_tx_p[3]),
.tx_p_out4(pcie_tx_p[4]),
.tx_p_out5(pcie_tx_p[5]),
.tx_p_out6(pcie_tx_p[6]),
.tx_p_out7(pcie_tx_p[7]),
.tx_p_out8(pcie_tx_p[8]),
.tx_p_out9(pcie_tx_p[9]),
.tx_p_out10(pcie_tx_p[10]),
.tx_p_out11(pcie_tx_p[11]),
.tx_p_out12(pcie_tx_p[12]),
.tx_p_out13(pcie_tx_p[13]),
.tx_p_out14(pcie_tx_p[14]),
.tx_p_out15(pcie_tx_p[15]),
.coreclkout_hip(coreclkout_hip),
.refclk0(clk_100m_pcie_0_p),
.refclk1(clk_100m_pcie_1_p),
.pin_perst_n(pcie_rst_n),
.ninit_done(ninit_done)
);
// QSFP28 interfaces
// QSFP1
wire qsfp1_mac_clk_int;
wire qsfp1_mac_rst_int;
wire [PTP_TS_WIDTH-1:0] qsfp1_mac_ptp_time_int;
wire [PTP_TS_WIDTH-1:0] qsfp1_mac_tx_ptp_ts_int;
wire [PTP_TAG_WIDTH-1:0] qsfp1_mac_tx_ptp_ts_tag_int;
wire qsfp1_mac_tx_ptp_ts_valid_int;
wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_mac_tx_axis_tdata_int;
wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_mac_tx_axis_tkeep_int;
wire qsfp1_mac_tx_axis_tvalid_int;
wire qsfp1_mac_tx_axis_tready_int;
wire qsfp1_mac_tx_axis_tlast_int;
wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfp1_mac_tx_axis_tuser_int;
wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_mac_rx_axis_tdata_int;
wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_mac_rx_axis_tkeep_int;
wire qsfp1_mac_rx_axis_tvalid_int;
wire qsfp1_mac_rx_axis_tlast_int;
wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfp1_mac_rx_axis_tuser_int;
wire qsfp1_mac_rx_status_int;
eth_mac_wrapper #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
.KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
.TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
.RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH)
)
qsfp1_mac_inst (
.ctrl_clk(clk_100mhz),
.ctrl_rst(rst_100mhz),
.tx_serial_data_p({qsfp1_tx_p[3], qsfp1_tx_p[1], qsfp1_tx_p[2], qsfp1_tx_p[0]}),
// .tx_serial_data_n({qsfp1_tx_n[3], qsfp1_tx_n[1], qsfp1_tx_n[2], qsfp1_tx_n[0]}),
.rx_serial_data_p({qsfp1_rx_p[3], qsfp1_rx_p[1], qsfp1_rx_p[2], qsfp1_rx_p[0]}),
// .rx_serial_data_n({qsfp1_rx_n[3], qsfp1_rx_n[1], qsfp1_rx_n[2], qsfp1_rx_n[0]}),
.ref_clk(clk_156p25m_qsfp0_p),
.mac_clk(qsfp1_mac_clk_int),
.mac_rst(qsfp1_mac_rst_int),
.mac_ptp_time(qsfp1_mac_ptp_time_int),
.mac_tx_ptp_ts(qsfp1_mac_tx_ptp_ts_int),
.mac_tx_ptp_ts_tag(qsfp1_mac_tx_ptp_ts_tag_int),
.mac_tx_ptp_ts_valid(qsfp1_mac_tx_ptp_ts_valid_int),
.mac_tx_axis_tdata(qsfp1_mac_tx_axis_tdata_int),
.mac_tx_axis_tkeep(qsfp1_mac_tx_axis_tkeep_int),
.mac_tx_axis_tvalid(qsfp1_mac_tx_axis_tvalid_int),
.mac_tx_axis_tready(qsfp1_mac_tx_axis_tready_int),
.mac_tx_axis_tlast(qsfp1_mac_tx_axis_tlast_int),
.mac_tx_axis_tuser(qsfp1_mac_tx_axis_tuser_int),
.mac_rx_axis_tdata(qsfp1_mac_rx_axis_tdata_int),
.mac_rx_axis_tkeep(qsfp1_mac_rx_axis_tkeep_int),
.mac_rx_axis_tvalid(qsfp1_mac_rx_axis_tvalid_int),
.mac_rx_axis_tlast(qsfp1_mac_rx_axis_tlast_int),
.mac_rx_axis_tuser(qsfp1_mac_rx_axis_tuser_int),
.mac_rx_status(qsfp1_mac_rx_status_int)
);
// QSFP2
wire qsfp2_mac_clk_int;
wire qsfp2_mac_rst_int;
wire [PTP_TS_WIDTH-1:0] qsfp2_mac_ptp_time_int;
wire [PTP_TS_WIDTH-1:0] qsfp2_mac_tx_ptp_ts_int;
wire [PTP_TAG_WIDTH-1:0] qsfp2_mac_tx_ptp_ts_tag_int;
wire qsfp2_mac_tx_ptp_ts_valid_int;
wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp2_mac_tx_axis_tdata_int;
wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp2_mac_tx_axis_tkeep_int;
wire qsfp2_mac_tx_axis_tvalid_int;
wire qsfp2_mac_tx_axis_tready_int;
wire qsfp2_mac_tx_axis_tlast_int;
wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfp2_mac_tx_axis_tuser_int;
wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp2_mac_rx_axis_tdata_int;
wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp2_mac_rx_axis_tkeep_int;
wire qsfp2_mac_rx_axis_tvalid_int;
wire qsfp2_mac_rx_axis_tlast_int;
wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfp2_mac_rx_axis_tuser_int;
wire qsfp2_mac_rx_status_int;
eth_mac_wrapper #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
.KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
.TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
.RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH)
)
qsfp2_mac_inst (
.ctrl_clk(clk_100mhz),
.ctrl_rst(rst_100mhz),
.tx_serial_data_p({qsfp2_tx_p[3], qsfp2_tx_p[1], qsfp2_tx_p[2], qsfp2_tx_p[0]}),
// .tx_serial_data_n({qsfp2_tx_n[3], qsfp2_tx_n[1], qsfp2_tx_n[2], qsfp2_tx_n[0]}),
.rx_serial_data_p({qsfp2_rx_p[3], qsfp2_rx_p[1], qsfp2_rx_p[2], qsfp2_rx_p[0]}),
// .rx_serial_data_n({qsfp2_rx_n[3], qsfp2_rx_n[1], qsfp2_rx_n[2], qsfp2_rx_n[0]}),
.ref_clk(clk_156p25m_qsfp0_p),
.mac_clk(qsfp2_mac_clk_int),
.mac_rst(qsfp2_mac_rst_int),
.mac_ptp_time(qsfp2_mac_ptp_time_int),
.mac_tx_ptp_ts(qsfp2_mac_tx_ptp_ts_int),
.mac_tx_ptp_ts_tag(qsfp2_mac_tx_ptp_ts_tag_int),
.mac_tx_ptp_ts_valid(qsfp2_mac_tx_ptp_ts_valid_int),
.mac_tx_axis_tdata(qsfp2_mac_tx_axis_tdata_int),
.mac_tx_axis_tkeep(qsfp2_mac_tx_axis_tkeep_int),
.mac_tx_axis_tvalid(qsfp2_mac_tx_axis_tvalid_int),
.mac_tx_axis_tready(qsfp2_mac_tx_axis_tready_int),
.mac_tx_axis_tlast(qsfp2_mac_tx_axis_tlast_int),
.mac_tx_axis_tuser(qsfp2_mac_tx_axis_tuser_int),
.mac_rx_axis_tdata(qsfp2_mac_rx_axis_tdata_int),
.mac_rx_axis_tkeep(qsfp2_mac_rx_axis_tkeep_int),
.mac_rx_axis_tvalid(qsfp2_mac_rx_axis_tvalid_int),
.mac_rx_axis_tlast(qsfp2_mac_rx_axis_tlast_int),
.mac_rx_axis_tuser(qsfp2_mac_rx_axis_tuser_int),
.mac_rx_status(qsfp2_mac_rx_status_int)
);
wire ptp_clk;
wire ptp_rst;
wire ptp_sample_clk;
assign ptp_sample_clk = clk_100mhz;
ref_div ref_div_inst (
.inclk(qsfp1_mac_clk_int),
.clock_div1x(),
.clock_div2x(ptp_clk),
.clock_div4x()
);
sync_reset #(
.N(4)
)
ptp_rst_reset_sync_inst (
.clk(ptp_clk),
.rst(qsfp1_mac_rst_int),
.out(ptp_rst)
);
fpga_core #(
// FW and board IDs
.FPGA_ID(FPGA_ID),
.FW_ID(FW_ID),
.FW_VER(FW_VER),
.BOARD_ID(BOARD_ID),
.BOARD_VER(BOARD_VER),
.BUILD_DATE(BUILD_DATE),
.GIT_HASH(GIT_HASH),
.RELEASE_INFO(RELEASE_INFO),
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
.PORT_MASK(PORT_MASK),
// Clock configuration
.CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM),
.CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM),
// PTP configuration
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE),
.TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE),
.RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE),
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE),
.MAX_RX_SIZE(MAX_RX_SIZE),
.TX_RAM_SIZE(TX_RAM_SIZE),
.RX_RAM_SIZE(RX_RAM_SIZE),
// Application block configuration
.APP_ID(APP_ID),
.APP_ENABLE(APP_ENABLE),
.APP_CTRL_ENABLE(APP_CTRL_ENABLE),
.APP_DMA_ENABLE(APP_DMA_ENABLE),
.APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE),
.APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE),
.APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE),
.APP_STAT_ENABLE(APP_STAT_ENABLE),
// DMA interface configuration
.DMA_IMM_ENABLE(DMA_IMM_ENABLE),
.DMA_IMM_WIDTH(DMA_IMM_WIDTH),
.DMA_LEN_WIDTH(DMA_LEN_WIDTH),
.DMA_TAG_WIDTH(DMA_TAG_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.RAM_PIPELINE(RAM_PIPELINE),
// PCIe interface configuration
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_EMPTY_WIDTH(SEG_EMPTY_WIDTH),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.PF_COUNT(PF_COUNT),
.VF_COUNT(VF_COUNT),
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.PCIE_DMA_READ_OP_TABLE_SIZE(PCIE_DMA_READ_OP_TABLE_SIZE),
.PCIE_DMA_READ_TX_LIMIT(PCIE_DMA_READ_TX_LIMIT),
.PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE),
.PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT),
// Interrupt configuration
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH),
// AXI lite interface configuration (control)
.AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
.AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH),
// AXI lite interface configuration (application control)
.AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH),
.AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH),
// Ethernet interface configuration
.AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
.AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
.AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH),
.AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
.AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH),
.AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE),
.AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE),
.AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE),
.AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE),
.AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE),
// Statistics counter subsystem
.STAT_ENABLE(STAT_ENABLE),
.STAT_DMA_ENABLE(STAT_DMA_ENABLE),
.STAT_PCIE_ENABLE(STAT_PCIE_ENABLE),
.STAT_INC_WIDTH(STAT_INC_WIDTH),
.STAT_ID_WIDTH(STAT_ID_WIDTH)
)
core_inst (
/*
* Clock: 250 MHz
* Synchronous reset
*/
.clk_250mhz(pcie_clk),
.rst_250mhz(pcie_rst),
/*
* PTP clock
*/
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
/*
* GPIO
*/
.user_pb(user_pb),
.user_led_g(user_led_g),
/*
* I2C
*/
.i2c2_scl_i(i2c2_scl_i),
.i2c2_scl_o(i2c2_scl_o),
.i2c2_scl_t(i2c2_scl_t),
.i2c2_sda_i(i2c2_sda_i),
.i2c2_sda_o(i2c2_sda_o),
.i2c2_sda_t(i2c2_sda_t),
.bmc_i2c2_disable(bmc_i2c2_disable),
/*
* P-Tile interface
*/
.rx_st_data(rx_st_data),
.rx_st_empty(rx_st_empty),
.rx_st_sop(rx_st_sop),
.rx_st_eop(rx_st_eop),
.rx_st_valid(rx_st_valid),
.rx_st_ready(rx_st_ready),
.rx_st_hdr(rx_st_hdr),
.rx_st_tlp_prfx(rx_st_tlp_prfx),
.rx_st_vf_active(rx_st_vf_active),
.rx_st_func_num(rx_st_func_num),
.rx_st_vf_num(rx_st_vf_num),
.rx_st_bar_range(rx_st_bar_range),
.rx_st_tlp_abort(rx_st_tlp_abort),
.tx_st_data(tx_st_data),
.tx_st_sop(tx_st_sop),
.tx_st_eop(tx_st_eop),
.tx_st_valid(tx_st_valid),
.tx_st_ready(tx_st_ready),
.tx_st_err(tx_st_err),
.tx_st_hdr(tx_st_hdr),
.tx_st_tlp_prfx(tx_st_tlp_prfx),
.rx_buffer_limit(rx_buffer_limit),
.rx_buffer_limit_tdm_idx(rx_buffer_limit_tdm_idx),
.tx_cdts_limit(tx_cdts_limit),
.tx_cdts_limit_tdm_idx(tx_cdts_limit_tdm_idx),
.tl_cfg_ctl(tl_cfg_ctl),
.tl_cfg_add(tl_cfg_add),
.tl_cfg_func(tl_cfg_func),
/*
* Ethernet: QSFP28
*/
.qsfp1_mac_clk(qsfp1_mac_clk_int),
.qsfp1_mac_rst(qsfp1_mac_rst_int),
.qsfp1_mac_ptp_time(qsfp1_mac_ptp_time_int),
.qsfp1_mac_tx_ptp_ts(qsfp1_mac_tx_ptp_ts_int),
.qsfp1_mac_tx_ptp_ts_tag(qsfp1_mac_tx_ptp_ts_tag_int),
.qsfp1_mac_tx_ptp_ts_valid(qsfp1_mac_tx_ptp_ts_valid_int),
.qsfp1_mac_tx_axis_tdata(qsfp1_mac_tx_axis_tdata_int),
.qsfp1_mac_tx_axis_tkeep(qsfp1_mac_tx_axis_tkeep_int),
.qsfp1_mac_tx_axis_tvalid(qsfp1_mac_tx_axis_tvalid_int),
.qsfp1_mac_tx_axis_tready(qsfp1_mac_tx_axis_tready_int),
.qsfp1_mac_tx_axis_tlast(qsfp1_mac_tx_axis_tlast_int),
.qsfp1_mac_tx_axis_tuser(qsfp1_mac_tx_axis_tuser_int),
.qsfp1_mac_rx_axis_tdata(qsfp1_mac_rx_axis_tdata_int),
.qsfp1_mac_rx_axis_tkeep(qsfp1_mac_rx_axis_tkeep_int),
.qsfp1_mac_rx_axis_tvalid(qsfp1_mac_rx_axis_tvalid_int),
.qsfp1_mac_rx_axis_tlast(qsfp1_mac_rx_axis_tlast_int),
.qsfp1_mac_rx_axis_tuser(qsfp1_mac_rx_axis_tuser_int),
.qsfp1_mac_rx_status(qsfp1_mac_rx_status_int),
.qsfp2_mac_clk(qsfp2_mac_clk_int),
.qsfp2_mac_rst(qsfp2_mac_rst_int),
.qsfp2_mac_ptp_time(qsfp2_mac_ptp_time_int),
.qsfp2_mac_tx_ptp_ts(qsfp2_mac_tx_ptp_ts_int),
.qsfp2_mac_tx_ptp_ts_tag(qsfp2_mac_tx_ptp_ts_tag_int),
.qsfp2_mac_tx_ptp_ts_valid(qsfp2_mac_tx_ptp_ts_valid_int),
.qsfp2_mac_tx_axis_tdata(qsfp2_mac_tx_axis_tdata_int),
.qsfp2_mac_tx_axis_tkeep(qsfp2_mac_tx_axis_tkeep_int),
.qsfp2_mac_tx_axis_tvalid(qsfp2_mac_tx_axis_tvalid_int),
.qsfp2_mac_tx_axis_tready(qsfp2_mac_tx_axis_tready_int),
.qsfp2_mac_tx_axis_tlast(qsfp2_mac_tx_axis_tlast_int),
.qsfp2_mac_tx_axis_tuser(qsfp2_mac_tx_axis_tuser_int),
.qsfp2_mac_rx_axis_tdata(qsfp2_mac_rx_axis_tdata_int),
.qsfp2_mac_rx_axis_tkeep(qsfp2_mac_rx_axis_tkeep_int),
.qsfp2_mac_rx_axis_tvalid(qsfp2_mac_rx_axis_tvalid_int),
.qsfp2_mac_rx_axis_tlast(qsfp2_mac_rx_axis_tlast_int),
.qsfp2_mac_rx_axis_tuser(qsfp2_mac_rx_axis_tuser_int),
.qsfp2_mac_rx_status(qsfp2_mac_rx_status_int)
);
endmodule
`resetall

902
fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga_core.v Normal file
View File

@ -0,0 +1,902 @@
/*
Copyright 2021, The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
The views and conclusions contained in the software and documentation are those
of the authors and should not be interpreted as representing official policies,
either expressed or implied, of The Regents of the University of California.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA core logic
*/
module fpga_core #
(
// FW and board IDs
parameter FPGA_ID = 32'hC32450DD,
parameter FW_ID = 32'h00000000,
parameter FW_VER = 32'h00_00_01_00,
parameter BOARD_ID = 32'h1172_A00D,
parameter BOARD_VER = 32'h01_00_00_00,
parameter BUILD_DATE = 32'd1563227611,
parameter GIT_HASH = 32'hdce357bf,
parameter RELEASE_INFO = 32'h00000000,
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
parameter PORT_MASK = 0,
// Clock configuration
parameter CLK_PERIOD_NS_NUM = 4,
parameter CLK_PERIOD_NS_DENOM = 1,
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 4096,
parameter PTP_CLK_PERIOD_NS_DENOM = 825,
parameter PTP_TS_WIDTH = 96,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 1,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 1,
parameter PTP_PEROUT_COUNT = 1,
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE,
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE,
parameter EVENT_QUEUE_INDEX_WIDTH = 5,
parameter TX_QUEUE_INDEX_WIDTH = 13,
parameter RX_QUEUE_INDEX_WIDTH = 8,
parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
parameter EVENT_QUEUE_PIPELINE = 3,
parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0),
parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0),
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Interface configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 8,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 131072,
parameter MAX_TX_SIZE = 9214,
parameter MAX_RX_SIZE = 9214,
parameter TX_RAM_SIZE = 131072,
parameter RX_RAM_SIZE = 131072,
// Application block configuration
parameter APP_ID = 32'h00000000,
parameter APP_ENABLE = 0,
parameter APP_CTRL_ENABLE = 1,
parameter APP_DMA_ENABLE = 1,
parameter APP_AXIS_DIRECT_ENABLE = 1,
parameter APP_AXIS_SYNC_ENABLE = 1,
parameter APP_AXIS_IF_ENABLE = 1,
parameter APP_STAT_ENABLE = 1,
// DMA interface configuration
parameter DMA_IMM_ENABLE = 0,
parameter DMA_IMM_WIDTH = 32,
parameter DMA_LEN_WIDTH = 16,
parameter DMA_TAG_WIDTH = 16,
parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
parameter RAM_PIPELINE = 2,
// PCIe interface configuration
parameter SEG_COUNT = 2,
parameter SEG_DATA_WIDTH = 256,
parameter SEG_EMPTY_WIDTH = $clog2(SEG_DATA_WIDTH/32),
parameter SEG_HDR_WIDTH = 128,
parameter SEG_PRFX_WIDTH = 32,
parameter TX_SEQ_NUM_WIDTH = 6,
parameter PF_COUNT = 1,
parameter VF_COUNT = 0,
parameter PCIE_TAG_COUNT = 256,
parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
parameter PCIE_DMA_READ_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 2**TX_SEQ_NUM_WIDTH,
parameter PCIE_DMA_WRITE_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
// AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32,
parameter AXIL_CTRL_ADDR_WIDTH = 24,
// AXI lite interface configuration (application control)
parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH,
parameter AXIL_APP_CTRL_ADDR_WIDTH = 24,
// Ethernet interface configuration
parameter AXIS_ETH_DATA_WIDTH = 512,
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8,
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH,
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1,
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_PIPELINE = 0,
parameter AXIS_ETH_TX_FIFO_PIPELINE = 2,
parameter AXIS_ETH_TX_TS_PIPELINE = 0,
parameter AXIS_ETH_RX_PIPELINE = 0,
parameter AXIS_ETH_RX_FIFO_PIPELINE = 2,
// Statistics counter subsystem
parameter STAT_ENABLE = 1,
parameter STAT_DMA_ENABLE = 1,
parameter STAT_PCIE_ENABLE = 1,
parameter STAT_INC_WIDTH = 24,
parameter STAT_ID_WIDTH = 12
)
(
/*
* Clock: 250 MHz
* Synchronous reset
*/
input wire clk_250mhz,
input wire rst_250mhz,
/*
* PTP clock
*/
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
/*
* GPIO
*/
input wire user_pb,
output wire [3:0] user_led_g,
/*
* I2C
*/
input wire i2c2_scl_i,
output wire i2c2_scl_o,
output wire i2c2_scl_t,
input wire i2c2_sda_i,
output wire i2c2_sda_o,
output wire i2c2_sda_t,
output wire bmc_i2c2_disable,
/*
* P-Tile interface
*/
input wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] rx_st_data,
input wire [SEG_COUNT*SEG_EMPTY_WIDTH-1:0] rx_st_empty,
input wire [SEG_COUNT-1:0] rx_st_sop,
input wire [SEG_COUNT-1:0] rx_st_eop,
input wire [SEG_COUNT-1:0] rx_st_valid,
output wire rx_st_ready,
input wire [SEG_COUNT*SEG_HDR_WIDTH-1:0] rx_st_hdr,
input wire [SEG_COUNT*SEG_PRFX_WIDTH-1:0] rx_st_tlp_prfx,
input wire [SEG_COUNT-1:0] rx_st_vf_active,
input wire [SEG_COUNT*3-1:0] rx_st_func_num,
input wire [SEG_COUNT*11-1:0] rx_st_vf_num,
input wire [SEG_COUNT*3-1:0] rx_st_bar_range,
input wire [SEG_COUNT-1:0] rx_st_tlp_abort,
output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] tx_st_data,
output wire [SEG_COUNT-1:0] tx_st_sop,
output wire [SEG_COUNT-1:0] tx_st_eop,
output wire [SEG_COUNT-1:0] tx_st_valid,
input wire tx_st_ready,
output wire [SEG_COUNT-1:0] tx_st_err,
output wire [SEG_COUNT*SEG_HDR_WIDTH-1:0] tx_st_hdr,
output wire [SEG_COUNT*SEG_PRFX_WIDTH-1:0] tx_st_tlp_prfx,
output wire [11:0] rx_buffer_limit,
output wire [1:0] rx_buffer_limit_tdm_idx,
input wire [15:0] tx_cdts_limit,
input wire [2:0] tx_cdts_limit_tdm_idx,
input wire [15:0] tl_cfg_ctl,
input wire [4:0] tl_cfg_add,
input wire [2:0] tl_cfg_func,
/*
* Ethernet: QSFP28
*/
input wire qsfp1_mac_clk,
input wire qsfp1_mac_rst,
output wire [PTP_TS_WIDTH-1:0] qsfp1_mac_ptp_time,
input wire [PTP_TS_WIDTH-1:0] qsfp1_mac_tx_ptp_ts,
input wire [TX_TAG_WIDTH-1:0] qsfp1_mac_tx_ptp_ts_tag,
input wire qsfp1_mac_tx_ptp_ts_valid,
output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_mac_tx_axis_tdata,
output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_mac_tx_axis_tkeep,
output wire qsfp1_mac_tx_axis_tvalid,
input wire qsfp1_mac_tx_axis_tready,
output wire qsfp1_mac_tx_axis_tlast,
output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfp1_mac_tx_axis_tuser,
input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_mac_rx_axis_tdata,
input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_mac_rx_axis_tkeep,
input wire qsfp1_mac_rx_axis_tvalid,
input wire qsfp1_mac_rx_axis_tlast,
input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfp1_mac_rx_axis_tuser,
input wire qsfp1_mac_rx_status,
input wire qsfp2_mac_clk,
input wire qsfp2_mac_rst,
output wire [PTP_TS_WIDTH-1:0] qsfp2_mac_ptp_time,
input wire [PTP_TS_WIDTH-1:0] qsfp2_mac_tx_ptp_ts,
input wire [TX_TAG_WIDTH-1:0] qsfp2_mac_tx_ptp_ts_tag,
input wire qsfp2_mac_tx_ptp_ts_valid,
output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp2_mac_tx_axis_tdata,
output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp2_mac_tx_axis_tkeep,
output wire qsfp2_mac_tx_axis_tvalid,
input wire qsfp2_mac_tx_axis_tready,
output wire qsfp2_mac_tx_axis_tlast,
output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfp2_mac_tx_axis_tuser,
input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp2_mac_rx_axis_tdata,
input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp2_mac_rx_axis_tkeep,
input wire qsfp2_mac_rx_axis_tvalid,
input wire qsfp2_mac_rx_axis_tlast,
input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfp2_mac_rx_axis_tuser,
input wire qsfp2_mac_rx_status
);
parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF;
parameter F_COUNT = PF_COUNT+VF_COUNT;
parameter AXIL_CTRL_STRB_WIDTH = (AXIL_CTRL_DATA_WIDTH/8);
parameter AXIL_IF_CTRL_ADDR_WIDTH = AXIL_CTRL_ADDR_WIDTH-$clog2(IF_COUNT);
parameter AXIL_CSR_ADDR_WIDTH = AXIL_IF_CTRL_ADDR_WIDTH-5-$clog2((PORTS_PER_IF+3)/8);
localparam RB_BASE_ADDR = 16'h1000;
localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}};
initial begin
if (PORT_COUNT > 2) begin
$error("Error: Max port count exceeded (instance %m)");
$finish;
end
end
// AXI lite connections
wire [AXIL_CSR_ADDR_WIDTH-1:0] axil_csr_awaddr;
wire [2:0] axil_csr_awprot;
wire axil_csr_awvalid;
wire axil_csr_awready;
wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_csr_wdata;
wire [AXIL_CTRL_STRB_WIDTH-1:0] axil_csr_wstrb;
wire axil_csr_wvalid;
wire axil_csr_wready;
wire [1:0] axil_csr_bresp;
wire axil_csr_bvalid;
wire axil_csr_bready;
wire [AXIL_CSR_ADDR_WIDTH-1:0] axil_csr_araddr;
wire [2:0] axil_csr_arprot;
wire axil_csr_arvalid;
wire axil_csr_arready;
wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_csr_rdata;
wire [1:0] axil_csr_rresp;
wire axil_csr_rvalid;
wire axil_csr_rready;
// PTP
wire [PTP_TS_WIDTH-1:0] ptp_ts_96;
wire ptp_ts_step;
wire ptp_pps;
wire ptp_pps_str;
wire [PTP_TS_WIDTH-1:0] ptp_sync_ts_96;
wire ptp_sync_ts_step;
wire ptp_sync_pps;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error;
wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse;
// control registers
wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_wr_addr;
wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_wr_data;
wire [AXIL_CTRL_STRB_WIDTH-1:0] ctrl_reg_wr_strb;
wire ctrl_reg_wr_en;
wire ctrl_reg_wr_wait;
wire ctrl_reg_wr_ack;
wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_rd_addr;
wire ctrl_reg_rd_en;
wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data;
wire ctrl_reg_rd_wait;
wire ctrl_reg_rd_ack;
reg ctrl_reg_wr_ack_reg = 1'b0;
reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}};
reg ctrl_reg_rd_ack_reg = 1'b0;
reg i2c2_scl_o_reg = 1'b1;
reg i2c2_sda_o_reg = 1'b1;
assign ctrl_reg_wr_wait = 1'b0;
assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg;
assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg;
assign ctrl_reg_rd_wait = 1'b0;
assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg;
assign i2c2_scl_o = i2c2_scl_o_reg;
assign i2c2_scl_t = i2c2_scl_o_reg;
assign i2c2_sda_o = i2c2_sda_o_reg;
assign i2c2_sda_t = i2c2_sda_o_reg;
assign bmc_i2c2_disable = 1'b1;
always @(posedge clk_250mhz) begin
ctrl_reg_wr_ack_reg <= 1'b0;
ctrl_reg_rd_data_reg <= {AXIL_CTRL_DATA_WIDTH{1'b0}};
ctrl_reg_rd_ack_reg <= 1'b0;
if (ctrl_reg_wr_en && !ctrl_reg_wr_ack_reg) begin
// write operation
ctrl_reg_wr_ack_reg <= 1'b0;
case ({ctrl_reg_wr_addr >> 2, 2'b00})
// I2C 0
RBB+8'h0C: begin
// I2C ctrl: control
if (ctrl_reg_wr_strb[0]) begin
i2c2_scl_o_reg <= ctrl_reg_wr_data[1];
end
if (ctrl_reg_wr_strb[1]) begin
i2c2_sda_o_reg <= ctrl_reg_wr_data[9];
end
end
default: ctrl_reg_wr_ack_reg <= 1'b0;
endcase
end
if (ctrl_reg_rd_en && !ctrl_reg_rd_ack_reg) begin
// read operation
ctrl_reg_rd_ack_reg <= 1'b1;
case ({ctrl_reg_rd_addr >> 2, 2'b00})
// I2C 0
RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C110; // I2C ctrl: Type
RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000100; // I2C ctrl: Version
RBB+8'h08: ctrl_reg_rd_data_reg <= 0; // I2C ctrl: Next header
RBB+8'h0C: begin
// I2C ctrl: control
ctrl_reg_rd_data_reg[0] <= i2c2_scl_i;
ctrl_reg_rd_data_reg[1] <= i2c2_scl_o_reg;
ctrl_reg_rd_data_reg[8] <= i2c2_sda_i;
ctrl_reg_rd_data_reg[9] <= i2c2_sda_o_reg;
end
default: ctrl_reg_rd_ack_reg <= 1'b0;
endcase
end
if (rst_250mhz) begin
ctrl_reg_wr_ack_reg <= 1'b0;
ctrl_reg_rd_ack_reg <= 1'b0;
i2c2_scl_o_reg <= 1'b1;
i2c2_sda_o_reg <= 1'b1;
end
end
assign user_led_g[0] = qsfp1_mac_rx_status;
assign user_led_g[1] = qsfp2_mac_rx_status;
assign user_led_g[2] = 1'b0;
assign user_led_g[3] = ptp_pps_str;
wire [PORT_COUNT-1:0] eth_tx_clk;
wire [PORT_COUNT-1:0] eth_tx_rst;
wire [PORT_COUNT-1:0] eth_tx_ptp_clk;
wire [PORT_COUNT-1:0] eth_tx_ptp_rst;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts_96;
wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step;
wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_tx_tdata;
wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_tx_tkeep;
wire [PORT_COUNT-1:0] axis_eth_tx_tvalid;
wire [PORT_COUNT-1:0] axis_eth_tx_tready;
wire [PORT_COUNT-1:0] axis_eth_tx_tlast;
wire [PORT_COUNT*AXIS_ETH_TX_USER_WIDTH-1:0] axis_eth_tx_tuser;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts;
wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready;
wire [PORT_COUNT-1:0] eth_tx_status;
wire [PORT_COUNT-1:0] eth_rx_clk;
wire [PORT_COUNT-1:0] eth_rx_rst;
wire [PORT_COUNT-1:0] eth_rx_ptp_clk;
wire [PORT_COUNT-1:0] eth_rx_ptp_rst;
wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts_96;
wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step;
wire [PORT_COUNT*AXIS_ETH_DATA_WIDTH-1:0] axis_eth_rx_tdata;
wire [PORT_COUNT*AXIS_ETH_KEEP_WIDTH-1:0] axis_eth_rx_tkeep;
wire [PORT_COUNT-1:0] axis_eth_rx_tvalid;
wire [PORT_COUNT-1:0] axis_eth_rx_tready;
wire [PORT_COUNT-1:0] axis_eth_rx_tlast;
wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser;
wire [PORT_COUNT-1:0] eth_rx_status;
mqnic_port_map_mac_axis #(
.MAC_COUNT(2),
.PORT_MASK(PORT_MASK),
.PORT_GROUP_SIZE(1),
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.PORT_COUNT(PORT_COUNT),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(TX_TAG_WIDTH),
.AXIS_DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
.AXIS_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
.AXIS_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH)
)
mqnic_port_map_mac_axis_inst (
// towards MAC
.mac_tx_clk({qsfp2_mac_clk, qsfp1_mac_clk}),
.mac_tx_rst({qsfp2_mac_rst, qsfp1_mac_rst}),
.mac_tx_ptp_clk({qsfp2_mac_clk, qsfp1_mac_clk}),
.mac_tx_ptp_rst({qsfp2_mac_rst, qsfp1_mac_rst}),
.mac_tx_ptp_ts_96({qsfp2_mac_ptp_time, qsfp1_mac_ptp_time}),
.mac_tx_ptp_ts_step(),
.m_axis_mac_tx_tdata({qsfp2_mac_tx_axis_tdata, qsfp1_mac_tx_axis_tdata}),
.m_axis_mac_tx_tkeep({qsfp2_mac_tx_axis_tkeep, qsfp1_mac_tx_axis_tkeep}),
.m_axis_mac_tx_tvalid({qsfp2_mac_tx_axis_tvalid, qsfp1_mac_tx_axis_tvalid}),
.m_axis_mac_tx_tready({qsfp2_mac_tx_axis_tready, qsfp1_mac_tx_axis_tready}),
.m_axis_mac_tx_tlast({qsfp2_mac_tx_axis_tlast, qsfp1_mac_tx_axis_tlast}),
.m_axis_mac_tx_tuser({qsfp2_mac_tx_axis_tuser, qsfp1_mac_tx_axis_tuser}),
.s_axis_mac_tx_ptp_ts({qsfp2_mac_tx_ptp_ts, qsfp1_mac_tx_ptp_ts}),
.s_axis_mac_tx_ptp_ts_tag({qsfp2_mac_tx_ptp_ts_tag, qsfp1_mac_tx_ptp_ts_tag}),
.s_axis_mac_tx_ptp_ts_valid({qsfp2_mac_tx_ptp_ts_valid, qsfp1_mac_tx_ptp_ts_valid}),
.s_axis_mac_tx_ptp_ts_ready(),
.mac_tx_status(2'b11),
.mac_rx_clk({qsfp2_mac_clk, qsfp1_mac_clk}),
.mac_rx_rst({qsfp2_mac_rst, qsfp1_mac_rst}),
.mac_rx_ptp_clk({qsfp2_mac_clk, qsfp1_mac_clk}),
.mac_rx_ptp_rst({qsfp2_mac_rst, qsfp1_mac_rst}),
.mac_rx_ptp_ts_96(),
.mac_rx_ptp_ts_step(),
.s_axis_mac_rx_tdata({qsfp2_mac_rx_axis_tdata, qsfp1_mac_rx_axis_tdata}),
.s_axis_mac_rx_tkeep({qsfp2_mac_rx_axis_tkeep, qsfp1_mac_rx_axis_tkeep}),
.s_axis_mac_rx_tvalid({qsfp2_mac_rx_axis_tvalid, qsfp1_mac_rx_axis_tvalid}),
.s_axis_mac_rx_tready(),
.s_axis_mac_rx_tlast({qsfp2_mac_rx_axis_tlast, qsfp1_mac_rx_axis_tlast}),
.s_axis_mac_rx_tuser({qsfp2_mac_rx_axis_tuser, qsfp1_mac_rx_axis_tuser}),
.mac_rx_status({qsfp2_mac_rx_status, qsfp1_mac_rx_status}),
// towards datapath
.tx_clk(eth_tx_clk),
.tx_rst(eth_tx_rst),
.tx_ptp_clk(eth_tx_ptp_clk),
.tx_ptp_rst(eth_tx_ptp_rst),
.tx_ptp_ts_96(eth_tx_ptp_ts_96),
.tx_ptp_ts_step(eth_tx_ptp_ts_step),
.s_axis_tx_tdata(axis_eth_tx_tdata),
.s_axis_tx_tkeep(axis_eth_tx_tkeep),
.s_axis_tx_tvalid(axis_eth_tx_tvalid),
.s_axis_tx_tready(axis_eth_tx_tready),
.s_axis_tx_tlast(axis_eth_tx_tlast),
.s_axis_tx_tuser(axis_eth_tx_tuser),
.m_axis_tx_ptp_ts(axis_eth_tx_ptp_ts),
.m_axis_tx_ptp_ts_tag(axis_eth_tx_ptp_ts_tag),
.m_axis_tx_ptp_ts_valid(axis_eth_tx_ptp_ts_valid),
.m_axis_tx_ptp_ts_ready(axis_eth_tx_ptp_ts_ready),
.tx_status(eth_tx_status),
.rx_clk(eth_rx_clk),
.rx_rst(eth_rx_rst),
.rx_ptp_clk(eth_rx_ptp_clk),
.rx_ptp_rst(eth_rx_ptp_rst),
.rx_ptp_ts_96(eth_rx_ptp_ts_96),
.rx_ptp_ts_step(eth_rx_ptp_ts_step),
.m_axis_rx_tdata(axis_eth_rx_tdata),
.m_axis_rx_tkeep(axis_eth_rx_tkeep),
.m_axis_rx_tvalid(axis_eth_rx_tvalid),
.m_axis_rx_tready(axis_eth_rx_tready),
.m_axis_rx_tlast(axis_eth_rx_tlast),
.m_axis_rx_tuser(axis_eth_rx_tuser),
.rx_status(eth_rx_status)
);
mqnic_core_pcie_ptile #(
// FW and board IDs
.FPGA_ID(FPGA_ID),
.FW_ID(FW_ID),
.FW_VER(FW_VER),
.BOARD_ID(BOARD_ID),
.BOARD_VER(BOARD_VER),
.BUILD_DATE(BUILD_DATE),
.GIT_HASH(GIT_HASH),
.RELEASE_INFO(RELEASE_INFO),
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
.PORT_COUNT(PORT_COUNT),
// Clock configuration
.CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM),
.CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM),
// PTP configuration
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_TX_CLOCK(0),
.PTP_SEPARATE_RX_CLOCK(0),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.EVENT_QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE),
.TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE),
.RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE),
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_CPL_ENABLE(PTP_TS_ENABLE),
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE),
.MAX_RX_SIZE(MAX_RX_SIZE),
.TX_RAM_SIZE(TX_RAM_SIZE),
.RX_RAM_SIZE(RX_RAM_SIZE),
// Application block configuration
.APP_ID(APP_ID),
.APP_ENABLE(APP_ENABLE),
.APP_CTRL_ENABLE(APP_CTRL_ENABLE),
.APP_DMA_ENABLE(APP_DMA_ENABLE),
.APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE),
.APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE),
.APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE),
.APP_STAT_ENABLE(APP_STAT_ENABLE),
.APP_GPIO_IN_WIDTH(32),
.APP_GPIO_OUT_WIDTH(32),
// DMA interface configuration
.DMA_IMM_ENABLE(DMA_IMM_ENABLE),
.DMA_IMM_WIDTH(DMA_IMM_WIDTH),
.DMA_LEN_WIDTH(DMA_LEN_WIDTH),
.DMA_TAG_WIDTH(DMA_TAG_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.RAM_PIPELINE(RAM_PIPELINE),
// PCIe interface configuration
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_EMPTY_WIDTH(SEG_EMPTY_WIDTH),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.PF_COUNT(PF_COUNT),
.VF_COUNT(VF_COUNT),
.F_COUNT(F_COUNT),
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.PCIE_DMA_READ_OP_TABLE_SIZE(PCIE_DMA_READ_OP_TABLE_SIZE),
.PCIE_DMA_READ_TX_LIMIT(PCIE_DMA_READ_TX_LIMIT),
.PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE),
.PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT),
// Interrupt configuration
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH),
// AXI lite interface configuration (control)
.AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
.AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH),
.AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH),
.AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH),
.AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH),
.AXIL_CSR_PASSTHROUGH_ENABLE(0),
.RB_NEXT_PTR(RB_BASE_ADDR),
// AXI lite interface configuration (application control)
.AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH),
.AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH),
// Ethernet interface configuration
.AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
.AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
.AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH),
.AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
.AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH),
.AXIS_ETH_RX_USE_READY(0),
.AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE),
.AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE),
.AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE),
.AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE),
.AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE),
// Statistics counter subsystem
.STAT_ENABLE(STAT_ENABLE),
.STAT_DMA_ENABLE(STAT_DMA_ENABLE),
.STAT_PCIE_ENABLE(STAT_PCIE_ENABLE),
.STAT_INC_WIDTH(STAT_INC_WIDTH),
.STAT_ID_WIDTH(STAT_ID_WIDTH)
)
core_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* P-Tile RX AVST interface
*/
.rx_st_data(rx_st_data),
.rx_st_empty(rx_st_empty),
.rx_st_sop(rx_st_sop),
.rx_st_eop(rx_st_eop),
.rx_st_valid(rx_st_valid),
.rx_st_ready(rx_st_ready),
.rx_st_hdr(rx_st_hdr),
.rx_st_tlp_prfx(rx_st_tlp_prfx),
.rx_st_vf_active(rx_st_vf_active),
.rx_st_func_num(rx_st_func_num),
.rx_st_vf_num(rx_st_vf_num),
.rx_st_bar_range(rx_st_bar_range),
.rx_st_tlp_abort(rx_st_tlp_abort),
/*
* P-Tile TX AVST interface
*/
.tx_st_data(tx_st_data),
.tx_st_sop(tx_st_sop),
.tx_st_eop(tx_st_eop),
.tx_st_valid(tx_st_valid),
.tx_st_ready(tx_st_ready),
.tx_st_err(tx_st_err),
.tx_st_hdr(tx_st_hdr),
.tx_st_tlp_prfx(tx_st_tlp_prfx),
/*
* P-Tile RX flow control
*/
.rx_buffer_limit(rx_buffer_limit),
.rx_buffer_limit_tdm_idx(rx_buffer_limit_tdm_idx),
/*
* P-Tile TX flow control
*/
.tx_cdts_limit(tx_cdts_limit),
.tx_cdts_limit_tdm_idx(tx_cdts_limit_tdm_idx),
/*
* P-Tile configuration interface
*/
.tl_cfg_ctl(tl_cfg_ctl),
.tl_cfg_add(tl_cfg_add),
.tl_cfg_func(tl_cfg_func),
/*
* AXI-Lite master interface (passthrough for NIC control and status)
*/
.m_axil_csr_awaddr(axil_csr_awaddr),
.m_axil_csr_awprot(axil_csr_awprot),
.m_axil_csr_awvalid(axil_csr_awvalid),
.m_axil_csr_awready(axil_csr_awready),
.m_axil_csr_wdata(axil_csr_wdata),
.m_axil_csr_wstrb(axil_csr_wstrb),
.m_axil_csr_wvalid(axil_csr_wvalid),
.m_axil_csr_wready(axil_csr_wready),
.m_axil_csr_bresp(axil_csr_bresp),
.m_axil_csr_bvalid(axil_csr_bvalid),
.m_axil_csr_bready(axil_csr_bready),
.m_axil_csr_araddr(axil_csr_araddr),
.m_axil_csr_arprot(axil_csr_arprot),
.m_axil_csr_arvalid(axil_csr_arvalid),
.m_axil_csr_arready(axil_csr_arready),
.m_axil_csr_rdata(axil_csr_rdata),
.m_axil_csr_rresp(axil_csr_rresp),
.m_axil_csr_rvalid(axil_csr_rvalid),
.m_axil_csr_rready(axil_csr_rready),
/*
* Control register interface
*/
.ctrl_reg_wr_addr(ctrl_reg_wr_addr),
.ctrl_reg_wr_data(ctrl_reg_wr_data),
.ctrl_reg_wr_strb(ctrl_reg_wr_strb),
.ctrl_reg_wr_en(ctrl_reg_wr_en),
.ctrl_reg_wr_wait(ctrl_reg_wr_wait),
.ctrl_reg_wr_ack(ctrl_reg_wr_ack),
.ctrl_reg_rd_addr(ctrl_reg_rd_addr),
.ctrl_reg_rd_en(ctrl_reg_rd_en),
.ctrl_reg_rd_data(ctrl_reg_rd_data),
.ctrl_reg_rd_wait(ctrl_reg_rd_wait),
.ctrl_reg_rd_ack(ctrl_reg_rd_ack),
/*
* PTP clock
*/
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_pps_str(ptp_pps_str),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_sync_pps(ptp_sync_pps),
.ptp_sync_ts_96(ptp_sync_ts_96),
.ptp_sync_ts_step(ptp_sync_ts_step),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),
/*
* Ethernet
*/
.eth_tx_clk(eth_tx_clk),
.eth_tx_rst(eth_tx_rst),
.eth_tx_ptp_clk(eth_tx_ptp_clk),
.eth_tx_ptp_rst(eth_tx_ptp_rst),
.eth_tx_ptp_ts_96(eth_tx_ptp_ts_96),
.eth_tx_ptp_ts_step(eth_tx_ptp_ts_step),
.m_axis_eth_tx_tdata(axis_eth_tx_tdata),
.m_axis_eth_tx_tkeep(axis_eth_tx_tkeep),
.m_axis_eth_tx_tvalid(axis_eth_tx_tvalid),
.m_axis_eth_tx_tready(axis_eth_tx_tready),
.m_axis_eth_tx_tlast(axis_eth_tx_tlast),
.m_axis_eth_tx_tuser(axis_eth_tx_tuser),
.s_axis_eth_tx_cpl_ts(axis_eth_tx_ptp_ts),
.s_axis_eth_tx_cpl_tag(axis_eth_tx_ptp_ts_tag),
.s_axis_eth_tx_cpl_valid(axis_eth_tx_ptp_ts_valid),
.s_axis_eth_tx_cpl_ready(axis_eth_tx_ptp_ts_ready),
.eth_tx_status(eth_tx_status),
.eth_rx_clk(eth_rx_clk),
.eth_rx_rst(eth_rx_rst),
.eth_rx_ptp_clk(eth_rx_ptp_clk),
.eth_rx_ptp_rst(eth_rx_ptp_rst),
.eth_rx_ptp_ts_96(eth_rx_ptp_ts_96),
.eth_rx_ptp_ts_step(eth_rx_ptp_ts_step),
.s_axis_eth_rx_tdata(axis_eth_rx_tdata),
.s_axis_eth_rx_tkeep(axis_eth_rx_tkeep),
.s_axis_eth_rx_tvalid(axis_eth_rx_tvalid),
.s_axis_eth_rx_tready(axis_eth_rx_tready),
.s_axis_eth_rx_tlast(axis_eth_rx_tlast),
.s_axis_eth_rx_tuser(axis_eth_rx_tuser),
.eth_rx_status(eth_rx_status),
/*
* Statistics input
*/
.s_axis_stat_tdata(0),
.s_axis_stat_tid(0),
.s_axis_stat_tvalid(1'b0),
.s_axis_stat_tready(),
/*
* GPIO
*/
.app_gpio_in(0),
.app_gpio_out(),
/*
* JTAG
*/
.app_jtag_tdi(1'b0),
.app_jtag_tdo(),
.app_jtag_tms(1'b0),
.app_jtag_tck(1'b0)
);
endmodule
`resetall

62
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/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`resetall
`timescale 1 ns / 1 ps
`default_nettype none
/*
* Synchronizes an asyncronous signal to a given clock by using a pipeline of
* two registers.
*/
module sync_signal #(
parameter WIDTH=1, // width of the input and output signals
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire [WIDTH-1:0] in,
output wire [WIDTH-1:0] out
);
reg [WIDTH-1:0] sync_reg[N-1:0];
/*
* The synchronized output is the last register in the pipeline.
*/
assign out = sync_reg[N-1];
integer k;
always @(posedge clk) begin
sync_reg[0] <= in;
for (k = 1; k < N; k = k + 1) begin
sync_reg[k] <= sync_reg[k-1];
end
end
endmodule
`resetall

268
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/*
Copyright (c) 2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Transceiver control
*/
module xcvr_ctrl (
input wire reconfig_clk,
input wire reconfig_rst,
input wire pll_locked_in,
output wire [18:0] xcvr_reconfig_address,
output wire xcvr_reconfig_read,
output wire xcvr_reconfig_write,
input wire [7:0] xcvr_reconfig_readdata,
output wire [7:0] xcvr_reconfig_writedata,
input wire xcvr_reconfig_waitrequest
);
localparam [3:0]
STATE_IDLE = 4'd0,
STATE_LOAD_PMA_1 = 4'd1,
STATE_LOAD_PMA_2 = 4'd2,
STATE_INIT_ADAPT_1 = 4'd3,
STATE_INIT_ADAPT_2 = 4'd4,
STATE_INIT_ADAPT_3 = 4'd5,
STATE_INIT_ADAPT_4 = 4'd6,
STATE_CONT_ADAPT_1 = 4'd7,
STATE_CONT_ADAPT_2 = 4'd8,
STATE_CONT_ADAPT_3 = 4'd9,
STATE_CONT_ADAPT_4 = 4'd10,
STATE_DONE = 4'd11;
reg [3:0] state_reg = STATE_IDLE, state_next;
reg [18:0] xcvr_reconfig_address_reg = 19'd0, xcvr_reconfig_address_next;
reg xcvr_reconfig_read_reg = 1'b0, xcvr_reconfig_read_next;
reg xcvr_reconfig_write_reg = 1'b0, xcvr_reconfig_write_next;
reg [7:0] xcvr_reconfig_writedata_reg = 8'd0, xcvr_reconfig_writedata_next;
reg [7:0] read_data_reg = 8'd0, read_data_next;
reg read_data_valid_reg = 1'b0, read_data_valid_next;
reg [15:0] delay_count_reg = 0, delay_count_next;
reg pll_locked_sync_1_reg = 0;
reg pll_locked_sync_2_reg = 0;
reg pll_locked_sync_3_reg = 0;
assign xcvr_reconfig_address = xcvr_reconfig_address_reg;
assign xcvr_reconfig_read = xcvr_reconfig_read_reg;
assign xcvr_reconfig_write = xcvr_reconfig_write_reg;
assign xcvr_reconfig_writedata = xcvr_reconfig_writedata_reg;
always @(posedge reconfig_clk) begin
pll_locked_sync_1_reg <= pll_locked_in;
pll_locked_sync_2_reg <= pll_locked_sync_1_reg;
pll_locked_sync_3_reg <= pll_locked_sync_2_reg;
end
always @* begin
state_next = STATE_IDLE;
xcvr_reconfig_address_next = xcvr_reconfig_address_reg;
xcvr_reconfig_read_next = 1'b0;
xcvr_reconfig_write_next = 1'b0;
xcvr_reconfig_writedata_next = xcvr_reconfig_writedata_reg;
read_data_next = read_data_reg;
read_data_valid_next = read_data_valid_reg;
delay_count_next = delay_count_reg;
if (xcvr_reconfig_read_reg || xcvr_reconfig_write_reg) begin
// operation in progress
if (xcvr_reconfig_waitrequest) begin
// wait state, hold command
xcvr_reconfig_read_next = xcvr_reconfig_read_reg;
xcvr_reconfig_write_next = xcvr_reconfig_write_reg;
end else begin
// release command
xcvr_reconfig_read_next = 1'b0;
xcvr_reconfig_write_next = 1'b0;
if (xcvr_reconfig_read_reg) begin
// latch read data
read_data_next = xcvr_reconfig_readdata;
read_data_valid_next = 1'b1;
end
end
state_next = state_reg;
end else if (delay_count_reg != 0) begin
// stall for delay
delay_count_next = delay_count_reg - 1;
state_next = state_reg;
end else begin
read_data_valid_next = 1'b0;
case (state_reg)
STATE_IDLE: begin
// wait for PLL to lock
if (pll_locked_sync_3_reg) begin
delay_count_next = 16'hffff;
state_next = STATE_LOAD_PMA_1;
end else begin
state_next = STATE_IDLE;
end
end
STATE_LOAD_PMA_1: begin
// load PMA config
xcvr_reconfig_address_next = 19'h40143;
xcvr_reconfig_writedata_next = 8'h80;
xcvr_reconfig_write_next = 1'b1;
state_next = STATE_LOAD_PMA_2;
end
STATE_LOAD_PMA_2: begin
// check status
if (read_data_valid_reg && read_data_reg[0]) begin
// start initial adaptation
xcvr_reconfig_address_next = 19'h200;
xcvr_reconfig_writedata_next = 8'hD2;
xcvr_reconfig_write_next = 1'b1;
state_next = STATE_INIT_ADAPT_1;
end else begin
// read status
xcvr_reconfig_address_next = 19'h40144;
xcvr_reconfig_read_next = 1'b1;
state_next = STATE_LOAD_PMA_2;
end
end
STATE_INIT_ADAPT_1: begin
// start initial adaptation
xcvr_reconfig_address_next = 19'h201;
xcvr_reconfig_writedata_next = 8'h02;
xcvr_reconfig_write_next = 1'b1;
state_next = STATE_INIT_ADAPT_2;
end
STATE_INIT_ADAPT_2: begin
// start initial adaptation
xcvr_reconfig_address_next = 19'h202;
xcvr_reconfig_writedata_next = 8'h01;
xcvr_reconfig_write_next = 1'b1;
state_next = STATE_INIT_ADAPT_3;
end
STATE_INIT_ADAPT_3: begin
// start initial adaptation
xcvr_reconfig_address_next = 19'h203;
xcvr_reconfig_writedata_next = 8'h96;
xcvr_reconfig_write_next = 1'b1;
state_next = STATE_INIT_ADAPT_4;
end
STATE_INIT_ADAPT_4: begin
// check status
if (read_data_valid_reg && read_data_reg == 8'h80) begin
// start continuous adaptation
xcvr_reconfig_address_next = 19'h200;
xcvr_reconfig_writedata_next = 8'hF6;
xcvr_reconfig_write_next = 1'b1;
state_next = STATE_CONT_ADAPT_1;
end else begin
// read status
xcvr_reconfig_address_next = 19'h207;
xcvr_reconfig_read_next = 1'b1;
state_next = STATE_INIT_ADAPT_4;
end
end
STATE_CONT_ADAPT_1: begin
// start continuous adaptation
xcvr_reconfig_address_next = 19'h201;
xcvr_reconfig_writedata_next = 8'h01;
xcvr_reconfig_write_next = 1'b1;
state_next = STATE_CONT_ADAPT_2;
end
STATE_CONT_ADAPT_2: begin
// start continuous adaptation
xcvr_reconfig_address_next = 19'h202;
xcvr_reconfig_writedata_next = 8'h03;
xcvr_reconfig_write_next = 1'b1;
state_next = STATE_CONT_ADAPT_3;
end
STATE_CONT_ADAPT_3: begin
// start continuous adaptation
xcvr_reconfig_address_next = 19'h203;
xcvr_reconfig_writedata_next = 8'h96;
xcvr_reconfig_write_next = 1'b1;
state_next = STATE_CONT_ADAPT_4;
end
STATE_CONT_ADAPT_4: begin
// check status
if (read_data_valid_reg && read_data_reg == 8'h80) begin
// done
state_next = STATE_DONE;
end else begin
// read status
xcvr_reconfig_address_next = 19'h207;
xcvr_reconfig_read_next = 1'b1;
state_next = STATE_CONT_ADAPT_4;
end
end
STATE_DONE: begin
// done with operation
state_next = STATE_DONE;
end
endcase
end
if (!pll_locked_sync_3_reg) begin
// go back to idle if PLL is unlocked
state_next = STATE_IDLE;
end
end
always @(posedge reconfig_clk) begin
state_reg <= state_next;
xcvr_reconfig_address_reg <= xcvr_reconfig_address_next;
xcvr_reconfig_read_reg <= xcvr_reconfig_read_next;
xcvr_reconfig_write_reg <= xcvr_reconfig_write_next;
xcvr_reconfig_writedata_reg <= xcvr_reconfig_writedata_next;
read_data_reg <= read_data_next;
read_data_valid_reg <= read_data_valid_next;
delay_count_reg <= delay_count_next;
if (reconfig_rst) begin
state_reg <= STATE_IDLE;
xcvr_reconfig_read_reg <= 1'b0;
xcvr_reconfig_write_reg <= 1'b0;
read_data_valid_reg <= 1'b0;
delay_count_reg <= 0;
end
end
endmodule
`resetall

284
fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/Makefile Normal file
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# Copyright 2020-2022, The Regents of the University of California.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
# OF SUCH DAMAGE.
#
# The views and conclusions contained in the software and documentation are those
# of the authors and should not be interpreted as representing official policies,
# either expressed or implied, of The Regents of the University of California.
TOPLEVEL_LANG = verilog
SIM ?= icarus
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
DUT = fpga_core
TOPLEVEL = $(DUT)
MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_ptile.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_l2_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rx_queue_map.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
VERILOG_SOURCES += ../../rtl/common/mqnic_rb_clk_info.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port_map_mac_axis.v
VERILOG_SOURCES += ../../rtl/common/cpl_write.v
VERILOG_SOURCES += ../../rtl/common/cpl_op_mux.v
VERILOG_SOURCES += ../../rtl/common/desc_fetch.v
VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
VERILOG_SOURCES += ../../rtl/common/rx_fifo.v
VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v
VERILOG_SOURCES += ../../rtl/common/tx_engine.v
VERILOG_SOURCES += ../../rtl/common/rx_engine.v
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
VERILOG_SOURCES += ../../rtl/common/rx_hash.v
VERILOG_SOURCES += ../../rtl/common/rx_checksum.v
VERILOG_SOURCES += ../../rtl/common/stats_counter.v
VERILOG_SOURCES += ../../rtl/common/stats_collect.v
VERILOG_SOURCES += ../../rtl/common/stats_pcie_if.v
VERILOG_SOURCES += ../../rtl/common/stats_pcie_tlp.v
VERILOG_SOURCES += ../../rtl/common/stats_dma_if_pcie.v
VERILOG_SOURCES += ../../rtl/common/stats_dma_latency.v
VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v
VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v
VERILOG_SOURCES += ../../rtl/common/tdma_scheduler.v
VERILOG_SOURCES += ../../rtl/common/tdma_ber.v
VERILOG_SOURCES += ../../rtl/common/tdma_ber_ch.v
VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_interconnect.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_rd.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_wr.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_rd.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_wr.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_rd.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_wr.v
VERILOG_SOURCES += ../../lib/axi/rtl/arbiter.v
VERILOG_SOURCES += ../../lib/axi/rtl/priority_encoder.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fc_count.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
VERILOG_SOURCES += ../../lib/pcie/rtl/irq_rate_limit.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_desc_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_sink.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_source.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_ptile_if.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_ptile_if_rx.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_ptile_if_tx.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_ptile_cfg.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_ptile_fc_counter.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters
# Structural configuration
export PARAM_IF_COUNT := 2
export PARAM_PORTS_PER_IF := 1
export PARAM_SCHED_PER_IF := $(PARAM_PORTS_PER_IF)
export PARAM_PORT_MASK := 0
# Clock configuration
export PARAM_CLK_PERIOD_NS_NUM := 4
export PARAM_CLK_PERIOD_NS_DENOM := 1
# PTP configuration
export PARAM_PTP_CLK_PERIOD_NS_NUM := 4096
export PARAM_PTP_CLK_PERIOD_NS_DENOM := 825
export PARAM_PTP_CLOCK_PIPELINE := 0
export PARAM_PTP_CLOCK_CDC_PIPELINE := 0
export PARAM_PTP_USE_SAMPLE_CLOCK := 1
export PARAM_PTP_PORT_CDC_PIPELINE := 0
export PARAM_PTP_PEROUT_ENABLE := 1
export PARAM_PTP_PEROUT_COUNT := 1
# Queue manager configuration
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE := 32
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE := $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
export PARAM_EVENT_QUEUE_INDEX_WIDTH := 6
export PARAM_TX_QUEUE_INDEX_WIDTH := 13
export PARAM_RX_QUEUE_INDEX_WIDTH := 8
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_TX_QUEUE_INDEX_WIDTH)
export PARAM_RX_CPL_QUEUE_INDEX_WIDTH := $(PARAM_RX_QUEUE_INDEX_WIDTH)
export PARAM_EVENT_QUEUE_PIPELINE := 3
export PARAM_TX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_RX_QUEUE_PIPELINE := $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_TX_CPL_QUEUE_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE := $(PARAM_RX_QUEUE_PIPELINE)
# TX and RX engine configuration
export PARAM_TX_DESC_TABLE_SIZE := 32
export PARAM_RX_DESC_TABLE_SIZE := 32
export PARAM_RX_INDIR_TBL_ADDR_WIDTH := $(shell python -c "print(min($(PARAM_RX_QUEUE_INDEX_WIDTH), 8))")
# Scheduler configuration
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE := $(PARAM_TX_DESC_TABLE_SIZE)
export PARAM_TX_SCHEDULER_PIPELINE := $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_TDMA_INDEX_WIDTH := 6
# Interface configuration
export PARAM_PTP_TS_ENABLE := 1
export PARAM_TX_CPL_FIFO_DEPTH := 32
export PARAM_TX_CHECKSUM_ENABLE := 1
export PARAM_RX_RSS_ENABLE := 1
export PARAM_RX_HASH_ENABLE := 1
export PARAM_RX_CHECKSUM_ENABLE := 1
export PARAM_TX_FIFO_DEPTH := 32768
export PARAM_RX_FIFO_DEPTH := 131072
export PARAM_MAX_TX_SIZE := 9214
export PARAM_MAX_RX_SIZE := 9214
export PARAM_TX_RAM_SIZE := 131072
export PARAM_RX_RAM_SIZE := 131072
# Application block configuration
export PARAM_APP_ID := $(shell echo $$((0x00000000)) )
export PARAM_APP_ENABLE := 0
export PARAM_APP_CTRL_ENABLE := 1
export PARAM_APP_DMA_ENABLE := 1
export PARAM_APP_AXIS_DIRECT_ENABLE := 1
export PARAM_APP_AXIS_SYNC_ENABLE := 1
export PARAM_APP_AXIS_IF_ENABLE := 1
export PARAM_APP_STAT_ENABLE := 1
# DMA interface configuration
export PARAM_DMA_IMM_ENABLE := 0
export PARAM_DMA_IMM_WIDTH := 32
export PARAM_DMA_LEN_WIDTH := 16
export PARAM_DMA_TAG_WIDTH := 16
export PARAM_RAM_ADDR_WIDTH := $(shell python -c "print((max($(PARAM_TX_RAM_SIZE), $(PARAM_RX_RAM_SIZE))-1).bit_length())")
export PARAM_RAM_PIPELINE := 2
# PCIe interface configuration
export PARAM_SEG_COUNT := 2
export PARAM_SEG_DATA_WIDTH := 256
export PARAM_PF_COUNT := 1
export PARAM_VF_COUNT := 0
# Interrupt configuration
export PARAM_IRQ_INDEX_WIDTH := $(PARAM_EVENT_QUEUE_INDEX_WIDTH)
# AXI lite interface configuration (control)
export PARAM_AXIL_CTRL_DATA_WIDTH := 32
export PARAM_AXIL_CTRL_ADDR_WIDTH := 24
# AXI lite interface configuration (application control)
export PARAM_AXIL_APP_CTRL_DATA_WIDTH := $(PARAM_AXIL_CTRL_DATA_WIDTH)
export PARAM_AXIL_APP_CTRL_ADDR_WIDTH := 24
# Ethernet interface configuration
export PARAM_AXIS_ETH_TX_PIPELINE := 0
export PARAM_AXIS_ETH_TX_FIFO_PIPELINE := 2
export PARAM_AXIS_ETH_TX_TS_PIPELINE := 0
export PARAM_AXIS_ETH_RX_PIPELINE := 0
export PARAM_AXIS_ETH_RX_FIFO_PIPELINE := 2
# Statistics counter subsystem
export PARAM_STAT_ENABLE := 1
export PARAM_STAT_DMA_ENABLE := 1
export PARAM_STAT_PCIE_ENABLE := 1
export PARAM_STAT_INC_WIDTH := 24
export PARAM_STAT_ID_WIDTH := 12
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
VERILOG_SOURCES += iverilog_dump.v
COMPILE_ARGS += -s iverilog_dump
endif
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim
iverilog_dump.v:
echo 'module iverilog_dump();' > $@
echo 'initial begin' >> $@
echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@
echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@
echo 'end' >> $@
echo 'endmodule' >> $@
clean::
@rm -rf iverilog_dump.v
@rm -rf dump.fst $(TOPLEVEL).fst

1
fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/mqnic.py Symbolic link
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../../../../../common/tb/mqnic.py

809
fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.py Normal file
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"""
Copyright 2020-2022, The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
The views and conclusions contained in the software and documentation are those
of the authors and should not be interpreted as representing official policies,
either expressed or implied, of The Regents of the University of California.
"""
import logging
import os
import sys
import scapy.utils
from scapy.layers.l2 import Ether
from scapy.layers.inet import IP, UDP
import cocotb_test.simulator
import cocotb
from cocotb.log import SimLog
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, FallingEdge, Timer
from cocotbext.axi import AxiStreamBus
from cocotbext.eth import EthMac
from cocotbext.pcie.core import RootComplex
from cocotbext.pcie.intel.ptile import PTilePcieDevice, PTileRxBus, PTileTxBus
try:
import mqnic
except ImportError:
# attempt import from current directory
sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
try:
import mqnic
finally:
del sys.path[0]
class TB(object):
def __init__(self, dut, msix_count=32):
self.dut = dut
self.log = SimLog("cocotb.tb")
self.log.setLevel(logging.DEBUG)
# PCIe
self.rc = RootComplex()
self.rc.max_payload_size = 0x1 # 256 bytes
self.rc.max_read_request_size = 0x2 # 512 bytes
self.dev = PTilePcieDevice(
# configuration options
pcie_generation=3,
pcie_link_width=16,
pld_clk_frequency=250e6,
pf_count=1,
max_payload_size=512,
enable_extended_tag=True,
pf0_msi_enable=False,
pf0_msi_count=1,
pf1_msi_enable=False,
pf1_msi_count=1,
pf2_msi_enable=False,
pf2_msi_count=1,
pf3_msi_enable=False,
pf3_msi_count=1,
pf0_msix_enable=True,
pf0_msix_table_size=msix_count-1,
pf0_msix_table_bir=0,
pf0_msix_table_offset=0x00010000,
pf0_msix_pba_bir=0,
pf0_msix_pba_offset=0x00018000,
pf1_msix_enable=False,
pf1_msix_table_size=0,
pf1_msix_table_bir=0,
pf1_msix_table_offset=0x00000000,
pf1_msix_pba_bir=0,
pf1_msix_pba_offset=0x00000000,
pf2_msix_enable=False,
pf2_msix_table_size=0,
pf2_msix_table_bir=0,
pf2_msix_table_offset=0x00000000,
pf2_msix_pba_bir=0,
pf2_msix_pba_offset=0x00000000,
pf3_msix_enable=False,
pf3_msix_table_size=0,
pf3_msix_table_bir=0,
pf3_msix_table_offset=0x00000000,
pf3_msix_pba_bir=0,
pf3_msix_pba_offset=0x00000000,
# signals
# Clock and reset
reset_status=dut.rst_250mhz,
# reset_status_n=dut.reset_status_n,
coreclkout_hip=dut.clk_250mhz,
# refclk0=dut.refclk0,
# refclk1=dut.refclk1,
# pin_perst_n=dut.pin_perst_n,
# RX interface
rx_bus=PTileRxBus.from_prefix(dut, "rx_st"),
# rx_par_err=dut.rx_par_err,
# TX interface
tx_bus=PTileTxBus.from_prefix(dut, "tx_st"),
# tx_par_err=dut.tx_par_err,
# RX flow control
rx_buffer_limit=dut.rx_buffer_limit,
rx_buffer_limit_tdm_idx=dut.rx_buffer_limit_tdm_idx,
# TX flow control
tx_cdts_limit=dut.tx_cdts_limit,
tx_cdts_limit_tdm_idx=dut.tx_cdts_limit_tdm_idx,
# Power management and hard IP status interface
# link_up=dut.link_up,
# dl_up=dut.dl_up,
# surprise_down_err=dut.surprise_down_err,
# ltssm_state=dut.ltssm_state,
# pm_state=dut.pm_state,
# pm_dstate=dut.pm_dstate,
# apps_pm_xmt_pme=dut.apps_pm_xmt_pme,
# app_req_retry_en=dut.app_req_retry_en,
# Interrupt interface
# app_int=dut.app_int,
# msi_pnd_func=dut.msi_pnd_func,
# msi_pnd_byte=dut.msi_pnd_byte,
# msi_pnd_addr=dut.msi_pnd_addr,
# Error interface
# serr_out=dut.serr_out,
# hip_enter_err_mode=dut.hip_enter_err_mode,
# app_err_valid=dut.app_err_valid,
# app_err_hdr=dut.app_err_hdr,
# app_err_info=dut.app_err_info,
# app_err_func_num=dut.app_err_func_num,
# Completion timeout interface
# cpl_timeout=dut.cpl_timeout,
# cpl_timeout_avmm_clk=dut.cpl_timeout_avmm_clk,
# cpl_timeout_avmm_address=dut.cpl_timeout_avmm_address,
# cpl_timeout_avmm_read=dut.cpl_timeout_avmm_read,
# cpl_timeout_avmm_readdata=dut.cpl_timeout_avmm_readdata,
# cpl_timeout_avmm_readdatavalid=dut.cpl_timeout_avmm_readdatavalid,
# cpl_timeout_avmm_write=dut.cpl_timeout_avmm_write,
# cpl_timeout_avmm_writedata=dut.cpl_timeout_avmm_writedata,
# cpl_timeout_avmm_waitrequest=dut.cpl_timeout_avmm_waitrequest,
# Configuration output
tl_cfg_func=dut.tl_cfg_func,
tl_cfg_add=dut.tl_cfg_add,
tl_cfg_ctl=dut.tl_cfg_ctl,
# dl_timer_update=dut.dl_timer_update,
# Configuration intercept interface
# cii_req=dut.cii_req,
# cii_hdr_poisoned=dut.cii_hdr_poisoned,
# cii_hdr_first_be=dut.cii_hdr_first_be,
# cii_func_num=dut.cii_func_num,
# cii_wr_vf_active=dut.cii_wr_vf_active,
# cii_vf_num=dut.cii_vf_num,
# cii_wr=dut.cii_wr,
# cii_addr=dut.cii_addr,
# cii_dout=dut.cii_dout,
# cii_override_en=dut.cii_override_en,
# cii_override_din=dut.cii_override_din,
# cii_halt=dut.cii_halt,
# Hard IP reconfiguration interface
# hip_reconfig_clk=dut.hip_reconfig_clk,
# hip_reconfig_address=dut.hip_reconfig_address,
# hip_reconfig_read=dut.hip_reconfig_read,
# hip_reconfig_readdata=dut.hip_reconfig_readdata,
# hip_reconfig_readdatavalid=dut.hip_reconfig_readdatavalid,
# hip_reconfig_write=dut.hip_reconfig_write,
# hip_reconfig_writedata=dut.hip_reconfig_writedata,
# hip_reconfig_waitrequest=dut.hip_reconfig_waitrequest,
# Page request service
# prs_event_valid=dut.prs_event_valid,
# prs_event_func=dut.prs_event_func,
# prs_event=dut.prs_event,
# SR-IOV (VF error)
# vf_err_ur_posted_s0=dut.vf_err_ur_posted_s0,
# vf_err_ur_posted_s1=dut.vf_err_ur_posted_s1,
# vf_err_ur_posted_s2=dut.vf_err_ur_posted_s2,
# vf_err_ur_posted_s3=dut.vf_err_ur_posted_s3,
# vf_err_func_num_s0=dut.vf_err_func_num_s0,
# vf_err_func_num_s1=dut.vf_err_func_num_s1,
# vf_err_func_num_s2=dut.vf_err_func_num_s2,
# vf_err_func_num_s3=dut.vf_err_func_num_s3,
# vf_err_ca_postedreq_s0=dut.vf_err_ca_postedreq_s0,
# vf_err_ca_postedreq_s1=dut.vf_err_ca_postedreq_s1,
# vf_err_ca_postedreq_s2=dut.vf_err_ca_postedreq_s2,
# vf_err_ca_postedreq_s3=dut.vf_err_ca_postedreq_s3,
# vf_err_vf_num_s0=dut.vf_err_vf_num_s0,
# vf_err_vf_num_s1=dut.vf_err_vf_num_s1,
# vf_err_vf_num_s2=dut.vf_err_vf_num_s2,
# vf_err_vf_num_s3=dut.vf_err_vf_num_s3,
# vf_err_poisonedwrreq_s0=dut.vf_err_poisonedwrreq_s0,
# vf_err_poisonedwrreq_s1=dut.vf_err_poisonedwrreq_s1,
# vf_err_poisonedwrreq_s2=dut.vf_err_poisonedwrreq_s2,
# vf_err_poisonedwrreq_s3=dut.vf_err_poisonedwrreq_s3,
# vf_err_poisonedcompl_s0=dut.vf_err_poisonedcompl_s0,
# vf_err_poisonedcompl_s1=dut.vf_err_poisonedcompl_s1,
# vf_err_poisonedcompl_s2=dut.vf_err_poisonedcompl_s2,
# vf_err_poisonedcompl_s3=dut.vf_err_poisonedcompl_s3,
# user_vfnonfatalmsg_func_num=dut.user_vfnonfatalmsg_func_num,
# user_vfnonfatalmsg_vfnum=dut.user_vfnonfatalmsg_vfnum,
# user_sent_vfnonfatalmsg=dut.user_sent_vfnonfatalmsg,
# vf_err_overflow=dut.vf_err_overflow,
# FLR
# flr_rcvd_pf=dut.flr_rcvd_pf,
# flr_rcvd_vf=dut.flr_rcvd_vf,
# flr_rcvd_pf_num=dut.flr_rcvd_pf_num,
# flr_rcvd_vf_num=dut.flr_rcvd_vf_num,
# flr_completed_pf=dut.flr_completed_pf,
# flr_completed_vf=dut.flr_completed_vf,
# flr_completed_pf_num=dut.flr_completed_pf_num,
# flr_completed_vf_num=dut.flr_completed_vf_num,
# VirtIO
# virtio_pcicfg_vfaccess=dut.virtio_pcicfg_vfaccess,
# virtio_pcicfg_vfnum=dut.virtio_pcicfg_vfnum,
# virtio_pcicfg_pfnum=dut.virtio_pcicfg_pfnum,
# virtio_pcicfg_bar=dut.virtio_pcicfg_bar,
# virtio_pcicfg_length=dut.virtio_pcicfg_length,
# virtio_pcicfg_baroffset=dut.virtio_pcicfg_baroffset,
# virtio_pcicfg_cfgdata=dut.virtio_pcicfg_cfgdata,
# virtio_pcicfg_cfgwr=dut.virtio_pcicfg_cfgwr,
# virtio_pcicfg_cfgrd=dut.virtio_pcicfg_cfgrd,
# virtio_pcicfg_appvfnum=dut.virtio_pcicfg_appvfnum,
# virtio_pcicfg_apppfnum=dut.virtio_pcicfg_apppfnum,
# virtio_pcicfg_rdack=dut.virtio_pcicfg_rdack,
# virtio_pcicfg_rdbe=dut.virtio_pcicfg_rdbe,
# virtio_pcicfg_data=dut.virtio_pcicfg_data,
)
# self.dev.log.setLevel(logging.DEBUG)
self.rc.make_port().connect(self.dev)
self.driver = mqnic.Driver()
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
cocotb.start_soon(Clock(dut.ptp_clk, 4.964, units="ns").start())
dut.ptp_rst.setimmediatevalue(0)
cocotb.start_soon(Clock(dut.ptp_sample_clk, 10, units="ns").start())
# Ethernet
cocotb.start_soon(Clock(dut.qsfp1_mac_clk, 2.482, units="ns").start())
self.qsfp1_mac = EthMac(
tx_clk=dut.qsfp1_mac_clk,
tx_rst=dut.qsfp1_mac_rst,
tx_bus=AxiStreamBus.from_prefix(dut, "qsfp1_mac_tx_axis"),
tx_ptp_time=dut.qsfp1_mac_ptp_time,
tx_ptp_ts=dut.qsfp1_mac_tx_ptp_ts,
tx_ptp_ts_tag=dut.qsfp1_mac_tx_ptp_ts_tag,
tx_ptp_ts_valid=dut.qsfp1_mac_tx_ptp_ts_valid,
rx_clk=dut.qsfp1_mac_clk,
rx_rst=dut.qsfp1_mac_rst,
rx_bus=AxiStreamBus.from_prefix(dut, "qsfp1_mac_rx_axis"),
rx_ptp_time=dut.qsfp1_mac_ptp_time,
ifg=12, speed=100e9
)
cocotb.start_soon(Clock(dut.qsfp2_mac_clk, 2.482, units="ns").start())
self.qsfp2_mac = EthMac(
tx_clk=dut.qsfp2_mac_clk,
tx_rst=dut.qsfp2_mac_rst,
tx_bus=AxiStreamBus.from_prefix(dut, "qsfp2_mac_tx_axis"),
tx_ptp_time=dut.qsfp2_mac_ptp_time,
tx_ptp_ts=dut.qsfp2_mac_tx_ptp_ts,
tx_ptp_ts_tag=dut.qsfp2_mac_tx_ptp_ts_tag,
tx_ptp_ts_valid=dut.qsfp2_mac_tx_ptp_ts_valid,
rx_clk=dut.qsfp2_mac_clk,
rx_rst=dut.qsfp2_mac_rst,
rx_bus=AxiStreamBus.from_prefix(dut, "qsfp2_mac_rx_axis"),
rx_ptp_time=dut.qsfp2_mac_ptp_time,
ifg=12, speed=100e9
)
dut.qsfp1_mac_rx_status.setimmediatevalue(1)
dut.qsfp2_mac_rx_status.setimmediatevalue(1)
dut.user_pb.setimmediatevalue(0)
dut.i2c2_scl_i.setimmediatevalue(1)
dut.i2c2_sda_i.setimmediatevalue(1)
self.loopback_enable = False
cocotb.start_soon(self._run_loopback())
async def init(self):
self.dut.ptp_rst.setimmediatevalue(0)
self.dut.qsfp1_mac_rst.setimmediatevalue(0)
self.dut.qsfp2_mac_rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk_250mhz)
await RisingEdge(self.dut.clk_250mhz)
self.dut.ptp_rst.setimmediatevalue(1)
self.dut.qsfp1_mac_rst.setimmediatevalue(1)
self.dut.qsfp2_mac_rst.setimmediatevalue(1)
await FallingEdge(self.dut.rst_250mhz)
await Timer(100, 'ns')
await RisingEdge(self.dut.clk_250mhz)
await RisingEdge(self.dut.clk_250mhz)
self.dut.ptp_rst.setimmediatevalue(0)
self.dut.qsfp1_mac_rst.setimmediatevalue(0)
self.dut.qsfp2_mac_rst.setimmediatevalue(0)
await self.rc.enumerate()
async def _run_loopback(self):
while True:
await RisingEdge(self.dut.clk_250mhz)
if self.loopback_enable:
if not self.qsfp1_mac.tx.empty():
await self.qsfp1_mac.rx.send(await self.qsfp1_mac.tx.recv())
if not self.qsfp2_mac.tx.empty():
await self.qsfp2_mac.rx.send(await self.qsfp2_mac.tx.recv())
@cocotb.test()
async def run_test_nic(dut):
tb = TB(dut, msix_count=2**len(dut.core_inst.core_pcie_inst.irq_index))
await tb.init()
tb.log.info("Init driver")
await tb.driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
await tb.driver.interfaces[0].open()
# await tb.driver.interfaces[1].open()
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].rb.write_dword(mqnic.MQNIC_RB_SCHED_RR_REG_CTRL, 0x00000001)
for k in range(tb.driver.interfaces[0].tx_queue_count):
await tb.driver.interfaces[0].sched_blocks[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete
await tb.driver.hw_regs.read_dword(0)
tb.log.info("Init complete")
tb.log.info("Send and receive single packet")
data = bytearray([x % 256 for x in range(1024)])
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.qsfp1_mac.tx.recv()
tb.log.info("Packet: %s", pkt)
await tb.qsfp1_mac.rx.send(pkt)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
# await tb.driver.interfaces[1].start_xmit(data, 0)
# pkt = await tb.qsfp2_mac.tx.recv()
# tb.log.info("Packet: %s", pkt)
# await tb.qsfp2_mac.rx.send(pkt)
# pkt = await tb.driver.interfaces[1].recv()
# tb.log.info("Packet: %s", pkt)
# assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
tb.log.info("RX and TX checksum tests")
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=2)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
pkt = await tb.qsfp1_mac.tx.recv()
tb.log.info("Packet: %s", pkt)
await tb.qsfp1_mac.rx.send(pkt)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert Ether(pkt.data).build() == test_pkt.build()
tb.log.info("Queue mapping offset test")
data = bytearray([x % 256 for x in range(1024)])
tb.loopback_enable = True
for k in range(4):
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, k)
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert pkt.queue == k
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, 0, 0)
tb.log.info("Queue mapping RSS mask test")
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0x00000003)
for k in range(4):
await tb.driver.interfaces[0].set_rx_queue_map_indir_table(0, k, k)
tb.loopback_enable = True
queues = set()
for k in range(64):
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=k+0)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
for k in range(64):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
queues.add(pkt.queue)
assert len(queues) == 4
tb.loopback_enable = False
await tb.driver.interfaces[0].set_rx_queue_map_rss_mask(0, 0)
tb.log.info("Multiple small packets")
count = 64
pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
tb.loopback_enable = True
for p in pkts:
await tb.driver.interfaces[0].start_xmit(p, 0)
for k in range(count):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.data == pkts[k]
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
tb.loopback_enable = False
tb.log.info("Multiple large packets")
count = 64
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
tb.loopback_enable = True
for p in pkts:
await tb.driver.interfaces[0].start_xmit(p, 0)
for k in range(count):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.data == pkts[k]
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
tb.loopback_enable = False
tb.log.info("Jumbo frames")
count = 64
pkts = [bytearray([(x+k) % 256 for x in range(9014)]) for k in range(count)]
tb.loopback_enable = True
for p in pkts:
await tb.driver.interfaces[0].start_xmit(p, 0)
for k in range(count):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.data == pkts[k]
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
tb.loopback_enable = False
await RisingEdge(dut.clk_250mhz)
await RisingEdge(dut.clk_250mhz)
# cocotb-test
tests_dir = os.path.dirname(__file__)
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib'))
app_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'app'))
axi_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axi', 'rtl'))
axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl'))
eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl'))
pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl'))
def test_fpga_core(request):
dut = "fpga_core"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = dut
verilog_sources = [
os.path.join(rtl_dir, f"{dut}.v"),
os.path.join(rtl_dir, "common", "mqnic_core_pcie_ptile.v"),
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
os.path.join(rtl_dir, "common", "mqnic_core.v"),
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_port_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_port_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_l2_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_rx_queue_map.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
os.path.join(rtl_dir, "common", "mqnic_rb_clk_info.v"),
os.path.join(rtl_dir, "common", "mqnic_port_map_mac_axis.v"),
os.path.join(rtl_dir, "common", "cpl_write.v"),
os.path.join(rtl_dir, "common", "cpl_op_mux.v"),
os.path.join(rtl_dir, "common", "desc_fetch.v"),
os.path.join(rtl_dir, "common", "desc_op_mux.v"),
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
os.path.join(rtl_dir, "common", "rx_fifo.v"),
os.path.join(rtl_dir, "common", "tx_req_mux.v"),
os.path.join(rtl_dir, "common", "tx_engine.v"),
os.path.join(rtl_dir, "common", "rx_engine.v"),
os.path.join(rtl_dir, "common", "tx_checksum.v"),
os.path.join(rtl_dir, "common", "rx_hash.v"),
os.path.join(rtl_dir, "common", "rx_checksum.v"),
os.path.join(rtl_dir, "common", "stats_counter.v"),
os.path.join(rtl_dir, "common", "stats_collect.v"),
os.path.join(rtl_dir, "common", "stats_pcie_if.v"),
os.path.join(rtl_dir, "common", "stats_pcie_tlp.v"),
os.path.join(rtl_dir, "common", "stats_dma_if_pcie.v"),
os.path.join(rtl_dir, "common", "stats_dma_latency.v"),
os.path.join(rtl_dir, "common", "mqnic_tx_scheduler_block_rr.v"),
os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"),
os.path.join(rtl_dir, "common", "tdma_scheduler.v"),
os.path.join(rtl_dir, "common", "tdma_ber.v"),
os.path.join(rtl_dir, "common", "tdma_ber_ch.v"),
os.path.join(eth_rtl_dir, "lfsr.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
os.path.join(eth_rtl_dir, "ptp_perout.v"),
os.path.join(axi_rtl_dir, "axil_interconnect.v"),
os.path.join(axi_rtl_dir, "axil_crossbar.v"),
os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"),
os.path.join(axi_rtl_dir, "axil_crossbar_rd.v"),
os.path.join(axi_rtl_dir, "axil_crossbar_wr.v"),
os.path.join(axi_rtl_dir, "axil_reg_if.v"),
os.path.join(axi_rtl_dir, "axil_reg_if_rd.v"),
os.path.join(axi_rtl_dir, "axil_reg_if_wr.v"),
os.path.join(axi_rtl_dir, "axil_register_rd.v"),
os.path.join(axi_rtl_dir, "axil_register_wr.v"),
os.path.join(axi_rtl_dir, "arbiter.v"),
os.path.join(axi_rtl_dir, "priority_encoder.v"),
os.path.join(axis_rtl_dir, "axis_adapter.v"),
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_demux.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_fc_count.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_mux.v"),
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
os.path.join(pcie_rtl_dir, "irq_rate_limit.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"),
os.path.join(pcie_rtl_dir, "dma_if_desc_mux.v"),
os.path.join(pcie_rtl_dir, "dma_ram_demux_rd.v"),
os.path.join(pcie_rtl_dir, "dma_ram_demux_wr.v"),
os.path.join(pcie_rtl_dir, "dma_psdpram.v"),
os.path.join(pcie_rtl_dir, "dma_client_axis_sink.v"),
os.path.join(pcie_rtl_dir, "dma_client_axis_source.v"),
os.path.join(pcie_rtl_dir, "pcie_ptile_if.v"),
os.path.join(pcie_rtl_dir, "pcie_ptile_if_rx.v"),
os.path.join(pcie_rtl_dir, "pcie_ptile_if_tx.v"),
os.path.join(pcie_rtl_dir, "pcie_ptile_cfg.v"),
os.path.join(pcie_rtl_dir, "pcie_ptile_fc_counter.v"),
os.path.join(pcie_rtl_dir, "pulse_merge.v"),
]
parameters = {}
# Structural configuration
parameters['IF_COUNT'] = 2
parameters['PORTS_PER_IF'] = 1
parameters['SCHED_PER_IF'] = parameters['PORTS_PER_IF']
parameters['PORT_MASK'] = 0
# Clock configuration
parameters['CLK_PERIOD_NS_NUM'] = 4
parameters['CLK_PERIOD_NS_DENOM'] = 1
# PTP configuration
parameters['PTP_CLK_PERIOD_NS_NUM'] = 4096
parameters['PTP_CLK_PERIOD_NS_DENOM'] = 825
parameters['PTP_CLOCK_PIPELINE'] = 0
parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
parameters['PTP_USE_SAMPLE_CLOCK'] = 1
parameters['PTP_PORT_CDC_PIPELINE'] = 0
parameters['PTP_PEROUT_ENABLE'] = 1
parameters['PTP_PEROUT_COUNT'] = 1
# Queue manager configuration
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
parameters['EVENT_QUEUE_INDEX_WIDTH'] = 6
parameters['TX_QUEUE_INDEX_WIDTH'] = 13
parameters['RX_QUEUE_INDEX_WIDTH'] = 8
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH']
parameters['EVENT_QUEUE_PIPELINE'] = 3
parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
# TX and RX engine configuration
parameters['TX_DESC_TABLE_SIZE'] = 32
parameters['RX_DESC_TABLE_SIZE'] = 32
parameters['RX_INDIR_TBL_ADDR_WIDTH'] = min(parameters['RX_QUEUE_INDEX_WIDTH'], 8)
# Scheduler configuration
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['TDMA_INDEX_WIDTH'] = 6
# Interface configuration
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768
parameters['RX_FIFO_DEPTH'] = 131072
parameters['MAX_TX_SIZE'] = 9214
parameters['MAX_RX_SIZE'] = 9214
parameters['TX_RAM_SIZE'] = 131072
parameters['RX_RAM_SIZE'] = 131072
# Application block configuration
parameters['APP_ID'] = 0x00000000
parameters['APP_ENABLE'] = 0
parameters['APP_CTRL_ENABLE'] = 1
parameters['APP_DMA_ENABLE'] = 1
parameters['APP_AXIS_DIRECT_ENABLE'] = 1
parameters['APP_AXIS_SYNC_ENABLE'] = 1
parameters['APP_AXIS_IF_ENABLE'] = 1
parameters['APP_STAT_ENABLE'] = 1
# DMA interface configuration
parameters['DMA_IMM_ENABLE'] = 0
parameters['DMA_IMM_WIDTH'] = 32
parameters['DMA_LEN_WIDTH'] = 16
parameters['DMA_TAG_WIDTH'] = 16
parameters['RAM_ADDR_WIDTH'] = (max(parameters['TX_RAM_SIZE'], parameters['RX_RAM_SIZE'])-1).bit_length()
parameters['RAM_PIPELINE'] = 2
# PCIe interface configuration
parameters['SEG_COUNT'] = 2
parameters['SEG_DATA_WIDTH'] = 256
parameters['PF_COUNT'] = 1
parameters['VF_COUNT'] = 0
# Interrupt configuration
parameters['IRQ_INDEX_WIDTH'] = parameters['EVENT_QUEUE_INDEX_WIDTH']
# AXI lite interface configuration (control)
parameters['AXIL_CTRL_DATA_WIDTH'] = 32
parameters['AXIL_CTRL_ADDR_WIDTH'] = 24
# AXI lite interface configuration (application control)
parameters['AXIL_APP_CTRL_DATA_WIDTH'] = parameters['AXIL_CTRL_DATA_WIDTH']
parameters['AXIL_APP_CTRL_ADDR_WIDTH'] = 24
# Ethernet interface configuration
parameters['AXIS_ETH_TX_PIPELINE'] = 0
parameters['AXIS_ETH_TX_FIFO_PIPELINE'] = 2
parameters['AXIS_ETH_TX_TS_PIPELINE'] = 0
parameters['AXIS_ETH_RX_PIPELINE'] = 0
parameters['AXIS_ETH_RX_FIFO_PIPELINE'] = 2
# Statistics counter subsystem
parameters['STAT_ENABLE'] = 1
parameters['STAT_DMA_ENABLE'] = 1
parameters['STAT_PCIE_ENABLE'] = 1
parameters['STAT_INC_WIDTH'] = 24
parameters['STAT_ID_WIDTH'] = 12
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
python_search=[tests_dir],
verilog_sources=verilog_sources,
toplevel=toplevel,
module=module,
parameters=parameters,
sim_build=sim_build,
extra_env=extra_env,
)