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Separate out input mux in AXI frame joiner

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This commit is contained in:
Alex Forencich 2014-10-28 01:55:42 -07:00
parent 0f62d31fef
commit 588c2742e8
2 changed files with 59 additions and 45 deletions
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30
rtl/axis_frame_join.py
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@ -156,6 +156,9 @@ reg input_tlast;
reg input_tuser; reg input_tuser;
reg output_tuser_reg = 0, output_tuser_next; reg output_tuser_reg = 0, output_tuser_next;
{% for p in ports %}
reg input_{{p}}_axis_tready_reg = 0, input_{{p}}_axis_tready_next;
{%- endfor %}
// internal datapath // internal datapath
reg [7:0] output_axis_tdata_int; reg [7:0] output_axis_tdata_int;
@ -165,14 +168,25 @@ reg output_axis_tlast_int;
reg output_axis_tuser_int; reg output_axis_tuser_int;
wire output_axis_tready_int_early; wire output_axis_tready_int_early;
{% for p in ports %} {% for p in ports %}
reg input_{{p}}_axis_tready_reg = 0, input_{{p}}_axis_tready_next;
{%- endfor %}
{% for p in ports %}
assign input_{{p}}_axis_tready = input_{{p}}_axis_tready_reg; assign input_{{p}}_axis_tready = input_{{p}}_axis_tready_reg;
{%- endfor %} {%- endfor %}
assign busy = busy_reg; assign busy = busy_reg;
always @* begin
// input port mux
case (port_sel_reg)
{%- for p in ports %}
{{w}}'d{{p}}: begin
input_tdata = input_{{p}}_axis_tdata;
input_tvalid = input_{{p}}_axis_tvalid;
input_tlast = input_{{p}}_axis_tlast;
input_tuser = input_{{p}}_axis_tuser;
end
{%- endfor %}
endcase
end
always @* begin always @* begin
state_next = 2'bz; state_next = 2'bz;
@ -252,16 +266,10 @@ always @* begin
STATE_TRANSFER: begin STATE_TRANSFER: begin
// transfer input data // transfer input data
// grab correct input lines, set ready line correctly // set ready for current input
case (port_sel_reg) case (port_sel_reg)
{%- for p in ports %} {%- for p in ports %}
{{w}}'d{{p}}: begin {{w}}'d{{p}}: input_{{p}}_axis_tready_next = output_axis_tready_int_early;
input_tdata = input_{{p}}_axis_tdata;
input_tvalid = input_{{p}}_axis_tvalid;
input_tlast = input_{{p}}_axis_tlast;
input_tuser = input_{{p}}_axis_tuser;
input_{{p}}_axis_tready_next = output_axis_tready_int_early;
end
{%- endfor %} {%- endfor %}
endcase endcase

74
rtl/axis_frame_join_4.v
View File

@ -104,6 +104,11 @@ reg input_tuser;
reg output_tuser_reg = 0, output_tuser_next; reg output_tuser_reg = 0, output_tuser_next;
reg input_0_axis_tready_reg = 0, input_0_axis_tready_next;
reg input_1_axis_tready_reg = 0, input_1_axis_tready_next;
reg input_2_axis_tready_reg = 0, input_2_axis_tready_next;
reg input_3_axis_tready_reg = 0, input_3_axis_tready_next;
// internal datapath // internal datapath
reg [7:0] output_axis_tdata_int; reg [7:0] output_axis_tdata_int;
reg output_axis_tvalid_int; reg output_axis_tvalid_int;
@ -112,11 +117,6 @@ reg output_axis_tlast_int;
reg output_axis_tuser_int; reg output_axis_tuser_int;
wire output_axis_tready_int_early; wire output_axis_tready_int_early;
reg input_0_axis_tready_reg = 0, input_0_axis_tready_next;
reg input_1_axis_tready_reg = 0, input_1_axis_tready_next;
reg input_2_axis_tready_reg = 0, input_2_axis_tready_next;
reg input_3_axis_tready_reg = 0, input_3_axis_tready_next;
assign input_0_axis_tready = input_0_axis_tready_reg; assign input_0_axis_tready = input_0_axis_tready_reg;
assign input_1_axis_tready = input_1_axis_tready_reg; assign input_1_axis_tready = input_1_axis_tready_reg;
assign input_2_axis_tready = input_2_axis_tready_reg; assign input_2_axis_tready = input_2_axis_tready_reg;
@ -124,6 +124,36 @@ assign input_3_axis_tready = input_3_axis_tready_reg;
assign busy = busy_reg; assign busy = busy_reg;
always @* begin
// input port mux
case (port_sel_reg)
2'd0: begin
input_tdata = input_0_axis_tdata;
input_tvalid = input_0_axis_tvalid;
input_tlast = input_0_axis_tlast;
input_tuser = input_0_axis_tuser;
end
2'd1: begin
input_tdata = input_1_axis_tdata;
input_tvalid = input_1_axis_tvalid;
input_tlast = input_1_axis_tlast;
input_tuser = input_1_axis_tuser;
end
2'd2: begin
input_tdata = input_2_axis_tdata;
input_tvalid = input_2_axis_tvalid;
input_tlast = input_2_axis_tlast;
input_tuser = input_2_axis_tuser;
end
2'd3: begin
input_tdata = input_3_axis_tdata;
input_tvalid = input_3_axis_tvalid;
input_tlast = input_3_axis_tlast;
input_tuser = input_3_axis_tuser;
end
endcase
end
always @* begin always @* begin
state_next = 2'bz; state_next = 2'bz;
@ -205,36 +235,12 @@ always @* begin
STATE_TRANSFER: begin STATE_TRANSFER: begin
// transfer input data // transfer input data
// grab correct input lines, set ready line correctly // set ready for current input
case (port_sel_reg) case (port_sel_reg)
2'd0: begin 2'd0: input_0_axis_tready_next = output_axis_tready_int_early;
input_tdata = input_0_axis_tdata; 2'd1: input_1_axis_tready_next = output_axis_tready_int_early;
input_tvalid = input_0_axis_tvalid; 2'd2: input_2_axis_tready_next = output_axis_tready_int_early;
input_tlast = input_0_axis_tlast; 2'd3: input_3_axis_tready_next = output_axis_tready_int_early;
input_tuser = input_0_axis_tuser;
input_0_axis_tready_next = output_axis_tready_int_early;
end
2'd1: begin
input_tdata = input_1_axis_tdata;
input_tvalid = input_1_axis_tvalid;
input_tlast = input_1_axis_tlast;
input_tuser = input_1_axis_tuser;
input_1_axis_tready_next = output_axis_tready_int_early;
end
2'd2: begin
input_tdata = input_2_axis_tdata;
input_tvalid = input_2_axis_tvalid;
input_tlast = input_2_axis_tlast;
input_tuser = input_2_axis_tuser;
input_2_axis_tready_next = output_axis_tready_int_early;
end
2'd3: begin
input_tdata = input_3_axis_tdata;
input_tvalid = input_3_axis_tvalid;
input_tlast = input_3_axis_tlast;
input_tuser = input_3_axis_tuser;
input_3_axis_tready_next = output_axis_tready_int_early;
end
endcase endcase
if (input_tvalid & output_axis_tready_int) begin if (input_tvalid & output_axis_tready_int) begin