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Use CMAC wrapper in 100G mqnic design for VCU118

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-11-10 18:24:43 -08:00
parent db621ffa7d
commit 596db2d756
11 changed files with 521 additions and 783 deletions
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4
fpga/mqnic/VCU118/fpga_100g/fpga.xdc
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@ -159,7 +159,7 @@ set_property -dict {LOC AP21 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp1_i
set_property -dict {LOC AN21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp1_lpmode] set_property -dict {LOC AN21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp1_lpmode]
# 156.25 MHz MGT reference clock # 156.25 MHz MGT reference clock
#create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports qsfp1_mgt_refclk_0_p] create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports qsfp1_mgt_refclk_0_p]
set_false_path -to [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode}] set_false_path -to [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode}]
set_output_delay 0 [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode}] set_output_delay 0 [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode}]
@ -195,7 +195,7 @@ set_property -dict {LOC AT21 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp2_i
set_property -dict {LOC AT24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp2_lpmode] set_property -dict {LOC AT24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp2_lpmode]
# 156.25 MHz MGT reference clock # 156.25 MHz MGT reference clock
#create_clock -period 6.400 -name qsfp2_mgt_refclk_0 [get_ports qsfp2_mgt_refclk_0_p] create_clock -period 6.400 -name qsfp2_mgt_refclk_0 [get_ports qsfp2_mgt_refclk_0_p]
set_false_path -to [get_ports {qsfp2_modsell qsfp2_resetl qsfp2_lpmode}] set_false_path -to [get_ports {qsfp2_modsell qsfp2_resetl qsfp2_lpmode}]
set_output_delay 0 [get_ports {qsfp2_modsell qsfp2_resetl qsfp2_lpmode}] set_output_delay 0 [get_ports {qsfp2_modsell qsfp2_resetl qsfp2_lpmode}]

10
fpga/mqnic/VCU118/fpga_100g/fpga/Makefile
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@ -43,6 +43,9 @@ SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v SYN_FILES += rtl/common/tx_checksum.v
SYN_FILES += rtl/common/rx_hash.v SYN_FILES += rtl/common/rx_hash.v
SYN_FILES += rtl/common/rx_checksum.v SYN_FILES += rtl/common/rx_checksum.v
SYN_FILES += rtl/common/rb_drp.v
SYN_FILES += rtl/common/cmac_gty_wrapper.v
SYN_FILES += rtl/common/cmac_gty_ch_wrapper.v
SYN_FILES += rtl/common/stats_counter.v SYN_FILES += rtl/common/stats_counter.v
SYN_FILES += rtl/common/stats_collect.v SYN_FILES += rtl/common/stats_collect.v
SYN_FILES += rtl/common/stats_pcie_if.v SYN_FILES += rtl/common/stats_pcie_if.v
@ -116,11 +119,14 @@ XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/cmac_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/cmac_gty_ch_wrapper.tcl
# IP # IP
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
IP_TCL_FILES += ip/cmac_usplus_0.tcl IP_TCL_FILES += ip/cmac_usplus.tcl
IP_TCL_FILES += ip/cmac_usplus_1.tcl IP_TCL_FILES += ip/cmac_gty.tcl
#IP_TCL_FILES += ip/ddr4_0.tcl #IP_TCL_FILES += ip/ddr4_0.tcl
# Configuration # Configuration

132
fpga/mqnic/VCU118/fpga_100g/ip/cmac_gty.tcl Normal file
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@ -0,0 +1,132 @@
# Copyright 2022, The Regents of the University of California.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
# OF SUCH DAMAGE.
#
# The views and conclusions contained in the software and documentation are those
# of the authors and should not be interpreted as representing official policies,
# either expressed or implied, of The Regents of the University of California.
set base_name {cmac_gty}
set preset {GTY-CAUI_4}
set freerun_freq {125}
set line_rate {25.78125}
set sec_line_rate {0}
set refclk_freq {156.25}
set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
set user_data_width {80}
set int_data_width $user_data_width
set rx_eq_mode {LPM}
set extra_ports [list]
set extra_pll_ports [list]
# DRP connections
lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out
lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out
# PLL reset and power down
lappend extra_pll_ports qpll0reset_in qpll1reset_in
lappend extra_pll_ports qpll0pd_in qpll1pd_in
# PLL clocking
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out
# channel power down
lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
# channel clock selection
lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in
# channel polarity
lappend extra_ports txpolarity_in rxpolarity_in
# channel TX driver
lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in
# channel CDR
lappend extra_ports rxcdrlock_out rxcdrhold_in
# channel EQ
lappend extra_ports rxlpmen_in
# channel digital monitor
lappend extra_ports dmonitorout_out
# channel PRBS
lappend extra_ports txprbsforceerr_in txprbssel_in rxprbscntreset_in rxprbssel_in rxprbserr_out rxprbslocked_out
# channel eye scan
lappend extra_ports eyescandataerror_out
# channel loopback
lappend extra_ports loopback_in
set config [dict create]
dict set config TX_LINE_RATE $line_rate
dict set config TX_REFCLK_FREQUENCY $refclk_freq
dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn
dict set config TX_USER_DATA_WIDTH $user_data_width
dict set config TX_INT_DATA_WIDTH $int_data_width
dict set config RX_LINE_RATE $line_rate
dict set config RX_REFCLK_FREQUENCY $refclk_freq
dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn
dict set config RX_USER_DATA_WIDTH $user_data_width
dict set config RX_INT_DATA_WIDTH $int_data_width
dict set config RX_EQ_MODE $rx_eq_mode
if {$sec_line_rate != 0} {
dict set config SECONDARY_QPLL_ENABLE true
dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq
} else {
dict set config SECONDARY_QPLL_ENABLE false
}
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {CORE}
dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
dict set config LOCATE_TX_USER_CLOCKING {EXAMPLE_DESIGN}
dict set config LOCATE_RX_USER_CLOCKING {EXAMPLE_DESIGN}
dict set config LOCATE_USER_DATA_WIDTH_SIZING {EXAMPLE_DESIGN}
dict set config FREERUN_FREQUENCY $freerun_freq
dict set config DISABLE_LOC_XDC {1}
proc create_gtwizard_ip {name preset config} {
create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name
set ip [get_ips $name]
set_property CONFIG.preset $preset $ip
set config_list {}
dict for {name value} $config {
lappend config_list "CONFIG.${name}" $value
}
set_property -dict $config_list $ip
# enable only one site
set_property CONFIG.CHANNEL_ENABLE [lindex [get_property CONFIG.CHANNEL_ENABLE $ip] 0] $ip
}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
create_gtwizard_ip "${base_name}_full" $preset $config
# variant with channel only
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_channel" $preset $config

19
fpga/mqnic/VCU118/fpga_100g/ip/cmac_usplus.tcl Normal file
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@ -0,0 +1,19 @@
create_ip -name cmac_usplus -vendor xilinx.com -library ip -module_name cmac_usplus
set_property -dict [list \
CONFIG.CMAC_CAUI4_MODE {1} \
CONFIG.NUM_LANES {4x25} \
CONFIG.USER_INTERFACE {AXIS} \
CONFIG.GT_DRP_CLK {125} \
CONFIG.GT_LOCATION {0} \
CONFIG.TX_FLOW_CONTROL {0} \
CONFIG.RX_FLOW_CONTROL {0} \
CONFIG.INCLUDE_RS_FEC {1} \
CONFIG.ENABLE_TIME_STAMPING {1}
] [get_ips cmac_usplus]
# disable LOC constraint
set_property generate_synth_checkpoint false [get_files [get_property IP_FILE [get_ips cmac_usplus]]]
generate_target synthesis [get_files [get_property IP_FILE [get_ips cmac_usplus]]]
set_property is_enabled false [get_files -of_objects [get_files [get_property IP_FILE [get_ips cmac_usplus]]] cmac_usplus.xdc]

21
fpga/mqnic/VCU118/fpga_100g/ip/cmac_usplus_0.tcl
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@ -1,21 +0,0 @@
create_ip -name cmac_usplus -vendor xilinx.com -library ip -module_name cmac_usplus_0
set_property -dict [list \
CONFIG.CMAC_CAUI4_MODE {1} \
CONFIG.NUM_LANES {4x25} \
CONFIG.GT_REF_CLK_FREQ {156.25} \
CONFIG.USER_INTERFACE {AXIS} \
CONFIG.GT_DRP_CLK {125} \
CONFIG.TX_FLOW_CONTROL {0} \
CONFIG.RX_FLOW_CONTROL {0} \
CONFIG.INCLUDE_RS_FEC {1} \
CONFIG.CMAC_CORE_SELECT {CMACE4_X0Y7} \
CONFIG.GT_GROUP_SELECT {X1Y48~X1Y51} \
CONFIG.LANE1_GT_LOC {X1Y48} \
CONFIG.LANE2_GT_LOC {X1Y49} \
CONFIG.LANE3_GT_LOC {X1Y50} \
CONFIG.LANE4_GT_LOC {X1Y51} \
CONFIG.ENABLE_PIPELINE_REG {1} \
CONFIG.ENABLE_TIME_STAMPING {1}
] [get_ips cmac_usplus_0]

21
fpga/mqnic/VCU118/fpga_100g/ip/cmac_usplus_1.tcl
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@ -1,21 +0,0 @@
create_ip -name cmac_usplus -vendor xilinx.com -library ip -module_name cmac_usplus_1
set_property -dict [list \
CONFIG.CMAC_CAUI4_MODE {1} \
CONFIG.NUM_LANES {4x25} \
CONFIG.GT_REF_CLK_FREQ {156.25} \
CONFIG.USER_INTERFACE {AXIS} \
CONFIG.GT_DRP_CLK {125} \
CONFIG.TX_FLOW_CONTROL {0} \
CONFIG.RX_FLOW_CONTROL {0} \
CONFIG.INCLUDE_RS_FEC {1} \
CONFIG.CMAC_CORE_SELECT {CMACE4_X0Y8} \
CONFIG.GT_GROUP_SELECT {X1Y52~X1Y55} \
CONFIG.LANE1_GT_LOC {X1Y52} \
CONFIG.LANE2_GT_LOC {X1Y53} \
CONFIG.LANE3_GT_LOC {X1Y54} \
CONFIG.LANE4_GT_LOC {X1Y55} \
CONFIG.ENABLE_PIPELINE_REG {1} \
CONFIG.ENABLE_TIME_STAMPING {1}
] [get_ips cmac_usplus_1]

6
fpga/mqnic/VCU118/fpga_100g/placement.xdc
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@ -26,9 +26,11 @@ add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_
resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y5:CLOCKREGION_X5Y8} resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y5:CLOCKREGION_X5Y8}
create_pblock pblock_eth create_pblock pblock_eth
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp0_cmac_pad_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp1_cmac_pad_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"] add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"] add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"]
add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"] add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"]
resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X0Y10:CLOCKREGION_X0Y14} resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X0Y10:CLOCKREGION_X0Y14}
# CMACs
set_property LOC CMACE4_X0Y7 [get_cells -hierarchical -filter {NAME =~ qsfp1_cmac_inst/cmac_inst/inst/i_cmac_usplus_top/* && REF_NAME==CMACE4}]
set_property LOC CMACE4_X0Y8 [get_cells -hierarchical -filter {NAME =~ qsfp2_cmac_inst/cmac_inst/inst/i_cmac_usplus_top/* && REF_NAME==CMACE4}]

949
fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v
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129
fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v
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@ -338,6 +338,15 @@ module fpga_core #
input wire qsfp1_rx_status, input wire qsfp1_rx_status,
input wire qsfp1_drp_clk,
input wire qsfp1_drp_rst,
output wire [23:0] qsfp1_drp_addr,
output wire [15:0] qsfp1_drp_di,
output wire qsfp1_drp_en,
output wire qsfp1_drp_we,
input wire [15:0] qsfp1_drp_do,
input wire qsfp1_drp_rdy,
output wire qsfp1_modsell, output wire qsfp1_modsell,
output wire qsfp1_resetl, output wire qsfp1_resetl,
input wire qsfp1_modprsl, input wire qsfp1_modprsl,
@ -372,6 +381,15 @@ module fpga_core #
input wire qsfp2_rx_ptp_rst, input wire qsfp2_rx_ptp_rst,
output wire [79:0] qsfp2_rx_ptp_time, output wire [79:0] qsfp2_rx_ptp_time,
input wire qsfp2_drp_clk,
input wire qsfp2_drp_rst,
output wire [23:0] qsfp2_drp_addr,
output wire [15:0] qsfp2_drp_di,
output wire qsfp2_drp_en,
output wire qsfp2_drp_we,
input wire [15:0] qsfp2_drp_do,
input wire qsfp2_drp_rdy,
input wire qsfp2_rx_status, input wire qsfp2_rx_status,
output wire qsfp2_modsell, output wire qsfp2_modsell,
@ -452,6 +470,9 @@ parameter AXIL_CSR_ADDR_WIDTH = AXIL_IF_CTRL_ADDR_WIDTH-5-$clog2((PORTS_PER_IF+3
localparam RB_BASE_ADDR = 16'h1000; localparam RB_BASE_ADDR = 16'h1000;
localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}}; localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}};
localparam RB_DRP_QSFP1_BASE = RB_BASE_ADDR + 16'h40;
localparam RB_DRP_QSFP2_BASE = RB_DRP_QSFP1_BASE + 16'h20;
initial begin initial begin
if (PORT_COUNT > 2) begin if (PORT_COUNT > 2) begin
$error("Error: Max port count exceeded (instance %m)"); $error("Error: Max port count exceeded (instance %m)");
@ -485,6 +506,18 @@ wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data;
wire ctrl_reg_rd_wait; wire ctrl_reg_rd_wait;
wire ctrl_reg_rd_ack; wire ctrl_reg_rd_ack;
wire qsfp1_drp_reg_wr_wait;
wire qsfp1_drp_reg_wr_ack;
wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp1_drp_reg_rd_data;
wire qsfp1_drp_reg_rd_wait;
wire qsfp1_drp_reg_rd_ack;
wire qsfp2_drp_reg_wr_wait;
wire qsfp2_drp_reg_wr_ack;
wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp2_drp_reg_rd_data;
wire qsfp2_drp_reg_rd_wait;
wire qsfp2_drp_reg_rd_ack;
reg ctrl_reg_wr_ack_reg = 1'b0; reg ctrl_reg_wr_ack_reg = 1'b0;
reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}}; reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}};
reg ctrl_reg_rd_ack_reg = 1'b0; reg ctrl_reg_rd_ack_reg = 1'b0;
@ -508,11 +541,11 @@ reg qspi_1_cs_reg = 1'b1;
reg [3:0] qspi_1_dq_o_reg = 4'd0; reg [3:0] qspi_1_dq_o_reg = 4'd0;
reg [3:0] qspi_1_dq_oe_reg = 4'd0; reg [3:0] qspi_1_dq_oe_reg = 4'd0;
assign ctrl_reg_wr_wait = 1'b0; assign ctrl_reg_wr_wait = qsfp1_drp_reg_wr_wait | qsfp2_drp_reg_wr_wait;
assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg; assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg | qsfp1_drp_reg_wr_ack | qsfp2_drp_reg_wr_ack;
assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg; assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg | qsfp1_drp_reg_rd_data | qsfp2_drp_reg_rd_data;
assign ctrl_reg_rd_wait = 1'b0; assign ctrl_reg_rd_wait = qsfp1_drp_reg_rd_wait | qsfp2_drp_reg_rd_wait;
assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg; assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg | qsfp1_drp_reg_rd_ack | qsfp2_drp_reg_rd_ack;
assign qsfp1_modsell = 1'b0; assign qsfp1_modsell = 1'b0;
assign qsfp2_modsell = 1'b0; assign qsfp2_modsell = 1'b0;
@ -642,7 +675,7 @@ always @(posedge clk_250mhz) begin
// QSPI flash // QSPI flash
RBB+8'h20: ctrl_reg_rd_data_reg <= 32'h0000C120; // SPI flash ctrl: Type RBB+8'h20: ctrl_reg_rd_data_reg <= 32'h0000C120; // SPI flash ctrl: Type
RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000200; // SPI flash ctrl: Version RBB+8'h24: ctrl_reg_rd_data_reg <= 32'h00000200; // SPI flash ctrl: Version
RBB+8'h28: ctrl_reg_rd_data_reg <= 0; // SPI flash ctrl: Next header RBB+8'h28: ctrl_reg_rd_data_reg <= RB_DRP_QSFP1_BASE; // SPI flash ctrl: Next header
RBB+8'h2C: begin RBB+8'h2C: begin
// SPI flash ctrl: format // SPI flash ctrl: format
ctrl_reg_rd_data_reg[3:0] <= 2; // configuration (two segments) ctrl_reg_rd_data_reg[3:0] <= 2; // configuration (two segments)
@ -693,6 +726,90 @@ always @(posedge clk_250mhz) begin
end end
end end
rb_drp #(
.DRP_ADDR_WIDTH(24),
.DRP_DATA_WIDTH(16),
.DRP_INFO({8'h09, 8'h03, 8'd2, 8'd4}),
.REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH),
.REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
.REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH),
.RB_BASE_ADDR(RB_DRP_QSFP1_BASE),
.RB_NEXT_PTR(RB_DRP_QSFP2_BASE)
)
qsfp1_rb_drp_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* Register interface
*/
.reg_wr_addr(ctrl_reg_wr_addr),
.reg_wr_data(ctrl_reg_wr_data),
.reg_wr_strb(ctrl_reg_wr_strb),
.reg_wr_en(ctrl_reg_wr_en),
.reg_wr_wait(qsfp1_drp_reg_wr_wait),
.reg_wr_ack(qsfp1_drp_reg_wr_ack),
.reg_rd_addr(ctrl_reg_rd_addr),
.reg_rd_en(ctrl_reg_rd_en),
.reg_rd_data(qsfp1_drp_reg_rd_data),
.reg_rd_wait(qsfp1_drp_reg_rd_wait),
.reg_rd_ack(qsfp1_drp_reg_rd_ack),
/*
* DRP
*/
.drp_clk(qsfp1_drp_clk),
.drp_rst(qsfp1_drp_rst),
.drp_addr(qsfp1_drp_addr),
.drp_di(qsfp1_drp_di),
.drp_en(qsfp1_drp_en),
.drp_we(qsfp1_drp_we),
.drp_do(qsfp1_drp_do),
.drp_rdy(qsfp1_drp_rdy)
);
rb_drp #(
.DRP_ADDR_WIDTH(24),
.DRP_DATA_WIDTH(16),
.DRP_INFO({8'h09, 8'h03, 8'd2, 8'd4}),
.REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH),
.REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
.REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH),
.RB_BASE_ADDR(RB_DRP_QSFP2_BASE),
.RB_NEXT_PTR(0)
)
qsfp2_rb_drp_inst (
.clk(clk_250mhz),
.rst(rst_250mhz),
/*
* Register interface
*/
.reg_wr_addr(ctrl_reg_wr_addr),
.reg_wr_data(ctrl_reg_wr_data),
.reg_wr_strb(ctrl_reg_wr_strb),
.reg_wr_en(ctrl_reg_wr_en),
.reg_wr_wait(qsfp2_drp_reg_wr_wait),
.reg_wr_ack(qsfp2_drp_reg_wr_ack),
.reg_rd_addr(ctrl_reg_rd_addr),
.reg_rd_en(ctrl_reg_rd_en),
.reg_rd_data(qsfp2_drp_reg_rd_data),
.reg_rd_wait(qsfp2_drp_reg_rd_wait),
.reg_rd_ack(qsfp2_drp_reg_rd_ack),
/*
* DRP
*/
.drp_clk(qsfp2_drp_clk),
.drp_rst(qsfp2_drp_rst),
.drp_addr(qsfp2_drp_addr),
.drp_di(qsfp2_drp_di),
.drp_en(qsfp2_drp_en),
.drp_we(qsfp2_drp_we),
.drp_do(qsfp2_drp_do),
.drp_rdy(qsfp2_drp_rdy)
);
assign pmod0[0] = ptp_perout_pulse; assign pmod0[0] = ptp_perout_pulse;
assign pmod0[7:1] = 0; assign pmod0[7:1] = 0;
assign pmod1[0] = ptp_perout_pulse; assign pmod1[0] = ptp_perout_pulse;

1
fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile
View File

@ -73,6 +73,7 @@ VERILOG_SOURCES += ../../rtl/common/rx_engine.v
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
VERILOG_SOURCES += ../../rtl/common/rx_hash.v VERILOG_SOURCES += ../../rtl/common/rx_hash.v
VERILOG_SOURCES += ../../rtl/common/rx_checksum.v VERILOG_SOURCES += ../../rtl/common/rx_checksum.v
VERILOG_SOURCES += ../../rtl/common/rb_drp.v
VERILOG_SOURCES += ../../rtl/common/stats_counter.v VERILOG_SOURCES += ../../rtl/common/stats_counter.v
VERILOG_SOURCES += ../../rtl/common/stats_collect.v VERILOG_SOURCES += ../../rtl/common/stats_collect.v
VERILOG_SOURCES += ../../rtl/common/stats_pcie_if.v VERILOG_SOURCES += ../../rtl/common/stats_pcie_if.v

12
fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -343,8 +343,19 @@ class TB(object):
) )
dut.qsfp1_rx_status.setimmediatevalue(1) dut.qsfp1_rx_status.setimmediatevalue(1)
cocotb.start_soon(Clock(dut.qsfp1_drp_clk, 8, units="ns").start())
dut.qsfp1_drp_rst.setimmediatevalue(0)
dut.qsfp1_drp_do.setimmediatevalue(0)
dut.qsfp1_drp_rdy.setimmediatevalue(0)
dut.qsfp2_rx_status.setimmediatevalue(1) dut.qsfp2_rx_status.setimmediatevalue(1)
cocotb.start_soon(Clock(dut.qsfp2_drp_clk, 8, units="ns").start())
dut.qsfp2_drp_rst.setimmediatevalue(0)
dut.qsfp2_drp_do.setimmediatevalue(0)
dut.qsfp2_drp_rdy.setimmediatevalue(0)
dut.btnu.setimmediatevalue(0) dut.btnu.setimmediatevalue(0)
dut.btnl.setimmediatevalue(0) dut.btnl.setimmediatevalue(0)
dut.btnd.setimmediatevalue(0) dut.btnd.setimmediatevalue(0)
@ -655,6 +666,7 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "tx_checksum.v"), os.path.join(rtl_dir, "common", "tx_checksum.v"),
os.path.join(rtl_dir, "common", "rx_hash.v"), os.path.join(rtl_dir, "common", "rx_hash.v"),
os.path.join(rtl_dir, "common", "rx_checksum.v"), os.path.join(rtl_dir, "common", "rx_checksum.v"),
os.path.join(rtl_dir, "common", "rb_drp.v"),
os.path.join(rtl_dir, "common", "stats_counter.v"), os.path.join(rtl_dir, "common", "stats_counter.v"),
os.path.join(rtl_dir, "common", "stats_collect.v"), os.path.join(rtl_dir, "common", "stats_collect.v"),
os.path.join(rtl_dir, "common", "stats_pcie_if.v"), os.path.join(rtl_dir, "common", "stats_pcie_if.v"),