diff --git a/fpga/lib/pcie/rtl/dma_if_pcie_us.v b/fpga/lib/pcie/rtl/dma_if_pcie_us.v index c8eb7cab3..d91cf2be9 100644 --- a/fpga/lib/pcie/rtl/dma_if_pcie_us.v +++ b/fpga/lib/pcie/rtl/dma_if_pcie_us.v @@ -71,10 +71,14 @@ module dma_if_pcie_us # parameter READ_OP_TABLE_SIZE = PCIE_TAG_COUNT, // In-flight transmit limit (read) parameter READ_TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1), + // Transmit flow control (read) + parameter READ_TX_FC_ENABLE = 0, // Operation table size (write) parameter WRITE_OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1), // In-flight transmit limit (write) - parameter WRITE_TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1) + parameter WRITE_TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1), + // Transmit flow control (write) + parameter WRITE_TX_FC_ENABLE = 0 ) ( input wire clk, @@ -108,6 +112,13 @@ module dma_if_pcie_us # input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1, input wire s_axis_rq_seq_num_valid_1, + /* + * Transmit flow control + */ + input wire [7:0] pcie_tx_fc_nph_av, + input wire [7:0] pcie_tx_fc_ph_av, + input wire [11:0] pcie_tx_fc_pd_av, + /* * AXI read descriptor input */ @@ -209,7 +220,8 @@ dma_if_pcie_us_rd #( .LEN_WIDTH(LEN_WIDTH), .TAG_WIDTH(TAG_WIDTH), .OP_TABLE_SIZE(READ_OP_TABLE_SIZE), - .TX_LIMIT(READ_TX_LIMIT) + .TX_LIMIT(READ_TX_LIMIT), + .TX_FC_ENABLE(READ_TX_FC_ENABLE) ) dma_if_pcie_us_rd_inst ( .clk(clk), @@ -243,6 +255,11 @@ dma_if_pcie_us_rd_inst ( .s_axis_rq_seq_num_1(axis_rq_seq_num_read_1), .s_axis_rq_seq_num_valid_1(axis_rq_seq_num_valid_read_1), + /* + * Transmit flow control + */ + .pcie_tx_fc_nph_av(pcie_tx_fc_nph_av), + /* * AXI read descriptor input */ @@ -302,7 +319,8 @@ dma_if_pcie_us_wr #( .LEN_WIDTH(LEN_WIDTH), .TAG_WIDTH(TAG_WIDTH), .OP_TABLE_SIZE(WRITE_OP_TABLE_SIZE), - .TX_LIMIT(WRITE_TX_LIMIT) + .TX_LIMIT(WRITE_TX_LIMIT), + .TX_FC_ENABLE(WRITE_TX_FC_ENABLE) ) dma_if_pcie_us_wr_inst ( .clk(clk), @@ -344,6 +362,12 @@ dma_if_pcie_us_wr_inst ( .m_axis_rq_seq_num_1(axis_rq_seq_num_read_1), .m_axis_rq_seq_num_valid_1(axis_rq_seq_num_valid_read_1), + /* + * Transmit flow control + */ + .pcie_tx_fc_ph_av(pcie_tx_fc_ph_av), + .pcie_tx_fc_pd_av(pcie_tx_fc_pd_av), + /* * AXI write descriptor input */ diff --git a/fpga/lib/pcie/rtl/dma_if_pcie_us_rd.v b/fpga/lib/pcie/rtl/dma_if_pcie_us_rd.v index 93031cf2a..1d4795a63 100644 --- a/fpga/lib/pcie/rtl/dma_if_pcie_us_rd.v +++ b/fpga/lib/pcie/rtl/dma_if_pcie_us_rd.v @@ -70,7 +70,9 @@ module dma_if_pcie_us_rd # // Operation table size parameter OP_TABLE_SIZE = PCIE_TAG_COUNT, // In-flight transmit limit - parameter TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1) + parameter TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1), + // Transmit flow control + parameter TX_FC_ENABLE = 0 ) ( input wire clk, @@ -104,6 +106,11 @@ module dma_if_pcie_us_rd # input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1, input wire s_axis_rq_seq_num_valid_1, + /* + * Transmit flow control + */ + input wire [7:0] pcie_tx_fc_nph_av, + /* * AXI read descriptor input */ @@ -346,6 +353,8 @@ reg tag_table_we_tlp_reg = 1'b0, tag_table_we_tlp_next; reg [10:0] max_read_request_size_dw_reg = 11'd0; +reg have_credit_reg = 1'b0; + reg [RQ_SEQ_NUM_WIDTH-1:0] active_tx_count_reg = {RQ_SEQ_NUM_WIDTH{1'b0}}; reg active_tx_count_av_reg = 1'b1; reg inc_active_tx; @@ -590,7 +599,7 @@ always @* begin end end REQ_STATE_START: begin - if (m_axis_rq_tready_int_reg && !tlp_cmd_valid_reg && new_tag_valid && (!RQ_SEQ_NUM_ENABLE || active_tx_count_av_reg)) begin + if (m_axis_rq_tready_int_reg && !tlp_cmd_valid_reg && new_tag_valid && (!TX_FC_ENABLE || have_credit_reg) && (!RQ_SEQ_NUM_ENABLE || active_tx_count_av_reg)) begin if (req_op_count_reg <= {max_read_request_size_dw_reg, 2'b00}-req_pcie_addr_reg[1:0]) begin // packet smaller than max read request size if (req_pcie_addr_reg[12] != req_pcie_addr_plus_op_count[12]) begin @@ -1215,6 +1224,8 @@ always @(posedge clk) begin max_read_request_size_dw_reg <= 11'd32 << (max_read_request_size > 5 ? 5 : max_read_request_size); + have_credit_reg <= pcie_tx_fc_nph_av > 4; + if (active_tx_count_reg < TX_LIMIT && inc_active_tx && !s_axis_rq_seq_num_valid_0 && !s_axis_rq_seq_num_valid_1) begin // inc by 1 active_tx_count_reg <= active_tx_count_reg + 1; diff --git a/fpga/lib/pcie/rtl/dma_if_pcie_us_wr.v b/fpga/lib/pcie/rtl/dma_if_pcie_us_wr.v index 3a1ec7772..9e0a2f34a 100644 --- a/fpga/lib/pcie/rtl/dma_if_pcie_us_wr.v +++ b/fpga/lib/pcie/rtl/dma_if_pcie_us_wr.v @@ -62,7 +62,9 @@ module dma_if_pcie_us_wr # // Operation table size parameter OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1), // In-flight transmit limit - parameter TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1) + parameter TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1), + // Transmit flow control + parameter TX_FC_ENABLE = 0 ) ( input wire clk, @@ -104,6 +106,12 @@ module dma_if_pcie_us_wr # output wire [RQ_SEQ_NUM_WIDTH-1:0] m_axis_rq_seq_num_1, output wire m_axis_rq_seq_num_valid_1, + /* + * Transmit flow control + */ + input wire [7:0] pcie_tx_fc_ph_av, + input wire [11:0] pcie_tx_fc_pd_av, + /* * AXI write descriptor input */ @@ -313,6 +321,8 @@ wire mask_fifo_full = mask_fifo_wr_ptr_reg == (mask_fifo_rd_ptr_reg ^ (1 << MASK reg [10:0] max_payload_size_dw_reg = 11'd0; +reg have_credit_reg = 1'b0; + reg [RQ_SEQ_NUM_WIDTH-1:0] active_tx_count_reg = {RQ_SEQ_NUM_WIDTH{1'b0}}; reg active_tx_count_av_reg = 1'b1; reg inc_active_tx; @@ -756,7 +766,7 @@ always @* begin end else begin tlp_state_next = TLP_STATE_PASSTHROUGH; end - end else if (op_table_active[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]] && op_table_tx_start_ptr_reg != op_table_start_ptr_reg && (!RQ_SEQ_NUM_ENABLE || active_tx_count_av_reg)) begin + end else if (op_table_active[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]] && op_table_tx_start_ptr_reg != op_table_start_ptr_reg && (!TX_FC_ENABLE || have_credit_reg) && (!RQ_SEQ_NUM_ENABLE || active_tx_count_av_reg)) begin s_axis_rq_tready_next = 1'b0; op_table_tx_start_en = 1'b1; tlp_state_next = TLP_STATE_HEADER_1; @@ -805,7 +815,7 @@ always @* begin last_tlp_next = op_table_last[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]]; tag_next = op_table_tag[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]]; - if (op_table_active[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]] && op_table_tx_start_ptr_reg != op_table_start_ptr_reg && !s_axis_rq_tvalid && (!RQ_SEQ_NUM_ENABLE || active_tx_count_av_reg)) begin + if (op_table_active[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]] && op_table_tx_start_ptr_reg != op_table_start_ptr_reg && !s_axis_rq_tvalid && (!TX_FC_ENABLE || have_credit_reg) && (!RQ_SEQ_NUM_ENABLE || active_tx_count_av_reg)) begin op_table_tx_start_en = 1'b1; tlp_state_next = TLP_STATE_HEADER_1; end else begin @@ -894,7 +904,7 @@ always @* begin last_tlp_next = op_table_last[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]]; tag_next = op_table_tag[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]]; - if (op_table_active[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]] && op_table_tx_start_ptr_reg != op_table_start_ptr_reg && !s_axis_rq_tvalid && (!RQ_SEQ_NUM_ENABLE || active_tx_count_av_reg)) begin + if (op_table_active[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]] && op_table_tx_start_ptr_reg != op_table_start_ptr_reg && !s_axis_rq_tvalid && (!TX_FC_ENABLE || have_credit_reg) && (!RQ_SEQ_NUM_ENABLE || active_tx_count_av_reg)) begin op_table_tx_start_en = 1'b1; tlp_state_next = TLP_STATE_HEADER_1; end else begin @@ -1001,6 +1011,8 @@ always @(posedge clk) begin max_payload_size_dw_reg <= 11'd32 << (max_payload_size > 5 ? 5 : max_payload_size); + have_credit_reg <= (pcie_tx_fc_ph_av > 4) && (pcie_tx_fc_pd_av > (max_payload_size_dw_reg >> 1)); + if (active_tx_count_reg < TX_LIMIT && inc_active_tx && !axis_rq_seq_num_valid_0_int && !axis_rq_seq_num_valid_1_int) begin // inc by 1 active_tx_count_reg <= active_tx_count_reg + 1; diff --git a/fpga/lib/pcie/rtl/pcie_us_axi_dma.v b/fpga/lib/pcie/rtl/pcie_us_axi_dma.v index 62ff4d7ae..68406a209 100644 --- a/fpga/lib/pcie/rtl/pcie_us_axi_dma.v +++ b/fpga/lib/pcie/rtl/pcie_us_axi_dma.v @@ -69,10 +69,14 @@ module pcie_us_axi_dma # parameter READ_OP_TABLE_SIZE = 2**(AXI_ID_WIDTH < PCIE_TAG_WIDTH ? AXI_ID_WIDTH : PCIE_TAG_WIDTH), // In-flight transmit limit (read) parameter READ_TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1), + // Transmit flow control (read) + parameter READ_TX_FC_ENABLE = 0, // Operation table size (write) parameter WRITE_OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1), // In-flight transmit limit (write) - parameter WRITE_TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1) + parameter WRITE_TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1), + // Transmit flow control (write) + parameter WRITE_TX_FC_ENABLE = 0 ) ( input wire clk, @@ -101,10 +105,17 @@ module pcie_us_axi_dma # /* * Transmit sequence number input */ - input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0, - input wire s_axis_rq_seq_num_valid_0, - input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1, - input wire s_axis_rq_seq_num_valid_1, + input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0, + input wire s_axis_rq_seq_num_valid_0, + input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1, + input wire s_axis_rq_seq_num_valid_1, + + /* + * Transmit flow control + */ + input wire [7:0] pcie_tx_fc_nph_av, + input wire [7:0] pcie_tx_fc_ph_av, + input wire [11:0] pcie_tx_fc_pd_av, /* * AXI read descriptor input @@ -226,7 +237,8 @@ pcie_us_axi_dma_rd #( .LEN_WIDTH(LEN_WIDTH), .TAG_WIDTH(TAG_WIDTH), .OP_TABLE_SIZE(READ_OP_TABLE_SIZE), - .TX_LIMIT(READ_TX_LIMIT) + .TX_LIMIT(READ_TX_LIMIT), + .TX_FC_ENABLE(READ_TX_FC_ENABLE) ) pcie_us_axi_dma_rd_inst ( .clk(clk), @@ -260,6 +272,11 @@ pcie_us_axi_dma_rd_inst ( .s_axis_rq_seq_num_1(axis_rq_seq_num_read_1), .s_axis_rq_seq_num_valid_1(axis_rq_seq_num_valid_read_1), + /* + * Transmit flow control + */ + .pcie_tx_fc_nph_av(pcie_tx_fc_nph_av), + /* * AXI read descriptor input */ @@ -330,7 +347,8 @@ pcie_us_axi_dma_wr #( .LEN_WIDTH(LEN_WIDTH), .TAG_WIDTH(TAG_WIDTH), .OP_TABLE_SIZE(WRITE_OP_TABLE_SIZE), - .TX_LIMIT(WRITE_TX_LIMIT) + .TX_LIMIT(WRITE_TX_LIMIT), + .TX_FC_ENABLE(WRITE_TX_FC_ENABLE) ) pcie_us_axi_dma_wr_inst ( .clk(clk), @@ -372,6 +390,12 @@ pcie_us_axi_dma_wr_inst ( .m_axis_rq_seq_num_1(axis_rq_seq_num_read_1), .m_axis_rq_seq_num_valid_1(axis_rq_seq_num_valid_read_1), + /* + * Transmit flow control + */ + .pcie_tx_fc_ph_av(pcie_tx_fc_ph_av), + .pcie_tx_fc_pd_av(pcie_tx_fc_pd_av), + /* * AXI write descriptor input */ diff --git a/fpga/lib/pcie/rtl/pcie_us_axi_dma_rd.v b/fpga/lib/pcie/rtl/pcie_us_axi_dma_rd.v index a0b1ea45d..b32b5b2a4 100644 --- a/fpga/lib/pcie/rtl/pcie_us_axi_dma_rd.v +++ b/fpga/lib/pcie/rtl/pcie_us_axi_dma_rd.v @@ -68,7 +68,9 @@ module pcie_us_axi_dma_rd # // Operation table size parameter OP_TABLE_SIZE = 2**(AXI_ID_WIDTH < PCIE_TAG_WIDTH ? AXI_ID_WIDTH : PCIE_TAG_WIDTH), // In-flight transmit limit - parameter TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1) + parameter TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1), + // Transmit flow control + parameter TX_FC_ENABLE = 0 ) ( input wire clk, @@ -97,10 +99,15 @@ module pcie_us_axi_dma_rd # /* * Transmit sequence number input */ - input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0, - input wire s_axis_rq_seq_num_valid_0, - input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1, - input wire s_axis_rq_seq_num_valid_1, + input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0, + input wire s_axis_rq_seq_num_valid_0, + input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1, + input wire s_axis_rq_seq_num_valid_1, + + /* + * Transmit flow control + */ + input wire [7:0] pcie_tx_fc_nph_av, /* * AXI read descriptor input @@ -354,6 +361,8 @@ reg tag_table_we_tlp_reg = 1'b0, tag_table_we_tlp_next; reg [10:0] max_read_request_size_dw_reg = 11'd0; +reg have_credit_reg = 1'b0; + reg [RQ_SEQ_NUM_WIDTH-1:0] active_tx_count_reg = {RQ_SEQ_NUM_WIDTH{1'b0}}; reg active_tx_count_av_reg = 1'b1; reg inc_active_tx; @@ -472,6 +481,7 @@ reg [TAG_WIDTH-1:0] op_table_tag [2**OP_TAG_WIDTH-1:0]; reg op_table_init [2**OP_TAG_WIDTH-1:0]; reg op_table_read_init [2**OP_TAG_WIDTH-1:0]; reg op_table_read_commit [2**OP_TAG_WIDTH-1:0]; +reg op_table_read_error [2**OP_TAG_WIDTH-1:0]; reg [OP_TABLE_READ_COUNT_WIDTH-1:0] op_table_read_count_start [2**OP_TAG_WIDTH-1:0]; reg [OP_TABLE_READ_COUNT_WIDTH-1:0] op_table_read_count_finish [2**OP_TAG_WIDTH-1:0]; reg op_table_write_init [2**OP_TAG_WIDTH-1:0]; @@ -630,7 +640,7 @@ always @* begin end end REQ_STATE_START: begin - if (m_axis_rq_tready_int_reg && !tlp_cmd_valid_reg && new_tag_valid && (!RQ_SEQ_NUM_ENABLE || active_tx_count_av_reg)) begin + if (m_axis_rq_tready_int_reg && !tlp_cmd_valid_reg && new_tag_valid && (!TX_FC_ENABLE || have_credit_reg) && (!RQ_SEQ_NUM_ENABLE || active_tx_count_av_reg)) begin if (req_op_count_reg <= {max_read_request_size_dw_reg, 2'b00}-req_pcie_addr_reg[1:0]) begin // packet smaller than max read request size if (req_pcie_addr_reg[12] != req_pcie_addr_plus_op_count[12]) begin @@ -1341,6 +1351,8 @@ always @(posedge clk) begin max_read_request_size_dw_reg <= 11'd32 << (max_read_request_size > 5 ? 5 : max_read_request_size); + have_credit_reg <= pcie_tx_fc_nph_av > 4; + if (inc_active_tx && !s_axis_rq_seq_num_valid_0 && !s_axis_rq_seq_num_valid_1) begin // inc by 1 active_tx_count_reg <= active_tx_count_reg + 1; diff --git a/fpga/lib/pcie/rtl/pcie_us_axi_dma_wr.v b/fpga/lib/pcie/rtl/pcie_us_axi_dma_wr.v index 6cdeb8c26..0827f8e16 100644 --- a/fpga/lib/pcie/rtl/pcie_us_axi_dma_wr.v +++ b/fpga/lib/pcie/rtl/pcie_us_axi_dma_wr.v @@ -60,7 +60,9 @@ module pcie_us_axi_dma_wr # // Operation table size parameter OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1), // In-flight transmit limit - parameter TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1) + parameter TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1), + // Transmit flow control + parameter TX_FC_ENABLE = 0 ) ( input wire clk, @@ -89,18 +91,24 @@ module pcie_us_axi_dma_wr # /* * Transmit sequence number input */ - input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0, - input wire s_axis_rq_seq_num_valid_0, - input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1, - input wire s_axis_rq_seq_num_valid_1, + input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0, + input wire s_axis_rq_seq_num_valid_0, + input wire [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1, + input wire s_axis_rq_seq_num_valid_1, /* * Transmit sequence number output (to read DMA) */ - output wire [RQ_SEQ_NUM_WIDTH-1:0] m_axis_rq_seq_num_0, - output wire m_axis_rq_seq_num_valid_0, - output wire [RQ_SEQ_NUM_WIDTH-1:0] m_axis_rq_seq_num_1, - output wire m_axis_rq_seq_num_valid_1, + output wire [RQ_SEQ_NUM_WIDTH-1:0] m_axis_rq_seq_num_0, + output wire m_axis_rq_seq_num_valid_0, + output wire [RQ_SEQ_NUM_WIDTH-1:0] m_axis_rq_seq_num_1, + output wire m_axis_rq_seq_num_valid_1, + + /* + * Transmit flow control + */ + input wire [7:0] pcie_tx_fc_ph_av, + input wire [11:0] pcie_tx_fc_pd_av, /* * AXI write descriptor input @@ -291,6 +299,8 @@ reg tlp_cmd_last_reg = 1'b0, tlp_cmd_last_next; reg [10:0] max_payload_size_dw_reg = 11'd0; +reg have_credit_reg = 1'b0; + reg [RQ_SEQ_NUM_WIDTH-1:0] active_tx_count_reg = {RQ_SEQ_NUM_WIDTH{1'b0}}; reg active_tx_count_av_reg = 1'b1; reg inc_active_tx; @@ -688,7 +698,7 @@ always @* begin end else begin tlp_state_next = TLP_STATE_PASSTHROUGH; end - end else if (op_table_active[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]] && op_table_tx_start_ptr_reg != op_table_start_ptr_reg && (!RQ_SEQ_NUM_ENABLE || active_tx_count_av_reg)) begin + end else if (op_table_active[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]] && op_table_tx_start_ptr_reg != op_table_start_ptr_reg && (!TX_FC_ENABLE || have_credit_reg) && (!RQ_SEQ_NUM_ENABLE || active_tx_count_av_reg)) begin s_axis_rq_tready_next = 1'b0; op_table_tx_start_en = 1'b1; if (AXIS_PCIE_DATA_WIDTH >= 256) begin @@ -755,7 +765,7 @@ always @* begin last_tlp_next = op_table_last[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]]; tag_next = op_table_tag[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]]; - if (op_table_active[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]] && op_table_tx_start_ptr_reg != op_table_start_ptr_reg && !s_axis_rq_tvalid && (!RQ_SEQ_NUM_ENABLE || active_tx_count_av_reg)) begin + if (op_table_active[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]] && op_table_tx_start_ptr_reg != op_table_start_ptr_reg && !s_axis_rq_tvalid && (!TX_FC_ENABLE || have_credit_reg) && (!RQ_SEQ_NUM_ENABLE || active_tx_count_av_reg)) begin op_table_tx_start_en = 1'b1; if (AXIS_PCIE_DATA_WIDTH >= 256) begin m_axi_rready_next = m_axis_rq_tready_int_early; @@ -885,7 +895,7 @@ always @* begin last_tlp_next = op_table_last[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]]; tag_next = op_table_tag[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]]; - if (op_table_active[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]] && op_table_tx_start_ptr_reg != op_table_start_ptr_reg && !s_axis_rq_tvalid && (!RQ_SEQ_NUM_ENABLE || active_tx_count_av_reg)) begin + if (op_table_active[op_table_tx_start_ptr_reg[OP_TAG_WIDTH-1:0]] && op_table_tx_start_ptr_reg != op_table_start_ptr_reg && !s_axis_rq_tvalid && (!TX_FC_ENABLE || have_credit_reg) && (!RQ_SEQ_NUM_ENABLE || active_tx_count_av_reg)) begin op_table_tx_start_en = 1'b1; if (AXIS_PCIE_DATA_WIDTH >= 256) begin m_axi_rready_next = m_axis_rq_tready_int_early; @@ -988,6 +998,8 @@ always @(posedge clk) begin max_payload_size_dw_reg <= 11'd32 << (max_payload_size > 5 ? 5 : max_payload_size); + have_credit_reg <= (pcie_tx_fc_ph_av > 4) && (pcie_tx_fc_pd_av > (max_payload_size_dw_reg >> 1)); + if (active_tx_count_reg < TX_LIMIT && inc_active_tx && !axis_rq_seq_num_valid_0_int && !axis_rq_seq_num_valid_1_int) begin // inc by 1 active_tx_count_reg <= active_tx_count_reg + 1; diff --git a/fpga/lib/pcie/tb/pcie.py b/fpga/lib/pcie/tb/pcie.py index da82d2107..753b5923f 100644 --- a/fpga/lib/pcie/tb/pcie.py +++ b/fpga/lib/pcie/tb/pcie.py @@ -546,6 +546,10 @@ class TLP(object): """Return size of TLP in bytes, including overhead""" return self.get_size()+12 + def get_data_credits(self): + """Return size of TLP in data credits (1 credit per 4 DW)""" + return int((len(self.data)+3)/4) + def pack(self): """Pack TLP as DWORD array""" pkt = [] diff --git a/fpga/lib/pcie/tb/pcie_us.py b/fpga/lib/pcie/tb/pcie_us.py index a36edb355..775beff15 100644 --- a/fpga/lib/pcie/tb/pcie_us.py +++ b/fpga/lib/pcie/tb/pcie_us.py @@ -2507,8 +2507,9 @@ class UltrascalePCIe(Device): self.rc_source.send(tlp.pack_us_rc()) # transmit flow control - #pcie_tfc_nph_av - #pcie_tfc_npd_av + # TODO + pcie_tfc_nph_av.next = 0x3 + pcie_tfc_npd_av.next = 0x3 # configuration management if cfg_mgmt_read_write_done: @@ -2599,13 +2600,77 @@ class UltrascalePCIe(Device): #cfg_msg_transmit_done # configuration flow control - #cfg_fc_ph - #cfg_fc_pd - #cfg_fc_nph - #cfg_fc_npd - #cfg_fc_cplh - #cfg_fc_cpld - #cfg_fc_sel + if (cfg_fc_sel == 0b000): + # Receive credits at link partner + # TODO + cfg_fc_ph.next = 0 + cfg_fc_pd.next = 0 + cfg_fc_nph.next = 0 + cfg_fc_npd.next = 0 + cfg_fc_cplh.next = 0 + cfg_fc_cpld.next = 0 + elif (cfg_fc_sel == 0b001): + # Receive credit limit + # TODO + cfg_fc_ph.next = 0x80 + cfg_fc_pd.next = 0x800 + cfg_fc_nph.next = 0x80 + cfg_fc_npd.next = 0x800 + cfg_fc_cplh.next = 0x80 + cfg_fc_cpld.next = 0x800 + elif (cfg_fc_sel == 0b010): + # Receive credits consumed + # TODO + cfg_fc_ph.next = 0 + cfg_fc_pd.next = 0 + cfg_fc_nph.next = 0 + cfg_fc_npd.next = 0 + cfg_fc_cplh.next = 0 + cfg_fc_cpld.next = 0 + elif (cfg_fc_sel == 0b011): + # Available space in receive buffer + # TODO + cfg_fc_ph.next = 0 + cfg_fc_pd.next = 0 + cfg_fc_nph.next = 0 + cfg_fc_npd.next = 0 + cfg_fc_cplh.next = 0 + cfg_fc_cpld.next = 0 + elif (cfg_fc_sel == 0b100): + # Transmit credits available + # TODO + cfg_fc_ph.next = 0x80 + cfg_fc_pd.next = 0x800 + cfg_fc_nph.next = 0x80 + cfg_fc_npd.next = 0x800 + cfg_fc_cplh.next = 0x80 + cfg_fc_cpld.next = 0x800 + elif (cfg_fc_sel == 0b101): + # Transmit credit limit + # TODO + cfg_fc_ph.next = 0x80 + cfg_fc_pd.next = 0x800 + cfg_fc_nph.next = 0x80 + cfg_fc_npd.next = 0x800 + cfg_fc_cplh.next = 0x80 + cfg_fc_cpld.next = 0x800 + elif (cfg_fc_sel == 0b110): + # Transmit credits consumed + # TODO + cfg_fc_ph.next = 0 + cfg_fc_pd.next = 0 + cfg_fc_nph.next = 0 + cfg_fc_npd.next = 0 + cfg_fc_cplh.next = 0 + cfg_fc_cpld.next = 0 + else: + # Reserved + cfg_fc_ph.next = 0 + cfg_fc_pd.next = 0 + cfg_fc_nph.next = 0 + cfg_fc_npd.next = 0 + cfg_fc_cplh.next = 0 + cfg_fc_cpld.next = 0 # per-function status #cfg_per_func_status_control diff --git a/fpga/lib/pcie/tb/pcie_usp.py b/fpga/lib/pcie/tb/pcie_usp.py index 38325c488..47bbe8573 100644 --- a/fpga/lib/pcie/tb/pcie_usp.py +++ b/fpga/lib/pcie/tb/pcie_usp.py @@ -833,8 +833,9 @@ class UltrascalePlusPCIe(Device): self.rc_source.send(tlp.pack_us_rc()) # transmit flow control - #pcie_tfc_nph_av - #pcie_tfc_npd_av + # TODO + pcie_tfc_nph_av.next = 0xf + pcie_tfc_npd_av.next = 0xf # configuration management # TODO four cycle delay @@ -910,13 +911,50 @@ class UltrascalePlusPCIe(Device): #cfg_msg_transmit_done # configuration flow control - #cfg_fc_ph - #cfg_fc_pd - #cfg_fc_nph - #cfg_fc_npd - #cfg_fc_cplh - #cfg_fc_cpld - #cfg_fc_sel + if (cfg_fc_sel == 0b010): + # Receive credits consumed + # TODO + cfg_fc_ph.next = 0 + cfg_fc_pd.next = 0 + cfg_fc_nph.next = 0 + cfg_fc_npd.next = 0 + cfg_fc_cplh.next = 0 + cfg_fc_cpld.next = 0 + elif (cfg_fc_sel == 0b100): + # Transmit credits available + # TODO + cfg_fc_ph.next = 0x80 + cfg_fc_pd.next = 0x800 + cfg_fc_nph.next = 0x80 + cfg_fc_npd.next = 0x800 + cfg_fc_cplh.next = 0x80 + cfg_fc_cpld.next = 0x800 + elif (cfg_fc_sel == 0b101): + # Transmit credit limit + # TODO + cfg_fc_ph.next = 0x80 + cfg_fc_pd.next = 0x800 + cfg_fc_nph.next = 0x80 + cfg_fc_npd.next = 0x800 + cfg_fc_cplh.next = 0x80 + cfg_fc_cpld.next = 0x800 + elif (cfg_fc_sel == 0b110): + # Transmit credits consumed + # TODO + cfg_fc_ph.next = 0 + cfg_fc_pd.next = 0 + cfg_fc_nph.next = 0 + cfg_fc_npd.next = 0 + cfg_fc_cplh.next = 0 + cfg_fc_cpld.next = 0 + else: + # Reserved + cfg_fc_ph.next = 0 + cfg_fc_pd.next = 0 + cfg_fc_nph.next = 0 + cfg_fc_npd.next = 0 + cfg_fc_cplh.next = 0 + cfg_fc_cpld.next = 0 # configuration control #cfg_hot_reset_in diff --git a/fpga/lib/pcie/tb/test_dma_if_pcie_us_256.py b/fpga/lib/pcie/tb/test_dma_if_pcie_us_256.py index 2351006de..827ea1830 100755 --- a/fpga/lib/pcie/tb/test_dma_if_pcie_us_256.py +++ b/fpga/lib/pcie/tb/test_dma_if_pcie_us_256.py @@ -70,8 +70,10 @@ def bench(): TAG_WIDTH = 8 READ_OP_TABLE_SIZE = PCIE_TAG_COUNT READ_TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1) + READ_TX_FC_ENABLE = 1 WRITE_OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1) WRITE_TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1) + WRITE_TX_FC_ENABLE = 1 # Inputs clk = Signal(bool(0)) @@ -88,6 +90,9 @@ def bench(): s_axis_rq_seq_num_valid_0 = Signal(bool(0)) s_axis_rq_seq_num_1 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:]) s_axis_rq_seq_num_valid_1 = Signal(bool(0)) + pcie_tx_fc_nph_av = Signal(intbv(0)[8:]) + pcie_tx_fc_ph_av = Signal(intbv(0)[8:]) + pcie_tx_fc_pd_av = Signal(intbv(0)[12:]) s_axis_read_desc_pcie_addr = Signal(intbv(0)[PCIE_ADDR_WIDTH:]) s_axis_read_desc_ram_sel = Signal(intbv(0)[RAM_SEL_WIDTH:]) s_axis_read_desc_ram_addr = Signal(intbv(0)[RAM_ADDR_WIDTH:]) @@ -275,6 +280,15 @@ def bench(): # pcie_tfc_nph_av=pcie_tfc_nph_av, # pcie_tfc_npd_av=pcie_tfc_npd_av, + # Configuration Flow Control Interface + cfg_fc_ph=pcie_tx_fc_ph_av, + cfg_fc_pd=pcie_tx_fc_pd_av, + cfg_fc_nph=pcie_tx_fc_nph_av, + #cfg_fc_npd=cfg_fc_npd, + #cfg_fc_cplh=cfg_fc_cplh, + #cfg_fc_cpld=cfg_fc_cpld, + cfg_fc_sel=Signal(intbv(0b100)[3:]), + # Configuration Control Interface # cfg_hot_reset_in=cfg_hot_reset_in, # cfg_hot_reset_out=cfg_hot_reset_out, @@ -336,6 +350,9 @@ def bench(): s_axis_rq_seq_num_valid_0=s_axis_rq_seq_num_valid_0, s_axis_rq_seq_num_1=s_axis_rq_seq_num_1, s_axis_rq_seq_num_valid_1=s_axis_rq_seq_num_valid_1, + pcie_tx_fc_nph_av=pcie_tx_fc_nph_av, + pcie_tx_fc_ph_av=pcie_tx_fc_ph_av, + pcie_tx_fc_pd_av=pcie_tx_fc_pd_av, s_axis_read_desc_pcie_addr=s_axis_read_desc_pcie_addr, s_axis_read_desc_ram_sel=s_axis_read_desc_ram_sel, s_axis_read_desc_ram_addr=s_axis_read_desc_ram_addr, diff --git a/fpga/lib/pcie/tb/test_dma_if_pcie_us_256.v b/fpga/lib/pcie/tb/test_dma_if_pcie_us_256.v index 9be7098be..7b307e9fc 100644 --- a/fpga/lib/pcie/tb/test_dma_if_pcie_us_256.v +++ b/fpga/lib/pcie/tb/test_dma_if_pcie_us_256.v @@ -52,8 +52,10 @@ parameter LEN_WIDTH = 16; parameter TAG_WIDTH = 8; parameter READ_OP_TABLE_SIZE = PCIE_TAG_COUNT; parameter READ_TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1); +parameter READ_TX_FC_ENABLE = 1; parameter WRITE_OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1); parameter WRITE_TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1); +parameter WRITE_TX_FC_ENABLE = 1; // Inputs reg clk = 0; @@ -70,6 +72,9 @@ reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0 = 0; reg s_axis_rq_seq_num_valid_0 = 0; reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1 = 0; reg s_axis_rq_seq_num_valid_1 = 0; +reg [7:0] pcie_tx_fc_nph_av = 0; +reg [7:0] pcie_tx_fc_ph_av = 0; +reg [11:0] pcie_tx_fc_pd_av = 0; reg [PCIE_ADDR_WIDTH-1:0] s_axis_read_desc_pcie_addr = 0; reg [RAM_SEL_WIDTH-1:0] s_axis_read_desc_ram_sel = 0; reg [RAM_ADDR_WIDTH-1:0] s_axis_read_desc_ram_addr = 0; @@ -135,6 +140,9 @@ initial begin s_axis_rq_seq_num_valid_0, s_axis_rq_seq_num_1, s_axis_rq_seq_num_valid_1, + pcie_tx_fc_nph_av, + pcie_tx_fc_ph_av, + pcie_tx_fc_pd_av, s_axis_read_desc_pcie_addr, s_axis_read_desc_ram_sel, s_axis_read_desc_ram_addr, @@ -211,8 +219,10 @@ dma_if_pcie_us #( .TAG_WIDTH(TAG_WIDTH), .READ_OP_TABLE_SIZE(READ_OP_TABLE_SIZE), .READ_TX_LIMIT(READ_TX_LIMIT), + .READ_TX_FC_ENABLE(READ_TX_FC_ENABLE), .WRITE_OP_TABLE_SIZE(WRITE_OP_TABLE_SIZE), - .WRITE_TX_LIMIT(WRITE_TX_LIMIT) + .WRITE_TX_LIMIT(WRITE_TX_LIMIT), + .WRITE_TX_FC_ENABLE(WRITE_TX_FC_ENABLE) ) UUT ( .clk(clk), @@ -233,6 +243,9 @@ UUT ( .s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0), .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + .pcie_tx_fc_nph_av(pcie_tx_fc_nph_av), + .pcie_tx_fc_ph_av(pcie_tx_fc_ph_av), + .pcie_tx_fc_pd_av(pcie_tx_fc_pd_av), .s_axis_read_desc_pcie_addr(s_axis_read_desc_pcie_addr), .s_axis_read_desc_ram_sel(s_axis_read_desc_ram_sel), .s_axis_read_desc_ram_addr(s_axis_read_desc_ram_addr), diff --git a/fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_128.py b/fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_128.py index 6dfb0ca9f..88790e459 100755 --- a/fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_128.py +++ b/fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_128.py @@ -53,7 +53,7 @@ def bench(): AXIS_PCIE_RC_USER_WIDTH = 75 AXIS_PCIE_RQ_USER_WIDTH = 60 RQ_SEQ_NUM_WIDTH = 4 if AXIS_PCIE_RQ_USER_WIDTH == 60 else 6 - RQ_SEQ_NUM_ENABLE = 1c + RQ_SEQ_NUM_ENABLE = 1 SEG_COUNT = max(2, int(AXIS_PCIE_DATA_WIDTH*2/128)) SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH*2/SEG_COUNT SEG_ADDR_WIDTH = 12 @@ -68,6 +68,7 @@ def bench(): TAG_WIDTH = 8 OP_TABLE_SIZE = PCIE_TAG_COUNT TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1) + TX_FC_ENABLE = 1 # Inputs clk = Signal(bool(0)) @@ -84,6 +85,7 @@ def bench(): s_axis_rq_seq_num_valid_0 = Signal(bool(0)) s_axis_rq_seq_num_1 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:]) s_axis_rq_seq_num_valid_1 = Signal(bool(0)) + pcie_tx_fc_nph_av = Signal(intbv(0)[8:]) s_axis_read_desc_pcie_addr = Signal(intbv(0)[PCIE_ADDR_WIDTH:]) s_axis_read_desc_ram_sel = Signal(intbv(0)[RAM_SEL_WIDTH:]) s_axis_read_desc_ram_addr = Signal(intbv(0)[RAM_ADDR_WIDTH:]) @@ -220,6 +222,15 @@ def bench(): # pcie_tfc_nph_av=pcie_tfc_nph_av, # pcie_tfc_npd_av=pcie_tfc_npd_av, + # Configuration Flow Control Interface + #cfg_fc_ph=cfg_fc_ph, + #cfg_fc_pd=cfg_fc_pd, + cfg_fc_nph=pcie_tx_fc_nph_av, + #cfg_fc_npd=cfg_fc_npd, + #cfg_fc_cplh=cfg_fc_cplh, + #cfg_fc_cpld=cfg_fc_cpld, + cfg_fc_sel=Signal(intbv(0b100)[3:]), + # Configuration Control Interface # cfg_hot_reset_in=cfg_hot_reset_in, # cfg_hot_reset_out=cfg_hot_reset_out, @@ -281,6 +292,7 @@ def bench(): s_axis_rq_seq_num_valid_0=s_axis_rq_seq_num_valid_0, s_axis_rq_seq_num_1=s_axis_rq_seq_num_1, s_axis_rq_seq_num_valid_1=s_axis_rq_seq_num_valid_1, + pcie_tx_fc_nph_av=pcie_tx_fc_nph_av, s_axis_read_desc_pcie_addr=s_axis_read_desc_pcie_addr, s_axis_read_desc_ram_sel=s_axis_read_desc_ram_sel, s_axis_read_desc_ram_addr=s_axis_read_desc_ram_addr, diff --git a/fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_128.v b/fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_128.v index 6b5fb25b5..1e3db208f 100644 --- a/fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_128.v +++ b/fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_128.v @@ -52,6 +52,7 @@ parameter LEN_WIDTH = 16; parameter TAG_WIDTH = 8; parameter OP_TABLE_SIZE = PCIE_TAG_COUNT; parameter TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1); +parameter TX_FC_ENABLE = 1; // Inputs reg clk = 0; @@ -68,6 +69,7 @@ reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0 = 0; reg s_axis_rq_seq_num_valid_0 = 0; reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1 = 0; reg s_axis_rq_seq_num_valid_1 = 0; +reg [7:0] pcie_tx_fc_nph_av = 0; reg [PCIE_ADDR_WIDTH-1:0] s_axis_read_desc_pcie_addr = 0; reg [RAM_SEL_WIDTH-1:0] s_axis_read_desc_ram_sel = 0; reg [RAM_ADDR_WIDTH-1:0] s_axis_read_desc_ram_addr = 0; @@ -115,6 +117,7 @@ initial begin s_axis_rq_seq_num_valid_0, s_axis_rq_seq_num_1, s_axis_rq_seq_num_valid_1, + pcie_tx_fc_nph_av, s_axis_read_desc_pcie_addr, s_axis_read_desc_ram_sel, s_axis_read_desc_ram_addr, @@ -172,7 +175,8 @@ dma_if_pcie_us_rd #( .LEN_WIDTH(LEN_WIDTH), .TAG_WIDTH(TAG_WIDTH), .OP_TABLE_SIZE(OP_TABLE_SIZE), - .TX_LIMIT(TX_LIMIT) + .TX_LIMIT(TX_LIMIT), + .TX_FC_ENABLE(TX_FC_ENABLE) ) UUT ( .clk(clk), @@ -193,6 +197,7 @@ UUT ( .s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0), .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + .pcie_tx_fc_nph_av(pcie_tx_fc_nph_av), .s_axis_read_desc_pcie_addr(s_axis_read_desc_pcie_addr), .s_axis_read_desc_ram_sel(s_axis_read_desc_ram_sel), .s_axis_read_desc_ram_addr(s_axis_read_desc_ram_addr), diff --git a/fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_256.py b/fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_256.py index 96f3e8e9c..a48044ea7 100755 --- a/fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_256.py +++ b/fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_256.py @@ -68,6 +68,7 @@ def bench(): TAG_WIDTH = 8 OP_TABLE_SIZE = PCIE_TAG_COUNT TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1) + TX_FC_ENABLE = 1 # Inputs clk = Signal(bool(0)) @@ -84,6 +85,7 @@ def bench(): s_axis_rq_seq_num_valid_0 = Signal(bool(0)) s_axis_rq_seq_num_1 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:]) s_axis_rq_seq_num_valid_1 = Signal(bool(0)) + pcie_tx_fc_nph_av = Signal(intbv(0)[8:]) s_axis_read_desc_pcie_addr = Signal(intbv(0)[PCIE_ADDR_WIDTH:]) s_axis_read_desc_ram_sel = Signal(intbv(0)[SEG_SEL_WIDTH:]) s_axis_read_desc_ram_addr = Signal(intbv(0)[RAM_ADDR_WIDTH:]) @@ -220,6 +222,15 @@ def bench(): # pcie_tfc_nph_av=pcie_tfc_nph_av, # pcie_tfc_npd_av=pcie_tfc_npd_av, + # Configuration Flow Control Interface + #cfg_fc_ph=cfg_fc_ph, + #cfg_fc_pd=cfg_fc_pd, + cfg_fc_nph=pcie_tx_fc_nph_av, + #cfg_fc_npd=cfg_fc_npd, + #cfg_fc_cplh=cfg_fc_cplh, + #cfg_fc_cpld=cfg_fc_cpld, + cfg_fc_sel=Signal(intbv(0b100)[3:]), + # Configuration Control Interface # cfg_hot_reset_in=cfg_hot_reset_in, # cfg_hot_reset_out=cfg_hot_reset_out, @@ -281,6 +292,7 @@ def bench(): s_axis_rq_seq_num_valid_0=s_axis_rq_seq_num_valid_0, s_axis_rq_seq_num_1=s_axis_rq_seq_num_1, s_axis_rq_seq_num_valid_1=s_axis_rq_seq_num_valid_1, + pcie_tx_fc_nph_av=pcie_tx_fc_nph_av, s_axis_read_desc_pcie_addr=s_axis_read_desc_pcie_addr, s_axis_read_desc_ram_sel=s_axis_read_desc_ram_sel, s_axis_read_desc_ram_addr=s_axis_read_desc_ram_addr, diff --git a/fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_256.v b/fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_256.v index afd8788ce..a97319140 100644 --- a/fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_256.v +++ b/fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_256.v @@ -52,6 +52,7 @@ parameter LEN_WIDTH = 16; parameter TAG_WIDTH = 8; parameter OP_TABLE_SIZE = PCIE_TAG_COUNT; parameter TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1); +parameter TX_FC_ENABLE = 1; // Inputs reg clk = 0; @@ -68,6 +69,7 @@ reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0 = 0; reg s_axis_rq_seq_num_valid_0 = 0; reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1 = 0; reg s_axis_rq_seq_num_valid_1 = 0; +reg [7:0] pcie_tx_fc_nph_av = 0; reg [PCIE_ADDR_WIDTH-1:0] s_axis_read_desc_pcie_addr = 0; reg [RAM_SEL_WIDTH-1:0] s_axis_read_desc_ram_sel = 0; reg [RAM_ADDR_WIDTH-1:0] s_axis_read_desc_ram_addr = 0; @@ -115,6 +117,7 @@ initial begin s_axis_rq_seq_num_valid_0, s_axis_rq_seq_num_1, s_axis_rq_seq_num_valid_1, + pcie_tx_fc_nph_av, s_axis_read_desc_pcie_addr, s_axis_read_desc_ram_sel, s_axis_read_desc_ram_addr, @@ -172,7 +175,8 @@ dma_if_pcie_us_rd #( .LEN_WIDTH(LEN_WIDTH), .TAG_WIDTH(TAG_WIDTH), .OP_TABLE_SIZE(OP_TABLE_SIZE), - .TX_LIMIT(TX_LIMIT) + .TX_LIMIT(TX_LIMIT), + .TX_FC_ENABLE(TX_FC_ENABLE) ) UUT ( .clk(clk), @@ -193,6 +197,7 @@ UUT ( .s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0), .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + .pcie_tx_fc_nph_av(pcie_tx_fc_nph_av), .s_axis_read_desc_pcie_addr(s_axis_read_desc_pcie_addr), .s_axis_read_desc_ram_sel(s_axis_read_desc_ram_sel), .s_axis_read_desc_ram_addr(s_axis_read_desc_ram_addr), diff --git a/fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_512.py b/fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_512.py index 5615886a0..7e8b3cc21 100755 --- a/fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_512.py +++ b/fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_512.py @@ -68,6 +68,7 @@ def bench(): TAG_WIDTH = 8 OP_TABLE_SIZE = PCIE_TAG_COUNT TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1) + TX_FC_ENABLE = 1 # Inputs clk = Signal(bool(0)) @@ -84,6 +85,7 @@ def bench(): s_axis_rq_seq_num_valid_0 = Signal(bool(0)) s_axis_rq_seq_num_1 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:]) s_axis_rq_seq_num_valid_1 = Signal(bool(0)) + pcie_tx_fc_nph_av = Signal(intbv(0)[8:]) s_axis_read_desc_pcie_addr = Signal(intbv(0)[PCIE_ADDR_WIDTH:]) s_axis_read_desc_ram_sel = Signal(intbv(0)[SEG_SEL_WIDTH:]) s_axis_read_desc_ram_addr = Signal(intbv(0)[RAM_ADDR_WIDTH:]) @@ -224,6 +226,15 @@ def bench(): # pcie_tfc_nph_av=pcie_tfc_nph_av, # pcie_tfc_npd_av=pcie_tfc_npd_av, + # Configuration Flow Control Interface + #cfg_fc_ph=cfg_fc_ph, + #cfg_fc_pd=cfg_fc_pd, + cfg_fc_nph=pcie_tx_fc_nph_av, + #cfg_fc_npd=cfg_fc_npd, + #cfg_fc_cplh=cfg_fc_cplh, + #cfg_fc_cpld=cfg_fc_cpld, + cfg_fc_sel=Signal(intbv(0b100)[3:]), + # Configuration Control Interface # cfg_hot_reset_in=cfg_hot_reset_in, # cfg_hot_reset_out=cfg_hot_reset_out, @@ -283,6 +294,7 @@ def bench(): s_axis_rq_seq_num_valid_0=s_axis_rq_seq_num_valid_0, s_axis_rq_seq_num_1=s_axis_rq_seq_num_1, s_axis_rq_seq_num_valid_1=s_axis_rq_seq_num_valid_1, + pcie_tx_fc_nph_av=pcie_tx_fc_nph_av, s_axis_read_desc_pcie_addr=s_axis_read_desc_pcie_addr, s_axis_read_desc_ram_sel=s_axis_read_desc_ram_sel, s_axis_read_desc_ram_addr=s_axis_read_desc_ram_addr, diff --git a/fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_512.v b/fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_512.v index 61d6c367e..7328b72b2 100644 --- a/fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_512.v +++ b/fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_512.v @@ -52,6 +52,7 @@ parameter LEN_WIDTH = 16; parameter TAG_WIDTH = 8; parameter OP_TABLE_SIZE = PCIE_TAG_COUNT; parameter TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1); +parameter TX_FC_ENABLE = 1; // Inputs reg clk = 0; @@ -68,6 +69,7 @@ reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0 = 0; reg s_axis_rq_seq_num_valid_0 = 0; reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1 = 0; reg s_axis_rq_seq_num_valid_1 = 0; +reg [7:0] pcie_tx_fc_nph_av = 0; reg [PCIE_ADDR_WIDTH-1:0] s_axis_read_desc_pcie_addr = 0; reg [RAM_SEL_WIDTH-1:0] s_axis_read_desc_ram_sel = 0; reg [RAM_ADDR_WIDTH-1:0] s_axis_read_desc_ram_addr = 0; @@ -115,6 +117,7 @@ initial begin s_axis_rq_seq_num_valid_0, s_axis_rq_seq_num_1, s_axis_rq_seq_num_valid_1, + pcie_tx_fc_nph_av, s_axis_read_desc_pcie_addr, s_axis_read_desc_ram_sel, s_axis_read_desc_ram_addr, @@ -172,7 +175,8 @@ dma_if_pcie_us_rd #( .LEN_WIDTH(LEN_WIDTH), .TAG_WIDTH(TAG_WIDTH), .OP_TABLE_SIZE(OP_TABLE_SIZE), - .TX_LIMIT(TX_LIMIT) + .TX_LIMIT(TX_LIMIT), + .TX_FC_ENABLE(TX_FC_ENABLE) ) UUT ( .clk(clk), @@ -193,6 +197,7 @@ UUT ( .s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0), .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + .pcie_tx_fc_nph_av(pcie_tx_fc_nph_av), .s_axis_read_desc_pcie_addr(s_axis_read_desc_pcie_addr), .s_axis_read_desc_ram_sel(s_axis_read_desc_ram_sel), .s_axis_read_desc_ram_addr(s_axis_read_desc_ram_addr), diff --git a/fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_64.py b/fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_64.py index 75d442210..3ee1b78cc 100755 --- a/fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_64.py +++ b/fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_64.py @@ -68,6 +68,7 @@ def bench(): TAG_WIDTH = 8 OP_TABLE_SIZE = PCIE_TAG_COUNT TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1) + TX_FC_ENABLE = 1 # Inputs clk = Signal(bool(0)) @@ -84,6 +85,7 @@ def bench(): s_axis_rq_seq_num_valid_0 = Signal(bool(0)) s_axis_rq_seq_num_1 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:]) s_axis_rq_seq_num_valid_1 = Signal(bool(0)) + pcie_tx_fc_nph_av = Signal(intbv(0)[8:]) s_axis_read_desc_pcie_addr = Signal(intbv(0)[PCIE_ADDR_WIDTH:]) s_axis_read_desc_ram_sel = Signal(intbv(0)[RAM_SEL_WIDTH:]) s_axis_read_desc_ram_addr = Signal(intbv(0)[RAM_ADDR_WIDTH:]) @@ -220,6 +222,15 @@ def bench(): # pcie_tfc_nph_av=pcie_tfc_nph_av, # pcie_tfc_npd_av=pcie_tfc_npd_av, + # Configuration Flow Control Interface + #cfg_fc_ph=cfg_fc_ph, + #cfg_fc_pd=cfg_fc_pd, + cfg_fc_nph=pcie_tx_fc_nph_av, + #cfg_fc_npd=cfg_fc_npd, + #cfg_fc_cplh=cfg_fc_cplh, + #cfg_fc_cpld=cfg_fc_cpld, + cfg_fc_sel=Signal(intbv(0b100)[3:]), + # Configuration Control Interface # cfg_hot_reset_in=cfg_hot_reset_in, # cfg_hot_reset_out=cfg_hot_reset_out, @@ -281,6 +292,7 @@ def bench(): s_axis_rq_seq_num_valid_0=s_axis_rq_seq_num_valid_0, s_axis_rq_seq_num_1=s_axis_rq_seq_num_1, s_axis_rq_seq_num_valid_1=s_axis_rq_seq_num_valid_1, + pcie_tx_fc_nph_av=pcie_tx_fc_nph_av, s_axis_read_desc_pcie_addr=s_axis_read_desc_pcie_addr, s_axis_read_desc_ram_sel=s_axis_read_desc_ram_sel, s_axis_read_desc_ram_addr=s_axis_read_desc_ram_addr, diff --git a/fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_64.v b/fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_64.v index 523bc9898..7c5b2b5ea 100644 --- a/fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_64.v +++ b/fpga/lib/pcie/tb/test_dma_if_pcie_us_rd_64.v @@ -52,6 +52,7 @@ parameter LEN_WIDTH = 16; parameter TAG_WIDTH = 8; parameter OP_TABLE_SIZE = PCIE_TAG_COUNT; parameter TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1); +parameter TX_FC_ENABLE = 1; // Inputs reg clk = 0; @@ -68,6 +69,7 @@ reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0 = 0; reg s_axis_rq_seq_num_valid_0 = 0; reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1 = 0; reg s_axis_rq_seq_num_valid_1 = 0; +reg [7:0] pcie_tx_fc_nph_av = 0; reg [PCIE_ADDR_WIDTH-1:0] s_axis_read_desc_pcie_addr = 0; reg [RAM_SEL_WIDTH-1:0] s_axis_read_desc_ram_sel = 0; reg [RAM_ADDR_WIDTH-1:0] s_axis_read_desc_ram_addr = 0; @@ -115,6 +117,7 @@ initial begin s_axis_rq_seq_num_valid_0, s_axis_rq_seq_num_1, s_axis_rq_seq_num_valid_1, + pcie_tx_fc_nph_av, s_axis_read_desc_pcie_addr, s_axis_read_desc_ram_sel, s_axis_read_desc_ram_addr, @@ -172,7 +175,8 @@ dma_if_pcie_us_rd #( .LEN_WIDTH(LEN_WIDTH), .TAG_WIDTH(TAG_WIDTH), .OP_TABLE_SIZE(OP_TABLE_SIZE), - .TX_LIMIT(TX_LIMIT) + .TX_LIMIT(TX_LIMIT), + .TX_FC_ENABLE(TX_FC_ENABLE) ) UUT ( .clk(clk), @@ -193,6 +197,7 @@ UUT ( .s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0), .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + .pcie_tx_fc_nph_av(pcie_tx_fc_nph_av), .s_axis_read_desc_pcie_addr(s_axis_read_desc_pcie_addr), .s_axis_read_desc_ram_sel(s_axis_read_desc_ram_sel), .s_axis_read_desc_ram_addr(s_axis_read_desc_ram_addr), diff --git a/fpga/lib/pcie/tb/test_dma_if_pcie_us_wr_128.py b/fpga/lib/pcie/tb/test_dma_if_pcie_us_wr_128.py index 14e73c776..fa9696cd4 100755 --- a/fpga/lib/pcie/tb/test_dma_if_pcie_us_wr_128.py +++ b/fpga/lib/pcie/tb/test_dma_if_pcie_us_wr_128.py @@ -62,6 +62,7 @@ def bench(): TAG_WIDTH = 8 OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1) TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1) + TX_FC_ENABLE = 1 # Inputs clk = Signal(bool(0)) @@ -78,6 +79,8 @@ def bench(): s_axis_rq_seq_num_valid_0 = Signal(bool(0)) s_axis_rq_seq_num_1 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:]) s_axis_rq_seq_num_valid_1 = Signal(bool(0)) + pcie_tx_fc_ph_av = Signal(intbv(0)[8:]) + pcie_tx_fc_pd_av = Signal(intbv(0)[12:]) s_axis_write_desc_pcie_addr = Signal(intbv(0)[PCIE_ADDR_WIDTH:]) s_axis_write_desc_ram_sel = Signal(intbv(0)[RAM_SEL_WIDTH:]) s_axis_write_desc_ram_addr = Signal(intbv(0)[RAM_ADDR_WIDTH:]) @@ -217,6 +220,15 @@ def bench(): # pcie_tfc_nph_av=pcie_tfc_nph_av, # pcie_tfc_npd_av=pcie_tfc_npd_av, + # Configuration Flow Control Interface + cfg_fc_ph=pcie_tx_fc_ph_av, + cfg_fc_pd=pcie_tx_fc_pd_av, + #cfg_fc_nph=cfg_fc_nph, + #cfg_fc_npd=cfg_fc_npd, + #cfg_fc_cplh=cfg_fc_cplh, + #cfg_fc_cpld=cfg_fc_cpld, + cfg_fc_sel=Signal(intbv(0b100)[3:]), + # Configuration Control Interface # cfg_hot_reset_in=cfg_hot_reset_in, # cfg_hot_reset_out=cfg_hot_reset_out, @@ -282,6 +294,8 @@ def bench(): m_axis_rq_seq_num_valid_0=m_axis_rq_seq_num_valid_0, m_axis_rq_seq_num_1=m_axis_rq_seq_num_1, m_axis_rq_seq_num_valid_1=m_axis_rq_seq_num_valid_1, + pcie_tx_fc_ph_av=pcie_tx_fc_ph_av, + pcie_tx_fc_pd_av=pcie_tx_fc_pd_av, s_axis_write_desc_pcie_addr=s_axis_write_desc_pcie_addr, s_axis_write_desc_ram_sel=s_axis_write_desc_ram_sel, s_axis_write_desc_ram_addr=s_axis_write_desc_ram_addr, diff --git a/fpga/lib/pcie/tb/test_dma_if_pcie_us_wr_128.v b/fpga/lib/pcie/tb/test_dma_if_pcie_us_wr_128.v index 6d283d6ed..5ef5e7e34 100644 --- a/fpga/lib/pcie/tb/test_dma_if_pcie_us_wr_128.v +++ b/fpga/lib/pcie/tb/test_dma_if_pcie_us_wr_128.v @@ -48,6 +48,7 @@ parameter LEN_WIDTH = 16; parameter TAG_WIDTH = 8; parameter OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1); parameter TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1); +parameter TX_FC_ENABLE = 1; // Inputs reg clk = 0; @@ -64,6 +65,8 @@ reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0 = 0; reg s_axis_rq_seq_num_valid_0 = 0; reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1 = 0; reg s_axis_rq_seq_num_valid_1 = 0; +reg [7:0] pcie_tx_fc_ph_av = 0; +reg [11:0] pcie_tx_fc_pd_av = 0; reg [PCIE_ADDR_WIDTH-1:0] s_axis_write_desc_pcie_addr = 0; reg [RAM_SEL_WIDTH-1:0] s_axis_write_desc_ram_sel = 0; reg [RAM_ADDR_WIDTH-1:0] s_axis_write_desc_ram_addr = 0; @@ -113,6 +116,8 @@ initial begin s_axis_rq_seq_num_valid_0, s_axis_rq_seq_num_1, s_axis_rq_seq_num_valid_1, + pcie_tx_fc_ph_av, + pcie_tx_fc_pd_av, s_axis_write_desc_pcie_addr, s_axis_write_desc_ram_sel, s_axis_write_desc_ram_addr, @@ -168,7 +173,8 @@ dma_if_pcie_us_wr #( .LEN_WIDTH(LEN_WIDTH), .TAG_WIDTH(TAG_WIDTH), .OP_TABLE_SIZE(OP_TABLE_SIZE), - .TX_LIMIT(TX_LIMIT) + .TX_LIMIT(TX_LIMIT), + .TX_FC_ENABLE(TX_FC_ENABLE) ) UUT ( .clk(clk), @@ -193,6 +199,8 @@ UUT ( .m_axis_rq_seq_num_valid_0(m_axis_rq_seq_num_valid_0), .m_axis_rq_seq_num_1(m_axis_rq_seq_num_1), .m_axis_rq_seq_num_valid_1(m_axis_rq_seq_num_valid_1), + .pcie_tx_fc_ph_av(pcie_tx_fc_ph_av), + .pcie_tx_fc_pd_av(pcie_tx_fc_pd_av), .s_axis_write_desc_pcie_addr(s_axis_write_desc_pcie_addr), .s_axis_write_desc_ram_sel(s_axis_write_desc_ram_sel), .s_axis_write_desc_ram_addr(s_axis_write_desc_ram_addr), diff --git a/fpga/lib/pcie/tb/test_dma_if_pcie_us_wr_256.py b/fpga/lib/pcie/tb/test_dma_if_pcie_us_wr_256.py index 4cdb966ee..6f85cc33d 100755 --- a/fpga/lib/pcie/tb/test_dma_if_pcie_us_wr_256.py +++ b/fpga/lib/pcie/tb/test_dma_if_pcie_us_wr_256.py @@ -62,6 +62,7 @@ def bench(): TAG_WIDTH = 8 OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1) TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1) + TX_FC_ENABLE = 1 # Inputs clk = Signal(bool(0)) @@ -78,6 +79,8 @@ def bench(): s_axis_rq_seq_num_valid_0 = Signal(bool(0)) s_axis_rq_seq_num_1 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:]) s_axis_rq_seq_num_valid_1 = Signal(bool(0)) + pcie_tx_fc_ph_av = Signal(intbv(0)[8:]) + pcie_tx_fc_pd_av = Signal(intbv(0)[12:]) s_axis_write_desc_pcie_addr = Signal(intbv(0)[PCIE_ADDR_WIDTH:]) s_axis_write_desc_ram_sel = Signal(intbv(0)[RAM_SEL_WIDTH:]) s_axis_write_desc_ram_addr = Signal(intbv(0)[RAM_ADDR_WIDTH:]) @@ -217,6 +220,15 @@ def bench(): # pcie_tfc_nph_av=pcie_tfc_nph_av, # pcie_tfc_npd_av=pcie_tfc_npd_av, + # Configuration Flow Control Interface + cfg_fc_ph=pcie_tx_fc_ph_av, + cfg_fc_pd=pcie_tx_fc_pd_av, + #cfg_fc_nph=cfg_fc_nph, + #cfg_fc_npd=cfg_fc_npd, + #cfg_fc_cplh=cfg_fc_cplh, + #cfg_fc_cpld=cfg_fc_cpld, + cfg_fc_sel=Signal(intbv(0b100)[3:]), + # Configuration Control Interface # cfg_hot_reset_in=cfg_hot_reset_in, # cfg_hot_reset_out=cfg_hot_reset_out, @@ -282,6 +294,8 @@ def bench(): m_axis_rq_seq_num_valid_0=m_axis_rq_seq_num_valid_0, m_axis_rq_seq_num_1=m_axis_rq_seq_num_1, m_axis_rq_seq_num_valid_1=m_axis_rq_seq_num_valid_1, + pcie_tx_fc_ph_av=pcie_tx_fc_ph_av, + pcie_tx_fc_pd_av=pcie_tx_fc_pd_av, s_axis_write_desc_pcie_addr=s_axis_write_desc_pcie_addr, s_axis_write_desc_ram_sel=s_axis_write_desc_ram_sel, s_axis_write_desc_ram_addr=s_axis_write_desc_ram_addr, diff --git a/fpga/lib/pcie/tb/test_dma_if_pcie_us_wr_256.v b/fpga/lib/pcie/tb/test_dma_if_pcie_us_wr_256.v index 54a12cb8d..ab28c38ae 100644 --- a/fpga/lib/pcie/tb/test_dma_if_pcie_us_wr_256.v +++ b/fpga/lib/pcie/tb/test_dma_if_pcie_us_wr_256.v @@ -48,6 +48,7 @@ parameter LEN_WIDTH = 16; parameter TAG_WIDTH = 8; parameter OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1); parameter TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1); +parameter TX_FC_ENABLE = 1; // Inputs reg clk = 0; @@ -64,6 +65,8 @@ reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0 = 0; reg s_axis_rq_seq_num_valid_0 = 0; reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1 = 0; reg s_axis_rq_seq_num_valid_1 = 0; +reg [7:0] pcie_tx_fc_ph_av = 0; +reg [11:0] pcie_tx_fc_pd_av = 0; reg [PCIE_ADDR_WIDTH-1:0] s_axis_write_desc_pcie_addr = 0; reg [RAM_SEL_WIDTH-1:0] s_axis_write_desc_ram_sel = 0; reg [RAM_ADDR_WIDTH-1:0] s_axis_write_desc_ram_addr = 0; @@ -113,6 +116,8 @@ initial begin s_axis_rq_seq_num_valid_0, s_axis_rq_seq_num_1, s_axis_rq_seq_num_valid_1, + pcie_tx_fc_ph_av, + pcie_tx_fc_pd_av, s_axis_write_desc_pcie_addr, s_axis_write_desc_ram_sel, s_axis_write_desc_ram_addr, @@ -168,7 +173,8 @@ dma_if_pcie_us_wr #( .LEN_WIDTH(LEN_WIDTH), .TAG_WIDTH(TAG_WIDTH), .OP_TABLE_SIZE(OP_TABLE_SIZE), - .TX_LIMIT(TX_LIMIT) + .TX_LIMIT(TX_LIMIT), + .TX_FC_ENABLE(TX_FC_ENABLE) ) UUT ( .clk(clk), @@ -193,6 +199,8 @@ UUT ( .m_axis_rq_seq_num_valid_0(m_axis_rq_seq_num_valid_0), .m_axis_rq_seq_num_1(m_axis_rq_seq_num_1), .m_axis_rq_seq_num_valid_1(m_axis_rq_seq_num_valid_1), + .pcie_tx_fc_ph_av(pcie_tx_fc_ph_av), + .pcie_tx_fc_pd_av(pcie_tx_fc_pd_av), .s_axis_write_desc_pcie_addr(s_axis_write_desc_pcie_addr), .s_axis_write_desc_ram_sel(s_axis_write_desc_ram_sel), .s_axis_write_desc_ram_addr(s_axis_write_desc_ram_addr), diff --git a/fpga/lib/pcie/tb/test_dma_if_pcie_us_wr_512.py b/fpga/lib/pcie/tb/test_dma_if_pcie_us_wr_512.py index d34d1f923..16987d876 100755 --- a/fpga/lib/pcie/tb/test_dma_if_pcie_us_wr_512.py +++ b/fpga/lib/pcie/tb/test_dma_if_pcie_us_wr_512.py @@ -62,6 +62,7 @@ def bench(): TAG_WIDTH = 8 OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1) TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1) + TX_FC_ENABLE = 1 # Inputs clk = Signal(bool(0)) @@ -78,6 +79,8 @@ def bench(): s_axis_rq_seq_num_valid_0 = Signal(bool(0)) s_axis_rq_seq_num_1 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:]) s_axis_rq_seq_num_valid_1 = Signal(bool(0)) + pcie_tx_fc_ph_av = Signal(intbv(0)[8:]) + pcie_tx_fc_pd_av = Signal(intbv(0)[12:]) s_axis_write_desc_pcie_addr = Signal(intbv(0)[PCIE_ADDR_WIDTH:]) s_axis_write_desc_ram_sel = Signal(intbv(0)[RAM_SEL_WIDTH:]) s_axis_write_desc_ram_addr = Signal(intbv(0)[RAM_ADDR_WIDTH:]) @@ -221,6 +224,15 @@ def bench(): # pcie_tfc_nph_av=pcie_tfc_nph_av, # pcie_tfc_npd_av=pcie_tfc_npd_av, + # Configuration Flow Control Interface + cfg_fc_ph=pcie_tx_fc_ph_av, + cfg_fc_pd=pcie_tx_fc_pd_av, + #cfg_fc_nph=cfg_fc_nph, + #cfg_fc_npd=cfg_fc_npd, + #cfg_fc_cplh=cfg_fc_cplh, + #cfg_fc_cpld=cfg_fc_cpld, + cfg_fc_sel=Signal(intbv(0b100)[3:]), + # Configuration Control Interface # cfg_hot_reset_in=cfg_hot_reset_in, # cfg_hot_reset_out=cfg_hot_reset_out, @@ -284,6 +296,8 @@ def bench(): m_axis_rq_seq_num_valid_0=m_axis_rq_seq_num_valid_0, m_axis_rq_seq_num_1=m_axis_rq_seq_num_1, m_axis_rq_seq_num_valid_1=m_axis_rq_seq_num_valid_1, + pcie_tx_fc_ph_av=pcie_tx_fc_ph_av, + pcie_tx_fc_pd_av=pcie_tx_fc_pd_av, s_axis_write_desc_pcie_addr=s_axis_write_desc_pcie_addr, s_axis_write_desc_ram_sel=s_axis_write_desc_ram_sel, s_axis_write_desc_ram_addr=s_axis_write_desc_ram_addr, diff --git a/fpga/lib/pcie/tb/test_dma_if_pcie_us_wr_512.v b/fpga/lib/pcie/tb/test_dma_if_pcie_us_wr_512.v index f562b191b..259d76095 100644 --- a/fpga/lib/pcie/tb/test_dma_if_pcie_us_wr_512.v +++ b/fpga/lib/pcie/tb/test_dma_if_pcie_us_wr_512.v @@ -48,6 +48,7 @@ parameter LEN_WIDTH = 16; parameter TAG_WIDTH = 8; parameter OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1); parameter TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1); +parameter TX_FC_ENABLE = 1; // Inputs reg clk = 0; @@ -64,6 +65,8 @@ reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0 = 0; reg s_axis_rq_seq_num_valid_0 = 0; reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1 = 0; reg s_axis_rq_seq_num_valid_1 = 0; +reg [7:0] pcie_tx_fc_ph_av = 0; +reg [11:0] pcie_tx_fc_pd_av = 0; reg [PCIE_ADDR_WIDTH-1:0] s_axis_write_desc_pcie_addr = 0; reg [RAM_SEL_WIDTH-1:0] s_axis_write_desc_ram_sel = 0; reg [RAM_ADDR_WIDTH-1:0] s_axis_write_desc_ram_addr = 0; @@ -113,6 +116,8 @@ initial begin s_axis_rq_seq_num_valid_0, s_axis_rq_seq_num_1, s_axis_rq_seq_num_valid_1, + pcie_tx_fc_ph_av, + pcie_tx_fc_pd_av, s_axis_write_desc_pcie_addr, s_axis_write_desc_ram_sel, s_axis_write_desc_ram_addr, @@ -168,7 +173,8 @@ dma_if_pcie_us_wr #( .LEN_WIDTH(LEN_WIDTH), .TAG_WIDTH(TAG_WIDTH), .OP_TABLE_SIZE(OP_TABLE_SIZE), - .TX_LIMIT(TX_LIMIT) + .TX_LIMIT(TX_LIMIT), + .TX_FC_ENABLE(TX_FC_ENABLE) ) UUT ( .clk(clk), @@ -193,6 +199,8 @@ UUT ( .m_axis_rq_seq_num_valid_0(m_axis_rq_seq_num_valid_0), .m_axis_rq_seq_num_1(m_axis_rq_seq_num_1), .m_axis_rq_seq_num_valid_1(m_axis_rq_seq_num_valid_1), + .pcie_tx_fc_ph_av(pcie_tx_fc_ph_av), + .pcie_tx_fc_pd_av(pcie_tx_fc_pd_av), .s_axis_write_desc_pcie_addr(s_axis_write_desc_pcie_addr), .s_axis_write_desc_ram_sel(s_axis_write_desc_ram_sel), .s_axis_write_desc_ram_addr(s_axis_write_desc_ram_addr), diff --git a/fpga/lib/pcie/tb/test_dma_if_pcie_us_wr_64.py b/fpga/lib/pcie/tb/test_dma_if_pcie_us_wr_64.py index bb921741b..7d935efc1 100755 --- a/fpga/lib/pcie/tb/test_dma_if_pcie_us_wr_64.py +++ b/fpga/lib/pcie/tb/test_dma_if_pcie_us_wr_64.py @@ -62,6 +62,7 @@ def bench(): TAG_WIDTH = 8 OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1) TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1) + TX_FC_ENABLE = 1 # Inputs clk = Signal(bool(0)) @@ -78,6 +79,8 @@ def bench(): s_axis_rq_seq_num_valid_0 = Signal(bool(0)) s_axis_rq_seq_num_1 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:]) s_axis_rq_seq_num_valid_1 = Signal(bool(0)) + pcie_tx_fc_ph_av = Signal(intbv(0)[8:]) + pcie_tx_fc_pd_av = Signal(intbv(0)[12:]) s_axis_write_desc_pcie_addr = Signal(intbv(0)[PCIE_ADDR_WIDTH:]) s_axis_write_desc_ram_sel = Signal(intbv(0)[RAM_SEL_WIDTH:]) s_axis_write_desc_ram_addr = Signal(intbv(0)[RAM_ADDR_WIDTH:]) @@ -217,6 +220,15 @@ def bench(): # pcie_tfc_nph_av=pcie_tfc_nph_av, # pcie_tfc_npd_av=pcie_tfc_npd_av, + # Configuration Flow Control Interface + cfg_fc_ph=pcie_tx_fc_ph_av, + cfg_fc_pd=pcie_tx_fc_pd_av, + #cfg_fc_nph=cfg_fc_nph, + #cfg_fc_npd=cfg_fc_npd, + #cfg_fc_cplh=cfg_fc_cplh, + #cfg_fc_cpld=cfg_fc_cpld, + cfg_fc_sel=Signal(intbv(0b100)[3:]), + # Configuration Control Interface # cfg_hot_reset_in=cfg_hot_reset_in, # cfg_hot_reset_out=cfg_hot_reset_out, @@ -282,6 +294,8 @@ def bench(): m_axis_rq_seq_num_valid_0=m_axis_rq_seq_num_valid_0, m_axis_rq_seq_num_1=m_axis_rq_seq_num_1, m_axis_rq_seq_num_valid_1=m_axis_rq_seq_num_valid_1, + pcie_tx_fc_ph_av=pcie_tx_fc_ph_av, + pcie_tx_fc_pd_av=pcie_tx_fc_pd_av, s_axis_write_desc_pcie_addr=s_axis_write_desc_pcie_addr, s_axis_write_desc_ram_sel=s_axis_write_desc_ram_sel, s_axis_write_desc_ram_addr=s_axis_write_desc_ram_addr, diff --git a/fpga/lib/pcie/tb/test_dma_if_pcie_us_wr_64.v b/fpga/lib/pcie/tb/test_dma_if_pcie_us_wr_64.v index 7196ecb66..5738e8170 100644 --- a/fpga/lib/pcie/tb/test_dma_if_pcie_us_wr_64.v +++ b/fpga/lib/pcie/tb/test_dma_if_pcie_us_wr_64.v @@ -48,6 +48,7 @@ parameter LEN_WIDTH = 16; parameter TAG_WIDTH = 8; parameter OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1); parameter TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1); +parameter TX_FC_ENABLE = 1; // Inputs reg clk = 0; @@ -64,6 +65,8 @@ reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0 = 0; reg s_axis_rq_seq_num_valid_0 = 0; reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1 = 0; reg s_axis_rq_seq_num_valid_1 = 0; +reg [7:0] pcie_tx_fc_ph_av = 0; +reg [11:0] pcie_tx_fc_pd_av = 0; reg [PCIE_ADDR_WIDTH-1:0] s_axis_write_desc_pcie_addr = 0; reg [RAM_SEL_WIDTH-1:0] s_axis_write_desc_ram_sel = 0; reg [RAM_ADDR_WIDTH-1:0] s_axis_write_desc_ram_addr = 0; @@ -113,6 +116,8 @@ initial begin s_axis_rq_seq_num_valid_0, s_axis_rq_seq_num_1, s_axis_rq_seq_num_valid_1, + pcie_tx_fc_ph_av, + pcie_tx_fc_pd_av, s_axis_write_desc_pcie_addr, s_axis_write_desc_ram_sel, s_axis_write_desc_ram_addr, @@ -168,7 +173,8 @@ dma_if_pcie_us_wr #( .LEN_WIDTH(LEN_WIDTH), .TAG_WIDTH(TAG_WIDTH), .OP_TABLE_SIZE(OP_TABLE_SIZE), - .TX_LIMIT(TX_LIMIT) + .TX_LIMIT(TX_LIMIT), + .TX_FC_ENABLE(TX_FC_ENABLE) ) UUT ( .clk(clk), @@ -193,6 +199,8 @@ UUT ( .m_axis_rq_seq_num_valid_0(m_axis_rq_seq_num_valid_0), .m_axis_rq_seq_num_1(m_axis_rq_seq_num_1), .m_axis_rq_seq_num_valid_1(m_axis_rq_seq_num_valid_1), + .pcie_tx_fc_ph_av(pcie_tx_fc_ph_av), + .pcie_tx_fc_pd_av(pcie_tx_fc_pd_av), .s_axis_write_desc_pcie_addr(s_axis_write_desc_pcie_addr), .s_axis_write_desc_ram_sel(s_axis_write_desc_ram_sel), .s_axis_write_desc_ram_addr(s_axis_write_desc_ram_addr), diff --git a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_256.py b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_256.py index f87378d09..47ba063e9 100755 --- a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_256.py +++ b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_256.py @@ -69,8 +69,10 @@ def bench(): TAG_WIDTH = 8 READ_OP_TABLE_SIZE = PCIE_TAG_COUNT READ_TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1) + READ_TX_FC_ENABLE = 1 WRITE_OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1) WRITE_TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1) + WRITE_TX_FC_ENABLE = 1 # Inputs clk = Signal(bool(0)) @@ -87,6 +89,9 @@ def bench(): s_axis_rq_seq_num_valid_0 = Signal(bool(0)) s_axis_rq_seq_num_1 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:]) s_axis_rq_seq_num_valid_1 = Signal(bool(0)) + pcie_tx_fc_nph_av = Signal(intbv(0)[8:]) + pcie_tx_fc_ph_av = Signal(intbv(0)[8:]) + pcie_tx_fc_pd_av = Signal(intbv(0)[12:]) s_axis_read_desc_pcie_addr = Signal(intbv(0)[PCIE_ADDR_WIDTH:]) s_axis_read_desc_axi_addr = Signal(intbv(0)[AXI_ADDR_WIDTH:]) s_axis_read_desc_len = Signal(intbv(0)[LEN_WIDTH:]) @@ -305,6 +310,15 @@ def bench(): # pcie_tfc_nph_av=pcie_tfc_nph_av, # pcie_tfc_npd_av=pcie_tfc_npd_av, + # Configuration Flow Control Interface + cfg_fc_ph=pcie_tx_fc_ph_av, + cfg_fc_pd=pcie_tx_fc_pd_av, + cfg_fc_nph=pcie_tx_fc_nph_av, + #cfg_fc_npd=cfg_fc_npd, + #cfg_fc_cplh=cfg_fc_cplh, + #cfg_fc_cpld=cfg_fc_cpld, + cfg_fc_sel=Signal(intbv(0b100)[3:]), + # Configuration Control Interface # cfg_hot_reset_in=cfg_hot_reset_in, # cfg_hot_reset_out=cfg_hot_reset_out, @@ -361,6 +375,9 @@ def bench(): s_axis_rq_seq_num_valid_0=s_axis_rq_seq_num_valid_0, s_axis_rq_seq_num_1=s_axis_rq_seq_num_1, s_axis_rq_seq_num_valid_1=s_axis_rq_seq_num_valid_1, + pcie_tx_fc_nph_av=pcie_tx_fc_nph_av, + pcie_tx_fc_ph_av=pcie_tx_fc_ph_av, + pcie_tx_fc_pd_av=pcie_tx_fc_pd_av, s_axis_read_desc_pcie_addr=s_axis_read_desc_pcie_addr, s_axis_read_desc_axi_addr=s_axis_read_desc_axi_addr, s_axis_read_desc_len=s_axis_read_desc_len, diff --git a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_256.v b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_256.v index 6e3c3b193..01fa902bf 100644 --- a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_256.v +++ b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_256.v @@ -51,8 +51,10 @@ parameter LEN_WIDTH = 20; parameter TAG_WIDTH = 8; parameter READ_OP_TABLE_SIZE = PCIE_TAG_COUNT; parameter READ_TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1); +parameter READ_TX_FC_ENABLE = 1; parameter WRITE_OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1); parameter WRITE_TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1); +parameter WRITE_TX_FC_ENABLE = 1; // Inputs reg clk = 0; @@ -69,6 +71,9 @@ reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0 = 0; reg s_axis_rq_seq_num_valid_0 = 0; reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1 = 0; reg s_axis_rq_seq_num_valid_1 = 0; +reg [7:0] pcie_tx_fc_nph_av = 0; +reg [7:0] pcie_tx_fc_ph_av = 0; +reg [11:0] pcie_tx_fc_pd_av = 0; reg [PCIE_ADDR_WIDTH-1:0] s_axis_read_desc_pcie_addr = 0; reg [AXI_ADDR_WIDTH-1:0] s_axis_read_desc_axi_addr = 0; reg [LEN_WIDTH-1:0] s_axis_read_desc_len = 0; @@ -154,6 +159,9 @@ initial begin s_axis_rq_seq_num_valid_0, s_axis_rq_seq_num_1, s_axis_rq_seq_num_valid_1, + pcie_tx_fc_nph_av, + pcie_tx_fc_ph_av, + pcie_tx_fc_pd_av, s_axis_read_desc_pcie_addr, s_axis_read_desc_axi_addr, s_axis_read_desc_len, @@ -249,8 +257,10 @@ pcie_us_axi_dma #( .TAG_WIDTH(TAG_WIDTH), .READ_OP_TABLE_SIZE(READ_OP_TABLE_SIZE), .READ_TX_LIMIT(READ_TX_LIMIT), + .READ_TX_FC_ENABLE(READ_TX_FC_ENABLE), .WRITE_OP_TABLE_SIZE(WRITE_OP_TABLE_SIZE), - .WRITE_TX_LIMIT(WRITE_TX_LIMIT) + .WRITE_TX_LIMIT(WRITE_TX_LIMIT), + .WRITE_TX_FC_ENABLE(WRITE_TX_FC_ENABLE) ) UUT ( .clk(clk), @@ -271,6 +281,9 @@ UUT ( .s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0), .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + .pcie_tx_fc_nph_av(pcie_tx_fc_nph_av), + .pcie_tx_fc_ph_av(pcie_tx_fc_ph_av), + .pcie_tx_fc_pd_av(pcie_tx_fc_pd_av), .s_axis_read_desc_pcie_addr(s_axis_read_desc_pcie_addr), .s_axis_read_desc_axi_addr(s_axis_read_desc_axi_addr), .s_axis_read_desc_len(s_axis_read_desc_len), diff --git a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_rd_128.py b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_rd_128.py index 0c61bb07f..5d7c76f5a 100755 --- a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_rd_128.py +++ b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_rd_128.py @@ -68,6 +68,7 @@ def bench(): TAG_WIDTH = 8 OP_TABLE_SIZE = PCIE_TAG_COUNT TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1) + TX_FC_ENABLE = 1 # Inputs clk = Signal(bool(0)) @@ -84,6 +85,7 @@ def bench(): s_axis_rq_seq_num_valid_0 = Signal(bool(0)) s_axis_rq_seq_num_1 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:]) s_axis_rq_seq_num_valid_1 = Signal(bool(0)) + pcie_tx_fc_nph_av = Signal(intbv(0)[8:]) s_axis_read_desc_pcie_addr = Signal(intbv(0)[PCIE_ADDR_WIDTH:]) s_axis_read_desc_axi_addr = Signal(intbv(0)[AXI_ADDR_WIDTH:]) s_axis_read_desc_len = Signal(intbv(0)[LEN_WIDTH:]) @@ -244,6 +246,15 @@ def bench(): # pcie_tfc_nph_av=pcie_tfc_nph_av, # pcie_tfc_npd_av=pcie_tfc_npd_av, + # Configuration Flow Control Interface + #cfg_fc_ph=cfg_fc_ph, + #cfg_fc_pd=cfg_fc_pd, + cfg_fc_nph=pcie_tx_fc_nph_av, + #cfg_fc_npd=cfg_fc_npd, + #cfg_fc_cplh=cfg_fc_cplh, + #cfg_fc_cpld=cfg_fc_cpld, + cfg_fc_sel=Signal(intbv(0b100)[3:]), + # Configuration Control Interface # cfg_hot_reset_in=cfg_hot_reset_in, # cfg_hot_reset_out=cfg_hot_reset_out, @@ -305,6 +316,7 @@ def bench(): s_axis_rq_seq_num_valid_0=s_axis_rq_seq_num_valid_0, s_axis_rq_seq_num_1=s_axis_rq_seq_num_1, s_axis_rq_seq_num_valid_1=s_axis_rq_seq_num_valid_1, + pcie_tx_fc_nph_av=pcie_tx_fc_nph_av, s_axis_read_desc_pcie_addr=s_axis_read_desc_pcie_addr, s_axis_read_desc_axi_addr=s_axis_read_desc_axi_addr, s_axis_read_desc_len=s_axis_read_desc_len, diff --git a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_rd_128.v b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_rd_128.v index 2ceb3adc1..69ee726ee 100644 --- a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_rd_128.v +++ b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_rd_128.v @@ -51,6 +51,7 @@ parameter LEN_WIDTH = 20; parameter TAG_WIDTH = 8; parameter OP_TABLE_SIZE = PCIE_TAG_COUNT; parameter TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1); +parameter TX_FC_ENABLE = 1; // Inputs reg clk = 0; @@ -67,6 +68,7 @@ reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0 = 0; reg s_axis_rq_seq_num_valid_0 = 0; reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1 = 0; reg s_axis_rq_seq_num_valid_1 = 0; +reg [7:0] pcie_tx_fc_nph_av = 0; reg [PCIE_ADDR_WIDTH-1:0] s_axis_read_desc_pcie_addr = 0; reg [AXI_ADDR_WIDTH-1:0] s_axis_read_desc_axi_addr = 0; reg [LEN_WIDTH-1:0] s_axis_read_desc_len = 0; @@ -126,6 +128,7 @@ initial begin s_axis_rq_seq_num_valid_0, s_axis_rq_seq_num_1, s_axis_rq_seq_num_valid_1, + pcie_tx_fc_nph_av, s_axis_read_desc_pcie_addr, s_axis_read_desc_axi_addr, s_axis_read_desc_len, @@ -194,7 +197,8 @@ pcie_us_axi_dma_rd #( .LEN_WIDTH(LEN_WIDTH), .TAG_WIDTH(TAG_WIDTH), .OP_TABLE_SIZE(OP_TABLE_SIZE), - .TX_LIMIT(TX_LIMIT) + .TX_LIMIT(TX_LIMIT), + .TX_FC_ENABLE(TX_FC_ENABLE) ) UUT ( .clk(clk), @@ -215,6 +219,7 @@ UUT ( .s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0), .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + .pcie_tx_fc_nph_av(pcie_tx_fc_nph_av), .s_axis_read_desc_pcie_addr(s_axis_read_desc_pcie_addr), .s_axis_read_desc_axi_addr(s_axis_read_desc_axi_addr), .s_axis_read_desc_len(s_axis_read_desc_len), diff --git a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_rd_256.py b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_rd_256.py index ddcd559d5..83e41c080 100755 --- a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_rd_256.py +++ b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_rd_256.py @@ -68,6 +68,7 @@ def bench(): TAG_WIDTH = 8 OP_TABLE_SIZE = PCIE_TAG_COUNT TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1) + TX_FC_ENABLE = 1 # Inputs clk = Signal(bool(0)) @@ -84,6 +85,7 @@ def bench(): s_axis_rq_seq_num_valid_0 = Signal(bool(0)) s_axis_rq_seq_num_1 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:]) s_axis_rq_seq_num_valid_1 = Signal(bool(0)) + pcie_tx_fc_nph_av = Signal(intbv(0)[8:]) s_axis_read_desc_pcie_addr = Signal(intbv(0)[PCIE_ADDR_WIDTH:]) s_axis_read_desc_axi_addr = Signal(intbv(0)[AXI_ADDR_WIDTH:]) s_axis_read_desc_len = Signal(intbv(0)[LEN_WIDTH:]) @@ -244,6 +246,15 @@ def bench(): # pcie_tfc_nph_av=pcie_tfc_nph_av, # pcie_tfc_npd_av=pcie_tfc_npd_av, + # Configuration Flow Control Interface + #cfg_fc_ph=cfg_fc_ph, + #cfg_fc_pd=cfg_fc_pd, + cfg_fc_nph=pcie_tx_fc_nph_av, + #cfg_fc_npd=cfg_fc_npd, + #cfg_fc_cplh=cfg_fc_cplh, + #cfg_fc_cpld=cfg_fc_cpld, + cfg_fc_sel=Signal(intbv(0b100)[3:]), + # Configuration Control Interface # cfg_hot_reset_in=cfg_hot_reset_in, # cfg_hot_reset_out=cfg_hot_reset_out, @@ -305,6 +316,7 @@ def bench(): s_axis_rq_seq_num_valid_0=s_axis_rq_seq_num_valid_0, s_axis_rq_seq_num_1=s_axis_rq_seq_num_1, s_axis_rq_seq_num_valid_1=s_axis_rq_seq_num_valid_1, + pcie_tx_fc_nph_av=pcie_tx_fc_nph_av, s_axis_read_desc_pcie_addr=s_axis_read_desc_pcie_addr, s_axis_read_desc_axi_addr=s_axis_read_desc_axi_addr, s_axis_read_desc_len=s_axis_read_desc_len, diff --git a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_rd_256.v b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_rd_256.v index 1c47a914a..79b6dc171 100644 --- a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_rd_256.v +++ b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_rd_256.v @@ -51,6 +51,7 @@ parameter LEN_WIDTH = 20; parameter TAG_WIDTH = 8; parameter OP_TABLE_SIZE = PCIE_TAG_COUNT; parameter TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1); +parameter TX_FC_ENABLE = 1; // Inputs reg clk = 0; @@ -67,6 +68,7 @@ reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0 = 0; reg s_axis_rq_seq_num_valid_0 = 0; reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1 = 0; reg s_axis_rq_seq_num_valid_1 = 0; +reg [7:0] pcie_tx_fc_nph_av = 0; reg [PCIE_ADDR_WIDTH-1:0] s_axis_read_desc_pcie_addr = 0; reg [AXI_ADDR_WIDTH-1:0] s_axis_read_desc_axi_addr = 0; reg [LEN_WIDTH-1:0] s_axis_read_desc_len = 0; @@ -126,6 +128,7 @@ initial begin s_axis_rq_seq_num_valid_0, s_axis_rq_seq_num_1, s_axis_rq_seq_num_valid_1, + pcie_tx_fc_nph_av, s_axis_read_desc_pcie_addr, s_axis_read_desc_axi_addr, s_axis_read_desc_len, @@ -194,7 +197,8 @@ pcie_us_axi_dma_rd #( .LEN_WIDTH(LEN_WIDTH), .TAG_WIDTH(TAG_WIDTH), .OP_TABLE_SIZE(OP_TABLE_SIZE), - .TX_LIMIT(TX_LIMIT) + .TX_LIMIT(TX_LIMIT), + .TX_FC_ENABLE(TX_FC_ENABLE) ) UUT ( .clk(clk), @@ -215,6 +219,7 @@ UUT ( .s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0), .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + .pcie_tx_fc_nph_av(pcie_tx_fc_nph_av), .s_axis_read_desc_pcie_addr(s_axis_read_desc_pcie_addr), .s_axis_read_desc_axi_addr(s_axis_read_desc_axi_addr), .s_axis_read_desc_len(s_axis_read_desc_len), diff --git a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_rd_512.py b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_rd_512.py index fd4afc750..9840d5bae 100755 --- a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_rd_512.py +++ b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_rd_512.py @@ -68,6 +68,7 @@ def bench(): TAG_WIDTH = 8 OP_TABLE_SIZE = PCIE_TAG_COUNT TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1) + TX_FC_ENABLE = 1 # Inputs clk = Signal(bool(0)) @@ -84,6 +85,7 @@ def bench(): s_axis_rq_seq_num_valid_0 = Signal(bool(0)) s_axis_rq_seq_num_1 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:]) s_axis_rq_seq_num_valid_1 = Signal(bool(0)) + pcie_tx_fc_nph_av = Signal(intbv(0)[8:]) s_axis_read_desc_pcie_addr = Signal(intbv(0)[PCIE_ADDR_WIDTH:]) s_axis_read_desc_axi_addr = Signal(intbv(0)[AXI_ADDR_WIDTH:]) s_axis_read_desc_len = Signal(intbv(0)[LEN_WIDTH:]) @@ -248,6 +250,15 @@ def bench(): # pcie_tfc_nph_av=pcie_tfc_nph_av, # pcie_tfc_npd_av=pcie_tfc_npd_av, + # Configuration Flow Control Interface + #cfg_fc_ph=cfg_fc_ph, + #cfg_fc_pd=cfg_fc_pd, + cfg_fc_nph=pcie_tx_fc_nph_av, + #cfg_fc_npd=cfg_fc_npd, + #cfg_fc_cplh=cfg_fc_cplh, + #cfg_fc_cpld=cfg_fc_cpld, + cfg_fc_sel=Signal(intbv(0b100)[3:]), + # Configuration Control Interface # cfg_hot_reset_in=cfg_hot_reset_in, # cfg_hot_reset_out=cfg_hot_reset_out, @@ -307,6 +318,7 @@ def bench(): s_axis_rq_seq_num_valid_0=s_axis_rq_seq_num_valid_0, s_axis_rq_seq_num_1=s_axis_rq_seq_num_1, s_axis_rq_seq_num_valid_1=s_axis_rq_seq_num_valid_1, + pcie_tx_fc_nph_av=pcie_tx_fc_nph_av, s_axis_read_desc_pcie_addr=s_axis_read_desc_pcie_addr, s_axis_read_desc_axi_addr=s_axis_read_desc_axi_addr, s_axis_read_desc_len=s_axis_read_desc_len, diff --git a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_rd_512.v b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_rd_512.v index 5e39a858d..27df9fa49 100644 --- a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_rd_512.v +++ b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_rd_512.v @@ -51,6 +51,7 @@ parameter LEN_WIDTH = 20; parameter TAG_WIDTH = 8; parameter OP_TABLE_SIZE = PCIE_TAG_COUNT; parameter TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1); +parameter TX_FC_ENABLE = 1; // Inputs reg clk = 0; @@ -67,6 +68,7 @@ reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0 = 0; reg s_axis_rq_seq_num_valid_0 = 0; reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1 = 0; reg s_axis_rq_seq_num_valid_1 = 0; +reg [7:0] pcie_tx_fc_nph_av = 0; reg [PCIE_ADDR_WIDTH-1:0] s_axis_read_desc_pcie_addr = 0; reg [AXI_ADDR_WIDTH-1:0] s_axis_read_desc_axi_addr = 0; reg [LEN_WIDTH-1:0] s_axis_read_desc_len = 0; @@ -126,6 +128,7 @@ initial begin s_axis_rq_seq_num_valid_0, s_axis_rq_seq_num_1, s_axis_rq_seq_num_valid_1, + pcie_tx_fc_nph_av, s_axis_read_desc_pcie_addr, s_axis_read_desc_axi_addr, s_axis_read_desc_len, @@ -194,7 +197,8 @@ pcie_us_axi_dma_rd #( .LEN_WIDTH(LEN_WIDTH), .TAG_WIDTH(TAG_WIDTH), .OP_TABLE_SIZE(OP_TABLE_SIZE), - .TX_LIMIT(TX_LIMIT) + .TX_LIMIT(TX_LIMIT), + .TX_FC_ENABLE(TX_FC_ENABLE) ) UUT ( .clk(clk), @@ -215,6 +219,7 @@ UUT ( .s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0), .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + .pcie_tx_fc_nph_av(pcie_tx_fc_nph_av), .s_axis_read_desc_pcie_addr(s_axis_read_desc_pcie_addr), .s_axis_read_desc_axi_addr(s_axis_read_desc_axi_addr), .s_axis_read_desc_len(s_axis_read_desc_len), diff --git a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_rd_64.py b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_rd_64.py index 6bdc3cef7..974b05362 100755 --- a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_rd_64.py +++ b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_rd_64.py @@ -68,6 +68,7 @@ def bench(): TAG_WIDTH = 8 OP_TABLE_SIZE = PCIE_TAG_COUNT TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1) + TX_FC_ENABLE = 1 # Inputs clk = Signal(bool(0)) @@ -84,6 +85,7 @@ def bench(): s_axis_rq_seq_num_valid_0 = Signal(bool(0)) s_axis_rq_seq_num_1 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:]) s_axis_rq_seq_num_valid_1 = Signal(bool(0)) + pcie_tx_fc_nph_av = Signal(intbv(0)[8:]) s_axis_read_desc_pcie_addr = Signal(intbv(0)[PCIE_ADDR_WIDTH:]) s_axis_read_desc_axi_addr = Signal(intbv(0)[AXI_ADDR_WIDTH:]) s_axis_read_desc_len = Signal(intbv(0)[LEN_WIDTH:]) @@ -244,6 +246,15 @@ def bench(): # pcie_tfc_nph_av=pcie_tfc_nph_av, # pcie_tfc_npd_av=pcie_tfc_npd_av, + # Configuration Flow Control Interface + #cfg_fc_ph=cfg_fc_ph, + #cfg_fc_pd=cfg_fc_pd, + cfg_fc_nph=pcie_tx_fc_nph_av, + #cfg_fc_npd=cfg_fc_npd, + #cfg_fc_cplh=cfg_fc_cplh, + #cfg_fc_cpld=cfg_fc_cpld, + cfg_fc_sel=Signal(intbv(0b100)[3:]), + # Configuration Control Interface # cfg_hot_reset_in=cfg_hot_reset_in, # cfg_hot_reset_out=cfg_hot_reset_out, @@ -305,6 +316,7 @@ def bench(): s_axis_rq_seq_num_valid_0=s_axis_rq_seq_num_valid_0, s_axis_rq_seq_num_1=s_axis_rq_seq_num_1, s_axis_rq_seq_num_valid_1=s_axis_rq_seq_num_valid_1, + pcie_tx_fc_nph_av=pcie_tx_fc_nph_av, s_axis_read_desc_pcie_addr=s_axis_read_desc_pcie_addr, s_axis_read_desc_axi_addr=s_axis_read_desc_axi_addr, s_axis_read_desc_len=s_axis_read_desc_len, diff --git a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_rd_64.v b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_rd_64.v index 606f20b38..4761f95c3 100644 --- a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_rd_64.v +++ b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_rd_64.v @@ -51,6 +51,7 @@ parameter LEN_WIDTH = 20; parameter TAG_WIDTH = 8; parameter OP_TABLE_SIZE = PCIE_TAG_COUNT; parameter TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1); +parameter TX_FC_ENABLE = 1; // Inputs reg clk = 0; @@ -67,6 +68,7 @@ reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0 = 0; reg s_axis_rq_seq_num_valid_0 = 0; reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1 = 0; reg s_axis_rq_seq_num_valid_1 = 0; +reg [7:0] pcie_tx_fc_nph_av = 0; reg [PCIE_ADDR_WIDTH-1:0] s_axis_read_desc_pcie_addr = 0; reg [AXI_ADDR_WIDTH-1:0] s_axis_read_desc_axi_addr = 0; reg [LEN_WIDTH-1:0] s_axis_read_desc_len = 0; @@ -126,6 +128,7 @@ initial begin s_axis_rq_seq_num_valid_0, s_axis_rq_seq_num_1, s_axis_rq_seq_num_valid_1, + pcie_tx_fc_nph_av, s_axis_read_desc_pcie_addr, s_axis_read_desc_axi_addr, s_axis_read_desc_len, @@ -194,7 +197,8 @@ pcie_us_axi_dma_rd #( .LEN_WIDTH(LEN_WIDTH), .TAG_WIDTH(TAG_WIDTH), .OP_TABLE_SIZE(OP_TABLE_SIZE), - .TX_LIMIT(TX_LIMIT) + .TX_LIMIT(TX_LIMIT), + .TX_FC_ENABLE(TX_FC_ENABLE) ) UUT ( .clk(clk), @@ -215,6 +219,7 @@ UUT ( .s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0), .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + .pcie_tx_fc_nph_av(pcie_tx_fc_nph_av), .s_axis_read_desc_pcie_addr(s_axis_read_desc_pcie_addr), .s_axis_read_desc_axi_addr(s_axis_read_desc_axi_addr), .s_axis_read_desc_len(s_axis_read_desc_len), diff --git a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_128.py b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_128.py index 10271186a..24b8a882a 100755 --- a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_128.py +++ b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_128.py @@ -61,6 +61,7 @@ def bench(): TAG_WIDTH = 8 OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1) TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1) + TX_FC_ENABLE = 1 # Inputs clk = Signal(bool(0)) @@ -77,6 +78,8 @@ def bench(): s_axis_rq_seq_num_valid_0 = Signal(bool(0)) s_axis_rq_seq_num_1 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:]) s_axis_rq_seq_num_valid_1 = Signal(bool(0)) + pcie_tx_fc_ph_av = Signal(intbv(0)[8:]) + pcie_tx_fc_pd_av = Signal(intbv(0)[12:]) s_axis_write_desc_pcie_addr = Signal(intbv(0)[PCIE_ADDR_WIDTH:]) s_axis_write_desc_axi_addr = Signal(intbv(0)[AXI_ADDR_WIDTH:]) s_axis_write_desc_len = Signal(intbv(0)[LEN_WIDTH:]) @@ -231,6 +234,15 @@ def bench(): # pcie_tfc_nph_av=pcie_tfc_nph_av, # pcie_tfc_npd_av=pcie_tfc_npd_av, + # Configuration Flow Control Interface + cfg_fc_ph=pcie_tx_fc_ph_av, + cfg_fc_pd=pcie_tx_fc_pd_av, + #cfg_fc_nph=cfg_fc_nph, + #cfg_fc_npd=cfg_fc_npd, + #cfg_fc_cplh=cfg_fc_cplh, + #cfg_fc_cpld=cfg_fc_cpld, + cfg_fc_sel=Signal(intbv(0b100)[3:]), + # Configuration Control Interface # cfg_hot_reset_in=cfg_hot_reset_in, # cfg_hot_reset_out=cfg_hot_reset_out, @@ -296,6 +308,8 @@ def bench(): m_axis_rq_seq_num_valid_0=m_axis_rq_seq_num_valid_0, m_axis_rq_seq_num_1=m_axis_rq_seq_num_1, m_axis_rq_seq_num_valid_1=m_axis_rq_seq_num_valid_1, + pcie_tx_fc_ph_av=pcie_tx_fc_ph_av, + pcie_tx_fc_pd_av=pcie_tx_fc_pd_av, s_axis_write_desc_pcie_addr=s_axis_write_desc_pcie_addr, s_axis_write_desc_axi_addr=s_axis_write_desc_axi_addr, s_axis_write_desc_len=s_axis_write_desc_len, diff --git a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_128.v b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_128.v index c3c3bbafe..b61a88641 100644 --- a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_128.v +++ b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_128.v @@ -47,6 +47,7 @@ parameter LEN_WIDTH = 20; parameter TAG_WIDTH = 8; parameter OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1); parameter TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1); +parameter TX_FC_ENABLE = 1; // Inputs reg clk = 0; @@ -63,6 +64,8 @@ reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0 = 0; reg s_axis_rq_seq_num_valid_0 = 0; reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1 = 0; reg s_axis_rq_seq_num_valid_1 = 0; +reg [7:0] pcie_tx_fc_ph_av = 0; +reg [11:0] pcie_tx_fc_pd_av = 0; reg [PCIE_ADDR_WIDTH-1:0] s_axis_write_desc_pcie_addr = 0; reg [AXI_ADDR_WIDTH-1:0] s_axis_write_desc_axi_addr = 0; reg [LEN_WIDTH-1:0] s_axis_write_desc_len = 0; @@ -120,6 +123,8 @@ initial begin s_axis_rq_seq_num_valid_0, s_axis_rq_seq_num_1, s_axis_rq_seq_num_valid_1, + pcie_tx_fc_ph_av, + pcie_tx_fc_pd_av, s_axis_write_desc_pcie_addr, s_axis_write_desc_axi_addr, s_axis_write_desc_len, @@ -182,7 +187,8 @@ pcie_us_axi_dma_wr #( .LEN_WIDTH(LEN_WIDTH), .TAG_WIDTH(TAG_WIDTH), .OP_TABLE_SIZE(OP_TABLE_SIZE), - .TX_LIMIT(TX_LIMIT) + .TX_LIMIT(TX_LIMIT), + .TX_FC_ENABLE(TX_FC_ENABLE) ) UUT ( .clk(clk), @@ -207,6 +213,8 @@ UUT ( .m_axis_rq_seq_num_valid_0(m_axis_rq_seq_num_valid_0), .m_axis_rq_seq_num_1(m_axis_rq_seq_num_1), .m_axis_rq_seq_num_valid_1(m_axis_rq_seq_num_valid_1), + .pcie_tx_fc_ph_av(pcie_tx_fc_ph_av), + .pcie_tx_fc_pd_av(pcie_tx_fc_pd_av), .s_axis_write_desc_pcie_addr(s_axis_write_desc_pcie_addr), .s_axis_write_desc_axi_addr(s_axis_write_desc_axi_addr), .s_axis_write_desc_len(s_axis_write_desc_len), diff --git a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_256.py b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_256.py index 6b7099d3f..68a1cbd57 100755 --- a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_256.py +++ b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_256.py @@ -61,6 +61,7 @@ def bench(): TAG_WIDTH = 8 OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1) TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1) + TX_FC_ENABLE = 1 # Inputs clk = Signal(bool(0)) @@ -77,6 +78,8 @@ def bench(): s_axis_rq_seq_num_valid_0 = Signal(bool(0)) s_axis_rq_seq_num_1 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:]) s_axis_rq_seq_num_valid_1 = Signal(bool(0)) + pcie_tx_fc_ph_av = Signal(intbv(0)[8:]) + pcie_tx_fc_pd_av = Signal(intbv(0)[12:]) s_axis_write_desc_pcie_addr = Signal(intbv(0)[PCIE_ADDR_WIDTH:]) s_axis_write_desc_axi_addr = Signal(intbv(0)[AXI_ADDR_WIDTH:]) s_axis_write_desc_len = Signal(intbv(0)[LEN_WIDTH:]) @@ -231,6 +234,15 @@ def bench(): # pcie_tfc_nph_av=pcie_tfc_nph_av, # pcie_tfc_npd_av=pcie_tfc_npd_av, + # Configuration Flow Control Interface + cfg_fc_ph=pcie_tx_fc_ph_av, + cfg_fc_pd=pcie_tx_fc_pd_av, + #cfg_fc_nph=cfg_fc_nph, + #cfg_fc_npd=cfg_fc_npd, + #cfg_fc_cplh=cfg_fc_cplh, + #cfg_fc_cpld=cfg_fc_cpld, + cfg_fc_sel=Signal(intbv(0b100)[3:]), + # Configuration Control Interface # cfg_hot_reset_in=cfg_hot_reset_in, # cfg_hot_reset_out=cfg_hot_reset_out, @@ -296,6 +308,8 @@ def bench(): m_axis_rq_seq_num_valid_0=m_axis_rq_seq_num_valid_0, m_axis_rq_seq_num_1=m_axis_rq_seq_num_1, m_axis_rq_seq_num_valid_1=m_axis_rq_seq_num_valid_1, + pcie_tx_fc_ph_av=pcie_tx_fc_ph_av, + pcie_tx_fc_pd_av=pcie_tx_fc_pd_av, s_axis_write_desc_pcie_addr=s_axis_write_desc_pcie_addr, s_axis_write_desc_axi_addr=s_axis_write_desc_axi_addr, s_axis_write_desc_len=s_axis_write_desc_len, diff --git a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_256.v b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_256.v index 6752e5d91..fb0d87dc1 100644 --- a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_256.v +++ b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_256.v @@ -47,6 +47,7 @@ parameter LEN_WIDTH = 20; parameter TAG_WIDTH = 8; parameter OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1); parameter TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1); +parameter TX_FC_ENABLE = 1; // Inputs reg clk = 0; @@ -63,6 +64,8 @@ reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0 = 0; reg s_axis_rq_seq_num_valid_0 = 0; reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1 = 0; reg s_axis_rq_seq_num_valid_1 = 0; +reg [7:0] pcie_tx_fc_ph_av = 0; +reg [11:0] pcie_tx_fc_pd_av = 0; reg [PCIE_ADDR_WIDTH-1:0] s_axis_write_desc_pcie_addr = 0; reg [AXI_ADDR_WIDTH-1:0] s_axis_write_desc_axi_addr = 0; reg [LEN_WIDTH-1:0] s_axis_write_desc_len = 0; @@ -120,6 +123,8 @@ initial begin s_axis_rq_seq_num_valid_0, s_axis_rq_seq_num_1, s_axis_rq_seq_num_valid_1, + pcie_tx_fc_ph_av, + pcie_tx_fc_pd_av, s_axis_write_desc_pcie_addr, s_axis_write_desc_axi_addr, s_axis_write_desc_len, @@ -182,7 +187,8 @@ pcie_us_axi_dma_wr #( .LEN_WIDTH(LEN_WIDTH), .TAG_WIDTH(TAG_WIDTH), .OP_TABLE_SIZE(OP_TABLE_SIZE), - .TX_LIMIT(TX_LIMIT) + .TX_LIMIT(TX_LIMIT), + .TX_FC_ENABLE(TX_FC_ENABLE) ) UUT ( .clk(clk), @@ -207,6 +213,8 @@ UUT ( .m_axis_rq_seq_num_valid_0(m_axis_rq_seq_num_valid_0), .m_axis_rq_seq_num_1(m_axis_rq_seq_num_1), .m_axis_rq_seq_num_valid_1(m_axis_rq_seq_num_valid_1), + .pcie_tx_fc_ph_av(pcie_tx_fc_ph_av), + .pcie_tx_fc_pd_av(pcie_tx_fc_pd_av), .s_axis_write_desc_pcie_addr(s_axis_write_desc_pcie_addr), .s_axis_write_desc_axi_addr(s_axis_write_desc_axi_addr), .s_axis_write_desc_len(s_axis_write_desc_len), diff --git a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_512.py b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_512.py index b7274f673..ee8df0092 100755 --- a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_512.py +++ b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_512.py @@ -61,6 +61,7 @@ def bench(): TAG_WIDTH = 8 OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1) TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1) + TX_FC_ENABLE = 1 # Inputs clk = Signal(bool(0)) @@ -77,6 +78,8 @@ def bench(): s_axis_rq_seq_num_valid_0 = Signal(bool(0)) s_axis_rq_seq_num_1 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:]) s_axis_rq_seq_num_valid_1 = Signal(bool(0)) + pcie_tx_fc_ph_av = Signal(intbv(0)[8:]) + pcie_tx_fc_pd_av = Signal(intbv(0)[12:]) s_axis_write_desc_pcie_addr = Signal(intbv(0)[PCIE_ADDR_WIDTH:]) s_axis_write_desc_axi_addr = Signal(intbv(0)[AXI_ADDR_WIDTH:]) s_axis_write_desc_len = Signal(intbv(0)[LEN_WIDTH:]) @@ -235,6 +238,15 @@ def bench(): # pcie_tfc_nph_av=pcie_tfc_nph_av, # pcie_tfc_npd_av=pcie_tfc_npd_av, + # Configuration Flow Control Interface + cfg_fc_ph=pcie_tx_fc_ph_av, + cfg_fc_pd=pcie_tx_fc_pd_av, + #cfg_fc_nph=cfg_fc_nph, + #cfg_fc_npd=cfg_fc_npd, + #cfg_fc_cplh=cfg_fc_cplh, + #cfg_fc_cpld=cfg_fc_cpld, + cfg_fc_sel=Signal(intbv(0b100)[3:]), + # Configuration Control Interface # cfg_hot_reset_in=cfg_hot_reset_in, # cfg_hot_reset_out=cfg_hot_reset_out, @@ -298,6 +310,8 @@ def bench(): m_axis_rq_seq_num_valid_0=m_axis_rq_seq_num_valid_0, m_axis_rq_seq_num_1=m_axis_rq_seq_num_1, m_axis_rq_seq_num_valid_1=m_axis_rq_seq_num_valid_1, + pcie_tx_fc_ph_av=pcie_tx_fc_ph_av, + pcie_tx_fc_pd_av=pcie_tx_fc_pd_av, s_axis_write_desc_pcie_addr=s_axis_write_desc_pcie_addr, s_axis_write_desc_axi_addr=s_axis_write_desc_axi_addr, s_axis_write_desc_len=s_axis_write_desc_len, diff --git a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_512.v b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_512.v index 01001e639..4cdf91fe1 100644 --- a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_512.v +++ b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_512.v @@ -47,6 +47,7 @@ parameter LEN_WIDTH = 20; parameter TAG_WIDTH = 8; parameter OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1); parameter TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1); +parameter TX_FC_ENABLE = 1; // Inputs reg clk = 0; @@ -63,6 +64,8 @@ reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0 = 0; reg s_axis_rq_seq_num_valid_0 = 0; reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1 = 0; reg s_axis_rq_seq_num_valid_1 = 0; +reg [7:0] pcie_tx_fc_ph_av = 0; +reg [11:0] pcie_tx_fc_pd_av = 0; reg [PCIE_ADDR_WIDTH-1:0] s_axis_write_desc_pcie_addr = 0; reg [AXI_ADDR_WIDTH-1:0] s_axis_write_desc_axi_addr = 0; reg [LEN_WIDTH-1:0] s_axis_write_desc_len = 0; @@ -120,6 +123,8 @@ initial begin s_axis_rq_seq_num_valid_0, s_axis_rq_seq_num_1, s_axis_rq_seq_num_valid_1, + pcie_tx_fc_ph_av, + pcie_tx_fc_pd_av, s_axis_write_desc_pcie_addr, s_axis_write_desc_axi_addr, s_axis_write_desc_len, @@ -182,7 +187,8 @@ pcie_us_axi_dma_wr #( .LEN_WIDTH(LEN_WIDTH), .TAG_WIDTH(TAG_WIDTH), .OP_TABLE_SIZE(OP_TABLE_SIZE), - .TX_LIMIT(TX_LIMIT) + .TX_LIMIT(TX_LIMIT), + .TX_FC_ENABLE(TX_FC_ENABLE) ) UUT ( .clk(clk), @@ -207,6 +213,8 @@ UUT ( .m_axis_rq_seq_num_valid_0(m_axis_rq_seq_num_valid_0), .m_axis_rq_seq_num_1(m_axis_rq_seq_num_1), .m_axis_rq_seq_num_valid_1(m_axis_rq_seq_num_valid_1), + .pcie_tx_fc_ph_av(pcie_tx_fc_ph_av), + .pcie_tx_fc_pd_av(pcie_tx_fc_pd_av), .s_axis_write_desc_pcie_addr(s_axis_write_desc_pcie_addr), .s_axis_write_desc_axi_addr(s_axis_write_desc_axi_addr), .s_axis_write_desc_len(s_axis_write_desc_len), diff --git a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_64.py b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_64.py index adca2865f..4e4fe795e 100755 --- a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_64.py +++ b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_64.py @@ -61,6 +61,7 @@ def bench(): TAG_WIDTH = 8 OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1) TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1) + TX_FC_ENABLE = 1 # Inputs clk = Signal(bool(0)) @@ -77,6 +78,8 @@ def bench(): s_axis_rq_seq_num_valid_0 = Signal(bool(0)) s_axis_rq_seq_num_1 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:]) s_axis_rq_seq_num_valid_1 = Signal(bool(0)) + pcie_tx_fc_ph_av = Signal(intbv(0)[8:]) + pcie_tx_fc_pd_av = Signal(intbv(0)[12:]) s_axis_write_desc_pcie_addr = Signal(intbv(0)[PCIE_ADDR_WIDTH:]) s_axis_write_desc_axi_addr = Signal(intbv(0)[AXI_ADDR_WIDTH:]) s_axis_write_desc_len = Signal(intbv(0)[LEN_WIDTH:]) @@ -231,6 +234,15 @@ def bench(): # pcie_tfc_nph_av=pcie_tfc_nph_av, # pcie_tfc_npd_av=pcie_tfc_npd_av, + # Configuration Flow Control Interface + cfg_fc_ph=pcie_tx_fc_ph_av, + cfg_fc_pd=pcie_tx_fc_pd_av, + #cfg_fc_nph=cfg_fc_nph, + #cfg_fc_npd=cfg_fc_npd, + #cfg_fc_cplh=cfg_fc_cplh, + #cfg_fc_cpld=cfg_fc_cpld, + cfg_fc_sel=Signal(intbv(0b100)[3:]), + # Configuration Control Interface # cfg_hot_reset_in=cfg_hot_reset_in, # cfg_hot_reset_out=cfg_hot_reset_out, @@ -296,6 +308,8 @@ def bench(): m_axis_rq_seq_num_valid_0=m_axis_rq_seq_num_valid_0, m_axis_rq_seq_num_1=m_axis_rq_seq_num_1, m_axis_rq_seq_num_valid_1=m_axis_rq_seq_num_valid_1, + pcie_tx_fc_ph_av=pcie_tx_fc_ph_av, + pcie_tx_fc_pd_av=pcie_tx_fc_pd_av, s_axis_write_desc_pcie_addr=s_axis_write_desc_pcie_addr, s_axis_write_desc_axi_addr=s_axis_write_desc_axi_addr, s_axis_write_desc_len=s_axis_write_desc_len, diff --git a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_64.v b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_64.v index 4a34c30cc..d5d803528 100644 --- a/fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_64.v +++ b/fpga/lib/pcie/tb/test_pcie_us_axi_dma_wr_64.v @@ -47,6 +47,7 @@ parameter LEN_WIDTH = 20; parameter TAG_WIDTH = 8; parameter OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1); parameter TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1); +parameter TX_FC_ENABLE = 1; // Inputs reg clk = 0; @@ -63,6 +64,8 @@ reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0 = 0; reg s_axis_rq_seq_num_valid_0 = 0; reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1 = 0; reg s_axis_rq_seq_num_valid_1 = 0; +reg [7:0] pcie_tx_fc_ph_av = 0; +reg [11:0] pcie_tx_fc_pd_av = 0; reg [PCIE_ADDR_WIDTH-1:0] s_axis_write_desc_pcie_addr = 0; reg [AXI_ADDR_WIDTH-1:0] s_axis_write_desc_axi_addr = 0; reg [LEN_WIDTH-1:0] s_axis_write_desc_len = 0; @@ -120,6 +123,8 @@ initial begin s_axis_rq_seq_num_valid_0, s_axis_rq_seq_num_1, s_axis_rq_seq_num_valid_1, + pcie_tx_fc_ph_av, + pcie_tx_fc_pd_av, s_axis_write_desc_pcie_addr, s_axis_write_desc_axi_addr, s_axis_write_desc_len, @@ -182,7 +187,8 @@ pcie_us_axi_dma_wr #( .LEN_WIDTH(LEN_WIDTH), .TAG_WIDTH(TAG_WIDTH), .OP_TABLE_SIZE(OP_TABLE_SIZE), - .TX_LIMIT(TX_LIMIT) + .TX_LIMIT(TX_LIMIT), + .TX_FC_ENABLE(TX_FC_ENABLE) ) UUT ( .clk(clk), @@ -207,6 +213,8 @@ UUT ( .m_axis_rq_seq_num_valid_0(m_axis_rq_seq_num_valid_0), .m_axis_rq_seq_num_1(m_axis_rq_seq_num_1), .m_axis_rq_seq_num_valid_1(m_axis_rq_seq_num_valid_1), + .pcie_tx_fc_ph_av(pcie_tx_fc_ph_av), + .pcie_tx_fc_pd_av(pcie_tx_fc_pd_av), .s_axis_write_desc_pcie_addr(s_axis_write_desc_pcie_addr), .s_axis_write_desc_axi_addr(s_axis_write_desc_axi_addr), .s_axis_write_desc_len(s_axis_write_desc_len),