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Improve ip_eth_tx_64 module timing performance
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commit
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@ -132,7 +132,7 @@ reg flush_save;
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reg transfer_in_save;
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reg [31:0] hdr_sum_temp;
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reg [15:0] hdr_sum_reg = 0, hdr_sum_next;
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reg [31:0] hdr_sum_reg = 0, hdr_sum_next;
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reg [63:0] last_word_data_reg = 0;
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reg [7:0] last_word_keep_reg = 0;
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@ -281,13 +281,15 @@ always @* begin
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if (input_ip_hdr_ready & input_ip_hdr_valid) begin
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store_ip_hdr = 1;
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hdr_sum_temp = {4'd4, 4'd5, input_ip_dscp, input_ip_ecn} +
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hdr_sum_next = {4'd4, 4'd5, input_ip_dscp, input_ip_ecn} +
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input_ip_length +
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input_ip_identification +
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{input_ip_flags, input_ip_fragment_offset} +
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{input_ip_ttl, input_ip_protocol};
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hdr_sum_temp = hdr_sum_temp[15:0] + hdr_sum_temp[31:16];
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hdr_sum_next = hdr_sum_temp[15:0] + hdr_sum_temp[16];
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{input_ip_ttl, input_ip_protocol} +
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input_ip_source_ip[31:16] +
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input_ip_source_ip[15: 0] +
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input_ip_dest_ip[31:16] +
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input_ip_dest_ip[15: 0];
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input_ip_hdr_ready_next = 0;
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output_eth_hdr_valid_next = 1;
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if (output_eth_payload_tready_int) begin
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@ -327,17 +329,12 @@ always @* begin
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output_eth_payload_tkeep_int = 8'hff;
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end
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8'h08: begin
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hdr_sum_temp = hdr_sum_reg +
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ip_source_ip_reg[31:16] +
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ip_source_ip_reg[15: 0] +
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ip_dest_ip_reg[31:16] +
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ip_dest_ip_reg[15: 0];
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hdr_sum_temp = hdr_sum_temp[15:0] + hdr_sum_temp[31:16];
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hdr_sum_next = hdr_sum_temp[15:0] + hdr_sum_temp[16];
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hdr_sum_temp = hdr_sum_reg[15:0] + hdr_sum_reg[31:16];
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hdr_sum_temp = hdr_sum_temp[15:0] + hdr_sum_temp[16];
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output_eth_payload_tdata_int[ 7: 0] = ip_ttl_reg;
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output_eth_payload_tdata_int[15: 8] = ip_protocol_reg;
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output_eth_payload_tdata_int[23:16] = ~hdr_sum_next[15: 8];
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output_eth_payload_tdata_int[31:24] = ~hdr_sum_next[ 7: 0];
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output_eth_payload_tdata_int[23:16] = ~hdr_sum_temp[15: 8];
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output_eth_payload_tdata_int[31:24] = ~hdr_sum_temp[ 7: 0];
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output_eth_payload_tdata_int[39:32] = ip_source_ip_reg[31:24];
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output_eth_payload_tdata_int[47:40] = ip_source_ip_reg[23:16];
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output_eth_payload_tdata_int[55:48] = ip_source_ip_reg[15: 8];
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