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Add ADM-PCIE-9V3 mqnic_tdma design
This commit is contained in:
Alex Forencich
parent
a9179dc550
commit
5b15f03f69
25
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/Makefile
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25
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/Makefile
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@ -0,0 +1,25 @@
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# Targets
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TARGETS:=
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# Subdirectories
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SUBDIRS = fpga
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SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS))
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# Rules
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.PHONY: all
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all: $(SUBDIRS) $(TARGETS)
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.PHONY: $(SUBDIRS)
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$(SUBDIRS):
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cd $@ && $(MAKE)
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.PHONY: $(SUBDIRS_CLEAN)
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$(SUBDIRS_CLEAN):
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cd $(@:.clean=) && $(MAKE) clean
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.PHONY: clean
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clean: $(SUBDIRS_CLEAN)
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-rm -rf $(TARGETS)
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program:
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#djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit
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24
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/README.md
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24
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/README.md
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# Corundum mqnic_tdma for ADM-PCIE-9V3
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## Introduction
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This design targets the Alpha Data ADM-PCIE-9V3 FPGA board.
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FPGA: xcvu3p-ffvc1517-2-i
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PHY: 10G BASE-R PHY IP core and internal GTY transceiver
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## How to build
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Run make to build. Ensure that the Xilinx Vivado toolchain components are
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in PATH.
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Run make to build the driver. Ensure the headers for the running kernel are
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installed, otherwise the driver cannot be compiled.
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## How to test
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Run make program to program the ADM-PCIE-9V3 board with Vivado. Then load the
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driver with insmod mqnic.ko. Check dmesg for output from driver
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initialization.
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118
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/common/vivado.mk
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118
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/common/vivado.mk
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###################################################################
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#
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# Xilinx Vivado FPGA Makefile
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#
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# Copyright (c) 2016 Alex Forencich
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#
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###################################################################
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#
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# Parameters:
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# FPGA_TOP - Top module name
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# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
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# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
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# SYN_FILES - space-separated list of source files
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# INC_FILES - space-separated list of include files
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# XDC_FILES - space-separated list of timing constraint files
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# XCI_FILES - space-separated list of IP XCI files
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#
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# Example:
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#
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# FPGA_TOP = fpga
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# FPGA_FAMILY = VirtexUltrascale
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# FPGA_DEVICE = xcvu095-ffva2104-2-e
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# SYN_FILES = rtl/fpga.v
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# XDC_FILES = fpga.xdc
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# XCI_FILES = ip/pcspma.xci
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# include ../common/vivado.mk
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#
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###################################################################
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# phony targets
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.PHONY: clean fpga
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# prevent make from deleting intermediate files and reports
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.PRECIOUS: %.xpr %.bit %.mcs %.prm
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.SECONDARY:
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CONFIG ?= config.mk
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-include ../$(CONFIG)
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SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES))
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INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES))
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XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES))
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ifdef XDC_FILES
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XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES))
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else
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XDC_FILES_REL = $(FPGA_TOP).xdc
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endif
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###################################################################
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# Main Targets
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#
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# all: build everything
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# clean: remove output files and project files
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###################################################################
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all: fpga
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fpga: $(FPGA_TOP).bit
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tmpclean:
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-rm -rf *.log *.jou *.cache *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
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-rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
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clean: tmpclean
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-rm -rf *.bit program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
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distclean: clean
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-rm -rf rev
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###################################################################
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# Target implementations
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###################################################################
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# Vivado project file
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%.xpr: Makefile $(XCI_FILES_REL)
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rm -rf defines.v
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touch defines.v
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for x in $(DEFS); do echo '`define' $$x >> defines.v; done
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echo "create_project -force -part $(FPGA_PART) $*" > create_project.tcl
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echo "add_files -fileset sources_1 defines.v" >> create_project.tcl
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for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done
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for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done
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for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done
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echo "exit" >> create_project.tcl
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vivado -nojournal -nolog -mode batch -source create_project.tcl
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# synthesis run
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%.runs/synth_1/%.dcp: %.xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL)
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echo "open_project $*.xpr" > run_synth.tcl
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echo "reset_run synth_1" >> run_synth.tcl
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echo "launch_runs synth_1" >> run_synth.tcl
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echo "wait_on_run synth_1" >> run_synth.tcl
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echo "exit" >> run_synth.tcl
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vivado -nojournal -nolog -mode batch -source run_synth.tcl
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# implementation run
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%.runs/impl_1/%_routed.dcp: %.runs/synth_1/%.dcp
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echo "open_project $*.xpr" > run_impl.tcl
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echo "reset_run impl_1" >> run_impl.tcl
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echo "launch_runs impl_1" >> run_impl.tcl
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echo "wait_on_run impl_1" >> run_impl.tcl
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echo "exit" >> run_impl.tcl
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vivado -nojournal -nolog -mode batch -source run_impl.tcl
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# bit file
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%.bit: %.runs/impl_1/%_routed.dcp
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echo "open_project $*.xpr" > generate_bit.tcl
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echo "open_run impl_1" >> generate_bit.tcl
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echo "write_bitstream -force $*.bit" >> generate_bit.tcl
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echo "exit" >> generate_bit.tcl
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vivado -nojournal -nolog -mode batch -source generate_bit.tcl
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mkdir -p rev
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EXT=bit; COUNT=100; \
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while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
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do COUNT=$$((COUNT+1)); done; \
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cp $@ rev/$*_rev$$COUNT.$$EXT; \
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echo "Output: rev/$*_rev$$COUNT.$$EXT";
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178
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/fpga.xdc
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178
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/fpga.xdc
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@ -0,0 +1,178 @@
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# XDC constraints for the ADM-PCIE-9V3
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# part: xcvu3p-ffvc1517-2-i
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# General configuration
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set_property CFGBVS GND [current_design]
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set_property CONFIG_VOLTAGE 1.8 [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
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set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
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set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
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set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design]
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set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
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set_property BITSTREAM.CONFIG.UNUSEDPIN {Pullnone} [current_design]
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set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
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# 300 MHz system clock
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set_property -dict {LOC AP26 IOSTANDARD LVDS} [get_ports clk_300mhz_p]
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set_property -dict {LOC AP27 IOSTANDARD LVDS} [get_ports clk_300mhz_n]
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create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p]
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# LEDs
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set_property -dict {LOC AT27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {user_led_g[0]}]
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set_property -dict {LOC AU27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {user_led_g[1]}]
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set_property -dict {LOC AU23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {user_led_r}]
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set_property -dict {LOC AH24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {front_led[0]}]
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set_property -dict {LOC AJ23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {front_led[1]}]
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# Switches
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set_property -dict {LOC AV27 IOSTANDARD LVCMOS18} [get_ports {user_sw[0]}]
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set_property -dict {LOC AW27 IOSTANDARD LVCMOS18} [get_ports {user_sw[1]}]
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# GPIO
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#set_property -dict {LOC G30 IOSTANDARD LVCMOS18} [get_ports gpio_p[0]]
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#set_property -dict {LOC F30 IOSTANDARD LVCMOS18} [get_ports gpio_n[0]]
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#set_property -dict {LOC J31 IOSTANDARD LVCMOS18} [get_ports gpio_p[1]]
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#set_property -dict {LOC H31 IOSTANDARD LVCMOS18} [get_ports gpio_n[1]]
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# QSFP28 Interfaces
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set_property -dict {LOC G38 } [get_ports qsfp_0_rx_0_p] ;# MGTYRXN0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4
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#set_property -dict {LOC G39 } [get_ports qsfp_0_rx_0_n] ;# MGTYRXP0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4
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set_property -dict {LOC E38 } [get_ports qsfp_0_rx_1_p] ;# MGTYRXN1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4
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#set_property -dict {LOC E39 } [get_ports qsfp_0_rx_1_n] ;# MGTYRXP1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4
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set_property -dict {LOC C38 } [get_ports qsfp_0_rx_2_p] ;# MGTYRXN2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4
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#set_property -dict {LOC C39 } [get_ports qsfp_0_rx_2_n] ;# MGTYRXP2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4
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set_property -dict {LOC B36 } [get_ports qsfp_0_rx_3_p] ;# MGTYRXN3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4
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#set_property -dict {LOC B37 } [get_ports qsfp_0_rx_3_n] ;# MGTYRXP3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4
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set_property -dict {LOC F35 } [get_ports qsfp_0_tx_0_p] ;# MGTYTXN0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4
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#set_property -dict {LOC F36 } [get_ports qsfp_0_tx_0_n] ;# MGTYTXP0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4
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set_property -dict {LOC D35 } [get_ports qsfp_0_tx_1_p] ;# MGTYTXN1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4
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#set_property -dict {LOC D36 } [get_ports qsfp_0_tx_1_n] ;# MGTYTXP1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4
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set_property -dict {LOC C33 } [get_ports qsfp_0_tx_2_p] ;# MGTYTXN2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4
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#set_property -dict {LOC C34 } [get_ports qsfp_0_tx_2_n] ;# MGTYTXP2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4
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set_property -dict {LOC A33 } [get_ports qsfp_0_tx_3_p] ;# MGTYTXN3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4
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#set_property -dict {LOC A34 } [get_ports qsfp_0_tx_3_n] ;# MGTYTXP3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4
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set_property -dict {LOC N33 } [get_ports qsfp_0_mgt_refclk_p] ;# MGTREFCLK0P_128 from ?
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#set_property -dict {LOC N34 } [get_ports qsfp_0_mgt_refclk_n] ;# MGTREFCLK0N_128 from ?
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set_property -dict {LOC F29 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_0_modprs_l]
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set_property -dict {LOC D31 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports qsfp_0_sel_l]
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# 161.1328125 MHz MGT reference clock
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create_clock -period 6.206 -name qsfp_0_mgt_refclk [get_ports qsfp_0_mgt_refclk_p]
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set_property -dict {LOC R38 } [get_ports qsfp_1_rx_0_p] ;# MGTYRXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
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#set_property -dict {LOC R39 } [get_ports qsfp_1_rx_0_n] ;# MGTYRXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC N38 } [get_ports qsfp_1_rx_1_p] ;# MGTYRXN1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
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#set_property -dict {LOC N39 } [get_ports qsfp_1_rx_1_n] ;# MGTYRXP1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC L38 } [get_ports qsfp_1_rx_2_p] ;# MGTYRXN2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
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#set_property -dict {LOC L39 } [get_ports qsfp_1_rx_2_n] ;# MGTYRXP2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC J38 } [get_ports qsfp_1_rx_3_p] ;# MGTYRXN3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
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#set_property -dict {LOC J39 } [get_ports qsfp_1_rx_3_n] ;# MGTYRXP3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC P35 } [get_ports qsfp_1_tx_0_p] ;# MGTYTXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
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#set_property -dict {LOC P36 } [get_ports qsfp_1_tx_0_n] ;# MGTYTXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC M35 } [get_ports qsfp_1_tx_1_p] ;# MGTYTXN1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
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#set_property -dict {LOC M36 } [get_ports qsfp_1_tx_1_n] ;# MGTYTXP1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC K35 } [get_ports qsfp_1_tx_2_p] ;# MGTYTXN2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
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#set_property -dict {LOC K36 } [get_ports qsfp_1_tx_2_n] ;# MGTYTXP2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC H35 } [get_ports qsfp_1_tx_3_p] ;# MGTYTXN3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
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#set_property -dict {LOC H36 } [get_ports qsfp_1_tx_3_n] ;# MGTYTXP3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC U33 } [get_ports qsfp_1_mgt_refclk_p] ;# MGTREFCLK0P_127 from ?
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#set_property -dict {LOC U34 } [get_ports qsfp_1_mgt_refclk_n] ;# MGTREFCLK0N_127 from ?
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set_property -dict {LOC F33 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_1_modprs_l]
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set_property -dict {LOC D30 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports qsfp_1_sel_l]
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# 161.1328125 MHz MGT reference clock
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create_clock -period 6.206 -name qsfp_1_mgt_refclk [get_ports qsfp_1_mgt_refclk_p]
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set_property -dict {LOC B29 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports qsfp_reset_l]
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set_property -dict {LOC C29 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_int_l]
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set_property -dict {LOC A28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports qsfp_i2c_scl]
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set_property -dict {LOC A29 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports qsfp_i2c_sda]
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# I2C interface
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set_property -dict {LOC AT25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_i2c_scl]
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set_property -dict {LOC AT26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_i2c_sda]
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set_property -dict {LOC AP23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_wp]
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# PCIe Interface
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set_property -dict {LOC J2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE3_CHANNEL_X0Y7 / GTYE3_COMMON_X0Y1
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#set_property -dict {LOC J1 } [get_ports {pcie_rx_n[0]}] ;# MGTYTXP3_227 GTYE3_CHANNEL_X0Y7 / GTYE3_COMMON_X0Y1
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set_property -dict {LOC H5 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXN3_227 GTYE3_CHANNEL_X0Y7 / GTYE3_COMMON_X0Y1
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#set_property -dict {LOC H4 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXP3_227 GTYE3_CHANNEL_X0Y7 / GTYE3_COMMON_X0Y1
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set_property -dict {LOC L2 } [get_ports {pcie_rx_p[1]}] ;# MGTYTXN2_227 GTYE3_CHANNEL_X0Y6 / GTYE3_COMMON_X0Y1
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#set_property -dict {LOC L1 } [get_ports {pcie_rx_n[1]}] ;# MGTYTXP2_227 GTYE3_CHANNEL_X0Y6 / GTYE3_COMMON_X0Y1
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set_property -dict {LOC K5 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXN2_227 GTYE3_CHANNEL_X0Y6 / GTYE3_COMMON_X0Y1
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#set_property -dict {LOC K4 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXP2_227 GTYE3_CHANNEL_X0Y6 / GTYE3_COMMON_X0Y1
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set_property -dict {LOC N2 } [get_ports {pcie_rx_p[2]}] ;# MGTYTXN1_227 GTYE3_CHANNEL_X0Y5 / GTYE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC N1 } [get_ports {pcie_rx_n[2]}] ;# MGTYTXP1_227 GTYE3_CHANNEL_X0Y5 / GTYE3_COMMON_X0Y1
|
||||
set_property -dict {LOC M5 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXN1_227 GTYE3_CHANNEL_X0Y5 / GTYE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC M4 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXP1_227 GTYE3_CHANNEL_X0Y5 / GTYE3_COMMON_X0Y1
|
||||
set_property -dict {LOC R2 } [get_ports {pcie_rx_p[3]}] ;# MGTYTXN0_227 GTYE3_CHANNEL_X0Y4 / GTYE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC R1 } [get_ports {pcie_rx_n[3]}] ;# MGTYTXP0_227 GTYE3_CHANNEL_X0Y4 / GTYE3_COMMON_X0Y1
|
||||
set_property -dict {LOC P5 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXN0_227 GTYE3_CHANNEL_X0Y4 / GTYE3_COMMON_X0Y1
|
||||
#set_property -dict {LOC P4 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXP0_227 GTYE3_CHANNEL_X0Y4 / GTYE3_COMMON_X0Y1
|
||||
set_property -dict {LOC U2 } [get_ports {pcie_rx_p[4]}] ;# MGTYTXN3_226 GTYE3_CHANNEL_X0Y3 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC U1 } [get_ports {pcie_rx_n[4]}] ;# MGTYTXP3_226 GTYE3_CHANNEL_X0Y3 / GTYE3_COMMON_X0Y0
|
||||
set_property -dict {LOC T5 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXN3_226 GTYE3_CHANNEL_X0Y3 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC T4 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXP3_226 GTYE3_CHANNEL_X0Y3 / GTYE3_COMMON_X0Y0
|
||||
set_property -dict {LOC W2 } [get_ports {pcie_rx_p[5]}] ;# MGTYTXN2_226 GTYE3_CHANNEL_X0Y2 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC W1 } [get_ports {pcie_rx_n[5]}] ;# MGTYTXP2_226 GTYE3_CHANNEL_X0Y2 / GTYE3_COMMON_X0Y0
|
||||
set_property -dict {LOC V5 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXN2_226 GTYE3_CHANNEL_X0Y2 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC V4 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXP2_226 GTYE3_CHANNEL_X0Y2 / GTYE3_COMMON_X0Y0
|
||||
set_property -dict {LOC AA2 } [get_ports {pcie_rx_p[6]}] ;# MGTYTXN1_226 GTYE3_CHANNEL_X0Y1 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AA1 } [get_ports {pcie_rx_n[6]}] ;# MGTYTXP1_226 GTYE3_CHANNEL_X0Y1 / GTYE3_COMMON_X0Y0
|
||||
set_property -dict {LOC AB5 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXN1_226 GTYE3_CHANNEL_X0Y1 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AB4 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXP1_226 GTYE3_CHANNEL_X0Y1 / GTYE3_COMMON_X0Y0
|
||||
set_property -dict {LOC AC2 } [get_ports {pcie_rx_p[7]}] ;# MGTYTXN0_226 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AC1 } [get_ports {pcie_rx_n[7]}] ;# MGTYTXP0_226 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
set_property -dict {LOC AD5 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXN0_226 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AD4 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXP0_226 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AE2 } [get_ports {pcie_rx_p[8]}] ;# MGTYTXN3_225 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AE1 } [get_ports {pcie_rx_n[8]}] ;# MGTYTXP3_225 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AF5 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXN3_225 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AF4 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXP3_225 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AG2 } [get_ports {pcie_rx_p[9]}] ;# MGTYTXN2_225 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AG1 } [get_ports {pcie_rx_n[9]}] ;# MGTYTXP2_225 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AH5 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXN2_225 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AH4 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXP2_225 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AJ2 } [get_ports {pcie_rx_p[10]}] ;# MGTYTXN1_225 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AJ1 } [get_ports {pcie_rx_n[10]}] ;# MGTYTXP1_225 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AK5 } [get_ports {pcie_tx_p[10]}] ;# MGTYTXN1_225 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AK4 } [get_ports {pcie_tx_n[10]}] ;# MGTYTXP1_225 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AL2 } [get_ports {pcie_rx_p[11]}] ;# MGTYTXN0_225 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AL1 } [get_ports {pcie_rx_n[11]}] ;# MGTYTXP0_225 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AM5 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXN0_225 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AM4 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXP0_225 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AN2 } [get_ports {pcie_rx_p[12]}] ;# MGTYTXN3_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AN1 } [get_ports {pcie_rx_n[12]}] ;# MGTYTXP3_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AP5 } [get_ports {pcie_tx_p[12]}] ;# MGTYTXN3_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AP4 } [get_ports {pcie_tx_n[12]}] ;# MGTYTXP3_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AR2 } [get_ports {pcie_rx_p[13]}] ;# MGTYTXN2_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AR1 } [get_ports {pcie_rx_n[13]}] ;# MGTYTXP2_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AT5 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXN2_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AT4 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXP2_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AU2 } [get_ports {pcie_rx_p[14]}] ;# MGTYTXN1_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AU1 } [get_ports {pcie_rx_n[14]}] ;# MGTYTXP1_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AU7 } [get_ports {pcie_tx_p[14]}] ;# MGTYTXN1_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AU6 } [get_ports {pcie_tx_n[14]}] ;# MGTYTXP1_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AV4 } [get_ports {pcie_rx_p[15]}] ;# MGTYTXN0_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AV3 } [get_ports {pcie_rx_n[15]}] ;# MGTYTXP0_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AW7 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXN0_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
#set_property -dict {LOC AW6 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXP0_224 GTYE3_CHANNEL_X0Y0 / GTYE3_COMMON_X0Y0
|
||||
set_property -dict {LOC AA7 } [get_ports pcie_refclk_1_p] ;# MGTREFCLK0P_226
|
||||
#set_property -dict {LOC AA6 } [get_ports pcie_refclk_1_n] ;# MGTREFCLK0N_226
|
||||
#set_property -dict {LOC AJ7 } [get_ports pcie_refclk_2_p] ;# MGTREFCLK0P_224
|
||||
#set_property -dict {LOC AJ6 } [get_ports pcie_refclk_2_n] ;# MGTREFCLK0N_224
|
||||
set_property -dict {LOC AJ31 IOSTANDARD LVCMOS18 PULLUP true} [get_ports perst_0]
|
||||
#set_property -dict {LOC AH29 IOSTANDARD LVCMOS18 PULLUP true} [get_ports perst_1]
|
||||
|
||||
# 100 MHz MGT reference clock
|
||||
create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_1_p]
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_2 [get_ports pcie_refclk_2_p]
|
||||
|
||||
# Flash
|
||||
#set_property -dict {LOC AF30 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {qspi1_dq[0]}]
|
||||
#set_property -dict {LOC AG30 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {qspi1_dq[1]}]
|
||||
#set_property -dict {LOC AF28 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {qspi1_dq[2]}]
|
||||
#set_property -dict {LOC AG28 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {qspi1_dq[3]}]
|
||||
#set_property -dict {LOC AV30 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {qspi1_cs}]
|
||||
|
||||
138
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/fpga/Makefile
Normal file
138
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/fpga/Makefile
Normal file
@ -0,0 +1,138 @@
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcvu3p-ffvc1517-2-i
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = rtl/fpga.v
|
||||
SYN_FILES += rtl/fpga_core.v
|
||||
SYN_FILES += rtl/debounce_switch.v
|
||||
SYN_FILES += rtl/sync_reset.v
|
||||
SYN_FILES += rtl/sync_signal.v
|
||||
SYN_FILES += rtl/common/interface.v
|
||||
SYN_FILES += rtl/common/port.v
|
||||
SYN_FILES += rtl/common/queue_manager.v
|
||||
SYN_FILES += rtl/common/cpl_queue_manager.v
|
||||
SYN_FILES += rtl/common/eth_interface.v
|
||||
SYN_FILES += rtl/common/event_queue.v
|
||||
SYN_FILES += rtl/common/event_mux.v
|
||||
SYN_FILES += rtl/common/tx_scheduler_tdma_rr.v
|
||||
SYN_FILES += rtl/common/tdma_scheduler.v
|
||||
SYN_FILES += rtl/common/tdma_ber.v
|
||||
SYN_FILES += rtl/common/tdma_ber_ch.v
|
||||
SYN_FILES += rtl/common/tx_engine.v
|
||||
SYN_FILES += rtl/common/rx_engine.v
|
||||
SYN_FILES += rtl/common/rx_checksum.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
|
||||
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
|
||||
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
|
||||
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
|
||||
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
|
||||
SYN_FILES += lib/eth/rtl/lfsr.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_clock.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_perout.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_ts_extract.v
|
||||
SYN_FILES += lib/axi/rtl/axi_crossbar.v
|
||||
SYN_FILES += lib/axi/rtl/axi_crossbar_addr.v
|
||||
SYN_FILES += lib/axi/rtl/axi_crossbar_rd.v
|
||||
SYN_FILES += lib/axi/rtl/axi_crossbar_wr.v
|
||||
SYN_FILES += lib/axi/rtl/axi_dma.v
|
||||
SYN_FILES += lib/axi/rtl/axi_dma_rd.v
|
||||
SYN_FILES += lib/axi/rtl/axi_dma_wr.v
|
||||
SYN_FILES += lib/axi/rtl/axi_interconnect.v
|
||||
SYN_FILES += lib/axi/rtl/axi_ram.v
|
||||
SYN_FILES += lib/axi/rtl/axi_ram_rd_if.v
|
||||
SYN_FILES += lib/axi/rtl/axi_ram_wr_if.v
|
||||
SYN_FILES += lib/axi/rtl/axi_register_rd.v
|
||||
SYN_FILES += lib/axi/rtl/axi_register_wr.v
|
||||
SYN_FILES += lib/axi/rtl/axil_interconnect.v
|
||||
SYN_FILES += lib/axi/rtl/arbiter.v
|
||||
SYN_FILES += lib/axi/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/axis/rtl/axis_adapter.v
|
||||
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
|
||||
SYN_FILES += lib/axis/rtl/axis_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_register.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_axi_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_axi_master_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_axi_master_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_axis_cq_demux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tag_manager.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axi_dma_desc_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = fpga.xdc
|
||||
XDC_FILES += lib/axis/syn/axis_async_fifo.tcl
|
||||
XDC_FILES += lib/eth/syn/ptp_clock_cdc.tcl
|
||||
XDC_FILES += ../../../common/syn/tdma_ber_ch.tcl
|
||||
|
||||
# IP
|
||||
XCI_FILES = ip/pcie4_uscale_plus_0.xci
|
||||
XCI_FILES += ip/gtwizard_ultrascale_0.xci
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(FPGA_TOP).bit
|
||||
echo "open_hw" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
%_primary.mcs %_secondary.mcs %_primary.prm %_secondary.prm: %.bit
|
||||
echo "write_cfgmem -force -format mcs -size 64 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(FPGA_TOP)_primary.mcs $(FPGA_TOP)_secondary.mcs $(FPGA_TOP)_primary.prm $(FPGA_TOP)_secondary.prm
|
||||
echo "open_hw" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu256-spi-x1_x2_x4_x8}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)_primary.mcs\" \"$(FPGA_TOP)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)_primary.prm\" \"$(FPGA_TOP)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
|
||||
1408
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/ip/gtwizard_ultrascale_0.xci
Normal file
1408
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/ip/gtwizard_ultrascale_0.xci
Normal file
File diff suppressed because it is too large
Load Diff
1320
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/ip/pcie4_uscale_plus_0.xci
Normal file
1320
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/ip/pcie4_uscale_plus_0.xci
Normal file
File diff suppressed because it is too large
Load Diff
1
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/lib
Symbolic link
1
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/lib
Symbolic link
@ -0,0 +1 @@
|
||||
../../../lib/
|
||||
1
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/common
Symbolic link
1
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/common
Symbolic link
@ -0,0 +1 @@
|
||||
../../../../common/rtl/
|
||||
89
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/debounce_switch.v
Normal file
89
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/debounce_switch.v
Normal file
@ -0,0 +1,89 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog-2001
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
|
||||
/*
|
||||
* Synchronizes switch and button inputs with a slow sampled shift register
|
||||
*/
|
||||
module debounce_switch #(
|
||||
parameter WIDTH=1, // width of the input and output signals
|
||||
parameter N=3, // length of shift register
|
||||
parameter RATE=125000 // clock division factor
|
||||
)(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
input wire [WIDTH-1:0] in,
|
||||
output wire [WIDTH-1:0] out
|
||||
);
|
||||
|
||||
reg [23:0] cnt_reg = 24'd0;
|
||||
|
||||
reg [N-1:0] debounce_reg[WIDTH-1:0];
|
||||
|
||||
reg [WIDTH-1:0] state;
|
||||
|
||||
/*
|
||||
* The synchronized output is the state register
|
||||
*/
|
||||
assign out = state;
|
||||
|
||||
integer k;
|
||||
|
||||
always @(posedge clk or posedge rst) begin
|
||||
if (rst) begin
|
||||
cnt_reg <= 0;
|
||||
state <= 0;
|
||||
|
||||
for (k = 0; k < WIDTH; k = k + 1) begin
|
||||
debounce_reg[k] <= 0;
|
||||
end
|
||||
end else begin
|
||||
if (cnt_reg < RATE) begin
|
||||
cnt_reg <= cnt_reg + 24'd1;
|
||||
end else begin
|
||||
cnt_reg <= 24'd0;
|
||||
end
|
||||
|
||||
if (cnt_reg == 24'd0) begin
|
||||
for (k = 0; k < WIDTH; k = k + 1) begin
|
||||
debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]};
|
||||
end
|
||||
end
|
||||
|
||||
for (k = 0; k < WIDTH; k = k + 1) begin
|
||||
if (|debounce_reg[k] == 0) begin
|
||||
state[k] <= 0;
|
||||
end else if (&debounce_reg[k] == 1) begin
|
||||
state[k] <= 1;
|
||||
end else begin
|
||||
state[k] <= state[k];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
1387
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v
Normal file
1387
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v
Normal file
File diff suppressed because it is too large
Load Diff
2091
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v
Normal file
2091
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v
Normal file
File diff suppressed because it is too large
Load Diff
52
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/sync_reset.v
Normal file
52
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/sync_reset.v
Normal file
@ -0,0 +1,52 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog-2001
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
|
||||
/*
|
||||
* Synchronizes an active-high asynchronous reset signal to a given clock by
|
||||
* using a pipeline of N registers.
|
||||
*/
|
||||
module sync_reset #(
|
||||
parameter N=2 // depth of synchronizer
|
||||
)(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
output wire sync_reset_out
|
||||
);
|
||||
|
||||
reg [N-1:0] sync_reg = {N{1'b1}};
|
||||
|
||||
assign sync_reset_out = sync_reg[N-1];
|
||||
|
||||
always @(posedge clk or posedge rst) begin
|
||||
if (rst)
|
||||
sync_reg <= {N{1'b1}};
|
||||
else
|
||||
sync_reg <= {sync_reg[N-2:0], 1'b0};
|
||||
end
|
||||
|
||||
endmodule
|
||||
58
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/sync_signal.v
Normal file
58
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/sync_signal.v
Normal file
@ -0,0 +1,58 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog-2001
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
|
||||
/*
|
||||
* Synchronizes an asyncronous signal to a given clock by using a pipeline of
|
||||
* two registers.
|
||||
*/
|
||||
module sync_signal #(
|
||||
parameter WIDTH=1, // width of the input and output signals
|
||||
parameter N=2 // depth of synchronizer
|
||||
)(
|
||||
input wire clk,
|
||||
input wire [WIDTH-1:0] in,
|
||||
output wire [WIDTH-1:0] out
|
||||
);
|
||||
|
||||
reg [WIDTH-1:0] sync_reg[N-1:0];
|
||||
|
||||
/*
|
||||
* The synchronized output is the last register in the pipeline.
|
||||
*/
|
||||
assign out = sync_reg[N-1];
|
||||
|
||||
integer k;
|
||||
|
||||
always @(posedge clk) begin
|
||||
sync_reg[0] <= in;
|
||||
for (k = 1; k < N; k = k + 1) begin
|
||||
sync_reg[k] <= sync_reg[k-1];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
1
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/axis_ep.py
Symbolic link
1
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/axis_ep.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/eth/tb/axis_ep.py
|
||||
1
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/mqnic.py
Symbolic link
1
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/mqnic.py
Symbolic link
@ -0,0 +1 @@
|
||||
../../../../common/tb/mqnic.py
|
||||
1
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/pcie.py
Symbolic link
1
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/pcie.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/pcie/tb/pcie.py
|
||||
1
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/pcie_us.py
Symbolic link
1
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/pcie_us.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/pcie/tb/pcie_us.py
|
||||
1
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/pcie_usp.py
Symbolic link
1
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/pcie_usp.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/pcie/tb/pcie_usp.py
|
||||
1026
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py
Executable file
1026
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.py
Executable file
File diff suppressed because it is too large
Load Diff
505
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.v
Normal file
505
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/test_fpga_core.v
Normal file
@ -0,0 +1,505 @@
|
||||
/*
|
||||
|
||||
Copyright 2019, The Regents of the University of California.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
|
||||
The views and conclusions contained in the software and documentation are those
|
||||
of the authors and should not be interpreted as representing official policies,
|
||||
either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* Testbench for fpga_core
|
||||
*/
|
||||
module test_fpga_core;
|
||||
|
||||
// Parameters
|
||||
|
||||
// Inputs
|
||||
reg clk = 0;
|
||||
reg rst = 0;
|
||||
reg [7:0] current_test = 0;
|
||||
|
||||
reg clk_156mhz = 0;
|
||||
reg rst_156mhz = 0;
|
||||
reg clk_250mhz = 0;
|
||||
reg rst_250mhz = 0;
|
||||
reg [1:0] user_sw = 0;
|
||||
reg m_axis_rq_tready = 0;
|
||||
reg [255:0] s_axis_rc_tdata = 0;
|
||||
reg [7:0] s_axis_rc_tkeep = 0;
|
||||
reg s_axis_rc_tlast = 0;
|
||||
reg [74:0] s_axis_rc_tuser = 0;
|
||||
reg s_axis_rc_tvalid = 0;
|
||||
reg [255:0] s_axis_cq_tdata = 0;
|
||||
reg [7:0] s_axis_cq_tkeep = 0;
|
||||
reg s_axis_cq_tlast = 0;
|
||||
reg [84:0] s_axis_cq_tuser = 0;
|
||||
reg s_axis_cq_tvalid = 0;
|
||||
reg m_axis_cc_tready = 0;
|
||||
reg [3:0] pcie_tfc_nph_av = 0;
|
||||
reg [3:0] pcie_tfc_npd_av = 0;
|
||||
reg [2:0] cfg_max_payload = 0;
|
||||
reg [2:0] cfg_max_read_req = 0;
|
||||
reg [31:0] cfg_mgmt_read_data = 0;
|
||||
reg cfg_mgmt_read_write_done = 0;
|
||||
reg [3:0] cfg_interrupt_msi_enable = 0;
|
||||
reg [11:0] cfg_interrupt_msi_mmenable = 0;
|
||||
reg cfg_interrupt_msi_mask_update = 0;
|
||||
reg [31:0] cfg_interrupt_msi_data = 0;
|
||||
reg cfg_interrupt_msi_sent = 0;
|
||||
reg cfg_interrupt_msi_fail = 0;
|
||||
reg qsfp_0_tx_clk_0 = 0;
|
||||
reg qsfp_0_tx_rst_0 = 0;
|
||||
reg qsfp_0_rx_clk_0 = 0;
|
||||
reg qsfp_0_rx_rst_0 = 0;
|
||||
reg [63:0] qsfp_0_rxd_0 = 0;
|
||||
reg [7:0] qsfp_0_rxc_0 = 0;
|
||||
reg qsfp_0_tx_clk_1 = 0;
|
||||
reg qsfp_0_tx_rst_1 = 0;
|
||||
reg qsfp_0_rx_clk_1 = 0;
|
||||
reg qsfp_0_rx_rst_1 = 0;
|
||||
reg [63:0] qsfp_0_rxd_1 = 0;
|
||||
reg [7:0] qsfp_0_rxc_1 = 0;
|
||||
reg qsfp_0_tx_clk_2 = 0;
|
||||
reg qsfp_0_tx_rst_2 = 0;
|
||||
reg qsfp_0_rx_clk_2 = 0;
|
||||
reg qsfp_0_rx_rst_2 = 0;
|
||||
reg [63:0] qsfp_0_rxd_2 = 0;
|
||||
reg [7:0] qsfp_0_rxc_2 = 0;
|
||||
reg qsfp_0_tx_clk_3 = 0;
|
||||
reg qsfp_0_tx_rst_3 = 0;
|
||||
reg qsfp_0_rx_clk_3 = 0;
|
||||
reg qsfp_0_rx_rst_3 = 0;
|
||||
reg [63:0] qsfp_0_rxd_3 = 0;
|
||||
reg [7:0] qsfp_0_rxc_3 = 0;
|
||||
reg qsfp_0_modprs_l = 0;
|
||||
reg qsfp_1_tx_clk_0 = 0;
|
||||
reg qsfp_1_tx_rst_0 = 0;
|
||||
reg qsfp_1_rx_clk_0 = 0;
|
||||
reg qsfp_1_rx_rst_0 = 0;
|
||||
reg [63:0] qsfp_1_rxd_0 = 0;
|
||||
reg [7:0] qsfp_1_rxc_0 = 0;
|
||||
reg qsfp_1_tx_clk_1 = 0;
|
||||
reg qsfp_1_tx_rst_1 = 0;
|
||||
reg qsfp_1_rx_clk_1 = 0;
|
||||
reg qsfp_1_rx_rst_1 = 0;
|
||||
reg [63:0] qsfp_1_rxd_1 = 0;
|
||||
reg [7:0] qsfp_1_rxc_1 = 0;
|
||||
reg qsfp_1_tx_clk_2 = 0;
|
||||
reg qsfp_1_tx_rst_2 = 0;
|
||||
reg qsfp_1_rx_clk_2 = 0;
|
||||
reg qsfp_1_rx_rst_2 = 0;
|
||||
reg [63:0] qsfp_1_rxd_2 = 0;
|
||||
reg [7:0] qsfp_1_rxc_2 = 0;
|
||||
reg qsfp_1_tx_clk_3 = 0;
|
||||
reg qsfp_1_tx_rst_3 = 0;
|
||||
reg qsfp_1_rx_clk_3 = 0;
|
||||
reg qsfp_1_rx_rst_3 = 0;
|
||||
reg [63:0] qsfp_1_rxd_3 = 0;
|
||||
reg [7:0] qsfp_1_rxc_3 = 0;
|
||||
reg qsfp_1_modprs_l = 0;
|
||||
reg qsfp_int_l = 0;
|
||||
reg qsfp_i2c_scl_i = 1;
|
||||
reg qsfp_i2c_sda_i = 1;
|
||||
reg eeprom_i2c_scl_i = 1;
|
||||
reg eeprom_i2c_sda_i = 1;
|
||||
|
||||
// Outputs
|
||||
wire [1:0] user_led_g;
|
||||
wire user_led_r;
|
||||
wire [1:0] front_led;
|
||||
wire [255:0] m_axis_rq_tdata;
|
||||
wire [7:0] m_axis_rq_tkeep;
|
||||
wire m_axis_rq_tlast;
|
||||
wire [59:0] m_axis_rq_tuser;
|
||||
wire m_axis_rq_tvalid;
|
||||
wire s_axis_rc_tready;
|
||||
wire s_axis_cq_tready;
|
||||
wire [255:0] m_axis_cc_tdata;
|
||||
wire [7:0] m_axis_cc_tkeep;
|
||||
wire m_axis_cc_tlast;
|
||||
wire [32:0] m_axis_cc_tuser;
|
||||
wire m_axis_cc_tvalid;
|
||||
wire [9:0] cfg_mgmt_addr;
|
||||
wire [7:0] cfg_mgmt_function_number;
|
||||
wire cfg_mgmt_write;
|
||||
wire [31:0] cfg_mgmt_write_data;
|
||||
wire [3:0] cfg_mgmt_byte_enable;
|
||||
wire cfg_mgmt_read;
|
||||
wire [3:0] cfg_interrupt_msi_select;
|
||||
wire [31:0] cfg_interrupt_msi_int;
|
||||
wire [31:0] cfg_interrupt_msi_pending_status;
|
||||
wire cfg_interrupt_msi_pending_status_data_enable;
|
||||
wire [3:0] cfg_interrupt_msi_pending_status_function_num;
|
||||
wire [2:0] cfg_interrupt_msi_attr;
|
||||
wire cfg_interrupt_msi_tph_present;
|
||||
wire [1:0] cfg_interrupt_msi_tph_type;
|
||||
wire [8:0] cfg_interrupt_msi_tph_st_tag;
|
||||
wire [3:0] cfg_interrupt_msi_function_number;
|
||||
wire status_error_cor;
|
||||
wire status_error_uncor;
|
||||
wire [63:0] qsfp_0_txd_0;
|
||||
wire [7:0] qsfp_0_txc_0;
|
||||
wire [63:0] qsfp_0_txd_1;
|
||||
wire [7:0] qsfp_0_txc_1;
|
||||
wire [63:0] qsfp_0_txd_2;
|
||||
wire [7:0] qsfp_0_txc_2;
|
||||
wire [63:0] qsfp_0_txd_3;
|
||||
wire [7:0] qsfp_0_txc_3;
|
||||
wire qsfp_0_sel_l;
|
||||
wire [63:0] qsfp_1_txd_0;
|
||||
wire [7:0] qsfp_1_txc_0;
|
||||
wire [63:0] qsfp_1_txd_1;
|
||||
wire [7:0] qsfp_1_txc_1;
|
||||
wire [63:0] qsfp_1_txd_2;
|
||||
wire [7:0] qsfp_1_txc_2;
|
||||
wire [63:0] qsfp_1_txd_3;
|
||||
wire [7:0] qsfp_1_txc_3;
|
||||
wire qsfp_1_sel_l;
|
||||
wire qsfp_reset_l;
|
||||
wire qsfp_i2c_scl_o;
|
||||
wire qsfp_i2c_scl_t;
|
||||
wire qsfp_i2c_sda_o;
|
||||
wire qsfp_i2c_sda_t;
|
||||
wire eeprom_i2c_scl_o;
|
||||
wire eeprom_i2c_scl_t;
|
||||
wire eeprom_i2c_sda_o;
|
||||
wire eeprom_i2c_sda_t;
|
||||
wire eeprom_wp;
|
||||
|
||||
initial begin
|
||||
// myhdl integration
|
||||
$from_myhdl(
|
||||
clk_156mhz,
|
||||
rst_156mhz,
|
||||
clk_250mhz,
|
||||
rst_250mhz,
|
||||
current_test,
|
||||
user_sw,
|
||||
m_axis_rq_tready,
|
||||
s_axis_rc_tdata,
|
||||
s_axis_rc_tkeep,
|
||||
s_axis_rc_tlast,
|
||||
s_axis_rc_tuser,
|
||||
s_axis_rc_tvalid,
|
||||
s_axis_cq_tdata,
|
||||
s_axis_cq_tkeep,
|
||||
s_axis_cq_tlast,
|
||||
s_axis_cq_tuser,
|
||||
s_axis_cq_tvalid,
|
||||
m_axis_cc_tready,
|
||||
pcie_tfc_nph_av,
|
||||
pcie_tfc_npd_av,
|
||||
cfg_max_payload,
|
||||
cfg_max_read_req,
|
||||
cfg_mgmt_read_data,
|
||||
cfg_mgmt_read_write_done,
|
||||
cfg_interrupt_msi_enable,
|
||||
cfg_interrupt_msi_mmenable,
|
||||
cfg_interrupt_msi_mask_update,
|
||||
cfg_interrupt_msi_data,
|
||||
cfg_interrupt_msi_sent,
|
||||
cfg_interrupt_msi_fail,
|
||||
qsfp_0_tx_clk_0,
|
||||
qsfp_0_tx_rst_0,
|
||||
qsfp_0_rx_clk_0,
|
||||
qsfp_0_rx_rst_0,
|
||||
qsfp_0_rxd_0,
|
||||
qsfp_0_rxc_0,
|
||||
qsfp_0_tx_clk_1,
|
||||
qsfp_0_tx_rst_1,
|
||||
qsfp_0_rx_clk_1,
|
||||
qsfp_0_rx_rst_1,
|
||||
qsfp_0_rxd_1,
|
||||
qsfp_0_rxc_1,
|
||||
qsfp_0_tx_clk_2,
|
||||
qsfp_0_tx_rst_2,
|
||||
qsfp_0_rx_clk_2,
|
||||
qsfp_0_rx_rst_2,
|
||||
qsfp_0_rxd_2,
|
||||
qsfp_0_rxc_2,
|
||||
qsfp_0_tx_clk_3,
|
||||
qsfp_0_tx_rst_3,
|
||||
qsfp_0_rx_clk_3,
|
||||
qsfp_0_rx_rst_3,
|
||||
qsfp_0_rxd_3,
|
||||
qsfp_0_rxc_3,
|
||||
qsfp_0_modprs_l,
|
||||
qsfp_1_tx_clk_0,
|
||||
qsfp_1_tx_rst_0,
|
||||
qsfp_1_rx_clk_0,
|
||||
qsfp_1_rx_rst_0,
|
||||
qsfp_1_rxd_0,
|
||||
qsfp_1_rxc_0,
|
||||
qsfp_1_tx_clk_1,
|
||||
qsfp_1_tx_rst_1,
|
||||
qsfp_1_rx_clk_1,
|
||||
qsfp_1_rx_rst_1,
|
||||
qsfp_1_rxd_1,
|
||||
qsfp_1_rxc_1,
|
||||
qsfp_1_tx_clk_2,
|
||||
qsfp_1_tx_rst_2,
|
||||
qsfp_1_rx_clk_2,
|
||||
qsfp_1_rx_rst_2,
|
||||
qsfp_1_rxd_2,
|
||||
qsfp_1_rxc_2,
|
||||
qsfp_1_tx_clk_3,
|
||||
qsfp_1_tx_rst_3,
|
||||
qsfp_1_rx_clk_3,
|
||||
qsfp_1_rx_rst_3,
|
||||
qsfp_1_rxd_3,
|
||||
qsfp_1_rxc_3,
|
||||
qsfp_1_modprs_l,
|
||||
qsfp_int_l,
|
||||
qsfp_i2c_scl_i,
|
||||
qsfp_i2c_sda_i,
|
||||
eeprom_i2c_scl_i,
|
||||
eeprom_i2c_sda_i
|
||||
);
|
||||
$to_myhdl(
|
||||
user_led_g,
|
||||
user_led_r,
|
||||
front_led,
|
||||
m_axis_rq_tdata,
|
||||
m_axis_rq_tkeep,
|
||||
m_axis_rq_tlast,
|
||||
m_axis_rq_tuser,
|
||||
m_axis_rq_tvalid,
|
||||
s_axis_rc_tready,
|
||||
s_axis_cq_tready,
|
||||
m_axis_cc_tdata,
|
||||
m_axis_cc_tkeep,
|
||||
m_axis_cc_tlast,
|
||||
m_axis_cc_tuser,
|
||||
m_axis_cc_tvalid,
|
||||
cfg_mgmt_addr,
|
||||
cfg_mgmt_function_number,
|
||||
cfg_mgmt_write,
|
||||
cfg_mgmt_write_data,
|
||||
cfg_mgmt_byte_enable,
|
||||
cfg_mgmt_read,
|
||||
cfg_interrupt_msi_select,
|
||||
cfg_interrupt_msi_int,
|
||||
cfg_interrupt_msi_pending_status,
|
||||
cfg_interrupt_msi_pending_status_data_enable,
|
||||
cfg_interrupt_msi_pending_status_function_num,
|
||||
cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type,
|
||||
cfg_interrupt_msi_tph_st_tag,
|
||||
cfg_interrupt_msi_function_number,
|
||||
status_error_cor,
|
||||
status_error_uncor,
|
||||
qsfp_0_txd_0,
|
||||
qsfp_0_txc_0,
|
||||
qsfp_0_txd_1,
|
||||
qsfp_0_txc_1,
|
||||
qsfp_0_txd_2,
|
||||
qsfp_0_txc_2,
|
||||
qsfp_0_txd_3,
|
||||
qsfp_0_txc_3,
|
||||
qsfp_0_sel_l,
|
||||
qsfp_1_txd_0,
|
||||
qsfp_1_txc_0,
|
||||
qsfp_1_txd_1,
|
||||
qsfp_1_txc_1,
|
||||
qsfp_1_txd_2,
|
||||
qsfp_1_txc_2,
|
||||
qsfp_1_txd_3,
|
||||
qsfp_1_txc_3,
|
||||
qsfp_1_sel_l,
|
||||
qsfp_reset_l,
|
||||
qsfp_i2c_scl_o,
|
||||
qsfp_i2c_scl_t,
|
||||
qsfp_i2c_sda_o,
|
||||
qsfp_i2c_sda_t,
|
||||
eeprom_i2c_scl_o,
|
||||
eeprom_i2c_scl_t,
|
||||
eeprom_i2c_sda_o,
|
||||
eeprom_i2c_sda_t,
|
||||
eeprom_wp
|
||||
);
|
||||
|
||||
// dump file
|
||||
$dumpfile("test_fpga_core.lxt");
|
||||
$dumpvars(0, test_fpga_core);
|
||||
end
|
||||
|
||||
fpga_core
|
||||
UUT (
|
||||
.clk_156mhz(clk_156mhz),
|
||||
.rst_156mhz(rst_156mhz),
|
||||
.clk_250mhz(clk_250mhz),
|
||||
.rst_250mhz(rst_250mhz),
|
||||
.user_led_g(user_led_g),
|
||||
.user_led_r(user_led_r),
|
||||
.front_led(front_led),
|
||||
.user_sw(user_sw),
|
||||
.m_axis_rq_tdata(m_axis_rq_tdata),
|
||||
.m_axis_rq_tkeep(m_axis_rq_tkeep),
|
||||
.m_axis_rq_tlast(m_axis_rq_tlast),
|
||||
.m_axis_rq_tready(m_axis_rq_tready),
|
||||
.m_axis_rq_tuser(m_axis_rq_tuser),
|
||||
.m_axis_rq_tvalid(m_axis_rq_tvalid),
|
||||
.s_axis_rc_tdata(s_axis_rc_tdata),
|
||||
.s_axis_rc_tkeep(s_axis_rc_tkeep),
|
||||
.s_axis_rc_tlast(s_axis_rc_tlast),
|
||||
.s_axis_rc_tready(s_axis_rc_tready),
|
||||
.s_axis_rc_tuser(s_axis_rc_tuser),
|
||||
.s_axis_rc_tvalid(s_axis_rc_tvalid),
|
||||
.s_axis_cq_tdata(s_axis_cq_tdata),
|
||||
.s_axis_cq_tkeep(s_axis_cq_tkeep),
|
||||
.s_axis_cq_tlast(s_axis_cq_tlast),
|
||||
.s_axis_cq_tready(s_axis_cq_tready),
|
||||
.s_axis_cq_tuser(s_axis_cq_tuser),
|
||||
.s_axis_cq_tvalid(s_axis_cq_tvalid),
|
||||
.m_axis_cc_tdata(m_axis_cc_tdata),
|
||||
.m_axis_cc_tkeep(m_axis_cc_tkeep),
|
||||
.m_axis_cc_tlast(m_axis_cc_tlast),
|
||||
.m_axis_cc_tready(m_axis_cc_tready),
|
||||
.m_axis_cc_tuser(m_axis_cc_tuser),
|
||||
.m_axis_cc_tvalid(m_axis_cc_tvalid),
|
||||
.pcie_tfc_nph_av(pcie_tfc_nph_av),
|
||||
.pcie_tfc_npd_av(pcie_tfc_npd_av),
|
||||
.cfg_max_payload(cfg_max_payload),
|
||||
.cfg_max_read_req(cfg_max_read_req),
|
||||
.cfg_mgmt_addr(cfg_mgmt_addr),
|
||||
.cfg_mgmt_function_number(cfg_mgmt_function_number),
|
||||
.cfg_mgmt_write(cfg_mgmt_write),
|
||||
.cfg_mgmt_write_data(cfg_mgmt_write_data),
|
||||
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
|
||||
.cfg_mgmt_read(cfg_mgmt_read),
|
||||
.cfg_mgmt_read_data(cfg_mgmt_read_data),
|
||||
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
.status_error_cor(status_error_cor),
|
||||
.status_error_uncor(status_error_uncor),
|
||||
.qsfp_0_tx_clk_0(qsfp_0_tx_clk_0),
|
||||
.qsfp_0_tx_rst_0(qsfp_0_tx_rst_0),
|
||||
.qsfp_0_txd_0(qsfp_0_txd_0),
|
||||
.qsfp_0_txc_0(qsfp_0_txc_0),
|
||||
.qsfp_0_rx_clk_0(qsfp_0_rx_clk_0),
|
||||
.qsfp_0_rx_rst_0(qsfp_0_rx_rst_0),
|
||||
.qsfp_0_rxd_0(qsfp_0_rxd_0),
|
||||
.qsfp_0_rxc_0(qsfp_0_rxc_0),
|
||||
.qsfp_0_tx_clk_1(qsfp_0_tx_clk_1),
|
||||
.qsfp_0_tx_rst_1(qsfp_0_tx_rst_1),
|
||||
.qsfp_0_txd_1(qsfp_0_txd_1),
|
||||
.qsfp_0_txc_1(qsfp_0_txc_1),
|
||||
.qsfp_0_rx_clk_1(qsfp_0_rx_clk_1),
|
||||
.qsfp_0_rx_rst_1(qsfp_0_rx_rst_1),
|
||||
.qsfp_0_rxd_1(qsfp_0_rxd_1),
|
||||
.qsfp_0_rxc_1(qsfp_0_rxc_1),
|
||||
.qsfp_0_tx_clk_2(qsfp_0_tx_clk_2),
|
||||
.qsfp_0_tx_rst_2(qsfp_0_tx_rst_2),
|
||||
.qsfp_0_txd_2(qsfp_0_txd_2),
|
||||
.qsfp_0_txc_2(qsfp_0_txc_2),
|
||||
.qsfp_0_rx_clk_2(qsfp_0_rx_clk_2),
|
||||
.qsfp_0_rx_rst_2(qsfp_0_rx_rst_2),
|
||||
.qsfp_0_rxd_2(qsfp_0_rxd_2),
|
||||
.qsfp_0_rxc_2(qsfp_0_rxc_2),
|
||||
.qsfp_0_tx_clk_3(qsfp_0_tx_clk_3),
|
||||
.qsfp_0_tx_rst_3(qsfp_0_tx_rst_3),
|
||||
.qsfp_0_txd_3(qsfp_0_txd_3),
|
||||
.qsfp_0_txc_3(qsfp_0_txc_3),
|
||||
.qsfp_0_rx_clk_3(qsfp_0_rx_clk_3),
|
||||
.qsfp_0_rx_rst_3(qsfp_0_rx_rst_3),
|
||||
.qsfp_0_rxd_3(qsfp_0_rxd_3),
|
||||
.qsfp_0_rxc_3(qsfp_0_rxc_3),
|
||||
.qsfp_0_modprs_l(qsfp_0_modprs_l),
|
||||
.qsfp_0_sel_l(qsfp_0_sel_l),
|
||||
.qsfp_1_tx_clk_0(qsfp_1_tx_clk_0),
|
||||
.qsfp_1_tx_rst_0(qsfp_1_tx_rst_0),
|
||||
.qsfp_1_txd_0(qsfp_1_txd_0),
|
||||
.qsfp_1_txc_0(qsfp_1_txc_0),
|
||||
.qsfp_1_rx_clk_0(qsfp_1_rx_clk_0),
|
||||
.qsfp_1_rx_rst_0(qsfp_1_rx_rst_0),
|
||||
.qsfp_1_rxd_0(qsfp_1_rxd_0),
|
||||
.qsfp_1_rxc_0(qsfp_1_rxc_0),
|
||||
.qsfp_1_tx_clk_1(qsfp_1_tx_clk_1),
|
||||
.qsfp_1_tx_rst_1(qsfp_1_tx_rst_1),
|
||||
.qsfp_1_txd_1(qsfp_1_txd_1),
|
||||
.qsfp_1_txc_1(qsfp_1_txc_1),
|
||||
.qsfp_1_rx_clk_1(qsfp_1_rx_clk_1),
|
||||
.qsfp_1_rx_rst_1(qsfp_1_rx_rst_1),
|
||||
.qsfp_1_rxd_1(qsfp_1_rxd_1),
|
||||
.qsfp_1_rxc_1(qsfp_1_rxc_1),
|
||||
.qsfp_1_tx_clk_2(qsfp_1_tx_clk_2),
|
||||
.qsfp_1_tx_rst_2(qsfp_1_tx_rst_2),
|
||||
.qsfp_1_txd_2(qsfp_1_txd_2),
|
||||
.qsfp_1_txc_2(qsfp_1_txc_2),
|
||||
.qsfp_1_rx_clk_2(qsfp_1_rx_clk_2),
|
||||
.qsfp_1_rx_rst_2(qsfp_1_rx_rst_2),
|
||||
.qsfp_1_rxd_2(qsfp_1_rxd_2),
|
||||
.qsfp_1_rxc_2(qsfp_1_rxc_2),
|
||||
.qsfp_1_tx_clk_3(qsfp_1_tx_clk_3),
|
||||
.qsfp_1_tx_rst_3(qsfp_1_tx_rst_3),
|
||||
.qsfp_1_txd_3(qsfp_1_txd_3),
|
||||
.qsfp_1_txc_3(qsfp_1_txc_3),
|
||||
.qsfp_1_rx_clk_3(qsfp_1_rx_clk_3),
|
||||
.qsfp_1_rx_rst_3(qsfp_1_rx_rst_3),
|
||||
.qsfp_1_rxd_3(qsfp_1_rxd_3),
|
||||
.qsfp_1_rxc_3(qsfp_1_rxc_3),
|
||||
.qsfp_1_modprs_l(qsfp_1_modprs_l),
|
||||
.qsfp_1_sel_l(qsfp_1_sel_l),
|
||||
.qsfp_reset_l(qsfp_reset_l),
|
||||
.qsfp_int_l(qsfp_int_l),
|
||||
.qsfp_i2c_scl_i(qsfp_i2c_scl_i),
|
||||
.qsfp_i2c_scl_o(qsfp_i2c_scl_o),
|
||||
.qsfp_i2c_scl_t(qsfp_i2c_scl_t),
|
||||
.qsfp_i2c_sda_i(qsfp_i2c_sda_i),
|
||||
.qsfp_i2c_sda_o(qsfp_i2c_sda_o),
|
||||
.qsfp_i2c_sda_t(qsfp_i2c_sda_t),
|
||||
.eeprom_i2c_scl_i(eeprom_i2c_scl_i),
|
||||
.eeprom_i2c_scl_o(eeprom_i2c_scl_o),
|
||||
.eeprom_i2c_scl_t(eeprom_i2c_scl_t),
|
||||
.eeprom_i2c_sda_i(eeprom_i2c_sda_i),
|
||||
.eeprom_i2c_sda_o(eeprom_i2c_sda_o),
|
||||
.eeprom_i2c_sda_t(eeprom_i2c_sda_t),
|
||||
.eeprom_wp(eeprom_wp)
|
||||
);
|
||||
|
||||
endmodule
|
||||
1
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/xgmii_ep.py
Symbolic link
1
fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/tb/xgmii_ep.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/eth/tb/xgmii_ep.py
|
||||
Loading…
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Reference in New Issue
Block a user