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Use false path constraints for status signals that change infrequently

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-01-17 14:25:30 -08:00
parent 79431bf221
commit 5b859b08a0
1 changed files with 6 additions and 10 deletions
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16
fpga/common/syn/vivado/mqnic_port.tcl
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@ -32,22 +32,18 @@
foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == mqnic_port || REF_NAME == mqnic_port)}] {
puts "Inserting timing constraints for mqnic_port instance $inst"
proc constrain_sync_chain {inst driver args} {
proc constrain_slow_sync {inst driver args} {
set sync_ffs [get_cells -hier [concat $driver $args] -filter "PARENT == $inst"]
if {[llength $sync_ffs]} {
set_property ASYNC_REG TRUE $sync_ffs
set src_clk [get_clocks -of_objects [get_cells "$inst/$driver"]]
set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 1.0}]
set_max_delay -from [get_cells "$inst/$driver"] -to [get_cells "$inst/[lindex $args 0]"] -datapath_only $src_clk_period
set_false_path -from [get_cells "$inst/$driver"] -to [get_cells "$inst/[lindex $args 0]"]
}
}
constrain_sync_chain $inst "rx_rst_sync_1_reg_reg" "rx_rst_sync_2_reg_reg" "rx_rst_sync_3_reg_reg"
constrain_sync_chain $inst "rx_status_sync_1_reg_reg" "rx_status_sync_2_reg_reg" "rx_status_sync_3_reg_reg"
constrain_sync_chain $inst "tx_rst_sync_1_reg_reg" "tx_rst_sync_2_reg_reg" "tx_rst_sync_3_reg_reg"
constrain_sync_chain $inst "tx_status_sync_1_reg_reg" "tx_status_sync_2_reg_reg" "tx_status_sync_3_reg_reg"
constrain_slow_sync $inst "rx_rst_sync_1_reg_reg" "rx_rst_sync_2_reg_reg" "rx_rst_sync_3_reg_reg"
constrain_slow_sync $inst "rx_status_sync_1_reg_reg" "rx_status_sync_2_reg_reg" "rx_status_sync_3_reg_reg"
constrain_slow_sync $inst "tx_rst_sync_1_reg_reg" "tx_rst_sync_2_reg_reg" "tx_rst_sync_3_reg_reg"
constrain_slow_sync $inst "tx_status_sync_1_reg_reg" "tx_status_sync_2_reg_reg" "tx_status_sync_3_reg_reg"
}