From 5b8898f2bc1013c1468c1b79b65dcc64a2ae4e3c Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 25 Jul 2019 17:44:13 -0700 Subject: [PATCH] Add VCU108 mqnic_tdma design --- fpga/mqnic_tdma/VCU108/fpga_10g/Makefile | 25 + fpga/mqnic_tdma/VCU108/fpga_10g/README.md | 24 + .../VCU108/fpga_10g/common/vivado.mk | 118 + fpga/mqnic_tdma/VCU108/fpga_10g/fpga.xdc | 154 ++ fpga/mqnic_tdma/VCU108/fpga_10g/fpga/Makefile | 140 + .../fpga_10g/ip/gtwizard_ultrascale_0.xci | 1402 ++++++++++ .../VCU108/fpga_10g/ip/pcie3_ultrascale_0.xci | 890 +++++++ fpga/mqnic_tdma/VCU108/fpga_10g/lib | 1 + fpga/mqnic_tdma/VCU108/fpga_10g/rtl/common | 1 + .../VCU108/fpga_10g/rtl/debounce_switch.v | 89 + fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga.v | 1052 ++++++++ .../VCU108/fpga_10g/rtl/fpga_core.v | 2286 +++++++++++++++++ .../VCU108/fpga_10g/rtl/sync_reset.v | 52 + .../VCU108/fpga_10g/rtl/sync_signal.v | 58 + fpga/mqnic_tdma/VCU108/fpga_10g/tb/axis_ep.py | 1 + fpga/mqnic_tdma/VCU108/fpga_10g/tb/mqnic.py | 1 + fpga/mqnic_tdma/VCU108/fpga_10g/tb/pcie.py | 1 + fpga/mqnic_tdma/VCU108/fpga_10g/tb/pcie_us.py | 1 + .../VCU108/fpga_10g/tb/test_fpga_core.py | 890 +++++++ .../VCU108/fpga_10g/tb/test_fpga_core.v | 424 +++ .../mqnic_tdma/VCU108/fpga_10g/tb/xgmii_ep.py | 1 + 21 files changed, 7611 insertions(+) create mode 100644 fpga/mqnic_tdma/VCU108/fpga_10g/Makefile create mode 100644 fpga/mqnic_tdma/VCU108/fpga_10g/README.md create mode 100644 fpga/mqnic_tdma/VCU108/fpga_10g/common/vivado.mk create mode 100644 fpga/mqnic_tdma/VCU108/fpga_10g/fpga.xdc create mode 100644 fpga/mqnic_tdma/VCU108/fpga_10g/fpga/Makefile create mode 100644 fpga/mqnic_tdma/VCU108/fpga_10g/ip/gtwizard_ultrascale_0.xci create mode 100644 fpga/mqnic_tdma/VCU108/fpga_10g/ip/pcie3_ultrascale_0.xci create mode 120000 fpga/mqnic_tdma/VCU108/fpga_10g/lib create mode 120000 fpga/mqnic_tdma/VCU108/fpga_10g/rtl/common create mode 100644 fpga/mqnic_tdma/VCU108/fpga_10g/rtl/debounce_switch.v create mode 100644 fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga.v create mode 100644 fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v create mode 100644 fpga/mqnic_tdma/VCU108/fpga_10g/rtl/sync_reset.v create mode 100644 fpga/mqnic_tdma/VCU108/fpga_10g/rtl/sync_signal.v create mode 120000 fpga/mqnic_tdma/VCU108/fpga_10g/tb/axis_ep.py create mode 120000 fpga/mqnic_tdma/VCU108/fpga_10g/tb/mqnic.py create mode 120000 fpga/mqnic_tdma/VCU108/fpga_10g/tb/pcie.py create mode 120000 fpga/mqnic_tdma/VCU108/fpga_10g/tb/pcie_us.py create mode 100755 fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.py create mode 100644 fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.v create mode 120000 fpga/mqnic_tdma/VCU108/fpga_10g/tb/xgmii_ep.py diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/Makefile b/fpga/mqnic_tdma/VCU108/fpga_10g/Makefile new file mode 100644 index 000000000..f504bd06f --- /dev/null +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/Makefile @@ -0,0 +1,25 @@ +# Targets +TARGETS:= + +# Subdirectories +SUBDIRS = fpga +SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) + +# Rules +.PHONY: all +all: $(SUBDIRS) $(TARGETS) + +.PHONY: $(SUBDIRS) +$(SUBDIRS): + cd $@ && $(MAKE) + +.PHONY: $(SUBDIRS_CLEAN) +$(SUBDIRS_CLEAN): + cd $(@:.clean=) && $(MAKE) clean + +.PHONY: clean +clean: $(SUBDIRS_CLEAN) + -rm -rf $(TARGETS) + +program: + #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/README.md b/fpga/mqnic_tdma/VCU108/fpga_10g/README.md new file mode 100644 index 000000000..a98333a04 --- /dev/null +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/README.md @@ -0,0 +1,24 @@ +# Corundum mqnic for VCU108 + +## Introduction + +This design targets the Xilinx VCU108 FPGA board. + +FPGA: xcvu095-ffva2104-2-e +PHY: 10G BASE-R PHY IP core and internal GTY transceiver + +## How to build + +Run make to build. Ensure that the Xilinx Vivado toolchain components are +in PATH. + +Run make to build the driver. Ensure the headers for the running kernel are +installed, otherwise the driver cannot be compiled. + +## How to test + +Run make program to program the VCU108 board with Vivado. Then load the +driver with insmod mqnic.ko. Check dmesg for output from driver +initialization. + + diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/common/vivado.mk b/fpga/mqnic_tdma/VCU108/fpga_10g/common/vivado.mk new file mode 100644 index 000000000..964ed04eb --- /dev/null +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/common/vivado.mk @@ -0,0 +1,118 @@ +################################################################### +# +# Xilinx Vivado FPGA Makefile +# +# Copyright (c) 2016 Alex Forencich +# +################################################################### +# +# Parameters: +# FPGA_TOP - Top module name +# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) +# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) +# SYN_FILES - space-separated list of source files +# INC_FILES - space-separated list of include files +# XDC_FILES - space-separated list of timing constraint files +# XCI_FILES - space-separated list of IP XCI files +# +# Example: +# +# FPGA_TOP = fpga +# FPGA_FAMILY = VirtexUltrascale +# FPGA_DEVICE = xcvu095-ffva2104-2-e +# SYN_FILES = rtl/fpga.v +# XDC_FILES = fpga.xdc +# XCI_FILES = ip/pcspma.xci +# include ../common/vivado.mk +# +################################################################### + +# phony targets +.PHONY: clean fpga + +# prevent make from deleting intermediate files and reports +.PRECIOUS: %.xpr %.bit %.mcs %.prm +.SECONDARY: + +CONFIG ?= config.mk +-include ../$(CONFIG) + +SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) +INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) +XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) + +ifdef XDC_FILES + XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) +else + XDC_FILES_REL = $(FPGA_TOP).xdc +endif + +################################################################### +# Main Targets +# +# all: build everything +# clean: remove output files and project files +################################################################### + +all: fpga + +fpga: $(FPGA_TOP).bit + +tmpclean: + -rm -rf *.log *.jou *.cache *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + +clean: tmpclean + -rm -rf *.bit program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl + +distclean: clean + -rm -rf rev + +################################################################### +# Target implementations +################################################################### + +# Vivado project file +%.xpr: Makefile $(XCI_FILES_REL) + rm -rf defines.v + touch defines.v + for x in $(DEFS); do echo '`define' $$x >> defines.v; done + echo "create_project -force -part $(FPGA_PART) $*" > create_project.tcl + echo "add_files -fileset sources_1 defines.v" >> create_project.tcl + for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done + for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done + for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done + echo "exit" >> create_project.tcl + vivado -nojournal -nolog -mode batch -source create_project.tcl + +# synthesis run +%.runs/synth_1/%.dcp: %.xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) + echo "open_project $*.xpr" > run_synth.tcl + echo "reset_run synth_1" >> run_synth.tcl + echo "launch_runs synth_1" >> run_synth.tcl + echo "wait_on_run synth_1" >> run_synth.tcl + echo "exit" >> run_synth.tcl + vivado -nojournal -nolog -mode batch -source run_synth.tcl + +# implementation run +%.runs/impl_1/%_routed.dcp: %.runs/synth_1/%.dcp + echo "open_project $*.xpr" > run_impl.tcl + echo "reset_run impl_1" >> run_impl.tcl + echo "launch_runs impl_1" >> run_impl.tcl + echo "wait_on_run impl_1" >> run_impl.tcl + echo "exit" >> run_impl.tcl + vivado -nojournal -nolog -mode batch -source run_impl.tcl + +# bit file +%.bit: %.runs/impl_1/%_routed.dcp + echo "open_project $*.xpr" > generate_bit.tcl + echo "open_run impl_1" >> generate_bit.tcl + echo "write_bitstream -force $*.bit" >> generate_bit.tcl + echo "exit" >> generate_bit.tcl + vivado -nojournal -nolog -mode batch -source generate_bit.tcl + mkdir -p rev + EXT=bit; COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.$$EXT ]; \ + do COUNT=$$((COUNT+1)); done; \ + cp $@ rev/$*_rev$$COUNT.$$EXT; \ + echo "Output: rev/$*_rev$$COUNT.$$EXT"; diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/fpga.xdc b/fpga/mqnic_tdma/VCU108/fpga_10g/fpga.xdc new file mode 100644 index 000000000..900eadd0d --- /dev/null +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/fpga.xdc @@ -0,0 +1,154 @@ +# XDC constraints for the Xilinx VCU108 board +# part: xcvu095-ffva2104-2-e + +# General configuration +set_property CFGBVS GND [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design] +set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type1 [current_design] +set_property CONFIG_MODE BPI16 [current_design] + +# System clocks +# 300 MHz +#set_property -dict {LOC G31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_p] +#set_property -dict {LOC F31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_n] +#create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p] + +#set_property -dict {LOC G22 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_2_p] +#set_property -dict {LOC G21 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_2_n] +#create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p] + +# 125 MHz +set_property -dict {LOC BC9 IOSTANDARD LVDS} [get_ports clk_125mhz_p] +set_property -dict {LOC BC8 IOSTANDARD LVDS} [get_ports clk_125mhz_n] +create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p] + +# 90 MHz +#set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz] +#create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz] + +# LEDs +set_property -dict {LOC AT32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}] +set_property -dict {LOC AV34 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}] +set_property -dict {LOC AY30 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[2]}] +set_property -dict {LOC BB32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[3]}] +set_property -dict {LOC BF32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[4]}] +set_property -dict {LOC AV36 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[5]}] +set_property -dict {LOC AY35 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[6]}] +set_property -dict {LOC BA37 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[7]}] + +# Reset button +#set_property -dict {LOC E36 IOSTANDARD LVCMOS12} [get_ports reset] + +# Push buttons +set_property -dict {LOC E34 IOSTANDARD LVCMOS12} [get_ports btnu] +set_property -dict {LOC M22 IOSTANDARD LVCMOS12} [get_ports btnl] +set_property -dict {LOC D9 IOSTANDARD LVCMOS12} [get_ports btnd] +set_property -dict {LOC A10 IOSTANDARD LVCMOS12} [get_ports btnr] +set_property -dict {LOC AW27 IOSTANDARD LVCMOS12} [get_ports btnc] + +# DIP switches +set_property -dict {LOC BC40 IOSTANDARD LVCMOS12} [get_ports {sw[0]}] +set_property -dict {LOC L19 IOSTANDARD LVCMOS12} [get_ports {sw[1]}] +set_property -dict {LOC C37 IOSTANDARD LVCMOS12} [get_ports {sw[2]}] +set_property -dict {LOC C38 IOSTANDARD LVCMOS12} [get_ports {sw[3]}] + +# UART +#set_property -dict {LOC BE24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd] +#set_property -dict {LOC BC24 IOSTANDARD LVCMOS18} [get_ports uart_rxd] +#set_property -dict {LOC BF24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_rts] +#set_property -dict {LOC BD22 IOSTANDARD LVCMOS18} [get_ports uart_cts] + +# Gigabit Ethernet SGMII PHY +#set_property -dict {LOC AR24 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_sgmii_rx_p] +#set_property -dict {LOC AT24 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_sgmii_rx_n] +#set_property -dict {LOC AR23 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_sgmii_tx_p] +#set_property -dict {LOC AR22 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_sgmii_tx_n] +#set_property -dict {LOC AT22 IOSTANDARD LVDS_25} [get_ports phy_sgmii_clk_p] +#set_property -dict {LOC AU22 IOSTANDARD LVDS_25} [get_ports phy_sgmii_clk_n] +#set_property -dict {LOC AU21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_reset_n] +#set_property -dict {LOC AT21 IOSTANDARD LVCMOS18} [get_ports phy_int_n] +#set_property -dict {LOC AV24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_mdio] +#set_property -dict {LOC AV21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_mdc] + +# 625 MHz ref clock from SGMII PHY +#create_clock -period 1.600 -name phy_sgmii_clk [get_ports phy_sgmii_clk_p] + +# QSFP+ Interface +set_property -dict {LOC AG45} [get_ports qsfp_rx1_p] ;# MGTYTXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3 +#set_property -dict {LOC AG46} [get_ports qsfp_rx1_n] ;# MGTYTXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3 +set_property -dict {LOC AF43} [get_ports qsfp_rx2_p] ;# MGTYTXP1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3 +#set_property -dict {LOC AF44} [get_ports qsfp_rx2_n] ;# MGTYTXN1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3 +set_property -dict {LOC AE45} [get_ports qsfp_rx3_p] ;# MGTYTXP2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3 +#set_property -dict {LOC AE46} [get_ports qsfp_rx3_n] ;# MGTYTXN2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3 +set_property -dict {LOC AD43} [get_ports qsfp_rx4_p] ;# MGTYTXP3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3 +#set_property -dict {LOC AD44} [get_ports qsfp_rx4_n] ;# MGTYTXN3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3 +set_property -dict {LOC AK42} [get_ports qsfp_tx1_p] ;# MGTYTXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3 +#set_property -dict {LOC AK43} [get_ports qsfp_tx1_n] ;# MGTYTXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3 +set_property -dict {LOC AJ40} [get_ports qsfp_tx2_p] ;# MGTYTXP1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3 +#set_property -dict {LOC AJ41} [get_ports qsfp_tx2_n] ;# MGTYTXN1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3 +set_property -dict {LOC AG40} [get_ports qsfp_tx3_p] ;# MGTYTXP2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3 +#set_property -dict {LOC AG41} [get_ports qsfp_tx3_n] ;# MGTYTXN2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3 +set_property -dict {LOC AE40} [get_ports qsfp_tx4_p] ;# MGTYTXP3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3 +#set_property -dict {LOC AE41} [get_ports qsfp_tx4_n] ;# MGTYTXN3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3 +set_property -dict {LOC AF38} [get_ports qsfp_mgt_refclk_0_p] ;# MGTREFCLK0P_127 from U32 SI570 via U102 SI53340 +#set_property -dict {LOC AF39} [get_ports qsfp_mgt_refclk_0_n] ;# MGTREFCLK0N_127 from U32 SI570 via U102 SI53340 +#set_property -dict {LOC AD38} [get_ports qsfp_mgt_refclk_1_p] ;# MGTREFCLK1P_127 from U57 CKOUT2 SI5328 +#set_property -dict {LOC AD39} [get_ports qsfp_mgt_refclk_1_n] ;# MGTREFCLK1N_127 from U57 CKOUT2 SI5328 +#set_property -dict {LOC AG34 IOSTANDARD LVDS} [get_ports qsfp_recclk_p] ;# to U57 CKIN1 SI5328 +#set_property -dict {LOC AH35 IOSTANDARD LVDS} [get_ports qsfp_recclk_n] ;# to U57 CKIN1 SI5328 +set_property -dict {LOC AL24 IOSTANDARD LVCMOS18} [get_ports qsfp_modsell] +set_property -dict {LOC AM24 IOSTANDARD LVCMOS18} [get_ports qsfp_resetl] +set_property -dict {LOC AL25 IOSTANDARD LVCMOS18} [get_ports qsfp_modprsl] +set_property -dict {LOC AL21 IOSTANDARD LVCMOS18} [get_ports qsfp_intl] +set_property -dict {LOC AM21 IOSTANDARD LVCMOS18} [get_ports qsfp_lpmode] + +# 156.25 MHz MGT reference clock +create_clock -period 6.400 -name qsfp_mgt_refclk_0 [get_ports qsfp_mgt_refclk_0_p] + +# I2C interface +set_property -dict {LOC AN21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_scl] +set_property -dict {LOC AP21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_sda] + +# PCIe Interface +set_property -dict {LOC BB2 } [get_ports {pcie_rx_p[7]}] ;# MGTHTXN0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0 +#set_property -dict {LOC BB1 } [get_ports {pcie_rx_n[7]}] ;# MGTHTXP0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0 +set_property -dict {LOC BE5 } [get_ports {pcie_tx_p[7]}] ;# MGTHTXN0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0 +#set_property -dict {LOC BE4 } [get_ports {pcie_tx_n[7]}] ;# MGTHTXP0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0 +set_property -dict {LOC AY2 } [get_ports {pcie_rx_p[6]}] ;# MGTHTXN1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0 +#set_property -dict {LOC AY1 } [get_ports {pcie_rx_n[6]}] ;# MGTHTXP1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0 +set_property -dict {LOC BC5 } [get_ports {pcie_tx_p[6]}] ;# MGTHTXN1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0 +#set_property -dict {LOC BC4 } [get_ports {pcie_tx_n[6]}] ;# MGTHTXP1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0 +set_property -dict {LOC AV2 } [get_ports {pcie_rx_p[5]}] ;# MGTHTXN2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0 +#set_property -dict {LOC AV1 } [get_ports {pcie_rx_n[5]}] ;# MGTHTXP2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0 +set_property -dict {LOC BA5 } [get_ports {pcie_tx_p[5]}] ;# MGTHTXN2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0 +#set_property -dict {LOC BA4 } [get_ports {pcie_tx_n[5]}] ;# MGTHTXP2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0 +set_property -dict {LOC AT2 } [get_ports {pcie_rx_p[4]}] ;# MGTHTXN3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0 +#set_property -dict {LOC AT1 } [get_ports {pcie_rx_n[4]}] ;# MGTHTXP3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0 +set_property -dict {LOC AW5 } [get_ports {pcie_tx_p[4]}] ;# MGTHTXN3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0 +#set_property -dict {LOC AW4 } [get_ports {pcie_tx_n[4]}] ;# MGTHTXP3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0 +set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[3]}] ;# MGTHTXN0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1 +#set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[3]}] ;# MGTHTXP0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1 +set_property -dict {LOC AU5 } [get_ports {pcie_tx_p[3]}] ;# MGTHTXN0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1 +#set_property -dict {LOC AU4 } [get_ports {pcie_tx_n[3]}] ;# MGTHTXP0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1 +set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[2]}] ;# MGTHTXN1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1 +#set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[2]}] ;# MGTHTXP1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1 +set_property -dict {LOC AT7 } [get_ports {pcie_tx_p[2]}] ;# MGTHTXN1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1 +#set_property -dict {LOC AT6 } [get_ports {pcie_tx_n[2]}] ;# MGTHTXP1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1 +set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[1]}] ;# MGTHTXN2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1 +#set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[1]}] ;# MGTHTXP2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1 +set_property -dict {LOC AR5 } [get_ports {pcie_tx_p[1]}] ;# MGTHTXN2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1 +#set_property -dict {LOC AR4 } [get_ports {pcie_tx_n[1]}] ;# MGTHTXP2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1 +set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[0]}] ;# MGTHTXN3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1 +#set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[0]}] ;# MGTHTXP3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1 +set_property -dict {LOC AP7 } [get_ports {pcie_tx_p[0]}] ;# MGTHTXN3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1 +#set_property -dict {LOC AP6 } [get_ports {pcie_tx_n[0]}] ;# MGTHTXP3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1 +set_property -dict {LOC AL9 } [get_ports pcie_mgt_refclk_p] ;# MGTREFCLK0P_225 +#set_property -dict {LOC AL8 } [get_ports pcie_mgt_refclk_n] ;# MGTREFCLK0N_225 +set_property -dict {LOC AM17 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n] + +# 100 MHz MGT reference clock +create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_mgt_refclk_p] + + diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/fpga/Makefile b/fpga/mqnic_tdma/VCU108/fpga_10g/fpga/Makefile new file mode 100644 index 000000000..777ce7593 --- /dev/null +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/fpga/Makefile @@ -0,0 +1,140 @@ + +# FPGA settings +FPGA_PART = xcvu095-ffva2104-2-e +FPGA_TOP = fpga +FPGA_ARCH = VirtexUltrascale + +# Files for synthesis +SYN_FILES = rtl/fpga.v +SYN_FILES += rtl/fpga_core.v +SYN_FILES += rtl/debounce_switch.v +SYN_FILES += rtl/sync_reset.v +SYN_FILES += rtl/sync_signal.v +SYN_FILES += rtl/common/interface.v +SYN_FILES += rtl/common/port.v +SYN_FILES += rtl/common/queue_manager.v +SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/event_queue.v +SYN_FILES += rtl/common/event_mux.v +SYN_FILES += rtl/common/tx_scheduler_tdma_rr.v +SYN_FILES += rtl/common/tdma_scheduler.v +SYN_FILES += rtl/common/tdma_ber.v +SYN_FILES += rtl/common/tdma_ber_ch.v +SYN_FILES += rtl/common/tx_engine.v +SYN_FILES += rtl/common/rx_engine.v +SYN_FILES += rtl/common/rx_checksum.v +SYN_FILES += lib/eth/rtl/eth_mac_10g.v +SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v +SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v +SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v +SYN_FILES += lib/eth/rtl/eth_phy_10g.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v +SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v +SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v +SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v +SYN_FILES += lib/eth/rtl/lfsr.v +SYN_FILES += lib/eth/rtl/ptp_clock.v +SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v +SYN_FILES += lib/eth/rtl/ptp_perout.v +SYN_FILES += lib/eth/rtl/ptp_ts_extract.v +SYN_FILES += lib/axi/rtl/axi_crossbar.v +SYN_FILES += lib/axi/rtl/axi_crossbar_addr.v +SYN_FILES += lib/axi/rtl/axi_crossbar_rd.v +SYN_FILES += lib/axi/rtl/axi_crossbar_wr.v +SYN_FILES += lib/axi/rtl/axi_dma.v +SYN_FILES += lib/axi/rtl/axi_dma_rd.v +SYN_FILES += lib/axi/rtl/axi_dma_wr.v +SYN_FILES += lib/axi/rtl/axi_interconnect.v +SYN_FILES += lib/axi/rtl/axi_ram.v +SYN_FILES += lib/axi/rtl/axi_ram_rd_if.v +SYN_FILES += lib/axi/rtl/axi_ram_wr_if.v +SYN_FILES += lib/axi/rtl/axi_register_rd.v +SYN_FILES += lib/axi/rtl/axi_register_wr.v +SYN_FILES += lib/axi/rtl/axil_interconnect.v +SYN_FILES += lib/axi/rtl/arbiter.v +SYN_FILES += lib/axi/rtl/priority_encoder.v +SYN_FILES += lib/axis/rtl/axis_adapter.v +SYN_FILES += lib/axis/rtl/axis_async_fifo.v +SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_arb_mux.v +SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_register.v +SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v +SYN_FILES += lib/pcie/rtl/pcie_us_axi_master.v +SYN_FILES += lib/pcie/rtl/pcie_us_axi_master_rd.v +SYN_FILES += lib/pcie/rtl/pcie_us_axi_master_wr.v +SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma.v +SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma_rd.v +SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma_wr.v +SYN_FILES += lib/pcie/rtl/pcie_us_axis_cq_demux.v +SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v +SYN_FILES += lib/pcie/rtl/pcie_us_msi.v +SYN_FILES += lib/pcie/rtl/pcie_tag_manager.v +SYN_FILES += lib/pcie/rtl/pcie_axi_dma_desc_mux.v +SYN_FILES += lib/pcie/rtl/pulse_merge.v + +# XDC files +XDC_FILES = fpga.xdc +XDC_FILES += lib/axis/syn/axis_async_fifo.tcl +XDC_FILES += lib/eth/syn/ptp_clock_cdc.tcl +XDC_FILES += ../../../common/syn/tdma_ber_ch.tcl + +# IP +XCI_FILES = ip/pcie3_ultrascale_0.xci +XCI_FILES += ip/gtwizard_ultrascale_0.xci + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +%.mcs %.prm: %.bit + echo "write_cfgmem -force -format mcs -size 128 -interface BPIx16 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in .mcs .prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt28gu01gaax1e-bpi-x16}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.BPI_RS_PINS {none} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl + diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/ip/gtwizard_ultrascale_0.xci b/fpga/mqnic_tdma/VCU108/fpga_10g/ip/gtwizard_ultrascale_0.xci new file mode 100644 index 000000000..a38021fba --- /dev/null +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/ip/gtwizard_ultrascale_0.xci @@ -0,0 +1,1402 @@ + + + xilinx.com + xci + unknown + 1.0 + + + gtwizard_ultrascale_0 + + + "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111000000000000" + 1 + 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TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/ip/pcie3_ultrascale_0.xci b/fpga/mqnic_tdma/VCU108/fpga_10g/ip/pcie3_ultrascale_0.xci new file mode 100644 index 000000000..68c7f1717 --- /dev/null +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/ip/pcie3_ultrascale_0.xci @@ -0,0 +1,890 @@ + + + xilinx.com + xci + unknown + 1.0 + + + pcie3_ultrascale_0 + + + + + + 100000000 + 0 + 0.000 + + + + 100000000 + 0 + 0.000 + + 0 + 0.000 + + 100000000 + 1 + 1 + 1 + 0 + 0 + undef + 0.000 + 32 + 0 + 0 + 85 + + 100000000 + 1 + 1 + 1 + 0 + 0 + undef + 0.000 + 32 + 0 + 0 + 75 + 0 + ACTIVE_LOW + 0 + + 100000000 + 1 + 1 + 1 + 0 + 0 + undef + 0.000 + 32 + 0 + 0 + 33 + + 100000000 + 1 + 1 + 1 + 0 + 0 + undef + 0.000 + 32 + 0 + 0 + 60 + 0x000 + FALSE + FALSE + FALSE + FALSE + FALSE + TRUE + 0x00000 + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + TRUE + TRUE + TRUE + TRUE + TRUE + TRUE + 16KB + 2 + 256 + FALSE + TRUE + 0 + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + FALSE + 0 + 1 + 0 + Add-in_Card + 0x000 + NONE + 0x00000000 + FALSE + TRUE + TRUE + FALSE + FALSE + NONE + 3 + 2.0 + TRUE + FALSE + FALSE + 0x300 + 0x000 + 0x00 + 0x11 + 0x4 + 0x11 + 0x4 + 0x00 + 0x0 + 0x00 + 0x0 + 0x00 + 0x0 + 0x00 + 0x0 + 0x80 + 0x020000 + 0x1001 + FALSE + FALSE + FALSE + FALSE + 0x0 + FALSE + TRUE + FALSE + 0x2 + 0x300 + 0x00 + 0x00 + 0x00 + 0x00 + 0x00 + 0x00 + 0x00 + 0x00 + 0x300 + 0x00 + FALSE + 0x1 + 0 + TRUE + 0x300 + 0x00 + 0 + 0x00000000 + 0 + 0x00000000 + 0x000 + 5 + 0xC0 + 0x274 + 0x90 + FALSE + FALSE + FALSE + FALSE + FALSE + 0x300 + 0x00000 + 0x00000 + 0x00000 + 0x00 + 0x000 + 0x00 + 0x0 + 0x00 + 0x0 + 0x00 + 0x0 + 0x00 + 0x0 + 0x00 + 0x0 + 0x00 + 0x0 + 0x0000 + 0x300 + 0x0000 + 0x0 + 0x0000 + 0x0000 + 0x00000553 + 0x0000 + 0x1001 + 0x1234 + TRUE + FALSE + FALSE + 0x300 + 0x0 + 0x0 + 0x000 + 0x1 + 0x000 + 0x1234 + FALSE + FALSE + 0x000 + 0x000 + 0x00 + 0x0 + 0x00 + 0x0 + 0x00 + 0x0 + 0x00 + 0x0 + 0x00 + 0x0 + 0x00 + 0x0 + 0x80 + 0x058000 + 0x8011 + 0x2 + 0x000 + 0x00 + 0x00 + 0x00 + 0x00 + 0x00 + 0x00 + 0x00 + 0x00 + 0x000 + 0x00 + FALSE + 0x0 + 0x00 + 0 + 0x00000000 + 0 + 0x00000000 + 0x000 + 0 + 0x00 + 0x000 + 0x00 + FALSE + 0x000 + 0x00000 + 0x00000 + 0x00000 + 0x00 + 0x00 + 0x0 + 0x00 + 0x0 + 0x00 + 0x0 + 0x00 + 0x0 + 0x00 + 0x0 + 0x00 + 0x0 + 0x0000 + 0x000 + 0x0000 + 0x0 + 0x0000 + 0x0001 + 0x00000553 + 0x0000 + 0x0007 + TRUE + FALSE + FALSE + 0x000 + 0x0 + 0x0 + 0x000 + 0x1 + 4 + FALSE + 2 + FALSE + 4 + 8 + TRUE + FALSE + TRUE + 0 + 0 + GTH_Quad_225 + 1 + 0x00000000 + FALSE + 0 + 0x000 + 0x00 + 0x028 + 0x20 + 0x198 + 0x20 + FALSE + FALSE + 0x0 + FALSE + TRUE + 3 + 0x000 + 0x80 + 0 + 0x00000000 + 0 + 0x00000000 + 0x000 + 0 + 0x00 + TRUE + FALSE + 0x000 + 0x0 + 0x0 + 0x000 + 0x1 + 0x000 + 0 + 0x00000000 + 0 + 0x00000000 + 0x000 + 0 + 0x00 + TRUE + FALSE + 0x000 + 0x0 + 0x0 + 0x000 + 0x1 + 0x000 + 0 + 0x00000000 + 0 + 0x00000000 + 0x000 + 0 + 0x00 + TRUE + FALSE + 0x000 + 0x0 + 0x0 + 0x000 + 0x1 + 0x000 + 0 + 0x00000000 + 0 + 0x00000000 + 0x000 + 0 + 0x00 + TRUE + FALSE + 0x000 + 0x0 + 0x0 + 0x000 + 0x1 + 0x000 + 0 + 0x00000000 + 0 + 0x00000000 + 0x000 + 0 + 0x00 + TRUE + FALSE + 0x000 + 0x0 + 0x0 + 0x000 + 0x1 + 0x000 + 0 + 0x00000000 + 0 + 0x00000000 + 0x000 + 0 + 0x00 + TRUE + FALSE + 0x000 + 0x0 + 0x0 + 0x000 + 0x1 + FALSE + 1 + 0 + 0 + 0 + 0 + 0 + 0 + Production + 0 + true + false + pcie3_ultrascale_0 + 15 + false + false + 020000 + 1001 + false + false + false + 00_Not_Supported + false + false + INTA + true + BAR_0 + 00000000 + BAR_0 + 00000000 + 000 + 32_vectors + false + false + false + false + 00 + 0 + N/A + 0000 + 00000553 + 0000 + 1001 + 1234 + true + false + false + 058000 + 8011 + NONE + BAR_0 + 00000000 + BAR_0 + 00000000 + 000 + 1_vector + 00 + 0 + 0 + N/A + 0001 + 00000553 + 0000 + 0007 + false + 4 + 8.0_GT/s + X8 + 100_MHz + Default + 0 + 0 + false + false + 1 + false + BAR_0 + 00000000 + BAR_0 + 00000000 + 000 + 1_vector + BAR_0 + 00000000 + BAR_0 + 00000000 + 000 + 1_vector + BAR_0 + 00000000 + BAR_0 + 00000000 + 000 + 1_vector + BAR_0 + 00000000 + BAR_0 + 00000000 + 000 + 1_vector + BAR_0 + 00000000 + BAR_0 + 00000000 + 000 + 1_vector + BAR_0 + 00000000 + BAR_0 + 00000000 + 000 + 1_vector + false + DWORD_Aligned + No_ASPM + 250 + true + 2FFFF + false + false + 256_bit + false + None + true + true + true + true + true + true + 500 + true + PCI_Express_Endpoint_device + false + false + false + false + true + false + false + false + false + false + false + false + false + False + false + false + false + false + false + false + true + 100_MHz + true + false + false + false + false + false + Internal + 1 + Add-in_Card + None + 00000000 + Basic + true + X0Y0 + true + Extreme + false + true + false + false + true + false + Megabytes + 16 + Memory + false + true + false + Megabytes + 16 + Memory + false + false + false + Megabytes + 4 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + Kilobytes + 2 + N/A + Network_controller + 02 + 00 + 00 + 512_bytes + false + false + false + Kilobytes + 2 + false + true + false + false + false + false + true + false + Kilobytes + 2 + Memory + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + Kilobytes + 2 + N/A + 0 + Ethernet_controller + false + false + true + false + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + Kilobytes + 2 + N/A + Memory_controller + 05 + 00 + 80 + 512_bytes + false + false + false + Kilobytes + 2 + true + false + false + false + false + true + false + Kilobytes + 2 + Memory + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + false + Kilobytes + 2 + N/A + false + false + Kilobytes + 2 + N/A + Other_memory_controller + false + false + QPLL1 + None + true + GTH_Quad_225 + false + ACTIVE_LOW + None + true + true + 1234 + None + virtexu + + + xcvu095 + ffva2104 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 5 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/lib b/fpga/mqnic_tdma/VCU108/fpga_10g/lib new file mode 120000 index 000000000..9512b3d5e --- /dev/null +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/lib @@ -0,0 +1 @@ +../../../lib/ \ No newline at end of file diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/common b/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/common new file mode 120000 index 000000000..449c9409c --- /dev/null +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/common @@ -0,0 +1 @@ +../../../../common/rtl/ \ No newline at end of file diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/debounce_switch.v b/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/debounce_switch.v new file mode 100644 index 000000000..bb631cc35 --- /dev/null +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/debounce_switch.v @@ -0,0 +1,89 @@ +/* + +Copyright (c) 2014-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog-2001 + +`timescale 1 ns / 1 ps + +/* + * Synchronizes switch and button inputs with a slow sampled shift register + */ +module debounce_switch #( + parameter WIDTH=1, // width of the input and output signals + parameter N=3, // length of shift register + parameter RATE=125000 // clock division factor +)( + input wire clk, + input wire rst, + input wire [WIDTH-1:0] in, + output wire [WIDTH-1:0] out +); + +reg [23:0] cnt_reg = 24'd0; + +reg [N-1:0] debounce_reg[WIDTH-1:0]; + +reg [WIDTH-1:0] state; + +/* + * The synchronized output is the state register + */ +assign out = state; + +integer k; + +always @(posedge clk or posedge rst) begin + if (rst) begin + cnt_reg <= 0; + state <= 0; + + for (k = 0; k < WIDTH; k = k + 1) begin + debounce_reg[k] <= 0; + end + end else begin + if (cnt_reg < RATE) begin + cnt_reg <= cnt_reg + 24'd1; + end else begin + cnt_reg <= 24'd0; + end + + if (cnt_reg == 24'd0) begin + for (k = 0; k < WIDTH; k = k + 1) begin + debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]}; + end + end + + for (k = 0; k < WIDTH; k = k + 1) begin + if (|debounce_reg[k] == 0) begin + state[k] <= 0; + end else if (&debounce_reg[k] == 1) begin + state[k] <= 1; + end else begin + state[k] <= state[k]; + end + end + end +end + +endmodule diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga.v b/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga.v new file mode 100644 index 000000000..e80d84e9f --- /dev/null +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga.v @@ -0,0 +1,1052 @@ +/* + +Copyright 2019, The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +The views and conclusions contained in the software and documentation are those +of the authors and should not be interpreted as representing official policies, +either expressed or implied, of The Regents of the University of California. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * FPGA top-level module + */ +module fpga ( + /* + * Clock: 100MHz LVDS + */ + input wire clk_125mhz_p, + input wire clk_125mhz_n, + + /* + * GPIO + */ + input wire btnu, + input wire btnl, + input wire btnd, + input wire btnr, + input wire btnc, + input wire [3:0] sw, + output wire [7:0] led, + + /* + * I2C for board management + */ + inout wire i2c_scl, + inout wire i2c_sda, + + /* + * PCI express + */ + input wire [7:0] pcie_rx_p, + input wire [7:0] pcie_rx_n, + output wire [7:0] pcie_tx_p, + output wire [7:0] pcie_tx_n, + input wire pcie_mgt_refclk_p, + input wire pcie_mgt_refclk_n, + input wire pcie_reset_n, + + /* + * Ethernet: QSFP28 + */ + input wire qsfp_rx1_p, + input wire qsfp_rx1_n, + input wire qsfp_rx2_p, + input wire qsfp_rx2_n, + input wire qsfp_rx3_p, + input wire qsfp_rx3_n, + input wire qsfp_rx4_p, + input wire qsfp_rx4_n, + output wire qsfp_tx1_p, + output wire qsfp_tx1_n, + output wire qsfp_tx2_p, + output wire qsfp_tx2_n, + output wire qsfp_tx3_p, + output wire qsfp_tx3_n, + output wire qsfp_tx4_p, + output wire qsfp_tx4_n, + input wire qsfp_mgt_refclk_0_p, + input wire qsfp_mgt_refclk_0_n, + // input wire qsfp_mgt_refclk_1_p, + // input wire qsfp_mgt_refclk_1_n, + // output wire qsfp_recclk_p, + // output wire qsfp_recclk_n, + output wire qsfp_modsell, + output wire qsfp_resetl, + input wire qsfp_modprsl, + input wire qsfp_intl, + output wire qsfp_lpmode +); + +parameter AXIS_PCIE_DATA_WIDTH = 256; +parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); + +// Clock and reset +wire pcie_user_clk; +wire pcie_user_reset; + +wire clk_125mhz_ibufg; +wire clk_125mhz_mmcm_out; + +// Internal 125 MHz clock +wire clk_125mhz_int; +wire rst_125mhz_int; + +// Internal 156.25 MHz clock +wire clk_156mhz_int; +wire rst_156mhz_int; + +wire mmcm_rst = pcie_user_reset; +wire mmcm_locked; +wire mmcm_clkfb; + +IBUFGDS #( + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") +) +clk_125mhz_ibufg_inst ( + .O (clk_125mhz_ibufg), + .I (clk_125mhz_p), + .IB (clk_125mhz_n) +); + +// MMCM instance +// 125 MHz in, 125 MHz out +// PFD range: 10 MHz to 500 MHz +// VCO range: 600 MHz to 1440 MHz +// M = 5, D = 1 sets Fvco = 625 MHz (in range) +// Divide by 5 to get output frequency of 125 MHz +MMCME3_BASE #( + .BANDWIDTH("OPTIMIZED"), + .CLKOUT0_DIVIDE_F(5), + .CLKOUT0_DUTY_CYCLE(0.5), + .CLKOUT0_PHASE(0), + .CLKOUT1_DIVIDE(1), + .CLKOUT1_DUTY_CYCLE(0.5), + .CLKOUT1_PHASE(0), + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.5), + .CLKOUT2_PHASE(0), + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.5), + .CLKOUT3_PHASE(0), + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.5), + .CLKOUT4_PHASE(0), + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.5), + .CLKOUT5_PHASE(0), + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.5), + .CLKOUT6_PHASE(0), + .CLKFBOUT_MULT_F(5), + .CLKFBOUT_PHASE(0), + .DIVCLK_DIVIDE(1), + .REF_JITTER1(0.010), + .CLKIN1_PERIOD(8.0), + .STARTUP_WAIT("FALSE"), + .CLKOUT4_CASCADE("FALSE") +) +clk_mmcm_inst ( + .CLKIN1(clk_125mhz_ibufg), + .CLKFBIN(mmcm_clkfb), + .RST(mmcm_rst), + .PWRDWN(1'b0), + .CLKOUT0(clk_125mhz_mmcm_out), + .CLKOUT0B(), + .CLKOUT1(), + .CLKOUT1B(), + .CLKOUT2(), + .CLKOUT2B(), + .CLKOUT3(), + .CLKOUT3B(), + .CLKOUT4(), + .CLKOUT5(), + .CLKOUT6(), + .CLKFBOUT(mmcm_clkfb), + .CLKFBOUTB(), + .LOCKED(mmcm_locked) +); + +BUFG +clk_125mhz_bufg_inst ( + .I(clk_125mhz_mmcm_out), + .O(clk_125mhz_int) +); + +sync_reset #( + .N(4) +) +sync_reset_125mhz_inst ( + .clk(clk_125mhz_int), + .rst(~mmcm_locked), + .sync_reset_out(rst_125mhz_int) +); + +// GPIO +wire btnu_int; +wire btnl_int; +wire btnd_int; +wire btnr_int; +wire btnc_int; +wire [3:0] sw_int; +wire qsfp_modprsl_int; +wire qsfp_intl_int; +wire i2c_scl_i; +wire i2c_scl_o; +wire i2c_scl_t; +wire i2c_sda_i; +wire i2c_sda_o; +wire i2c_sda_t; + +debounce_switch #( + .WIDTH(9), + .N(4), + .RATE(250000) +) +debounce_switch_inst ( + .clk(pcie_user_clk), + .rst(pcie_user_reset), + .in({btnu, + btnl, + btnd, + btnr, + btnc, + sw}), + .out({btnu_int, + btnl_int, + btnd_int, + btnr_int, + btnc_int, + sw_int}) +); + +sync_signal #( + .WIDTH(4), + .N(2) +) +sync_signal_inst ( + .clk(pcie_user_clk), + .in({qsfp_modprsl, qsfp_intl, + i2c_scl, i2c_sda}), + .out({qsfp_modprsl_int, qsfp_intl_int, + i2c_scl_i, i2c_sda_i}) +); + +assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o; +assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o; + +// PCIe +wire pcie_sys_clk; +wire pcie_sys_clk_gt; + +IBUFDS_GTE3 #( + .REFCLK_HROW_CK_SEL(2'b00) +) +ibufds_gte3_pcie_mgt_refclk_inst ( + .I (pcie_mgt_refclk_p), + .IB (pcie_mgt_refclk_n), + .CEB (1'b0), + .O (pcie_sys_clk_gt), + .ODIV2 (pcie_sys_clk) +); + +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rq_tdata; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rq_tkeep; +wire axis_rq_tlast; +wire axis_rq_tready; +wire [59:0] axis_rq_tuser; +wire axis_rq_tvalid; + +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep; +wire axis_rc_tlast; +wire axis_rc_tready; +wire [74:0] axis_rc_tuser; +wire axis_rc_tvalid; + +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep; +wire axis_cq_tlast; +wire axis_cq_tready; +wire [84:0] axis_cq_tuser; +wire axis_cq_tvalid; + +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep; +wire axis_cc_tlast; +wire axis_cc_tready; +wire [32:0] axis_cc_tuser; +wire axis_cc_tvalid; + +wire [1:0] pcie_tfc_nph_av; +wire [1:0] pcie_tfc_npd_av; + +wire [2:0] cfg_max_payload; +wire [2:0] cfg_max_read_req; + +wire [18:0] cfg_mgmt_addr; +wire cfg_mgmt_write; +wire [31:0] cfg_mgmt_write_data; +wire [3:0] cfg_mgmt_byte_enable; +wire cfg_mgmt_read; +wire [31:0] cfg_mgmt_read_data; +wire cfg_mgmt_read_write_done; + +wire [3:0] cfg_interrupt_msi_enable; +wire [7:0] cfg_interrupt_msi_vf_enable; +wire [11:0] cfg_interrupt_msi_mmenable; +wire cfg_interrupt_msi_mask_update; +wire [31:0] cfg_interrupt_msi_data; +wire [3:0] cfg_interrupt_msi_select; +wire [31:0] cfg_interrupt_msi_int; +wire [31:0] cfg_interrupt_msi_pending_status; +wire cfg_interrupt_msi_pending_status_data_enable; +wire [3:0] cfg_interrupt_msi_pending_status_function_num; +wire cfg_interrupt_msi_sent; +wire cfg_interrupt_msi_fail; +wire [2:0] cfg_interrupt_msi_attr; +wire cfg_interrupt_msi_tph_present; +wire [1:0] cfg_interrupt_msi_tph_type; +wire [8:0] cfg_interrupt_msi_tph_st_tag; +wire [3:0] cfg_interrupt_msi_function_number; + +wire status_error_cor; +wire status_error_uncor; + +pcie3_ultrascale_0 +pcie3_ultrascale_inst ( + .pci_exp_txn(pcie_tx_n), + .pci_exp_txp(pcie_tx_p), + .pci_exp_rxn(pcie_rx_n), + .pci_exp_rxp(pcie_rx_p), + .user_clk(pcie_user_clk), + .user_reset(pcie_user_reset), + .user_lnk_up(), + + .s_axis_rq_tdata(axis_rq_tdata), + .s_axis_rq_tkeep(axis_rq_tkeep), + .s_axis_rq_tlast(axis_rq_tlast), + .s_axis_rq_tready(axis_rq_tready), + .s_axis_rq_tuser(axis_rq_tuser), + .s_axis_rq_tvalid(axis_rq_tvalid), + + .m_axis_rc_tdata(axis_rc_tdata), + .m_axis_rc_tkeep(axis_rc_tkeep), + .m_axis_rc_tlast(axis_rc_tlast), + .m_axis_rc_tready(axis_rc_tready), + .m_axis_rc_tuser(axis_rc_tuser), + .m_axis_rc_tvalid(axis_rc_tvalid), + + .m_axis_cq_tdata(axis_cq_tdata), + .m_axis_cq_tkeep(axis_cq_tkeep), + .m_axis_cq_tlast(axis_cq_tlast), + .m_axis_cq_tready(axis_cq_tready), + .m_axis_cq_tuser(axis_cq_tuser), + .m_axis_cq_tvalid(axis_cq_tvalid), + + .s_axis_cc_tdata(axis_cc_tdata), + .s_axis_cc_tkeep(axis_cc_tkeep), + .s_axis_cc_tlast(axis_cc_tlast), + .s_axis_cc_tready(axis_cc_tready), + .s_axis_cc_tuser(axis_cc_tuser), + .s_axis_cc_tvalid(axis_cc_tvalid), + + .pcie_rq_seq_num(), + .pcie_rq_seq_num_vld(), + .pcie_rq_tag(), + .pcie_rq_tag_av(), + .pcie_rq_tag_vld(), + + .pcie_tfc_nph_av(pcie_tfc_nph_av), + .pcie_tfc_npd_av(pcie_tfc_npd_av), + + .pcie_cq_np_req(1'b1), + .pcie_cq_np_req_count(), + + .cfg_phy_link_down(), + .cfg_phy_link_status(), + .cfg_negotiated_width(), + .cfg_current_speed(), + .cfg_max_payload(cfg_max_payload), + .cfg_max_read_req(cfg_max_read_req), + .cfg_function_status(), + .cfg_function_power_state(), + .cfg_vf_status(), + .cfg_vf_power_state(), + .cfg_link_power_state(), + + .cfg_mgmt_addr(cfg_mgmt_addr), + .cfg_mgmt_write(cfg_mgmt_write), + .cfg_mgmt_write_data(cfg_mgmt_write_data), + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), + .cfg_mgmt_read(cfg_mgmt_read), + .cfg_mgmt_read_data(cfg_mgmt_read_data), + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), + .cfg_mgmt_type1_cfg_reg_access(1'b0), + + .cfg_err_cor_out(), + .cfg_err_nonfatal_out(), + .cfg_err_fatal_out(), + .cfg_local_error(), + .cfg_ltr_enable(), + .cfg_ltssm_state(), + .cfg_rcb_status(), + .cfg_dpa_substate_change(), + .cfg_obff_enable(), + .cfg_pl_status_change(), + .cfg_tph_requester_enable(), + .cfg_tph_st_mode(), + .cfg_vf_tph_requester_enable(), + .cfg_vf_tph_st_mode(), + + .cfg_msg_received(), + .cfg_msg_received_data(), + .cfg_msg_received_type(), + .cfg_msg_transmit(1'b0), + .cfg_msg_transmit_type(3'd0), + .cfg_msg_transmit_data(32'd0), + .cfg_msg_transmit_done(), + + .cfg_fc_ph(), + .cfg_fc_pd(), + .cfg_fc_nph(), + .cfg_fc_npd(), + .cfg_fc_cplh(), + .cfg_fc_cpld(), + .cfg_fc_sel(3'd0), + + .cfg_per_func_status_control(3'd0), + .cfg_per_func_status_data(), + .cfg_per_function_number(4'd0), + .cfg_per_function_output_request(1'b0), + .cfg_per_function_update_done(), + + .cfg_dsn(64'd0), + + .cfg_power_state_change_ack(1'b1), + .cfg_power_state_change_interrupt(), + + .cfg_err_cor_in(status_error_cor), + .cfg_err_uncor_in(status_error_uncor), + .cfg_flr_in_process(), + .cfg_flr_done(4'd0), + .cfg_vf_flr_in_process(), + .cfg_vf_flr_done(8'd0), + + .cfg_link_training_enable(1'b1), + + .cfg_interrupt_int(4'd0), + .cfg_interrupt_pending(4'd0), + .cfg_interrupt_sent(), + .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), + .cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable), + .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), + .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), + .cfg_interrupt_msi_data(cfg_interrupt_msi_data), + .cfg_interrupt_msi_select(cfg_interrupt_msi_select), + .cfg_interrupt_msi_int(cfg_interrupt_msi_int), + .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), + .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), + .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), + .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), + .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), + .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr), + .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present), + .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type), + .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag), + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + + .cfg_hot_reset_out(), + + .cfg_config_space_enable(1'b1), + .cfg_req_pm_transition_l23_ready(1'b0), + .cfg_hot_reset_in(1'b0), + + .cfg_ds_port_number(8'd0), + .cfg_ds_bus_number(8'd0), + .cfg_ds_device_number(5'd0), + .cfg_ds_function_number(3'd0), + + .cfg_subsys_vend_id(16'h1234), + + .sys_clk(pcie_sys_clk), + .sys_clk_gt(pcie_sys_clk_gt), + .sys_reset(pcie_reset_n), + .pcie_perstn1_in(1'b0), + .pcie_perstn0_out(), + .pcie_perstn1_out(), + + .int_qpll1lock_out(), + .int_qpll1outrefclk_out(), + .int_qpll1outclk_out(), + .phy_rdy_out() +); + +// XGMII 10G PHY +wire qsfp_tx_clk_1_int; +wire qsfp_tx_rst_1_int; +wire [63:0] qsfp_txd_1_int; +wire [7:0] qsfp_txc_1_int; +wire qsfp_tx_prbs31_enable_1_int; +wire qsfp_rx_clk_1_int; +wire qsfp_rx_rst_1_int; +wire [63:0] qsfp_rxd_1_int; +wire [7:0] qsfp_rxc_1_int; +wire qsfp_rx_prbs31_enable_1_int; +wire [6:0] qsfp_rx_error_count_1_int; +wire qsfp_tx_clk_2_int; +wire qsfp_tx_rst_2_int; +wire [63:0] qsfp_txd_2_int; +wire [7:0] qsfp_txc_2_int; +wire qsfp_tx_prbs31_enable_2_int; +wire qsfp_rx_clk_2_int; +wire qsfp_rx_rst_2_int; +wire [63:0] qsfp_rxd_2_int; +wire [7:0] qsfp_rxc_2_int; +wire qsfp_rx_prbs31_enable_2_int; +wire [6:0] qsfp_rx_error_count_2_int; +wire qsfp_tx_clk_3_int; +wire qsfp_tx_rst_3_int; +wire [63:0] qsfp_txd_3_int; +wire [7:0] qsfp_txc_3_int; +wire qsfp_tx_prbs31_enable_3_int; +wire qsfp_rx_clk_3_int; +wire qsfp_rx_rst_3_int; +wire [63:0] qsfp_rxd_3_int; +wire [7:0] qsfp_rxc_3_int; +wire qsfp_rx_prbs31_enable_3_int; +wire [6:0] qsfp_rx_error_count_3_int; +wire qsfp_tx_clk_4_int; +wire qsfp_tx_rst_4_int; +wire [63:0] qsfp_txd_4_int; +wire [7:0] qsfp_txc_4_int; +wire qsfp_tx_prbs31_enable_4_int; +wire qsfp_rx_clk_4_int; +wire qsfp_rx_rst_4_int; +wire [63:0] qsfp_rxd_4_int; +wire [7:0] qsfp_rxc_4_int; +wire qsfp_rx_prbs31_enable_4_int; +wire [6:0] qsfp_rx_error_count_4_int; + +wire qsfp_rx_block_lock_1; +wire qsfp_rx_block_lock_2; +wire qsfp_rx_block_lock_3; +wire qsfp_rx_block_lock_4; + +wire qsfp_mgt_refclk_0; + +wire [3:0] gt_txclkout; +wire gt_txusrclk; + +wire [3:0] gt_rxclkout; +wire [3:0] gt_rxusrclk; + +wire gt_reset_tx_done; +wire gt_reset_rx_done; + +wire [3:0] gt_txprgdivresetdone; +wire [3:0] gt_txpmaresetdone; +wire [3:0] gt_rxprgdivresetdone; +wire [3:0] gt_rxpmaresetdone; + +wire gt_tx_reset = ~((>_txprgdivresetdone) & (>_txpmaresetdone)); +wire gt_rx_reset = ~>_rxpmaresetdone; + +reg gt_userclk_tx_active = 1'b0; +reg [3:0] gt_userclk_rx_active = 1'b0; + +IBUFDS_GTE3 ibufds_gte3_qsfp_mgt_refclk_0_inst ( + .I (qsfp_mgt_refclk_0_p), + .IB (qsfp_mgt_refclk_0_n), + .CEB (1'b0), + .O (qsfp_mgt_refclk_0), + .ODIV2 () +); + + +BUFG_GT bufg_gt_tx_usrclk_inst ( + .CE (1'b1), + .CEMASK (1'b0), + .CLR (gt_tx_reset), + .CLRMASK (1'b0), + .DIV (3'd0), + .I (gt_txclkout[0]), + .O (gt_txusrclk) +); + +assign clk_156mhz_int = gt_txusrclk; + +always @(posedge gt_txusrclk, posedge gt_tx_reset) begin + if (gt_tx_reset) begin + gt_userclk_tx_active <= 1'b0; + end else begin + gt_userclk_tx_active <= 1'b1; + end +end + +genvar n; + +generate + +for (n = 0; n < 4; n = n + 1) begin + + BUFG_GT bufg_gt_rx_usrclk_inst ( + .CE (1'b1), + .CEMASK (1'b0), + .CLR (gt_rx_reset), + .CLRMASK (1'b0), + .DIV (3'd0), + .I (gt_rxclkout[n]), + .O (gt_rxusrclk[n]) + ); + + always @(posedge gt_rxusrclk[n], posedge gt_rx_reset) begin + if (gt_rx_reset) begin + gt_userclk_rx_active[n] <= 1'b0; + end else begin + gt_userclk_rx_active[n] <= 1'b1; + end + end + +end + +endgenerate + +sync_reset #( + .N(4) +) +sync_reset_156mhz_inst ( + .clk(clk_156mhz_int), + .rst(~gt_reset_tx_done), + .sync_reset_out(rst_156mhz_int) +); + +wire [5:0] qsfp_gt_txheader_1; +wire [127:0] qsfp_gt_txdata_1; +wire qsfp_gt_rxgearboxslip_1; +wire [5:0] qsfp_gt_rxheader_1; +wire [1:0] qsfp_gt_rxheadervalid_1; +wire [127:0] qsfp_gt_rxdata_1; +wire [1:0] qsfp_gt_rxdatavalid_1; + +wire [5:0] qsfp_gt_txheader_2; +wire [127:0] qsfp_gt_txdata_2; +wire qsfp_gt_rxgearboxslip_2; +wire [5:0] qsfp_gt_rxheader_2; +wire [1:0] qsfp_gt_rxheadervalid_2; +wire [127:0] qsfp_gt_rxdata_2; +wire [1:0] qsfp_gt_rxdatavalid_2; + +wire [5:0] qsfp_gt_txheader_3; +wire [127:0] qsfp_gt_txdata_3; +wire qsfp_gt_rxgearboxslip_3; +wire [5:0] qsfp_gt_rxheader_3; +wire [1:0] qsfp_gt_rxheadervalid_3; +wire [127:0] qsfp_gt_rxdata_3; +wire [1:0] qsfp_gt_rxdatavalid_3; + +wire [5:0] qsfp_gt_txheader_4; +wire [127:0] qsfp_gt_txdata_4; +wire qsfp_gt_rxgearboxslip_4; +wire [5:0] qsfp_gt_rxheader_4; +wire [1:0] qsfp_gt_rxheadervalid_4; +wire [127:0] qsfp_gt_rxdata_4; +wire [1:0] qsfp_gt_rxdatavalid_4; + +gtwizard_ultrascale_0 +qsfp_gty_inst ( + .gtwiz_userclk_tx_active_in(>_userclk_tx_active), + .gtwiz_userclk_rx_active_in(>_userclk_rx_active), + + .gtwiz_reset_clk_freerun_in(clk_125mhz_int), + .gtwiz_reset_all_in(rst_125mhz_int), + + .gtwiz_reset_tx_pll_and_datapath_in(1'b0), + .gtwiz_reset_tx_datapath_in(1'b0), + + .gtwiz_reset_rx_pll_and_datapath_in(1'b0), + .gtwiz_reset_rx_datapath_in(1'b0), + + .gtwiz_reset_rx_cdr_stable_out(), + + .gtwiz_reset_tx_done_out(gt_reset_tx_done), + .gtwiz_reset_rx_done_out(gt_reset_rx_done), + + .gtrefclk00_in({1{qsfp_mgt_refclk_0}}), + + .qpll0outclk_out(), + .qpll0outrefclk_out(), + + .gtyrxn_in({qsfp_rx4_n, qsfp_rx3_n, qsfp_rx2_n, qsfp_rx1_n}), + .gtyrxp_in({qsfp_rx4_p, qsfp_rx3_p, qsfp_rx2_p, qsfp_rx1_p}), + + .rxusrclk_in(gt_rxusrclk), + .rxusrclk2_in(gt_rxusrclk), + + .txdata_in({qsfp_gt_txdata_4, qsfp_gt_txdata_3, qsfp_gt_txdata_2, qsfp_gt_txdata_1}), + .txheader_in({qsfp_gt_txheader_4, qsfp_gt_txheader_3, qsfp_gt_txheader_2, qsfp_gt_txheader_1}), + .txsequence_in({4{1'b0}}), + + .txusrclk_in({4{gt_txusrclk}}), + .txusrclk2_in({4{gt_txusrclk}}), + + .gtpowergood_out(), + + .gtytxn_out({qsfp_tx4_n, qsfp_tx3_n, qsfp_tx2_n, qsfp_tx1_n}), + .gtytxp_out({qsfp_tx4_p, qsfp_tx3_p, qsfp_tx2_p, qsfp_tx1_p}), + + .rxgearboxslip_in({qsfp_gt_rxgearboxslip_4, qsfp_gt_rxgearboxslip_3, qsfp_gt_rxgearboxslip_2, qsfp_gt_rxgearboxslip_1}), + .rxdata_out({qsfp_gt_rxdata_4, qsfp_gt_rxdata_3, qsfp_gt_rxdata_2, qsfp_gt_rxdata_1}), + .rxdatavalid_out({qsfp_gt_rxdatavalid_4, qsfp_gt_rxdatavalid_3, qsfp_gt_rxdatavalid_2, qsfp_gt_rxdatavalid_1}), + .rxheader_out({qsfp_gt_rxheader_4, qsfp_gt_rxheader_3, qsfp_gt_rxheader_2, qsfp_gt_rxheader_1}), + .rxheadervalid_out({qsfp_gt_rxheadervalid_4, qsfp_gt_rxheadervalid_3, qsfp_gt_rxheadervalid_2, qsfp_gt_rxheadervalid_1}), + .rxoutclk_out(gt_rxclkout), + .rxpmaresetdone_out(gt_rxpmaresetdone), + .rxprgdivresetdone_out(gt_rxprgdivresetdone), + .rxstartofseq_out(), + + .txoutclk_out(gt_txclkout), + .txpmaresetdone_out(gt_txpmaresetdone), + .txprgdivresetdone_out(gt_txprgdivresetdone) +); + +assign qsfp_tx_clk_1_int = clk_156mhz_int; +assign qsfp_tx_rst_1_int = rst_156mhz_int; + +assign qsfp_rx_clk_1_int = gt_rxusrclk[0]; + +sync_reset #( + .N(4) +) +qsfp_rx_rst_1_reset_sync_inst ( + .clk(qsfp_rx_clk_1_int), + .rst(~gt_reset_rx_done), + .sync_reset_out(qsfp_rx_rst_1_int) +); + +eth_phy_10g #( + .BIT_REVERSE(1), + .PRBS31_ENABLE(1) +) +qsfp_phy_1_inst ( + .tx_clk(qsfp_tx_clk_1_int), + .tx_rst(qsfp_tx_rst_1_int), + .rx_clk(qsfp_rx_clk_1_int), + .rx_rst(qsfp_rx_rst_1_int), + .xgmii_txd(qsfp_txd_1_int), + .xgmii_txc(qsfp_txc_1_int), + .xgmii_rxd(qsfp_rxd_1_int), + .xgmii_rxc(qsfp_rxc_1_int), + .serdes_tx_data(qsfp_gt_txdata_1), + .serdes_tx_hdr(qsfp_gt_txheader_1), + .serdes_rx_data(qsfp_gt_rxdata_1), + .serdes_rx_hdr(qsfp_gt_rxheader_1), + .serdes_rx_bitslip(qsfp_gt_rxgearboxslip_1), + .rx_error_count(qsfp_rx_error_count_1_int), + .rx_block_lock(qsfp_rx_block_lock_1), + .rx_high_ber(), + .rx_prbs31_enable(qsfp_rx_prbs31_enable_1_int), + .tx_prbs31_enable(qsfp_tx_prbs31_enable_1_int) +); + +assign qsfp_tx_clk_2_int = clk_156mhz_int; +assign qsfp_tx_rst_2_int = rst_156mhz_int; + +assign qsfp_rx_clk_2_int = gt_rxusrclk[1]; + +sync_reset #( + .N(4) +) +qsfp_rx_rst_2_reset_sync_inst ( + .clk(qsfp_rx_clk_2_int), + .rst(~gt_reset_rx_done), + .sync_reset_out(qsfp_rx_rst_2_int) +); + +eth_phy_10g #( + .BIT_REVERSE(1), + .PRBS31_ENABLE(1) +) +qsfp_phy_2_inst ( + .tx_clk(qsfp_tx_clk_2_int), + .tx_rst(qsfp_tx_rst_2_int), + .rx_clk(qsfp_rx_clk_2_int), + .rx_rst(qsfp_rx_rst_2_int), + .xgmii_txd(qsfp_txd_2_int), + .xgmii_txc(qsfp_txc_2_int), + .xgmii_rxd(qsfp_rxd_2_int), + .xgmii_rxc(qsfp_rxc_2_int), + .serdes_tx_data(qsfp_gt_txdata_2), + .serdes_tx_hdr(qsfp_gt_txheader_2), + .serdes_rx_data(qsfp_gt_rxdata_2), + .serdes_rx_hdr(qsfp_gt_rxheader_2), + .serdes_rx_bitslip(qsfp_gt_rxgearboxslip_2), + .rx_error_count(qsfp_rx_error_count_2_int), + .rx_block_lock(qsfp_rx_block_lock_2), + .rx_high_ber(), + .rx_prbs31_enable(qsfp_rx_prbs31_enable_2_int), + .tx_prbs31_enable(qsfp_tx_prbs31_enable_2_int) +); + +assign qsfp_tx_clk_3_int = clk_156mhz_int; +assign qsfp_tx_rst_3_int = rst_156mhz_int; + +assign qsfp_rx_clk_3_int = gt_rxusrclk[2]; + +sync_reset #( + .N(4) +) +qsfp_rx_rst_3_reset_sync_inst ( + .clk(qsfp_rx_clk_3_int), + .rst(~gt_reset_rx_done), + .sync_reset_out(qsfp_rx_rst_3_int) +); + +eth_phy_10g #( + .BIT_REVERSE(1), + .PRBS31_ENABLE(1) +) +qsfp_phy_3_inst ( + .tx_clk(qsfp_tx_clk_3_int), + .tx_rst(qsfp_tx_rst_3_int), + .rx_clk(qsfp_rx_clk_3_int), + .rx_rst(qsfp_rx_rst_3_int), + .xgmii_txd(qsfp_txd_3_int), + .xgmii_txc(qsfp_txc_3_int), + .xgmii_rxd(qsfp_rxd_3_int), + .xgmii_rxc(qsfp_rxc_3_int), + .serdes_tx_data(qsfp_gt_txdata_3), + .serdes_tx_hdr(qsfp_gt_txheader_3), + .serdes_rx_data(qsfp_gt_rxdata_3), + .serdes_rx_hdr(qsfp_gt_rxheader_3), + .serdes_rx_bitslip(qsfp_gt_rxgearboxslip_3), + .rx_error_count(qsfp_rx_error_count_3_int), + .rx_block_lock(qsfp_rx_block_lock_3), + .rx_high_ber(), + .rx_prbs31_enable(qsfp_rx_prbs31_enable_3_int), + .tx_prbs31_enable(qsfp_tx_prbs31_enable_3_int) +); + +assign qsfp_tx_clk_4_int = clk_156mhz_int; +assign qsfp_tx_rst_4_int = rst_156mhz_int; + +assign qsfp_rx_clk_4_int = gt_rxusrclk[3]; + +sync_reset #( + .N(4) +) +qsfp_rx_rst_4_reset_sync_inst ( + .clk(qsfp_rx_clk_4_int), + .rst(~gt_reset_rx_done), + .sync_reset_out(qsfp_rx_rst_4_int) +); + +eth_phy_10g #( + .BIT_REVERSE(1), + .PRBS31_ENABLE(1) +) +qsfp_phy_4_inst ( + .tx_clk(qsfp_tx_clk_4_int), + .tx_rst(qsfp_tx_rst_4_int), + .rx_clk(qsfp_rx_clk_4_int), + .rx_rst(qsfp_rx_rst_4_int), + .xgmii_txd(qsfp_txd_4_int), + .xgmii_txc(qsfp_txc_4_int), + .xgmii_rxd(qsfp_rxd_4_int), + .xgmii_rxc(qsfp_rxc_4_int), + .serdes_tx_data(qsfp_gt_txdata_4), + .serdes_tx_hdr(qsfp_gt_txheader_4), + .serdes_rx_data(qsfp_gt_rxdata_4), + .serdes_rx_hdr(qsfp_gt_rxheader_4), + .serdes_rx_bitslip(qsfp_gt_rxgearboxslip_4), + .rx_error_count(qsfp_rx_error_count_4_int), + .rx_block_lock(qsfp_rx_block_lock_4), + .rx_high_ber(), + .rx_prbs31_enable(qsfp_rx_prbs31_enable_4_int), + .tx_prbs31_enable(qsfp_tx_prbs31_enable_4_int) +); + +fpga_core #( + .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH) +) +core_inst ( + /* + * Clock: 156.25 MHz, 250 MHz + * Synchronous reset + */ + .clk_156mhz(clk_156mhz_int), + .rst_156mhz(rst_156mhz_int), + .clk_250mhz(pcie_user_clk), + .rst_250mhz(pcie_user_reset), + + /* + * GPIO + */ + .btnu(btnu_int), + .btnl(btnl_int), + .btnd(btnd_int), + .btnr(btnr_int), + .btnc(btnc_int), + .sw(sw_int), + .led(led), + + /* + * I2C + */ + .i2c_scl_i(i2c_scl_i), + .i2c_scl_o(i2c_scl_o), + .i2c_scl_t(i2c_scl_t), + .i2c_sda_i(i2c_sda_i), + .i2c_sda_o(i2c_sda_o), + .i2c_sda_t(i2c_sda_t), + + /* + * PCIe + */ + .m_axis_rq_tdata(axis_rq_tdata), + .m_axis_rq_tkeep(axis_rq_tkeep), + .m_axis_rq_tlast(axis_rq_tlast), + .m_axis_rq_tready(axis_rq_tready), + .m_axis_rq_tuser(axis_rq_tuser), + .m_axis_rq_tvalid(axis_rq_tvalid), + + .s_axis_rc_tdata(axis_rc_tdata), + .s_axis_rc_tkeep(axis_rc_tkeep), + .s_axis_rc_tlast(axis_rc_tlast), + .s_axis_rc_tready(axis_rc_tready), + .s_axis_rc_tuser(axis_rc_tuser), + .s_axis_rc_tvalid(axis_rc_tvalid), + + .s_axis_cq_tdata(axis_cq_tdata), + .s_axis_cq_tkeep(axis_cq_tkeep), + .s_axis_cq_tlast(axis_cq_tlast), + .s_axis_cq_tready(axis_cq_tready), + .s_axis_cq_tuser(axis_cq_tuser), + .s_axis_cq_tvalid(axis_cq_tvalid), + + .m_axis_cc_tdata(axis_cc_tdata), + .m_axis_cc_tkeep(axis_cc_tkeep), + .m_axis_cc_tlast(axis_cc_tlast), + .m_axis_cc_tready(axis_cc_tready), + .m_axis_cc_tuser(axis_cc_tuser), + .m_axis_cc_tvalid(axis_cc_tvalid), + + .pcie_tfc_nph_av(pcie_tfc_nph_av), + .pcie_tfc_npd_av(pcie_tfc_npd_av), + + .cfg_max_payload(cfg_max_payload), + .cfg_max_read_req(cfg_max_read_req), + + .cfg_mgmt_addr(cfg_mgmt_addr), + .cfg_mgmt_write(cfg_mgmt_write), + .cfg_mgmt_write_data(cfg_mgmt_write_data), + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), + .cfg_mgmt_read(cfg_mgmt_read), + .cfg_mgmt_read_data(cfg_mgmt_read_data), + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), + + .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), + .cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable), + .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), + .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), + .cfg_interrupt_msi_data(cfg_interrupt_msi_data), + .cfg_interrupt_msi_select(cfg_interrupt_msi_select), + .cfg_interrupt_msi_int(cfg_interrupt_msi_int), + .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), + .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), + .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), + .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), + .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), + .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr), + .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present), + .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type), + .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag), + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + + .status_error_cor(status_error_cor), + .status_error_uncor(status_error_uncor), + + /* + * Ethernet: QSFP28 + */ + .qsfp_tx_clk_1(qsfp_tx_clk_1_int), + .qsfp_tx_rst_1(qsfp_tx_rst_1_int), + .qsfp_txd_1(qsfp_txd_1_int), + .qsfp_txc_1(qsfp_txc_1_int), + .qsfp_tx_prbs31_enable_1(qsfp_tx_prbs31_enable_1_int), + .qsfp_rx_clk_1(qsfp_rx_clk_1_int), + .qsfp_rx_rst_1(qsfp_rx_rst_1_int), + .qsfp_rxd_1(qsfp_rxd_1_int), + .qsfp_rxc_1(qsfp_rxc_1_int), + .qsfp_rx_prbs31_enable_1(qsfp_rx_prbs31_enable_1_int), + .qsfp_rx_error_count_1(qsfp_rx_error_count_1_int), + .qsfp_tx_clk_2(qsfp_tx_clk_2_int), + .qsfp_tx_rst_2(qsfp_tx_rst_2_int), + .qsfp_txd_2(qsfp_txd_2_int), + .qsfp_txc_2(qsfp_txc_2_int), + .qsfp_tx_prbs31_enable_2(qsfp_tx_prbs31_enable_2_int), + .qsfp_rx_clk_2(qsfp_rx_clk_2_int), + .qsfp_rx_rst_2(qsfp_rx_rst_2_int), + .qsfp_rxd_2(qsfp_rxd_2_int), + .qsfp_rxc_2(qsfp_rxc_2_int), + .qsfp_rx_prbs31_enable_2(qsfp_rx_prbs31_enable_2_int), + .qsfp_rx_error_count_2(qsfp_rx_error_count_2_int), + .qsfp_tx_clk_3(qsfp_tx_clk_3_int), + .qsfp_tx_rst_3(qsfp_tx_rst_3_int), + .qsfp_txd_3(qsfp_txd_3_int), + .qsfp_txc_3(qsfp_txc_3_int), + .qsfp_tx_prbs31_enable_3(qsfp_tx_prbs31_enable_3_int), + .qsfp_rx_clk_3(qsfp_rx_clk_3_int), + .qsfp_rx_rst_3(qsfp_rx_rst_3_int), + .qsfp_rxd_3(qsfp_rxd_3_int), + .qsfp_rxc_3(qsfp_rxc_3_int), + .qsfp_rx_prbs31_enable_3(qsfp_rx_prbs31_enable_3_int), + .qsfp_rx_error_count_3(qsfp_rx_error_count_3_int), + .qsfp_tx_clk_4(qsfp_tx_clk_4_int), + .qsfp_tx_rst_4(qsfp_tx_rst_4_int), + .qsfp_txd_4(qsfp_txd_4_int), + .qsfp_txc_4(qsfp_txc_4_int), + .qsfp_tx_prbs31_enable_4(qsfp_tx_prbs31_enable_4_int), + .qsfp_rx_clk_4(qsfp_rx_clk_4_int), + .qsfp_rx_rst_4(qsfp_rx_rst_4_int), + .qsfp_rxd_4(qsfp_rxd_4_int), + .qsfp_rxc_4(qsfp_rxc_4_int), + .qsfp_rx_prbs31_enable_4(qsfp_rx_prbs31_enable_4_int), + .qsfp_rx_error_count_4(qsfp_rx_error_count_4_int), + + .qsfp_modprsl(qsfp_modprsl_int), + .qsfp_modsell(qsfp_modsell), + .qsfp_resetl(qsfp_resetl), + .qsfp_intl(qsfp_intl_int), + .qsfp_lpmode(qsfp_lpmode) +); + +endmodule diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v b/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v new file mode 100644 index 000000000..e0f9004be --- /dev/null +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v @@ -0,0 +1,2286 @@ +/* + +Copyright 2019, The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +The views and conclusions contained in the software and documentation are those +of the authors and should not be interpreted as representing official policies, +either expressed or implied, of The Regents of the University of California. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * FPGA core logic + */ +module fpga_core # +( + parameter TARGET = "XILINX", + parameter AXIS_PCIE_DATA_WIDTH = 256, + parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32) +) +( + /* + * Clock: 156.25 MHz, 250 MHz + * Synchronous reset + */ + input wire clk_156mhz, + input wire rst_156mhz, + input wire clk_250mhz, + input wire rst_250mhz, + + /* + * GPIO + */ + input wire btnu, + input wire btnl, + input wire btnd, + input wire btnr, + input wire btnc, + input wire [3:0] sw, + output wire [7:0] led, + + /* + * I2C + */ + input wire i2c_scl_i, + output wire i2c_scl_o, + output wire i2c_scl_t, + input wire i2c_sda_i, + output wire i2c_sda_o, + output wire i2c_sda_t, + + /* + * PCIe + */ + output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata, + output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep, + output wire m_axis_rq_tlast, + input wire m_axis_rq_tready, + output wire [59:0] m_axis_rq_tuser, + output wire m_axis_rq_tvalid, + + input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata, + input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep, + input wire s_axis_rc_tlast, + output wire s_axis_rc_tready, + input wire [74:0] s_axis_rc_tuser, + input wire s_axis_rc_tvalid, + + input wire [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata, + input wire [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep, + input wire s_axis_cq_tlast, + output wire s_axis_cq_tready, + input wire [84:0] s_axis_cq_tuser, + input wire s_axis_cq_tvalid, + + output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata, + output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep, + output wire m_axis_cc_tlast, + input wire m_axis_cc_tready, + output wire [32:0] m_axis_cc_tuser, + output wire m_axis_cc_tvalid, + + input wire [1:0] pcie_tfc_nph_av, + input wire [1:0] pcie_tfc_npd_av, + + input wire [2:0] cfg_max_payload, + input wire [2:0] cfg_max_read_req, + + output wire [18:0] cfg_mgmt_addr, + output wire cfg_mgmt_write, + output wire [31:0] cfg_mgmt_write_data, + output wire [3:0] cfg_mgmt_byte_enable, + output wire cfg_mgmt_read, + input wire [31:0] cfg_mgmt_read_data, + input wire cfg_mgmt_read_write_done, + + input wire [3:0] cfg_interrupt_msi_enable, + input wire [7:0] cfg_interrupt_msi_vf_enable, + input wire [11:0] cfg_interrupt_msi_mmenable, + input wire cfg_interrupt_msi_mask_update, + input wire [31:0] cfg_interrupt_msi_data, + output wire [3:0] cfg_interrupt_msi_select, + output wire [31:0] cfg_interrupt_msi_int, + output wire [31:0] cfg_interrupt_msi_pending_status, + output wire cfg_interrupt_msi_pending_status_data_enable, + output wire [3:0] cfg_interrupt_msi_pending_status_function_num, + input wire cfg_interrupt_msi_sent, + input wire cfg_interrupt_msi_fail, + output wire [2:0] cfg_interrupt_msi_attr, + output wire cfg_interrupt_msi_tph_present, + output wire [1:0] cfg_interrupt_msi_tph_type, + output wire [8:0] cfg_interrupt_msi_tph_st_tag, + output wire [3:0] cfg_interrupt_msi_function_number, + + output wire status_error_cor, + output wire status_error_uncor, + + /* + * Ethernet: QSFP28 + */ + input wire qsfp_tx_clk_1, + input wire qsfp_tx_rst_1, + output wire [63:0] qsfp_txd_1, + output wire [7:0] qsfp_txc_1, + output wire qsfp_tx_prbs31_enable_1, + input wire qsfp_rx_clk_1, + input wire qsfp_rx_rst_1, + input wire [63:0] qsfp_rxd_1, + input wire [7:0] qsfp_rxc_1, + output wire qsfp_rx_prbs31_enable_1, + input wire [6:0] qsfp_rx_error_count_1, + input wire qsfp_tx_clk_2, + input wire qsfp_tx_rst_2, + output wire [63:0] qsfp_txd_2, + output wire [7:0] qsfp_txc_2, + output wire qsfp_tx_prbs31_enable_2, + input wire qsfp_rx_clk_2, + input wire qsfp_rx_rst_2, + input wire [63:0] qsfp_rxd_2, + input wire [7:0] qsfp_rxc_2, + output wire qsfp_rx_prbs31_enable_2, + input wire [6:0] qsfp_rx_error_count_2, + input wire qsfp_tx_clk_3, + input wire qsfp_tx_rst_3, + output wire [63:0] qsfp_txd_3, + output wire [7:0] qsfp_txc_3, + output wire qsfp_tx_prbs31_enable_3, + input wire qsfp_rx_clk_3, + input wire qsfp_rx_rst_3, + input wire [63:0] qsfp_rxd_3, + input wire [7:0] qsfp_rxc_3, + output wire qsfp_rx_prbs31_enable_3, + input wire [6:0] qsfp_rx_error_count_3, + input wire qsfp_tx_clk_4, + input wire qsfp_tx_rst_4, + output wire [63:0] qsfp_txd_4, + output wire [7:0] qsfp_txc_4, + output wire qsfp_tx_prbs31_enable_4, + input wire qsfp_rx_clk_4, + input wire qsfp_rx_rst_4, + input wire [63:0] qsfp_rxd_4, + input wire [7:0] qsfp_rxc_4, + output wire qsfp_rx_prbs31_enable_4, + input wire [6:0] qsfp_rx_error_count_4, + + input wire qsfp_modprsl, + output wire qsfp_modsell, + output wire qsfp_resetl, + input wire qsfp_intl, + output wire qsfp_lpmode, + + /* + * BPI Flash + */ + input wire [15:0] flash_dq_i, + output wire [15:0] flash_dq_o, + output wire flash_dq_oe, + output wire [22:0] flash_addr, + output wire flash_region, + output wire flash_region_oe, + output wire flash_ce_n, + output wire flash_oe_n, + output wire flash_we_n, + output wire flash_adv_n +); + +parameter PCIE_ADDR_WIDTH = 64; + +// AXI lite interface parameters +parameter AXIL_DATA_WIDTH = 32; +parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8); +parameter AXIL_ADDR_WIDTH = 24; + +// AXI interface parameters +parameter AXI_ID_WIDTH = 8; +parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH; +parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8); +parameter AXI_ADDR_WIDTH = 24; + +// AXI stream interface parameters +parameter AXIS_DATA_WIDTH = AXI_DATA_WIDTH; +parameter AXIS_KEEP_WIDTH = AXI_STRB_WIDTH; + +// PCIe DMA parameters +parameter PCIE_DMA_LEN_WIDTH = 16; +parameter PCIE_DMA_TAG_WIDTH = 16; + +// PHC parameters +parameter PTP_PERIOD_NS_WIDTH = 4; +parameter PTP_OFFSET_NS_WIDTH = 32; +parameter PTP_FNS_WIDTH = 32; +parameter PTP_PERIOD_NS = 4'd4; +parameter PTP_PERIOD_FNS = 32'd0; + +// FW and board IDs +parameter FW_ID = 32'd0; +parameter FW_VER = {16'd0, 16'd1}; +parameter BOARD_ID = {16'h10ee, 16'h806c}; +parameter BOARD_VER = {16'd0, 16'd1}; + +// Structural parameters +parameter IF_COUNT = 1; +parameter PORTS_PER_IF = 1; + +parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF; + +// Queue manager parameters (interface) +parameter TX_OP_TABLE_SIZE = 16; +parameter RX_OP_TABLE_SIZE = 16; +parameter TX_CPL_OP_TABLE_SIZE = 16; +parameter RX_CPL_OP_TABLE_SIZE = 16; +parameter TX_QUEUE_INDEX_WIDTH = 6; +parameter RX_QUEUE_INDEX_WIDTH = 6; +parameter TX_CPL_QUEUE_INDEX_WIDTH = 6; +parameter RX_CPL_QUEUE_INDEX_WIDTH = 6; + +// TX and RX engine parameters (port) +parameter TX_DESC_TABLE_SIZE = 16; +parameter TX_PKT_TABLE_SIZE = 8; +parameter RX_DESC_TABLE_SIZE = 16; +parameter RX_PKT_TABLE_SIZE = 8; + +// Scheduler parameters (port) +parameter TX_SCHEDULER = "TDMA_RR"; +parameter TDMA_INDEX_WIDTH = 6; + +// Timstamping parameters (port) +parameter LOGIC_PTP_PERIOD_NS = 6'h4; +parameter LOGIC_PTP_PERIOD_FNS = 16'h0000; +parameter IF_PTP_PERIOD_NS = 6'h6; +parameter IF_PTP_PERIOD_FNS = 16'h6666; +parameter PTP_TS_ENABLE = 1; +parameter PTP_TS_WIDTH = 96; +parameter TX_PTP_TS_FIFO_DEPTH = 32; +parameter RX_PTP_TS_FIFO_DEPTH = 32; + +// Interface parameters (port) +parameter TX_CHECKSUM_ENABLE = 1; +parameter RX_CHECKSUM_ENABLE = 1; +parameter ENABLE_PADDING = 1; +parameter ENABLE_DIC = 1; +parameter MIN_FRAME_LENGTH = 64; +parameter TX_FIFO_DEPTH = 32768; +parameter RX_FIFO_DEPTH = 32768; + +// AXI lite connections +wire [AXIL_ADDR_WIDTH-1:0] axil_pcie_awaddr; +wire [2:0] axil_pcie_awprot; +wire axil_pcie_awvalid; +wire axil_pcie_awready; +wire [AXIL_DATA_WIDTH-1:0] axil_pcie_wdata; +wire [AXIL_STRB_WIDTH-1:0] axil_pcie_wstrb; +wire axil_pcie_wvalid; +wire axil_pcie_wready; +wire [1:0] axil_pcie_bresp; +wire axil_pcie_bvalid; +wire axil_pcie_bready; +wire [AXIL_ADDR_WIDTH-1:0] axil_pcie_araddr; +wire [2:0] axil_pcie_arprot; +wire axil_pcie_arvalid; +wire axil_pcie_arready; +wire [AXIL_DATA_WIDTH-1:0] axil_pcie_rdata; +wire [1:0] axil_pcie_rresp; +wire axil_pcie_rvalid; +wire axil_pcie_rready; + +wire [AXIL_ADDR_WIDTH-1:0] axil_csr_awaddr; +wire [2:0] axil_csr_awprot; +wire axil_csr_awvalid; +wire axil_csr_awready; +wire [AXIL_DATA_WIDTH-1:0] axil_csr_wdata; +wire [AXIL_STRB_WIDTH-1:0] axil_csr_wstrb; +wire axil_csr_wvalid; +wire axil_csr_wready; +wire [1:0] axil_csr_bresp; +wire axil_csr_bvalid; +wire axil_csr_bready; +wire [AXIL_ADDR_WIDTH-1:0] axil_csr_araddr; +wire [2:0] axil_csr_arprot; +wire axil_csr_arvalid; +wire axil_csr_arready; +wire [AXIL_DATA_WIDTH-1:0] axil_csr_rdata; +wire [1:0] axil_csr_rresp; +wire axil_csr_rvalid; +wire axil_csr_rready; + +wire [AXIL_ADDR_WIDTH-1:0] axil_ber_awaddr; +wire [2:0] axil_ber_awprot; +wire axil_ber_awvalid; +wire axil_ber_awready; +wire [AXIL_DATA_WIDTH-1:0] axil_ber_wdata; +wire [AXIL_STRB_WIDTH-1:0] axil_ber_wstrb; +wire axil_ber_wvalid; +wire axil_ber_wready; +wire [1:0] axil_ber_bresp; +wire axil_ber_bvalid; +wire axil_ber_bready; +wire [AXIL_ADDR_WIDTH-1:0] axil_ber_araddr; +wire [2:0] axil_ber_arprot; +wire axil_ber_arvalid; +wire axil_ber_arready; +wire [AXIL_DATA_WIDTH-1:0] axil_ber_rdata; +wire [1:0] axil_ber_rresp; +wire axil_ber_rvalid; +wire axil_ber_rready; + +// AXI connections +wire [AXI_ID_WIDTH-1:0] axi_pcie_awid; +wire [AXI_ADDR_WIDTH-1:0] axi_pcie_awaddr; +wire [7:0] axi_pcie_awlen; +wire [2:0] axi_pcie_awsize; +wire [1:0] axi_pcie_awburst; +wire axi_pcie_awlock; +wire [3:0] axi_pcie_awcache; +wire [2:0] axi_pcie_awprot; +wire axi_pcie_awvalid; +wire axi_pcie_awready; +wire [AXI_DATA_WIDTH-1:0] axi_pcie_wdata; +wire [AXI_STRB_WIDTH-1:0] axi_pcie_wstrb; +wire axi_pcie_wlast; +wire axi_pcie_wvalid; +wire axi_pcie_wready; +wire [AXI_ID_WIDTH-1:0] axi_pcie_bid; +wire [1:0] axi_pcie_bresp; +wire axi_pcie_bvalid; +wire axi_pcie_bready; +wire [AXI_ID_WIDTH-1:0] axi_pcie_arid; +wire [AXI_ADDR_WIDTH-1:0] axi_pcie_araddr; +wire [7:0] axi_pcie_arlen; +wire [2:0] axi_pcie_arsize; +wire [1:0] axi_pcie_arburst; +wire axi_pcie_arlock; +wire [3:0] axi_pcie_arcache; +wire [2:0] axi_pcie_arprot; +wire axi_pcie_arvalid; +wire axi_pcie_arready; +wire [AXI_ID_WIDTH-1:0] axi_pcie_rid; +wire [AXI_DATA_WIDTH-1:0] axi_pcie_rdata; +wire [1:0] axi_pcie_rresp; +wire axi_pcie_rlast; +wire axi_pcie_rvalid; +wire axi_pcie_rready; + +wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_awid; +wire [AXI_ADDR_WIDTH-1:0] axi_pcie_dma_awaddr; +wire [7:0] axi_pcie_dma_awlen; +wire [2:0] axi_pcie_dma_awsize; +wire [1:0] axi_pcie_dma_awburst; +wire axi_pcie_dma_awlock; +wire [3:0] axi_pcie_dma_awcache; +wire [2:0] axi_pcie_dma_awprot; +wire axi_pcie_dma_awvalid; +wire axi_pcie_dma_awready; +wire [AXI_DATA_WIDTH-1:0] axi_pcie_dma_wdata; +wire [AXI_STRB_WIDTH-1:0] axi_pcie_dma_wstrb; +wire axi_pcie_dma_wlast; +wire axi_pcie_dma_wvalid; +wire axi_pcie_dma_wready; +wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_bid; +wire [1:0] axi_pcie_dma_bresp; +wire axi_pcie_dma_bvalid; +wire axi_pcie_dma_bready; +wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_arid; +wire [AXI_ADDR_WIDTH-1:0] axi_pcie_dma_araddr; +wire [7:0] axi_pcie_dma_arlen; +wire [2:0] axi_pcie_dma_arsize; +wire [1:0] axi_pcie_dma_arburst; +wire axi_pcie_dma_arlock; +wire [3:0] axi_pcie_dma_arcache; +wire [2:0] axi_pcie_dma_arprot; +wire axi_pcie_dma_arvalid; +wire axi_pcie_dma_arready; +wire [AXI_ID_WIDTH-1:0] axi_pcie_dma_rid; +wire [AXI_DATA_WIDTH-1:0] axi_pcie_dma_rdata; +wire [1:0] axi_pcie_dma_rresp; +wire axi_pcie_dma_rlast; +wire axi_pcie_dma_rvalid; +wire axi_pcie_dma_rready; + +// Error handling +wire [2:0] status_error_uncor_int; +wire [2:0] status_error_cor_int; + +wire [31:0] msi_irq; + +wire ext_tag_enable; + +// PCIe DMA control +wire [PCIE_ADDR_WIDTH-1:0] pcie_axi_dma_read_desc_pcie_addr; +wire [AXI_ADDR_WIDTH-1:0] pcie_axi_dma_read_desc_axi_addr; +wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_axi_dma_read_desc_len; +wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_read_desc_tag; +wire pcie_axi_dma_read_desc_valid; +wire pcie_axi_dma_read_desc_ready; + +wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_read_desc_status_tag; +wire pcie_axi_dma_read_desc_status_valid; + +wire [PCIE_ADDR_WIDTH-1:0] pcie_axi_dma_write_desc_pcie_addr; +wire [AXI_ADDR_WIDTH-1:0] pcie_axi_dma_write_desc_axi_addr; +wire [PCIE_DMA_LEN_WIDTH-1:0] pcie_axi_dma_write_desc_len; +wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_write_desc_tag; +wire pcie_axi_dma_write_desc_valid; +wire pcie_axi_dma_write_desc_ready; + +wire [PCIE_DMA_TAG_WIDTH-1:0] pcie_axi_dma_write_desc_status_tag; +wire pcie_axi_dma_write_desc_status_valid; + +wire pcie_dma_enable = 1; + +wire [95:0] ptp_ts_96; +wire ptp_ts_step; +wire ptp_pps; + +reg ptp_perout_enable_reg = 1'b0; +wire ptp_perout_locked; +wire ptp_perout_error; +wire ptp_perout_pulse; + +// control registers +reg axil_csr_awready_reg = 1'b0; +reg axil_csr_wready_reg = 1'b0; +reg axil_csr_bvalid_reg = 1'b0; +reg axil_csr_arready_reg = 1'b0; +reg [AXIL_DATA_WIDTH-1:0] axil_csr_rdata_reg = {AXIL_DATA_WIDTH{1'b0}}; +reg axil_csr_rvalid_reg = 1'b0; + +reg qsfp_modsell_reg = 1'b0; +reg qsfp_lpmode_reg = 1'b0; + +reg qsfp_resetl_reg = 1'b1; + +reg i2c_scl_o_reg = 1'b1; +reg i2c_sda_o_reg = 1'b1; + +reg [15:0] flash_dq_o_reg = 16'd0; +reg flash_dq_oe_reg = 1'b0; +reg [22:0] flash_addr_reg = 23'd0; +reg flash_region_reg = 1'b0; +reg flash_region_oe_reg = 1'b0; +reg flash_ce_n_reg = 1'b1; +reg flash_oe_n_reg = 1'b1; +reg flash_we_n_reg = 1'b1; +reg flash_adv_n_reg = 1'b1; + +reg pcie_dma_enable_reg = 0; + +reg [95:0] get_ptp_ts_96_reg = 0; +reg [95:0] set_ptp_ts_96_reg = 0; +reg set_ptp_ts_96_valid_reg = 0; +reg [PTP_PERIOD_NS_WIDTH-1:0] set_ptp_period_ns_reg = 0; +reg [PTP_FNS_WIDTH-1:0] set_ptp_period_fns_reg = 0; +reg set_ptp_period_valid_reg = 0; +reg [PTP_OFFSET_NS_WIDTH-1:0] set_ptp_offset_ns_reg = 0; +reg [PTP_FNS_WIDTH-1:0] set_ptp_offset_fns_reg = 0; +reg [15:0] set_ptp_offset_count_reg = 0; +reg set_ptp_offset_valid_reg = 0; +wire set_ptp_offset_active; + +reg [95:0] set_ptp_perout_start_ts_96_reg = 0; +reg set_ptp_perout_start_ts_96_valid_reg = 0; +reg [95:0] set_ptp_perout_period_ts_96_reg = 0; +reg set_ptp_perout_period_ts_96_valid_reg = 0; +reg [95:0] set_ptp_perout_width_ts_96_reg = 0; +reg set_ptp_perout_width_ts_96_valid_reg = 0; + +assign axil_csr_awready = axil_csr_awready_reg; +assign axil_csr_wready = axil_csr_wready_reg; +assign axil_csr_bresp = 2'b00; +assign axil_csr_bvalid = axil_csr_bvalid_reg; +assign axil_csr_arready = axil_csr_arready_reg; +assign axil_csr_rdata = axil_csr_rdata_reg; +assign axil_csr_rresp = 2'b00; +assign axil_csr_rvalid = axil_csr_rvalid_reg; + +assign qsfp_modsell = qsfp_modsell_reg; +assign qsfp_lpmode = qsfp_lpmode_reg; + +assign qsfp_resetl = qsfp_resetl_reg; + +assign i2c_scl_o = i2c_scl_o_reg; +assign i2c_scl_t = i2c_scl_o_reg; +assign i2c_sda_o = i2c_sda_o_reg; +assign i2c_sda_t = i2c_sda_o_reg; + +assign flash_dq_o = flash_dq_o_reg; +assign flash_dq_oe = flash_dq_oe_reg; +assign flash_addr = flash_addr_reg; +assign flash_region = flash_region_reg; +assign flash_region_oe = flash_region_oe_reg; +assign flash_ce_n = flash_ce_n_reg; +assign flash_oe_n = flash_oe_n_reg; +assign flash_we_n = flash_we_n_reg; +assign flash_adv_n = flash_adv_n_reg; + +//assign pcie_dma_enable = pcie_dma_enable_reg; + +always @(posedge clk_250mhz) begin + axil_csr_awready_reg <= 1'b0; + axil_csr_wready_reg <= 1'b0; + axil_csr_bvalid_reg <= axil_csr_bvalid_reg && !axil_csr_bready; + axil_csr_arready_reg <= 1'b0; + axil_csr_rvalid_reg <= axil_csr_rvalid_reg && !axil_csr_rready; + + pcie_dma_enable_reg <= pcie_dma_enable_reg; + + set_ptp_ts_96_valid_reg <= 1'b0; + set_ptp_period_valid_reg <= 1'b0; + set_ptp_offset_valid_reg <= 1'b0; + + set_ptp_perout_start_ts_96_valid_reg <= 1'b0; + set_ptp_perout_period_ts_96_valid_reg <= 1'b0; + set_ptp_perout_width_ts_96_valid_reg <= 1'b0; + + if (axil_csr_awvalid && axil_csr_wvalid && !axil_csr_bvalid) begin + // write operation + axil_csr_awready_reg <= 1'b1; + axil_csr_wready_reg <= 1'b1; + axil_csr_bvalid_reg <= 1'b1; + + case ({axil_csr_awaddr[15:2], 2'b00}) + // GPIO + 16'h0100: begin + // GPIO out + if (axil_csr_wstrb[1]) begin + qsfp_modsell_reg <= axil_csr_wdata[9]; + end + if (axil_csr_wstrb[0]) begin + qsfp_resetl_reg <= axil_csr_wdata[0]; + qsfp_lpmode_reg <= axil_csr_wdata[2]; + end + if (axil_csr_wstrb[2]) begin + i2c_scl_o_reg <= axil_csr_wdata[16]; + i2c_sda_o_reg <= axil_csr_wdata[17]; + end + end + // Flash + 16'h0144: begin + // Flash address + flash_addr_reg <= axil_csr_wdata[22:0]; + flash_region_reg <= axil_csr_wdata[23]; + end + 16'h0148: flash_dq_o_reg <= axil_csr_wdata; // Flash data + 16'h014C: begin + // Flash control + if (axil_csr_wstrb[0]) begin + flash_ce_n_reg <= axil_csr_wdata[0]; + flash_oe_n_reg <= axil_csr_wdata[1]; + flash_we_n_reg <= axil_csr_wdata[2]; + flash_adv_n_reg <= axil_csr_wdata[3]; + end + if (axil_csr_wstrb[1]) begin + flash_dq_oe_reg <= axil_csr_wdata[8]; + end + if (axil_csr_wstrb[2]) begin + flash_region_oe_reg <= axil_csr_wdata[16]; + end + end + // PHC + 16'h0230: set_ptp_ts_96_reg[15:0] <= axil_csr_wdata; // PTP set fns + 16'h0234: set_ptp_ts_96_reg[45:16] <= axil_csr_wdata;// PTP set ns + 16'h0238: set_ptp_ts_96_reg[79:48] <= axil_csr_wdata;// PTP set sec l + 16'h023C: begin + // PTP set sec h + set_ptp_ts_96_reg[95:80] <= axil_csr_wdata; + set_ptp_ts_96_valid_reg <= 1'b1; + end + 16'h0240: set_ptp_period_fns_reg <= axil_csr_wdata;// PTP period fns + 16'h0244: begin + // PTP period ns + set_ptp_period_ns_reg <= axil_csr_wdata; + set_ptp_period_valid_reg <= 1'b1; + end + 16'h0250: set_ptp_offset_fns_reg <= axil_csr_wdata;// PTP offset fns + 16'h0254: set_ptp_offset_ns_reg <= axil_csr_wdata; // PTP offset ns + 16'h0258: begin + // PTP offset count + set_ptp_offset_count_reg <= axil_csr_wdata; + set_ptp_offset_valid_reg <= 1'b1; + end + 16'h0260: begin + // PTP perout control + ptp_perout_enable_reg <= axil_csr_wdata[0]; + end + 16'h0270: set_ptp_perout_start_ts_96_reg[15:0] <= axil_csr_wdata; // PTP perout start fns + 16'h0274: set_ptp_perout_start_ts_96_reg[45:16] <= axil_csr_wdata; // PTP perout start ns + 16'h0278: set_ptp_perout_start_ts_96_reg[79:48] <= axil_csr_wdata; // PTP perout start sec l + 16'h027C: begin + // PTP perout start sec h + set_ptp_perout_start_ts_96_reg[95:80] <= axil_csr_wdata; + set_ptp_perout_start_ts_96_valid_reg <= 1'b1; + end + 16'h0280: set_ptp_perout_period_ts_96_reg[15:0] <= axil_csr_wdata; // PTP perout period fns + 16'h0284: set_ptp_perout_period_ts_96_reg[45:16] <= axil_csr_wdata; // PTP perout period ns + 16'h0288: set_ptp_perout_period_ts_96_reg[79:48] <= axil_csr_wdata; // PTP perout period sec l + 16'h028C: begin + // PTP perout period sec h + set_ptp_perout_period_ts_96_reg[95:80] <= axil_csr_wdata; + set_ptp_perout_period_ts_96_valid_reg <= 1'b1; + end + 16'h0290: set_ptp_perout_width_ts_96_reg[15:0] <= axil_csr_wdata; // PTP perout width fns + 16'h0294: set_ptp_perout_width_ts_96_reg[45:16] <= axil_csr_wdata; // PTP perout width ns + 16'h0298: set_ptp_perout_width_ts_96_reg[79:48] <= axil_csr_wdata; // PTP perout width sec l + 16'h029C: begin + // PTP perout width sec h + set_ptp_perout_width_ts_96_reg[95:80] <= axil_csr_wdata; + set_ptp_perout_width_ts_96_valid_reg <= 1'b1; + end + endcase + end + + if (axil_csr_arvalid && !axil_csr_rvalid) begin + // read operation + axil_csr_arready_reg <= 1'b1; + axil_csr_rvalid_reg <= 1'b1; + axil_csr_rdata_reg <= {AXIL_DATA_WIDTH{1'b0}}; + + case ({axil_csr_araddr[15:2], 2'b00}) + 16'h0000: axil_csr_rdata_reg <= FW_ID; // fw_id + 16'h0004: axil_csr_rdata_reg <= FW_VER; // fw_ver + 16'h0008: axil_csr_rdata_reg <= BOARD_ID; // board_id + 16'h000C: axil_csr_rdata_reg <= BOARD_VER; // board_ver + 16'h0010: axil_csr_rdata_reg <= 1; // phc_count + 16'h0014: axil_csr_rdata_reg <= 16'h0200; // phc_offset + 16'h0018: axil_csr_rdata_reg <= 16'h0080; // phc_stride + 16'h0020: axil_csr_rdata_reg <= IF_COUNT; // if_count + 16'h0024: axil_csr_rdata_reg <= 24'h800000; // if_stride + 16'h002C: axil_csr_rdata_reg <= 24'h040000; // if_csr_offset + // GPIO + 16'h0100: begin + // GPIO out + axil_csr_rdata_reg[9] <= qsfp_modsell_reg; + axil_csr_rdata_reg[0] <= qsfp_resetl_reg; + axil_csr_rdata_reg[2] <= qsfp_lpmode_reg; + axil_csr_rdata_reg[16] <= i2c_scl_o_reg; + axil_csr_rdata_reg[17] <= i2c_sda_o_reg; + end + 16'h0104: begin + // GPIO in + axil_csr_rdata_reg[8] <= qsfp_modprsl; + axil_csr_rdata_reg[9] <= qsfp_modsell; + axil_csr_rdata_reg[0] <= qsfp_resetl; + axil_csr_rdata_reg[1] <= qsfp_intl; + axil_csr_rdata_reg[2] <= qsfp_lpmode; + axil_csr_rdata_reg[16] <= i2c_scl_i; + axil_csr_rdata_reg[17] <= i2c_sda_i; + end + // Flash + 16'h0140: axil_csr_rdata_reg <= 32'd0; // Flash ID + 16'h0144: begin + // Flash address + axil_csr_rdata_reg[22:0] <= flash_addr_reg; + axil_csr_rdata_reg[23] <= flash_region_reg; + end + 16'h0148: axil_csr_rdata_reg <= flash_dq_i; // Flash data + 16'h014C: begin + // Flash control + axil_csr_rdata_reg[0] <= flash_ce_n_reg; // chip enable (inverted) + axil_csr_rdata_reg[1] <= flash_oe_n_reg; // output enable (inverted) + axil_csr_rdata_reg[2] <= flash_we_n_reg; // write enable (inverted) + axil_csr_rdata_reg[3] <= flash_adv_n_reg; // address valid (inverted) + axil_csr_rdata_reg[8] <= flash_dq_oe_reg; // data output enable + axil_csr_rdata_reg[16] <= flash_region_oe_reg; // region output enable (addr bit 23) + end + // PHC + 16'h0200: axil_csr_rdata_reg <= {8'd0, 8'd0, 8'd0, 8'd1}; // PHC features + 16'h0210: axil_csr_rdata_reg <= ptp_ts_96[15:0]; // PTP cur fns + 16'h0214: axil_csr_rdata_reg <= ptp_ts_96[45:16]; // PTP cur ns + 16'h0218: axil_csr_rdata_reg <= ptp_ts_96[79:48]; // PTP cur sec l + 16'h021C: axil_csr_rdata_reg <= ptp_ts_96[95:80]; // PTP cur sec h + 16'h0220: begin + // PTP get fns + get_ptp_ts_96_reg <= ptp_ts_96; + axil_csr_rdata_reg <= ptp_ts_96[15:0]; + end + 16'h0224: axil_csr_rdata_reg <= get_ptp_ts_96_reg[45:16]; // PTP get ns + 16'h0228: axil_csr_rdata_reg <= get_ptp_ts_96_reg[79:48]; // PTP get sec l + 16'h022C: axil_csr_rdata_reg <= get_ptp_ts_96_reg[95:80]; // PTP get sec h + 16'h0230: axil_csr_rdata_reg <= set_ptp_ts_96_reg[15:0]; // PTP set fns + 16'h0234: axil_csr_rdata_reg <= set_ptp_ts_96_reg[45:16]; // PTP set ns + 16'h0238: axil_csr_rdata_reg <= set_ptp_ts_96_reg[79:48]; // PTP set sec l + 16'h023C: axil_csr_rdata_reg <= set_ptp_ts_96_reg[95:80]; // PTP set sec h + 16'h0240: axil_csr_rdata_reg <= set_ptp_period_fns_reg; // PTP period fns + 16'h0244: axil_csr_rdata_reg <= set_ptp_period_ns_reg; // PTP period ns + 16'h0248: axil_csr_rdata_reg <= PTP_PERIOD_FNS; // PTP nom period fns + 16'h024C: axil_csr_rdata_reg <= PTP_PERIOD_NS; // PTP nom period ns + 16'h0250: axil_csr_rdata_reg <= set_ptp_offset_fns_reg; // PTP offset fns + 16'h0254: axil_csr_rdata_reg <= set_ptp_offset_ns_reg; // PTP offset ns + 16'h0258: axil_csr_rdata_reg <= set_ptp_offset_count_reg; // PTP offset count + 16'h025C: axil_csr_rdata_reg <= set_ptp_offset_active; // PTP offset status + 16'h0260: begin + // PTP perout control + axil_csr_rdata_reg[0] <= ptp_perout_enable_reg; + end + 16'h0264: begin + // PTP perout status + axil_csr_rdata_reg[0] <= ptp_perout_locked; + axil_csr_rdata_reg[1] <= ptp_perout_error; + end + 16'h0270: axil_csr_rdata_reg <= set_ptp_perout_start_ts_96_reg[15:0]; // PTP perout start fns + 16'h0274: axil_csr_rdata_reg <= set_ptp_perout_start_ts_96_reg[45:16]; // PTP perout start ns + 16'h0278: axil_csr_rdata_reg <= set_ptp_perout_start_ts_96_reg[79:48]; // PTP perout start sec l + 16'h027C: axil_csr_rdata_reg <= set_ptp_perout_start_ts_96_reg[95:80]; // PTP perout start sec h + 16'h0280: axil_csr_rdata_reg <= set_ptp_perout_period_ts_96_reg[15:0]; // PTP perout period fns + 16'h0284: axil_csr_rdata_reg <= set_ptp_perout_period_ts_96_reg[45:16]; // PTP perout period ns + 16'h0288: axil_csr_rdata_reg <= set_ptp_perout_period_ts_96_reg[79:48]; // PTP perout period sec l + 16'h028C: axil_csr_rdata_reg <= set_ptp_perout_period_ts_96_reg[95:80]; // PTP perout period sec h + 16'h0290: axil_csr_rdata_reg <= set_ptp_perout_width_ts_96_reg[15:0]; // PTP perout width fns + 16'h0294: axil_csr_rdata_reg <= set_ptp_perout_width_ts_96_reg[45:16]; // PTP perout width ns + 16'h0298: axil_csr_rdata_reg <= set_ptp_perout_width_ts_96_reg[79:48]; // PTP perout width sec l + 16'h029C: axil_csr_rdata_reg <= set_ptp_perout_width_ts_96_reg[95:80]; // PTP perout width sec h + endcase + end + + if (rst_250mhz) begin + axil_csr_awready_reg <= 1'b0; + axil_csr_wready_reg <= 1'b0; + axil_csr_bvalid_reg <= 1'b0; + axil_csr_arready_reg <= 1'b0; + axil_csr_rvalid_reg <= 1'b0; + + qsfp_modsell_reg <= 1'b0; + qsfp_lpmode_reg <= 1'b0; + + qsfp_resetl_reg <= 1'b1; + + i2c_scl_o_reg <= 1'b1; + i2c_sda_o_reg <= 1'b1; + + flash_dq_o_reg <= 16'd0; + flash_dq_oe_reg <= 1'b0; + flash_addr_reg <= 23'd0; + flash_region_reg <= 1'b0; + flash_region_oe_reg <= 1'b0; + flash_ce_n_reg <= 1'b1; + flash_oe_n_reg <= 1'b1; + flash_we_n_reg <= 1'b1; + flash_adv_n_reg <= 1'b1; + + pcie_dma_enable_reg <= 1'b0; + + ptp_perout_enable_reg <= 1'b0; + end +end + +pcie_us_cfg #( + .PF_COUNT(1), + .VF_COUNT(0), + .VF_OFFSET(64), + .PCIE_CAP_OFFSET(12'h0C0) +) +pcie_us_cfg_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * Configuration outputs + */ + .ext_tag_enable(ext_tag_enable), + .max_read_request_size(), + .max_payload_size(), + + /* + * Interface to Ultrascale PCIe IP core + */ + .cfg_mgmt_addr(cfg_mgmt_addr[9:0]), + .cfg_mgmt_function_number(cfg_mgmt_addr[17:10]), + .cfg_mgmt_write(cfg_mgmt_write), + .cfg_mgmt_write_data(cfg_mgmt_write_data), + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), + .cfg_mgmt_read(cfg_mgmt_read), + .cfg_mgmt_read_data(cfg_mgmt_read_data), + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done) +); + +assign cfg_mgmt_addr[18] = 1'b0; + +// Completer mux/demux +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_0; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_0; +wire axis_cq_tvalid_bar_0; +wire axis_cq_tready_bar_0; +wire axis_cq_tlast_bar_0; +wire [84:0] axis_cq_tuser_bar_0; + +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_0; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_0; +wire axis_cc_tvalid_bar_0; +wire axis_cc_tready_bar_0; +wire axis_cc_tlast_bar_0; +wire [32:0] axis_cc_tuser_bar_0; + +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cq_tdata_bar_1; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cq_tkeep_bar_1; +wire axis_cq_tvalid_bar_1; +wire axis_cq_tready_bar_1; +wire axis_cq_tlast_bar_1; +wire [84:0] axis_cq_tuser_bar_1; + +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_cc_tdata_bar_1; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_cc_tkeep_bar_1; +wire axis_cc_tvalid_bar_1; +wire axis_cc_tready_bar_1; +wire axis_cc_tlast_bar_1; +wire [32:0] axis_cc_tuser_bar_1; + +wire [2:0] bar_id; +wire [1:0] select; + +pcie_us_axis_cq_demux #( + .M_COUNT(2), + .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), + .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH) +) +cq_demux_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * AXI input (CQ) + */ + .s_axis_cq_tdata(s_axis_cq_tdata), + .s_axis_cq_tkeep(s_axis_cq_tkeep), + .s_axis_cq_tvalid(s_axis_cq_tvalid), + .s_axis_cq_tready(s_axis_cq_tready), + .s_axis_cq_tlast(s_axis_cq_tlast), + .s_axis_cq_tuser(s_axis_cq_tuser), + + /* + * AXI output (CQ) + */ + .m_axis_cq_tdata({axis_cq_tdata_bar_1, axis_cq_tdata_bar_0}), + .m_axis_cq_tkeep({axis_cq_tkeep_bar_1, axis_cq_tkeep_bar_0}), + .m_axis_cq_tvalid({axis_cq_tvalid_bar_1, axis_cq_tvalid_bar_0}), + .m_axis_cq_tready({axis_cq_tready_bar_1, axis_cq_tready_bar_0}), + .m_axis_cq_tlast({axis_cq_tlast_bar_1, axis_cq_tlast_bar_0}), + .m_axis_cq_tuser({axis_cq_tuser_bar_1, axis_cq_tuser_bar_0}), + + /* + * Fields + */ + .req_type(), + .target_function(), + .bar_id(bar_id), + .msg_code(), + .msg_routing(), + + /* + * Control + */ + .enable(1), + .drop(0), + .select(select) +); + +assign select[1] = bar_id == 3'd1; +assign select[0] = bar_id == 3'd0; + +axis_arb_mux #( + .S_COUNT(2), + .DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), + .KEEP_ENABLE(1), + .KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .ID_ENABLE(0), + .DEST_ENABLE(0), + .USER_ENABLE(1), + .USER_WIDTH(33) +) +cc_mux_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * AXI inputs + */ + .s_axis_tdata({axis_cc_tdata_bar_1, axis_cc_tdata_bar_0}), + .s_axis_tkeep({axis_cc_tkeep_bar_1, axis_cc_tkeep_bar_0}), + .s_axis_tvalid({axis_cc_tvalid_bar_1, axis_cc_tvalid_bar_0}), + .s_axis_tready({axis_cc_tready_bar_1, axis_cc_tready_bar_0}), + .s_axis_tlast({axis_cc_tlast_bar_1, axis_cc_tlast_bar_0}), + .s_axis_tid(0), + .s_axis_tdest(0), + .s_axis_tuser({axis_cc_tuser_bar_1, axis_cc_tuser_bar_0}), + + /* + * AXI output + */ + .m_axis_tdata(m_axis_cc_tdata), + .m_axis_tkeep(m_axis_cc_tkeep), + .m_axis_tvalid(m_axis_cc_tvalid), + .m_axis_tready(m_axis_cc_tready), + .m_axis_tlast(m_axis_cc_tlast), + .m_axis_tid(), + .m_axis_tdest(), + .m_axis_tuser(m_axis_cc_tuser) +); + +pcie_us_axil_master #( + .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), + .AXI_DATA_WIDTH(AXIL_DATA_WIDTH), + .AXI_ADDR_WIDTH(AXIL_ADDR_WIDTH), + .ENABLE_PARITY(0) +) +pcie_us_axil_master_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * AXI input (CQ) + */ + .s_axis_cq_tdata(axis_cq_tdata_bar_0), + .s_axis_cq_tkeep(axis_cq_tkeep_bar_0), + .s_axis_cq_tvalid(axis_cq_tvalid_bar_0), + .s_axis_cq_tready(axis_cq_tready_bar_0), + .s_axis_cq_tlast(axis_cq_tlast_bar_0), + .s_axis_cq_tuser(axis_cq_tuser_bar_0), + + /* + * AXI input (CC) + */ + .m_axis_cc_tdata(axis_cc_tdata_bar_0), + .m_axis_cc_tkeep(axis_cc_tkeep_bar_0), + .m_axis_cc_tvalid(axis_cc_tvalid_bar_0), + .m_axis_cc_tready(axis_cc_tready_bar_0), + .m_axis_cc_tlast(axis_cc_tlast_bar_0), + .m_axis_cc_tuser(axis_cc_tuser_bar_0), + + /* + * AXI Lite Master output + */ + .m_axil_awaddr(axil_pcie_awaddr), + .m_axil_awprot(axil_pcie_awprot), + .m_axil_awvalid(axil_pcie_awvalid), + .m_axil_awready(axil_pcie_awready), + .m_axil_wdata(axil_pcie_wdata), + .m_axil_wstrb(axil_pcie_wstrb), + .m_axil_wvalid(axil_pcie_wvalid), + .m_axil_wready(axil_pcie_wready), + .m_axil_bresp(axil_pcie_bresp), + .m_axil_bvalid(axil_pcie_bvalid), + .m_axil_bready(axil_pcie_bready), + .m_axil_araddr(axil_pcie_araddr), + .m_axil_arprot(axil_pcie_arprot), + .m_axil_arvalid(axil_pcie_arvalid), + .m_axil_arready(axil_pcie_arready), + .m_axil_rdata(axil_pcie_rdata), + .m_axil_rresp(axil_pcie_rresp), + .m_axil_rvalid(axil_pcie_rvalid), + .m_axil_rready(axil_pcie_rready), + + /* + * Configuration + */ + .completer_id({8'd0, 5'd0, 3'd0}), + .completer_id_enable(1'b0), + + /* + * Status + */ + .status_error_cor(status_error_cor_int[0]), + .status_error_uncor(status_error_uncor_int[0]) +); + +pcie_us_axi_master #( + .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), + .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXI_DATA_WIDTH(AXI_DATA_WIDTH), + .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), + .AXI_STRB_WIDTH(AXI_STRB_WIDTH), + .AXI_ID_WIDTH(AXI_ID_WIDTH) +) +pcie_us_axi_master_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * AXI input (CQ) + */ + .s_axis_cq_tdata(axis_cq_tdata_bar_1), + .s_axis_cq_tkeep(axis_cq_tkeep_bar_1), + .s_axis_cq_tvalid(axis_cq_tvalid_bar_1), + .s_axis_cq_tready(axis_cq_tready_bar_1), + .s_axis_cq_tlast(axis_cq_tlast_bar_1), + .s_axis_cq_tuser(axis_cq_tuser_bar_1), + + /* + * AXI output (CC) + */ + .m_axis_cc_tdata(axis_cc_tdata_bar_1), + .m_axis_cc_tkeep(axis_cc_tkeep_bar_1), + .m_axis_cc_tvalid(axis_cc_tvalid_bar_1), + .m_axis_cc_tready(axis_cc_tready_bar_1), + .m_axis_cc_tlast(axis_cc_tlast_bar_1), + .m_axis_cc_tuser(axis_cc_tuser_bar_1), + + /* + * AXI Master output + */ + .m_axi_awid(axi_pcie_awid), + .m_axi_awaddr(axi_pcie_awaddr), + .m_axi_awlen(axi_pcie_awlen), + .m_axi_awsize(axi_pcie_awsize), + .m_axi_awburst(axi_pcie_awburst), + .m_axi_awlock(axi_pcie_awlock), + .m_axi_awcache(axi_pcie_awcache), + .m_axi_awprot(axi_pcie_awprot), + .m_axi_awvalid(axi_pcie_awvalid), + .m_axi_awready(axi_pcie_awready), + .m_axi_wdata(axi_pcie_wdata), + .m_axi_wstrb(axi_pcie_wstrb), + .m_axi_wlast(axi_pcie_wlast), + .m_axi_wvalid(axi_pcie_wvalid), + .m_axi_wready(axi_pcie_wready), + .m_axi_bid(axi_pcie_bid), + .m_axi_bresp(axi_pcie_bresp), + .m_axi_bvalid(axi_pcie_bvalid), + .m_axi_bready(axi_pcie_bready), + .m_axi_arid(axi_pcie_arid), + .m_axi_araddr(axi_pcie_araddr), + .m_axi_arlen(axi_pcie_arlen), + .m_axi_arsize(axi_pcie_arsize), + .m_axi_arburst(axi_pcie_arburst), + .m_axi_arlock(axi_pcie_arlock), + .m_axi_arcache(axi_pcie_arcache), + .m_axi_arprot(axi_pcie_arprot), + .m_axi_arvalid(axi_pcie_arvalid), + .m_axi_arready(axi_pcie_arready), + .m_axi_rid(axi_pcie_rid), + .m_axi_rdata(axi_pcie_rdata), + .m_axi_rresp(axi_pcie_rresp), + .m_axi_rlast(axi_pcie_rlast), + .m_axi_rvalid(axi_pcie_rvalid), + .m_axi_rready(axi_pcie_rready), + + /* + * Configuration + */ + .completer_id({8'd0, 5'd0, 3'd0}), + .completer_id_enable(1'b0), + .max_payload_size(cfg_max_payload), + + /* + * Status + */ + .status_error_cor(status_error_cor_int[1]), + .status_error_uncor(status_error_uncor_int[1]) +); + +wire [AXIS_PCIE_DATA_WIDTH-1:0] axis_rc_tdata_r; +wire [AXIS_PCIE_KEEP_WIDTH-1:0] axis_rc_tkeep_r; +wire axis_rc_tlast_r; +wire axis_rc_tready_r; +wire [74:0] axis_rc_tuser_r; +wire axis_rc_tvalid_r; + +axis_register #( + .DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), + .KEEP_ENABLE(1), + .KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .LAST_ENABLE(1), + .ID_ENABLE(0), + .DEST_ENABLE(0), + .USER_ENABLE(1), + .USER_WIDTH(75) +) +rq_reg ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * AXI input + */ + .s_axis_tdata(s_axis_rc_tdata), + .s_axis_tkeep(s_axis_rc_tkeep), + .s_axis_tvalid(s_axis_rc_tvalid), + .s_axis_tready(s_axis_rc_tready), + .s_axis_tlast(s_axis_rc_tlast), + .s_axis_tid(0), + .s_axis_tdest(0), + .s_axis_tuser(s_axis_rc_tuser), + + /* + * AXI output + */ + .m_axis_tdata(axis_rc_tdata_r), + .m_axis_tkeep(axis_rc_tkeep_r), + .m_axis_tvalid(axis_rc_tvalid_r), + .m_axis_tready(axis_rc_tready_r), + .m_axis_tlast(axis_rc_tlast_r), + .m_axis_tid(), + .m_axis_tdest(), + .m_axis_tuser(axis_rc_tuser_r) +); + +pcie_us_axi_dma #( + .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH), + .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH), + .AXI_DATA_WIDTH(AXI_DATA_WIDTH), + .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), + .AXI_STRB_WIDTH(AXI_STRB_WIDTH), + .AXI_ID_WIDTH(AXI_ID_WIDTH), + .AXI_MAX_BURST_LEN(256), + .PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH), + .PCIE_CLIENT_TAG(1), + .PCIE_TAG_COUNT(64), + .LEN_WIDTH(PCIE_DMA_LEN_WIDTH), + .TAG_WIDTH(PCIE_DMA_TAG_WIDTH) +) +pcie_us_axi_dma_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * AXI input (RC) + */ + .s_axis_rc_tdata(axis_rc_tdata_r), + .s_axis_rc_tkeep(axis_rc_tkeep_r), + .s_axis_rc_tvalid(axis_rc_tvalid_r), + .s_axis_rc_tready(axis_rc_tready_r), + .s_axis_rc_tlast(axis_rc_tlast_r), + .s_axis_rc_tuser(axis_rc_tuser_r), + + /* + * AXI output (RQ) + */ + .m_axis_rq_tdata(m_axis_rq_tdata), + .m_axis_rq_tkeep(m_axis_rq_tkeep), + .m_axis_rq_tvalid(m_axis_rq_tvalid), + .m_axis_rq_tready(m_axis_rq_tready), + .m_axis_rq_tlast(m_axis_rq_tlast), + .m_axis_rq_tuser(m_axis_rq_tuser), + + /* + * Tag input + */ + .s_axis_pcie_rq_tag(0), + .s_axis_pcie_rq_tag_valid(0), + + /* + * AXI read descriptor input + */ + .s_axis_read_desc_pcie_addr(pcie_axi_dma_read_desc_pcie_addr), + .s_axis_read_desc_axi_addr(pcie_axi_dma_read_desc_axi_addr), + .s_axis_read_desc_len(pcie_axi_dma_read_desc_len), + .s_axis_read_desc_tag(pcie_axi_dma_read_desc_tag), + .s_axis_read_desc_valid(pcie_axi_dma_read_desc_valid), + .s_axis_read_desc_ready(pcie_axi_dma_read_desc_ready), + + /* + * AXI read descriptor status output + */ + .m_axis_read_desc_status_tag(pcie_axi_dma_read_desc_status_tag), + .m_axis_read_desc_status_valid(pcie_axi_dma_read_desc_status_valid), + + /* + * AXI write descriptor input + */ + .s_axis_write_desc_pcie_addr(pcie_axi_dma_write_desc_pcie_addr), + .s_axis_write_desc_axi_addr(pcie_axi_dma_write_desc_axi_addr), + .s_axis_write_desc_len(pcie_axi_dma_write_desc_len), + .s_axis_write_desc_tag(pcie_axi_dma_write_desc_tag), + .s_axis_write_desc_valid(pcie_axi_dma_write_desc_valid), + .s_axis_write_desc_ready(pcie_axi_dma_write_desc_ready), + + /* + * AXI write descriptor status output + */ + .m_axis_write_desc_status_tag(pcie_axi_dma_write_desc_status_tag), + .m_axis_write_desc_status_valid(pcie_axi_dma_write_desc_status_valid), + + /* + * AXI Master output + */ + .m_axi_awid(axi_pcie_dma_awid), + .m_axi_awaddr(axi_pcie_dma_awaddr), + .m_axi_awlen(axi_pcie_dma_awlen), + .m_axi_awsize(axi_pcie_dma_awsize), + .m_axi_awburst(axi_pcie_dma_awburst), + .m_axi_awlock(axi_pcie_dma_awlock), + .m_axi_awcache(axi_pcie_dma_awcache), + .m_axi_awprot(axi_pcie_dma_awprot), + .m_axi_awvalid(axi_pcie_dma_awvalid), + .m_axi_awready(axi_pcie_dma_awready), + .m_axi_wdata(axi_pcie_dma_wdata), + .m_axi_wstrb(axi_pcie_dma_wstrb), + .m_axi_wlast(axi_pcie_dma_wlast), + .m_axi_wvalid(axi_pcie_dma_wvalid), + .m_axi_wready(axi_pcie_dma_wready), + .m_axi_bid(axi_pcie_dma_bid), + .m_axi_bresp(axi_pcie_dma_bresp), + .m_axi_bvalid(axi_pcie_dma_bvalid), + .m_axi_bready(axi_pcie_dma_bready), + .m_axi_arid(axi_pcie_dma_arid), + .m_axi_araddr(axi_pcie_dma_araddr), + .m_axi_arlen(axi_pcie_dma_arlen), + .m_axi_arsize(axi_pcie_dma_arsize), + .m_axi_arburst(axi_pcie_dma_arburst), + .m_axi_arlock(axi_pcie_dma_arlock), + .m_axi_arcache(axi_pcie_dma_arcache), + .m_axi_arprot(axi_pcie_dma_arprot), + .m_axi_arvalid(axi_pcie_dma_arvalid), + .m_axi_arready(axi_pcie_dma_arready), + .m_axi_rid(axi_pcie_dma_rid), + .m_axi_rdata(axi_pcie_dma_rdata), + .m_axi_rresp(axi_pcie_dma_rresp), + .m_axi_rlast(axi_pcie_dma_rlast), + .m_axi_rvalid(axi_pcie_dma_rvalid), + .m_axi_rready(axi_pcie_dma_rready), + + /* + * Configuration + */ + .read_enable(pcie_dma_enable), + .write_enable(pcie_dma_enable), + .ext_tag_enable(ext_tag_enable), + .requester_id({8'd0, 5'd0, 3'd0}), + .requester_id_enable(1'b0), + .max_read_request_size(cfg_max_read_req), + .max_payload_size(cfg_max_payload), + + /* + * Status + */ + .status_error_cor(status_error_cor_int[2]), + .status_error_uncor(status_error_uncor_int[2]) +); + +pulse_merge #( + .INPUT_WIDTH(3), + .COUNT_WIDTH(4) +) +status_error_cor_pm_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + .pulse_in(status_error_cor_int), + .count_out(), + .pulse_out(status_error_cor) +); + +pulse_merge #( + .INPUT_WIDTH(3), + .COUNT_WIDTH(4) +) +status_error_uncor_pm_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + .pulse_in(status_error_uncor_int), + .count_out(), + .pulse_out(status_error_uncor) +); + +pcie_us_msi #( + .MSI_COUNT(32) +) +pcie_us_msi_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + .msi_irq(msi_irq), + + .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), + .cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable), + .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), + .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), + .cfg_interrupt_msi_data(cfg_interrupt_msi_data), + .cfg_interrupt_msi_select(cfg_interrupt_msi_select), + .cfg_interrupt_msi_int(cfg_interrupt_msi_int), + .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), + .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), + .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), + .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), + .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), + .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr), + .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present), + .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type), + .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag), + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number) +); + +parameter IF_AXIL_ADDR_WIDTH = 32'd23; +parameter IF_AXIL_BASE_ADDR_WIDTH = IF_COUNT*AXIL_ADDR_WIDTH; +parameter IF_AXIL_BASE_ADDR = calcIFAxiLiteBaseAddrs(IF_AXIL_ADDR_WIDTH); + +function [IF_AXIL_BASE_ADDR_WIDTH-1:0] calcIFAxiLiteBaseAddrs(input [31:0] if_addr_width); + integer i; + begin + calcIFAxiLiteBaseAddrs = {IF_AXIL_BASE_ADDR_WIDTH{1'b0}}; + for (i = 0; i < IF_COUNT; i = i + 1) begin + calcIFAxiLiteBaseAddrs[i * AXIL_ADDR_WIDTH +: AXIL_ADDR_WIDTH] = i * (2**if_addr_width); + end + end +endfunction + +parameter IF_AXI_ADDR_WIDTH = 32'd23; +parameter IF_AXI_BASE_ADDR_WIDTH = IF_COUNT*AXI_ADDR_WIDTH; +parameter IF_AXI_BASE_ADDR = calcIFAxiBaseAddrs(IF_AXI_ADDR_WIDTH); + +function [IF_AXI_BASE_ADDR_WIDTH-1:0] calcIFAxiBaseAddrs(input [31:0] if_addr_width); + integer i; + begin + calcIFAxiBaseAddrs = {IF_AXI_BASE_ADDR_WIDTH{1'b0}}; + for (i = 0; i < IF_COUNT; i = i + 1) begin + calcIFAxiBaseAddrs[i * AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = i * (2**if_addr_width); + end + end +endfunction + +parameter IF_AXI_ID_WIDTH = AXI_ID_WIDTH+$clog2(2); + +wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_awaddr; +wire [IF_COUNT*3-1:0] axil_if_awprot; +wire [IF_COUNT-1:0] axil_if_awvalid; +wire [IF_COUNT-1:0] axil_if_awready; +wire [IF_COUNT*AXIL_DATA_WIDTH-1:0] axil_if_wdata; +wire [IF_COUNT*AXIL_STRB_WIDTH-1:0] axil_if_wstrb; +wire [IF_COUNT-1:0] axil_if_wvalid; +wire [IF_COUNT-1:0] axil_if_wready; +wire [IF_COUNT*2-1:0] axil_if_bresp; +wire [IF_COUNT-1:0] axil_if_bvalid; +wire [IF_COUNT-1:0] axil_if_bready; +wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_araddr; +wire [IF_COUNT*3-1:0] axil_if_arprot; +wire [IF_COUNT-1:0] axil_if_arvalid; +wire [IF_COUNT-1:0] axil_if_arready; +wire [IF_COUNT*AXIL_DATA_WIDTH-1:0] axil_if_rdata; +wire [IF_COUNT*2-1:0] axil_if_rresp; +wire [IF_COUNT-1:0] axil_if_rvalid; +wire [IF_COUNT-1:0] axil_if_rready; + +wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_csr_awaddr; +wire [IF_COUNT*3-1:0] axil_if_csr_awprot; +wire [IF_COUNT-1:0] axil_if_csr_awvalid; +wire [IF_COUNT-1:0] axil_if_csr_awready; +wire [IF_COUNT*AXIL_DATA_WIDTH-1:0] axil_if_csr_wdata; +wire [IF_COUNT*AXIL_STRB_WIDTH-1:0] axil_if_csr_wstrb; +wire [IF_COUNT-1:0] axil_if_csr_wvalid; +wire [IF_COUNT-1:0] axil_if_csr_wready; +wire [IF_COUNT*2-1:0] axil_if_csr_bresp; +wire [IF_COUNT-1:0] axil_if_csr_bvalid; +wire [IF_COUNT-1:0] axil_if_csr_bready; +wire [IF_COUNT*AXIL_ADDR_WIDTH-1:0] axil_if_csr_araddr; +wire [IF_COUNT*3-1:0] axil_if_csr_arprot; +wire [IF_COUNT-1:0] axil_if_csr_arvalid; +wire [IF_COUNT-1:0] axil_if_csr_arready; +wire [IF_COUNT*AXIL_DATA_WIDTH-1:0] axil_if_csr_rdata; +wire [IF_COUNT*2-1:0] axil_if_csr_rresp; +wire [IF_COUNT-1:0] axil_if_csr_rvalid; +wire [IF_COUNT-1:0] axil_if_csr_rready; + +wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_awid; +wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] axi_if_awaddr; +wire [IF_COUNT*8-1:0] axi_if_awlen; +wire [IF_COUNT*3-1:0] axi_if_awsize; +wire [IF_COUNT*2-1:0] axi_if_awburst; +wire [IF_COUNT-1:0] axi_if_awlock; +wire [IF_COUNT*4-1:0] axi_if_awcache; +wire [IF_COUNT*3-1:0] axi_if_awprot; +wire [IF_COUNT-1:0] axi_if_awvalid; +wire [IF_COUNT-1:0] axi_if_awready; +wire [IF_COUNT*AXI_DATA_WIDTH-1:0] axi_if_wdata; +wire [IF_COUNT*AXI_STRB_WIDTH-1:0] axi_if_wstrb; +wire [IF_COUNT-1:0] axi_if_wlast; +wire [IF_COUNT-1:0] axi_if_wvalid; +wire [IF_COUNT-1:0] axi_if_wready; +wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_bid; +wire [IF_COUNT*2-1:0] axi_if_bresp; +wire [IF_COUNT-1:0] axi_if_bvalid; +wire [IF_COUNT-1:0] axi_if_bready; +wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_arid; +wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] axi_if_araddr; +wire [IF_COUNT*8-1:0] axi_if_arlen; +wire [IF_COUNT*3-1:0] axi_if_arsize; +wire [IF_COUNT*2-1:0] axi_if_arburst; +wire [IF_COUNT-1:0] axi_if_arlock; +wire [IF_COUNT*4-1:0] axi_if_arcache; +wire [IF_COUNT*3-1:0] axi_if_arprot; +wire [IF_COUNT-1:0] axi_if_arvalid; +wire [IF_COUNT-1:0] axi_if_arready; +wire [IF_COUNT*IF_AXI_ID_WIDTH-1:0] axi_if_rid; +wire [IF_COUNT*AXI_DATA_WIDTH-1:0] axi_if_rdata; +wire [IF_COUNT*2-1:0] axi_if_rresp; +wire [IF_COUNT-1:0] axi_if_rlast; +wire [IF_COUNT-1:0] axi_if_rvalid; +wire [IF_COUNT-1:0] axi_if_rready; + +axil_interconnect #( + .DATA_WIDTH(AXIL_DATA_WIDTH), + .ADDR_WIDTH(AXIL_ADDR_WIDTH), + .S_COUNT(1), + .M_COUNT(IF_COUNT), + .M_BASE_ADDR(IF_AXIL_BASE_ADDR), + .M_ADDR_WIDTH({IF_COUNT{IF_AXIL_ADDR_WIDTH}}), + .M_CONNECT_READ({IF_COUNT{1'b1}}), + .M_CONNECT_WRITE({IF_COUNT{1'b1}}) +) +axil_interconnect_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + .s_axil_awaddr(axil_pcie_awaddr), + .s_axil_awprot(axil_pcie_awprot), + .s_axil_awvalid(axil_pcie_awvalid), + .s_axil_awready(axil_pcie_awready), + .s_axil_wdata(axil_pcie_wdata), + .s_axil_wstrb(axil_pcie_wstrb), + .s_axil_wvalid(axil_pcie_wvalid), + .s_axil_wready(axil_pcie_wready), + .s_axil_bresp(axil_pcie_bresp), + .s_axil_bvalid(axil_pcie_bvalid), + .s_axil_bready(axil_pcie_bready), + .s_axil_araddr(axil_pcie_araddr), + .s_axil_arprot(axil_pcie_arprot), + .s_axil_arvalid(axil_pcie_arvalid), + .s_axil_arready(axil_pcie_arready), + .s_axil_rdata(axil_pcie_rdata), + .s_axil_rresp(axil_pcie_rresp), + .s_axil_rvalid(axil_pcie_rvalid), + .s_axil_rready(axil_pcie_rready), + .m_axil_awaddr(axil_if_awaddr), + .m_axil_awprot(axil_if_awprot), + .m_axil_awvalid(axil_if_awvalid), + .m_axil_awready(axil_if_awready), + .m_axil_wdata(axil_if_wdata), + .m_axil_wstrb(axil_if_wstrb), + .m_axil_wvalid(axil_if_wvalid), + .m_axil_wready(axil_if_wready), + .m_axil_bresp(axil_if_bresp), + .m_axil_bvalid(axil_if_bvalid), + .m_axil_bready(axil_if_bready), + .m_axil_araddr(axil_if_araddr), + .m_axil_arprot(axil_if_arprot), + .m_axil_arvalid(axil_if_arvalid), + .m_axil_arready(axil_if_arready), + .m_axil_rdata(axil_if_rdata), + .m_axil_rresp(axil_if_rresp), + .m_axil_rvalid(axil_if_rvalid), + .m_axil_rready(axil_if_rready) +); + +function [31:0] w_32(input [31:0] val); + w_32 = val; +endfunction + +axil_interconnect #( + .DATA_WIDTH(AXIL_DATA_WIDTH), + .ADDR_WIDTH(AXIL_ADDR_WIDTH), + .S_COUNT(IF_COUNT), + .M_COUNT(2), + .M_BASE_ADDR({24'h020000, 24'h000000}), + .M_ADDR_WIDTH({w_32(8+6+$clog2(4)), w_32(17)}), + .M_CONNECT_READ({2{{IF_COUNT{1'b1}}}}), + .M_CONNECT_WRITE({2{{IF_COUNT{1'b1}}}}) +) +axil_csr_interconnect_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + .s_axil_awaddr(axil_if_csr_awaddr & {IF_COUNT{23'h03ffff}}), + .s_axil_awprot(axil_if_csr_awprot), + .s_axil_awvalid(axil_if_csr_awvalid), + .s_axil_awready(axil_if_csr_awready), + .s_axil_wdata(axil_if_csr_wdata), + .s_axil_wstrb(axil_if_csr_wstrb), + .s_axil_wvalid(axil_if_csr_wvalid), + .s_axil_wready(axil_if_csr_wready), + .s_axil_bresp(axil_if_csr_bresp), + .s_axil_bvalid(axil_if_csr_bvalid), + .s_axil_bready(axil_if_csr_bready), + .s_axil_araddr(axil_if_csr_araddr & {IF_COUNT{23'h03ffff}}), + .s_axil_arprot(axil_if_csr_arprot), + .s_axil_arvalid(axil_if_csr_arvalid), + .s_axil_arready(axil_if_csr_arready), + .s_axil_rdata(axil_if_csr_rdata), + .s_axil_rresp(axil_if_csr_rresp), + .s_axil_rvalid(axil_if_csr_rvalid), + .s_axil_rready(axil_if_csr_rready), + .m_axil_awaddr( {axil_ber_awaddr, axil_csr_awaddr}), + .m_axil_awprot( {axil_ber_awprot, axil_csr_awprot}), + .m_axil_awvalid( {axil_ber_awvalid, axil_csr_awvalid}), + .m_axil_awready( {axil_ber_awready, axil_csr_awready}), + .m_axil_wdata( {axil_ber_wdata, axil_csr_wdata}), + .m_axil_wstrb( {axil_ber_wstrb, axil_csr_wstrb}), + .m_axil_wvalid( {axil_ber_wvalid, axil_csr_wvalid}), + .m_axil_wready( {axil_ber_wready, axil_csr_wready}), + .m_axil_bresp( {axil_ber_bresp, axil_csr_bresp}), + .m_axil_bvalid( {axil_ber_bvalid, axil_csr_bvalid}), + .m_axil_bready( {axil_ber_bready, axil_csr_bready}), + .m_axil_araddr( {axil_ber_araddr, axil_csr_araddr}), + .m_axil_arprot( {axil_ber_arprot, axil_csr_arprot}), + .m_axil_arvalid( {axil_ber_arvalid, axil_csr_arvalid}), + .m_axil_arready( {axil_ber_arready, axil_csr_arready}), + .m_axil_rdata( {axil_ber_rdata, axil_csr_rdata}), + .m_axil_rresp( {axil_ber_rresp, axil_csr_rresp}), + .m_axil_rvalid( {axil_ber_rvalid, axil_csr_rvalid}), + .m_axil_rready( {axil_ber_rready, axil_csr_rready}) +); + +axi_crossbar #( + .S_COUNT(2), + .M_COUNT(IF_COUNT), + .DATA_WIDTH(AXI_DATA_WIDTH), + .ADDR_WIDTH(AXI_ADDR_WIDTH), + .STRB_WIDTH(AXI_STRB_WIDTH), + .S_ID_WIDTH(AXI_ID_WIDTH), + .M_ID_WIDTH(IF_AXI_ID_WIDTH), + .AWUSER_ENABLE(0), + .WUSER_ENABLE(0), + .BUSER_ENABLE(0), + .ARUSER_ENABLE(0), + .RUSER_ENABLE(0), + .S_THREADS({2{32'd2}}), + .S_ACCEPT({2{32'd16}}), + .M_REGIONS(1), + .M_BASE_ADDR(IF_AXI_BASE_ADDR), + .M_ADDR_WIDTH({IF_COUNT{IF_AXI_ADDR_WIDTH}}), + .M_CONNECT_READ({IF_COUNT{{2{1'b1}}}}), + .M_CONNECT_WRITE({IF_COUNT{{2{1'b1}}}}), + .M_ISSUE({IF_COUNT{32'd4}}), + .M_SECURE({IF_COUNT{1'b0}}) +) +axi_crossbar_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + .s_axi_awid( {axi_pcie_dma_awid, axi_pcie_awid}), + .s_axi_awaddr( {axi_pcie_dma_awaddr, axi_pcie_awaddr}), + .s_axi_awlen( {axi_pcie_dma_awlen, axi_pcie_awlen}), + .s_axi_awsize( {axi_pcie_dma_awsize, axi_pcie_awsize}), + .s_axi_awburst( {axi_pcie_dma_awburst, axi_pcie_awburst}), + .s_axi_awlock( {axi_pcie_dma_awlock, axi_pcie_awlock}), + .s_axi_awcache( {axi_pcie_dma_awcache, axi_pcie_awcache}), + .s_axi_awprot( {axi_pcie_dma_awprot, axi_pcie_awprot}), + .s_axi_awqos(0), + .s_axi_awuser(0), + .s_axi_awvalid( {axi_pcie_dma_awvalid, axi_pcie_awvalid}), + .s_axi_awready( {axi_pcie_dma_awready, axi_pcie_awready}), + .s_axi_wdata( {axi_pcie_dma_wdata, axi_pcie_wdata}), + .s_axi_wstrb( {axi_pcie_dma_wstrb, axi_pcie_wstrb}), + .s_axi_wlast( {axi_pcie_dma_wlast, axi_pcie_wlast}), + .s_axi_wuser(0), + .s_axi_wvalid( {axi_pcie_dma_wvalid, axi_pcie_wvalid}), + .s_axi_wready( {axi_pcie_dma_wready, axi_pcie_wready}), + .s_axi_bid( {axi_pcie_dma_bid, axi_pcie_bid}), + .s_axi_bresp( {axi_pcie_dma_bresp, axi_pcie_bresp}), + .s_axi_buser(), + .s_axi_bvalid( {axi_pcie_dma_bvalid, axi_pcie_bvalid}), + .s_axi_bready( {axi_pcie_dma_bready, axi_pcie_bready}), + .s_axi_arid( {axi_pcie_dma_arid, axi_pcie_arid}), + .s_axi_araddr( {axi_pcie_dma_araddr, axi_pcie_araddr}), + .s_axi_arlen( {axi_pcie_dma_arlen, axi_pcie_arlen}), + .s_axi_arsize( {axi_pcie_dma_arsize, axi_pcie_arsize}), + .s_axi_arburst( {axi_pcie_dma_arburst, axi_pcie_arburst}), + .s_axi_arlock( {axi_pcie_dma_arlock, axi_pcie_arlock}), + .s_axi_arcache( {axi_pcie_dma_arcache, axi_pcie_arcache}), + .s_axi_arprot( {axi_pcie_dma_arprot, axi_pcie_arprot}), + .s_axi_arqos(0), + .s_axi_aruser(0), + .s_axi_arvalid( {axi_pcie_dma_arvalid, axi_pcie_arvalid}), + .s_axi_arready( {axi_pcie_dma_arready, axi_pcie_arready}), + .s_axi_rid( {axi_pcie_dma_rid, axi_pcie_rid}), + .s_axi_rdata( {axi_pcie_dma_rdata, axi_pcie_rdata}), + .s_axi_rresp( {axi_pcie_dma_rresp, axi_pcie_rresp}), + .s_axi_rlast( {axi_pcie_dma_rlast, axi_pcie_rlast}), + .s_axi_ruser(), + .s_axi_rvalid( {axi_pcie_dma_rvalid, axi_pcie_rvalid}), + .s_axi_rready( {axi_pcie_dma_rready, axi_pcie_rready}), + + + .m_axi_awid( {axi_if_awid}), + .m_axi_awaddr( {axi_if_awaddr}), + .m_axi_awlen( {axi_if_awlen}), + .m_axi_awsize( {axi_if_awsize}), + .m_axi_awburst( {axi_if_awburst}), + .m_axi_awlock( {axi_if_awlock}), + .m_axi_awcache( {axi_if_awcache}), + .m_axi_awprot( {axi_if_awprot}), + .m_axi_awqos(), + .m_axi_awregion(), + .m_axi_awuser(), + .m_axi_awvalid( {axi_if_awvalid}), + .m_axi_awready( {axi_if_awready}), + .m_axi_wdata( {axi_if_wdata}), + .m_axi_wstrb( {axi_if_wstrb}), + .m_axi_wlast( {axi_if_wlast}), + .m_axi_wuser(), + .m_axi_wvalid( {axi_if_wvalid}), + .m_axi_wready( {axi_if_wready}), + .m_axi_bid( {axi_if_bid}), + .m_axi_bresp( {axi_if_bresp}), + .m_axi_buser(0), + .m_axi_bvalid( {axi_if_bvalid}), + .m_axi_bready( {axi_if_bready}), + .m_axi_arid( {axi_if_arid}), + .m_axi_araddr( {axi_if_araddr}), + .m_axi_arlen( {axi_if_arlen}), + .m_axi_arsize( {axi_if_arsize}), + .m_axi_arburst( {axi_if_arburst}), + .m_axi_arlock( {axi_if_arlock}), + .m_axi_arcache( {axi_if_arcache}), + .m_axi_arprot( {axi_if_arprot}), + .m_axi_arqos(), + .m_axi_arregion(), + .m_axi_aruser(), + .m_axi_arvalid( {axi_if_arvalid}), + .m_axi_arready( {axi_if_arready}), + .m_axi_rid( {axi_if_rid}), + .m_axi_rdata( {axi_if_rdata}), + .m_axi_rresp( {axi_if_rresp}), + .m_axi_rlast( {axi_if_rlast}), + .m_axi_ruser(0), + .m_axi_rvalid( {axi_if_rvalid}), + .m_axi_rready( {axi_if_rready}) +); + +parameter IF_PCIE_DMA_TAG_WIDTH = PCIE_DMA_TAG_WIDTH-$clog2(IF_COUNT); + +wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_axi_dma_read_desc_pcie_addr; +wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_read_desc_axi_addr; +wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_axi_dma_read_desc_len; +wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_read_desc_tag; +wire [IF_COUNT-1:0] if_pcie_axi_dma_read_desc_valid; +wire [IF_COUNT-1:0] if_pcie_axi_dma_read_desc_ready; + +wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_read_desc_status_tag; +wire [IF_COUNT-1:0] if_pcie_axi_dma_read_desc_status_valid; + +wire [IF_COUNT*PCIE_ADDR_WIDTH-1:0] if_pcie_axi_dma_write_desc_pcie_addr; +wire [IF_COUNT*AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_write_desc_axi_addr; +wire [IF_COUNT*PCIE_DMA_LEN_WIDTH-1:0] if_pcie_axi_dma_write_desc_len; +wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_write_desc_tag; +wire [IF_COUNT-1:0] if_pcie_axi_dma_write_desc_valid; +wire [IF_COUNT-1:0] if_pcie_axi_dma_write_desc_ready; + +wire [IF_COUNT*IF_PCIE_DMA_TAG_WIDTH-1:0] if_pcie_axi_dma_write_desc_status_tag; +wire [IF_COUNT-1:0] if_pcie_axi_dma_write_desc_status_valid; + +pcie_axi_dma_desc_mux # +( + .PORTS(IF_COUNT), + .PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH), + .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), + .LEN_WIDTH(PCIE_DMA_LEN_WIDTH), + .S_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH), + .M_TAG_WIDTH(PCIE_DMA_TAG_WIDTH), + .ARB_TYPE("ROUND_ROBIN"), + .LSB_PRIORITY("HIGH") +) +pcie_axi_dma_read_desc_mux_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * Descriptor output + */ + .m_axis_desc_pcie_addr(pcie_axi_dma_read_desc_pcie_addr), + .m_axis_desc_axi_addr(pcie_axi_dma_read_desc_axi_addr), + .m_axis_desc_len(pcie_axi_dma_read_desc_len), + .m_axis_desc_tag(pcie_axi_dma_read_desc_tag), + .m_axis_desc_valid(pcie_axi_dma_read_desc_valid), + .m_axis_desc_ready(pcie_axi_dma_read_desc_ready), + + /* + * Descriptor status input + */ + .s_axis_desc_status_tag(pcie_axi_dma_read_desc_status_tag), + .s_axis_desc_status_valid(pcie_axi_dma_read_desc_status_valid), + + /* + * Descriptor input + */ + .s_axis_desc_pcie_addr(if_pcie_axi_dma_read_desc_pcie_addr), + .s_axis_desc_axi_addr(if_pcie_axi_dma_read_desc_axi_addr), + .s_axis_desc_len(if_pcie_axi_dma_read_desc_len), + .s_axis_desc_tag(if_pcie_axi_dma_read_desc_tag), + .s_axis_desc_valid(if_pcie_axi_dma_read_desc_valid), + .s_axis_desc_ready(if_pcie_axi_dma_read_desc_ready), + + /* + * Descriptor status output + */ + .m_axis_desc_status_tag(if_pcie_axi_dma_read_desc_status_tag), + .m_axis_desc_status_valid(if_pcie_axi_dma_read_desc_status_valid) +); + +pcie_axi_dma_desc_mux # +( + .PORTS(IF_COUNT), + .PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH), + .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), + .LEN_WIDTH(PCIE_DMA_LEN_WIDTH), + .S_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH), + .M_TAG_WIDTH(PCIE_DMA_TAG_WIDTH), + .ARB_TYPE("ROUND_ROBIN"), + .LSB_PRIORITY("HIGH") +) +pcie_axi_dma_write_desc_mux_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * Descriptor output + */ + .m_axis_desc_pcie_addr(pcie_axi_dma_write_desc_pcie_addr), + .m_axis_desc_axi_addr(pcie_axi_dma_write_desc_axi_addr), + .m_axis_desc_len(pcie_axi_dma_write_desc_len), + .m_axis_desc_tag(pcie_axi_dma_write_desc_tag), + .m_axis_desc_valid(pcie_axi_dma_write_desc_valid), + .m_axis_desc_ready(pcie_axi_dma_write_desc_ready), + + /* + * Descriptor status input + */ + .s_axis_desc_status_tag(pcie_axi_dma_write_desc_status_tag), + .s_axis_desc_status_valid(pcie_axi_dma_write_desc_status_valid), + + /* + * Descriptor input + */ + .s_axis_desc_pcie_addr(if_pcie_axi_dma_write_desc_pcie_addr), + .s_axis_desc_axi_addr(if_pcie_axi_dma_write_desc_axi_addr), + .s_axis_desc_len(if_pcie_axi_dma_write_desc_len), + .s_axis_desc_tag(if_pcie_axi_dma_write_desc_tag), + .s_axis_desc_valid(if_pcie_axi_dma_write_desc_valid), + .s_axis_desc_ready(if_pcie_axi_dma_write_desc_ready), + + /* + * Descriptor status output + */ + .m_axis_desc_status_tag(if_pcie_axi_dma_write_desc_status_tag), + .m_axis_desc_status_valid(if_pcie_axi_dma_write_desc_status_valid) +); + +// PTP clock +ptp_clock #( + .PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH), + .OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH), + .FNS_WIDTH(PTP_FNS_WIDTH), + .PERIOD_NS(PTP_PERIOD_NS), + .PERIOD_FNS(PTP_PERIOD_FNS), + .DRIFT_ENABLE(0) +) +ptp_clock_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * Timestamp inputs for synchronization + */ + .input_ts_96(set_ptp_ts_96_reg), + .input_ts_96_valid(set_ptp_ts_96_valid_reg), + .input_ts_64(0), + .input_ts_64_valid(1'b0), + + /* + * Period adjustment + */ + .input_period_ns(set_ptp_period_ns_reg), + .input_period_fns(set_ptp_period_fns_reg), + .input_period_valid(set_ptp_period_valid_reg), + + /* + * Offset adjustment + */ + .input_adj_ns(set_ptp_offset_ns_reg), + .input_adj_fns(set_ptp_offset_fns_reg), + .input_adj_count(set_ptp_offset_count_reg), + .input_adj_valid(set_ptp_offset_valid_reg), + .input_adj_active(set_ptp_offset_active), + + /* + * Drift adjustment + */ + .input_drift_ns(0), + .input_drift_fns(0), + .input_drift_rate(0), + .input_drift_valid(0), + + /* + * Timestamp outputs + */ + .output_ts_96(ptp_ts_96), + .output_ts_64(), + .output_ts_step(ptp_ts_step), + + /* + * PPS output + */ + .output_pps(ptp_pps) +); + +assign sma_out = ptp_perout_pulse; +assign sma_out_en = 1'b0; +assign sma_term_en = 1'b0; + +ptp_perout #( + .FNS_ENABLE(0), + .OUT_START_S(0), + .OUT_START_NS(0), + .OUT_START_FNS(0), + .OUT_PERIOD_S(1), + .OUT_PERIOD_NS(0), + .OUT_PERIOD_FNS(0), + .OUT_WIDTH_S(0), + .OUT_WIDTH_NS(500000000), + .OUT_WIDTH_FNS(0) +) +ptp_perout_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + .input_ts_96(ptp_ts_96), + .input_ts_step(ptp_ts_step), + .enable(ptp_perout_enable_reg), + .input_start(set_ptp_perout_start_ts_96_reg), + .input_start_valid(set_ptp_perout_start_ts_96_valid_reg), + .input_period(set_ptp_perout_period_ts_96_reg), + .input_period_valid(set_ptp_perout_period_ts_96_valid_reg), + .input_width(set_ptp_perout_width_ts_96_reg), + .input_width_valid(set_ptp_perout_width_ts_96_valid_reg), + .locked(ptp_perout_locked), + .error(ptp_perout_error), + .output_pulse(ptp_perout_pulse) +); + +reg [26:0] pps_led_counter_reg = 0; +reg pps_led_reg = 0; + +always @(posedge clk_250mhz) begin + if (ptp_pps) begin + pps_led_counter_reg <= 125000000; + end else if (pps_led_counter_reg > 0) begin + pps_led_counter_reg <= pps_led_counter_reg - 1; + end + + pps_led_reg <= pps_led_counter_reg > 0; +end + +// BER tester +tdma_ber #( + .COUNT(4), + .INDEX_WIDTH(6), + .SLICE_WIDTH(5), + .AXIL_DATA_WIDTH(AXIL_DATA_WIDTH), + .AXIL_ADDR_WIDTH(8+6+$clog2(4)), + .AXIL_STRB_WIDTH(AXIL_STRB_WIDTH), + .SCHEDULE_START_S(0), + .SCHEDULE_START_NS(0), + .SCHEDULE_PERIOD_S(0), + .SCHEDULE_PERIOD_NS(1000000), + .TIMESLOT_PERIOD_S(0), + .TIMESLOT_PERIOD_NS(100000), + .ACTIVE_PERIOD_S(0), + .ACTIVE_PERIOD_NS(90000) +) +tdma_ber_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + .phy_tx_clk({qsfp_tx_clk_4, qsfp_tx_clk_3, qsfp_tx_clk_2, qsfp_tx_clk_1}), + .phy_rx_clk({qsfp_rx_clk_4, qsfp_rx_clk_3, qsfp_rx_clk_2, qsfp_rx_clk_1}), + .phy_rx_error_count({qsfp_rx_error_count_4, qsfp_rx_error_count_3, qsfp_rx_error_count_2, qsfp_rx_error_count_1}), + .phy_tx_prbs31_enable({qsfp_tx_prbs31_enable_4, qsfp_tx_prbs31_enable_3, qsfp_tx_prbs31_enable_2, qsfp_tx_prbs31_enable_1}), + .phy_rx_prbs31_enable({qsfp_rx_prbs31_enable_4, qsfp_rx_prbs31_enable_3, qsfp_rx_prbs31_enable_2, qsfp_rx_prbs31_enable_1}), + .s_axil_awaddr(axil_ber_awaddr), + .s_axil_awprot(axil_ber_awprot), + .s_axil_awvalid(axil_ber_awvalid), + .s_axil_awready(axil_ber_awready), + .s_axil_wdata(axil_ber_wdata), + .s_axil_wstrb(axil_ber_wstrb), + .s_axil_wvalid(axil_ber_wvalid), + .s_axil_wready(axil_ber_wready), + .s_axil_bresp(axil_ber_bresp), + .s_axil_bvalid(axil_ber_bvalid), + .s_axil_bready(axil_ber_bready), + .s_axil_araddr(axil_ber_araddr), + .s_axil_arprot(axil_ber_arprot), + .s_axil_arvalid(axil_ber_arvalid), + .s_axil_arready(axil_ber_arready), + .s_axil_rdata(axil_ber_rdata), + .s_axil_rresp(axil_ber_rresp), + .s_axil_rvalid(axil_ber_rvalid), + .s_axil_rready(axil_ber_rready), + .ptp_ts_96(ptp_ts_96), + .ptp_ts_step(ptp_ts_step) +); + +wire [PORT_COUNT-1:0] port_xgmii_tx_clk = {qsfp_tx_clk_1}; +wire [PORT_COUNT-1:0] port_xgmii_tx_rst = {qsfp_tx_rst_1}; +wire [PORT_COUNT-1:0] port_xgmii_rx_clk = {qsfp_rx_clk_1}; +wire [PORT_COUNT-1:0] port_xgmii_rx_rst = {qsfp_rx_rst_1}; +wire [PORT_COUNT*64-1:0] port_xgmii_txd; +wire [PORT_COUNT*8-1:0] port_xgmii_txc; +wire [PORT_COUNT*64-1:0] port_xgmii_rxd = {qsfp_rxd_1}; +wire [PORT_COUNT*8-1:0] port_xgmii_rxc = {qsfp_rxc_1}; + +assign {qsfp_txd_1} = port_xgmii_txd; +assign {qsfp_txc_1} = port_xgmii_txc; + +// assign qsfp_txd_1 = 64'h0707070707070707; +// assign qsfp_txc_1 = 8'hff; +assign qsfp_txd_2 = 64'h0707070707070707; +assign qsfp_txc_2 = 8'hff; +assign qsfp_txd_3 = 64'h0707070707070707; +assign qsfp_txc_3 = 8'hff; +assign qsfp_txd_4 = 64'h0707070707070707; +assign qsfp_txc_4 = 8'hff; + +assign led[0] = pps_led_reg; +assign led[7:1] = 0; + +wire [IF_COUNT*32-1:0] if_msi_irq; + +assign msi_irq = if_msi_irq[31:0]; + +generate + genvar m, n; + + for (n = 0; n < IF_COUNT; n = n + 1) begin : iface + + wire [AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_read_desc_axi_addr_int; + assign if_pcie_axi_dma_read_desc_axi_addr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = if_pcie_axi_dma_read_desc_axi_addr_int | n*24'h800000; + wire [AXI_ADDR_WIDTH-1:0] if_pcie_axi_dma_write_desc_axi_addr_int; + assign if_pcie_axi_dma_write_desc_axi_addr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = if_pcie_axi_dma_write_desc_axi_addr_int | n*24'h800000; + + wire [PORTS_PER_IF*AXIS_DATA_WIDTH-1:0] tx_axis_tdata; + wire [PORTS_PER_IF*AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep; + wire [PORTS_PER_IF-1:0] tx_axis_tvalid; + wire [PORTS_PER_IF-1:0] tx_axis_tready; + wire [PORTS_PER_IF-1:0] tx_axis_tlast; + wire [PORTS_PER_IF-1:0] tx_axis_tuser; + + wire [PORTS_PER_IF*PTP_TS_WIDTH-1:0] tx_ptp_ts_96; + wire [PORTS_PER_IF-1:0] tx_ptp_ts_valid; + wire [PORTS_PER_IF-1:0] tx_ptp_ts_ready; + + wire [PORTS_PER_IF*AXIS_DATA_WIDTH-1:0] rx_axis_tdata; + wire [PORTS_PER_IF*AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep; + wire [PORTS_PER_IF-1:0] rx_axis_tvalid; + wire [PORTS_PER_IF-1:0] rx_axis_tready; + wire [PORTS_PER_IF-1:0] rx_axis_tlast; + wire [PORTS_PER_IF-1:0] rx_axis_tuser; + + wire [PORTS_PER_IF*PTP_TS_WIDTH-1:0] rx_ptp_ts_96; + wire [PORTS_PER_IF-1:0] rx_ptp_ts_valid; + wire [PORTS_PER_IF-1:0] rx_ptp_ts_ready; + + interface # + ( + .PORTS(PORTS_PER_IF), + .PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH), + .PCIE_DMA_LEN_WIDTH(PCIE_DMA_LEN_WIDTH), + .PCIE_DMA_TAG_WIDTH(IF_PCIE_DMA_TAG_WIDTH), + .TX_OP_TABLE_SIZE(TX_OP_TABLE_SIZE), + .RX_OP_TABLE_SIZE(RX_OP_TABLE_SIZE), + .TX_CPL_OP_TABLE_SIZE(TX_CPL_OP_TABLE_SIZE), + .RX_CPL_OP_TABLE_SIZE(RX_CPL_OP_TABLE_SIZE), + .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), + .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), + .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), + .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), + .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), + .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE), + .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), + .TX_SCHEDULER(TX_SCHEDULER), + .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), + .INT_WIDTH(8), + .QUEUE_PTR_WIDTH(16), + .QUEUE_LOG_SIZE_WIDTH(4), + .RAM_ADDR_WIDTH(16), + .RAM_SIZE(2**15), + .PTP_TS_ENABLE(PTP_TS_ENABLE), + .PTP_TS_WIDTH(PTP_TS_WIDTH), + .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), + .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .AXIL_DATA_WIDTH(AXIL_DATA_WIDTH), + .AXIL_ADDR_WIDTH(IF_AXIL_ADDR_WIDTH), + .AXIL_STRB_WIDTH(AXIL_STRB_WIDTH), + .AXI_DATA_WIDTH(AXI_DATA_WIDTH), + .AXI_ADDR_WIDTH(IF_AXI_ADDR_WIDTH), + .AXI_STRB_WIDTH(AXI_STRB_WIDTH), + .AXI_ID_WIDTH(IF_AXI_ID_WIDTH), + .AXI_BASE_ADDR(n*2**IF_AXI_ADDR_WIDTH), + .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH), + .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH) + ) + interface_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + + /* + * PCIe DMA read descriptor output + */ + .m_axis_pcie_axi_dma_read_desc_pcie_addr(if_pcie_axi_dma_read_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]), + .m_axis_pcie_axi_dma_read_desc_axi_addr(if_pcie_axi_dma_read_desc_axi_addr_int), + .m_axis_pcie_axi_dma_read_desc_len(if_pcie_axi_dma_read_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]), + .m_axis_pcie_axi_dma_read_desc_tag(if_pcie_axi_dma_read_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), + .m_axis_pcie_axi_dma_read_desc_valid(if_pcie_axi_dma_read_desc_valid[n]), + .m_axis_pcie_axi_dma_read_desc_ready(if_pcie_axi_dma_read_desc_ready[n]), + + /* + * PCIe DMA read descriptor status input + */ + .s_axis_pcie_axi_dma_read_desc_status_tag(if_pcie_axi_dma_read_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), + .s_axis_pcie_axi_dma_read_desc_status_valid(if_pcie_axi_dma_read_desc_status_valid[n]), + + /* + * PCIe DMA write descriptor output + */ + .m_axis_pcie_axi_dma_write_desc_pcie_addr(if_pcie_axi_dma_write_desc_pcie_addr[n*PCIE_ADDR_WIDTH +: PCIE_ADDR_WIDTH]), + .m_axis_pcie_axi_dma_write_desc_axi_addr(if_pcie_axi_dma_write_desc_axi_addr_int), + .m_axis_pcie_axi_dma_write_desc_len(if_pcie_axi_dma_write_desc_len[n*PCIE_DMA_LEN_WIDTH +: PCIE_DMA_LEN_WIDTH]), + .m_axis_pcie_axi_dma_write_desc_tag(if_pcie_axi_dma_write_desc_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), + .m_axis_pcie_axi_dma_write_desc_valid(if_pcie_axi_dma_write_desc_valid[n]), + .m_axis_pcie_axi_dma_write_desc_ready(if_pcie_axi_dma_write_desc_ready[n]), + + /* + * PCIe DMA write descriptor status input + */ + .s_axis_pcie_axi_dma_write_desc_status_tag(if_pcie_axi_dma_write_desc_status_tag[n*IF_PCIE_DMA_TAG_WIDTH +: IF_PCIE_DMA_TAG_WIDTH]), + .s_axis_pcie_axi_dma_write_desc_status_valid(if_pcie_axi_dma_write_desc_status_valid[n]), + + /* + * AXI-Lite slave interface + */ + .s_axil_awaddr(axil_if_awaddr[n*AXIL_ADDR_WIDTH +: AXIL_ADDR_WIDTH]), + .s_axil_awprot(axil_if_awprot[n*3 +: 3]), + .s_axil_awvalid(axil_if_awvalid[n]), + .s_axil_awready(axil_if_awready[n]), + .s_axil_wdata(axil_if_wdata[n*AXIL_DATA_WIDTH +: AXIL_DATA_WIDTH]), + .s_axil_wstrb(axil_if_wstrb[n*AXIL_STRB_WIDTH +: AXIL_STRB_WIDTH]), + .s_axil_wvalid(axil_if_wvalid[n]), + .s_axil_wready(axil_if_wready[n]), + .s_axil_bresp(axil_if_bresp[n*2 +: 2]), + .s_axil_bvalid(axil_if_bvalid[n]), + .s_axil_bready(axil_if_bready[n]), + .s_axil_araddr(axil_if_araddr[n*AXIL_ADDR_WIDTH +: AXIL_ADDR_WIDTH]), + .s_axil_arprot(axil_if_arprot[n*3 +: 3]), + .s_axil_arvalid(axil_if_arvalid[n]), + .s_axil_arready(axil_if_arready[n]), + .s_axil_rdata(axil_if_rdata[n*AXIL_DATA_WIDTH +: AXIL_DATA_WIDTH]), + .s_axil_rresp(axil_if_rresp[n*2 +: 2]), + .s_axil_rvalid(axil_if_rvalid[n]), + .s_axil_rready(axil_if_rready[n]), + + /* + * AXI-Lite master interface (passthrough for NIC control and status) + */ + .m_axil_csr_awaddr(axil_if_csr_awaddr[n*AXIL_ADDR_WIDTH +: AXIL_ADDR_WIDTH]), + .m_axil_csr_awprot(axil_if_csr_awprot[n*3 +: 3]), + .m_axil_csr_awvalid(axil_if_csr_awvalid[n]), + .m_axil_csr_awready(axil_if_csr_awready[n]), + .m_axil_csr_wdata(axil_if_csr_wdata[n*AXIL_DATA_WIDTH +: AXIL_DATA_WIDTH]), + .m_axil_csr_wstrb(axil_if_csr_wstrb[n*AXIL_STRB_WIDTH +: AXIL_STRB_WIDTH]), + .m_axil_csr_wvalid(axil_if_csr_wvalid[n]), + .m_axil_csr_wready(axil_if_csr_wready[n]), + .m_axil_csr_bresp(axil_if_csr_bresp[n*2 +: 2]), + .m_axil_csr_bvalid(axil_if_csr_bvalid[n]), + .m_axil_csr_bready(axil_if_csr_bready[n]), + .m_axil_csr_araddr(axil_if_csr_araddr[n*AXIL_ADDR_WIDTH +: AXIL_ADDR_WIDTH]), + .m_axil_csr_arprot(axil_if_csr_arprot[n*3 +: 3]), + .m_axil_csr_arvalid(axil_if_csr_arvalid[n]), + .m_axil_csr_arready(axil_if_csr_arready[n]), + .m_axil_csr_rdata(axil_if_csr_rdata[n*AXIL_DATA_WIDTH +: AXIL_DATA_WIDTH]), + .m_axil_csr_rresp(axil_if_csr_rresp[n*2 +: 2]), + .m_axil_csr_rvalid(axil_if_csr_rvalid[n]), + .m_axil_csr_rready(axil_if_csr_rready[n]), + + /* + * AXI slave inteface + */ + .s_axi_awid(axi_if_awid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]), + .s_axi_awaddr(axi_if_awaddr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH]), + .s_axi_awlen(axi_if_awlen[n*8 +: 8]), + .s_axi_awsize(axi_if_awsize[n*3 +: 3]), + .s_axi_awburst(axi_if_awburst[n*2 +: 2]), + .s_axi_awlock(axi_if_awlock[n]), + .s_axi_awcache(axi_if_awcache[n*4 +: 4]), + .s_axi_awprot(axi_if_awprot[n*3 +: 3]), + .s_axi_awvalid(axi_if_awvalid[n]), + .s_axi_awready(axi_if_awready[n]), + .s_axi_wdata(axi_if_wdata[n*AXI_DATA_WIDTH +: AXI_DATA_WIDTH]), + .s_axi_wstrb(axi_if_wstrb[n*AXI_STRB_WIDTH +: AXI_STRB_WIDTH]), + .s_axi_wlast(axi_if_wlast[n]), + .s_axi_wvalid(axi_if_wvalid[n]), + .s_axi_wready(axi_if_wready[n]), + .s_axi_bid(axi_if_bid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]), + .s_axi_bresp(axi_if_bresp[n*2 +: 2]), + .s_axi_bvalid(axi_if_bvalid[n]), + .s_axi_bready(axi_if_bready[n]), + .s_axi_arid(axi_if_arid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]), + .s_axi_araddr(axi_if_araddr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH]), + .s_axi_arlen(axi_if_arlen[n*8 +: 8]), + .s_axi_arsize(axi_if_arsize[n*3 +: 3]), + .s_axi_arburst(axi_if_arburst[n*2 +: 2]), + .s_axi_arlock(axi_if_arlock[n]), + .s_axi_arcache(axi_if_arcache[n*4 +: 4]), + .s_axi_arprot(axi_if_arprot[n*3 +: 3]), + .s_axi_arvalid(axi_if_arvalid[n]), + .s_axi_arready(axi_if_arready[n]), + .s_axi_rid(axi_if_rid[n*IF_AXI_ID_WIDTH +: IF_AXI_ID_WIDTH]), + .s_axi_rdata(axi_if_rdata[n*AXI_DATA_WIDTH +: AXI_DATA_WIDTH]), + .s_axi_rresp(axi_if_rresp[n*2 +: 2]), + .s_axi_rlast(axi_if_rlast[n]), + .s_axi_rvalid(axi_if_rvalid[n]), + .s_axi_rready(axi_if_rready[n]), + + /* + * Transmit data output + */ + .tx_axis_tdata(tx_axis_tdata), + .tx_axis_tkeep(tx_axis_tkeep), + .tx_axis_tvalid(tx_axis_tvalid), + .tx_axis_tready(tx_axis_tready), + .tx_axis_tlast(tx_axis_tlast), + .tx_axis_tuser(tx_axis_tuser), + + /* + * Transmit timestamp input + */ + .s_axis_tx_ptp_ts_96(tx_ptp_ts_96), + .s_axis_tx_ptp_ts_valid(tx_ptp_ts_valid), + .s_axis_tx_ptp_ts_ready(tx_ptp_ts_ready), + + /* + * Receive data input + */ + .rx_axis_tdata(rx_axis_tdata), + .rx_axis_tkeep(rx_axis_tkeep), + .rx_axis_tvalid(rx_axis_tvalid), + .rx_axis_tready(rx_axis_tready), + .rx_axis_tlast(rx_axis_tlast), + .rx_axis_tuser(rx_axis_tuser), + + /* + * Receive timestamp input + */ + .s_axis_rx_ptp_ts_96(rx_ptp_ts_96), + .s_axis_rx_ptp_ts_valid(rx_ptp_ts_valid), + .s_axis_rx_ptp_ts_ready(rx_ptp_ts_ready), + + /* + * PTP clock + */ + .ptp_ts_96(ptp_ts_96), + .ptp_ts_step(ptp_ts_step), + + /* + * MSI interrupts + */ + .msi_irq(if_msi_irq[n*32 +: 32]) + ); + + for (m = 0; m < PORTS_PER_IF; m = m + 1) begin : mac + + eth_mac_10g_fifo #( + .DATA_WIDTH(64), + .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH), + .AXIS_KEEP_ENABLE(AXIS_KEEP_WIDTH > 1), + .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), + .TX_FIFO_DEPTH(TX_FIFO_DEPTH), + .TX_FRAME_FIFO(1), + .RX_FIFO_DEPTH(RX_FIFO_DEPTH), + .RX_FRAME_FIFO(1), + .LOGIC_PTP_PERIOD_NS(LOGIC_PTP_PERIOD_NS), + .LOGIC_PTP_PERIOD_FNS(LOGIC_PTP_PERIOD_FNS), + .PTP_PERIOD_NS(IF_PTP_PERIOD_NS), + .PTP_PERIOD_FNS(IF_PTP_PERIOD_FNS), + .PTP_USE_SAMPLE_CLOCK(0), + .TX_PTP_TS_ENABLE(PTP_TS_ENABLE), + .RX_PTP_TS_ENABLE(PTP_TS_ENABLE), + .TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH), + .RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH), + .PTP_TS_WIDTH(PTP_TS_WIDTH), + .TX_PTP_TAG_ENABLE(0), + .PTP_TAG_WIDTH(16) + ) + eth_mac_inst ( + .rx_clk(port_xgmii_rx_clk[n*PORTS_PER_IF+m]), + .rx_rst(port_xgmii_rx_rst[n*PORTS_PER_IF+m]), + .tx_clk(port_xgmii_tx_clk[n*PORTS_PER_IF+m]), + .tx_rst(port_xgmii_tx_rst[n*PORTS_PER_IF+m]), + .logic_clk(clk_250mhz), + .logic_rst(rst_250mhz), + .ptp_sample_clk(clk_250mhz), + + .tx_axis_tdata(tx_axis_tdata[m*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]), + .tx_axis_tkeep(tx_axis_tkeep[m*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]), + .tx_axis_tvalid(tx_axis_tvalid[m +: 1]), + .tx_axis_tready(tx_axis_tready[m +: 1]), + .tx_axis_tlast(tx_axis_tlast[m +: 1]), + .tx_axis_tuser(tx_axis_tuser[m +: 1]), + + .s_axis_tx_ptp_ts_tag(0), + .s_axis_tx_ptp_ts_valid(0), + .s_axis_tx_ptp_ts_ready(), + + .m_axis_tx_ptp_ts_96(tx_ptp_ts_96[m*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .m_axis_tx_ptp_ts_tag(), + .m_axis_tx_ptp_ts_valid(tx_ptp_ts_valid[m +: 1]), + .m_axis_tx_ptp_ts_ready(tx_ptp_ts_ready[m +: 1]), + + .rx_axis_tdata(rx_axis_tdata[m*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]), + .rx_axis_tkeep(rx_axis_tkeep[m*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]), + .rx_axis_tvalid(rx_axis_tvalid[m +: 1]), + .rx_axis_tready(rx_axis_tready[m +: 1]), + .rx_axis_tlast(rx_axis_tlast[m +: 1]), + .rx_axis_tuser(rx_axis_tuser[m +: 1]), + + .m_axis_rx_ptp_ts_96(rx_ptp_ts_96[m*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .m_axis_rx_ptp_ts_valid(rx_ptp_ts_valid[m +: 1]), + .m_axis_rx_ptp_ts_ready(rx_ptp_ts_ready[m +: 1]), + + .xgmii_rxd(port_xgmii_rxd[(n*PORTS_PER_IF+m)*64 +: 64]), + .xgmii_rxc(port_xgmii_rxc[(n*PORTS_PER_IF+m)*8 +: 8]), + .xgmii_txd(port_xgmii_txd[(n*PORTS_PER_IF+m)*64 +: 64]), + .xgmii_txc(port_xgmii_txc[(n*PORTS_PER_IF+m)*8 +: 8]), + + .tx_error_underflow(), + .tx_fifo_overflow(), + .tx_fifo_bad_frame(), + .tx_fifo_good_frame(), + .rx_error_bad_frame(), + .rx_error_bad_fcs(), + .rx_fifo_overflow(), + .rx_fifo_bad_frame(), + .rx_fifo_good_frame(), + + .ptp_ts_96(ptp_ts_96), + + .ifg_delay(8'd12) + ); + + end + + end + +endgenerate + +endmodule diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/sync_reset.v b/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/sync_reset.v new file mode 100644 index 000000000..acbcf1c6e --- /dev/null +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/sync_reset.v @@ -0,0 +1,52 @@ +/* + +Copyright (c) 2014-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog-2001 + +`timescale 1 ns / 1 ps + +/* + * Synchronizes an active-high asynchronous reset signal to a given clock by + * using a pipeline of N registers. + */ +module sync_reset #( + parameter N=2 // depth of synchronizer +)( + input wire clk, + input wire rst, + output wire sync_reset_out +); + +reg [N-1:0] sync_reg = {N{1'b1}}; + +assign sync_reset_out = sync_reg[N-1]; + +always @(posedge clk or posedge rst) begin + if (rst) + sync_reg <= {N{1'b1}}; + else + sync_reg <= {sync_reg[N-2:0], 1'b0}; +end + +endmodule diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/sync_signal.v b/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/sync_signal.v new file mode 100644 index 000000000..b2a8ce3de --- /dev/null +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/sync_signal.v @@ -0,0 +1,58 @@ +/* + +Copyright (c) 2014-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog-2001 + +`timescale 1 ns / 1 ps + +/* + * Synchronizes an asyncronous signal to a given clock by using a pipeline of + * two registers. + */ +module sync_signal #( + parameter WIDTH=1, // width of the input and output signals + parameter N=2 // depth of synchronizer +)( + input wire clk, + input wire [WIDTH-1:0] in, + output wire [WIDTH-1:0] out +); + +reg [WIDTH-1:0] sync_reg[N-1:0]; + +/* + * The synchronized output is the last register in the pipeline. + */ +assign out = sync_reg[N-1]; + +integer k; + +always @(posedge clk) begin + sync_reg[0] <= in; + for (k = 1; k < N; k = k + 1) begin + sync_reg[k] <= sync_reg[k-1]; + end +end + +endmodule diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/tb/axis_ep.py b/fpga/mqnic_tdma/VCU108/fpga_10g/tb/axis_ep.py new file mode 120000 index 000000000..385bb0300 --- /dev/null +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/tb/axis_ep.py @@ -0,0 +1 @@ +../lib/eth/tb/axis_ep.py \ No newline at end of file diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/tb/mqnic.py b/fpga/mqnic_tdma/VCU108/fpga_10g/tb/mqnic.py new file mode 120000 index 000000000..f2c96aec4 --- /dev/null +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/tb/mqnic.py @@ -0,0 +1 @@ +../../../../common/tb/mqnic.py \ No newline at end of file diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/tb/pcie.py b/fpga/mqnic_tdma/VCU108/fpga_10g/tb/pcie.py new file mode 120000 index 000000000..abea2f963 --- /dev/null +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/tb/pcie.py @@ -0,0 +1 @@ +../lib/pcie/tb/pcie.py \ No newline at end of file diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/tb/pcie_us.py b/fpga/mqnic_tdma/VCU108/fpga_10g/tb/pcie_us.py new file mode 120000 index 000000000..ef028ec29 --- /dev/null +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/tb/pcie_us.py @@ -0,0 +1 @@ +../lib/pcie/tb/pcie_us.py \ No newline at end of file diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.py b/fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.py new file mode 100755 index 000000000..248df2f8a --- /dev/null +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.py @@ -0,0 +1,890 @@ +#!/usr/bin/env python +""" + +Copyright 2019, The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +The views and conclusions contained in the software and documentation are those +of the authors and should not be interpreted as representing official policies, +either expressed or implied, of The Regents of the University of California. + +""" + +from myhdl import * +import os + +import pcie +import pcie_us +import xgmii_ep + +import struct + +import mqnic + +module = 'fpga_core' +testbench = 'test_%s' % module + +srcs = [] + +srcs.append("../rtl/%s.v" % module) +srcs.append("../tb/ila_0.v") +srcs.append("../rtl/common/interface.v") +srcs.append("../rtl/common/port.v") +srcs.append("../rtl/common/queue_manager.v") +srcs.append("../rtl/common/cpl_queue_manager.v") +srcs.append("../rtl/common/tx_engine.v") +srcs.append("../rtl/common/rx_engine.v") +srcs.append("../rtl/common/rx_checksum.v") +srcs.append("../rtl/common/tx_scheduler_tdma_rr.v") +srcs.append("../rtl/common/tdma_scheduler.v") +srcs.append("../rtl/common/event_queue.v") +srcs.append("../rtl/common/event_mux.v") +srcs.append("../rtl/common/tdma_ber.v") +srcs.append("../rtl/common/tdma_ber_ch.v") +srcs.append("../lib/eth/rtl/eth_mac_10g_fifo.v") +srcs.append("../lib/eth/rtl/eth_mac_10g.v") +srcs.append("../lib/eth/rtl/axis_xgmii_rx_64.v") +srcs.append("../lib/eth/rtl/axis_xgmii_tx_64.v") +srcs.append("../lib/eth/rtl/lfsr.v") +srcs.append("../lib/eth/rtl/ptp_clock.v") +srcs.append("../lib/eth/rtl/ptp_clock_cdc.v") +srcs.append("../lib/eth/rtl/ptp_perout.v") +srcs.append("../lib/eth/rtl/ptp_ts_extract.v") +srcs.append("../lib/axi/rtl/axi_crossbar.v") +srcs.append("../lib/axi/rtl/axi_crossbar_addr.v") +srcs.append("../lib/axi/rtl/axi_crossbar_rd.v") +srcs.append("../lib/axi/rtl/axi_crossbar_wr.v") +srcs.append("../lib/axi/rtl/axi_dma.v") +srcs.append("../lib/axi/rtl/axi_dma_rd.v") +srcs.append("../lib/axi/rtl/axi_dma_wr.v") +srcs.append("../lib/axi/rtl/axi_interconnect.v") +srcs.append("../lib/axi/rtl/axi_ram.v") +srcs.append("../lib/axi/rtl/axi_ram_rd_if.v") +srcs.append("../lib/axi/rtl/axi_ram_wr_if.v") +srcs.append("../lib/axi/rtl/axi_register_rd.v") +srcs.append("../lib/axi/rtl/axi_register_wr.v") +srcs.append("../lib/axi/rtl/axil_interconnect.v") +srcs.append("../lib/axi/rtl/arbiter.v") +srcs.append("../lib/axi/rtl/priority_encoder.v") +srcs.append("../lib/axis/rtl/axis_adapter.v") +srcs.append("../lib/axis/rtl/axis_arb_mux.v") +srcs.append("../lib/axis/rtl/axis_async_fifo.v") +srcs.append("../lib/axis/rtl/axis_async_fifo_adapter.v") +srcs.append("../lib/axis/rtl/axis_fifo.v") +srcs.append("../lib/axis/rtl/axis_register.v") +srcs.append("../lib/pcie/rtl/pcie_axi_dma_desc_mux.v") +srcs.append("../lib/pcie/rtl/pcie_us_axil_master.v") +srcs.append("../lib/pcie/rtl/pcie_us_axi_master.v") +srcs.append("../lib/pcie/rtl/pcie_us_axi_master_rd.v") +srcs.append("../lib/pcie/rtl/pcie_us_axi_master_wr.v") +srcs.append("../lib/pcie/rtl/pcie_us_axi_dma.v") +srcs.append("../lib/pcie/rtl/pcie_us_axi_dma_rd.v") +srcs.append("../lib/pcie/rtl/pcie_us_axi_dma_wr.v") +srcs.append("../lib/pcie/rtl/pcie_us_axis_cq_demux.v") +srcs.append("../lib/pcie/rtl/pcie_us_cfg.v") +srcs.append("../lib/pcie/rtl/pcie_us_msi.v") +srcs.append("../lib/pcie/rtl/pcie_tag_manager.v") +srcs.append("../lib/pcie/rtl/pulse_merge.v") +srcs.append("%s.v" % testbench) + +src = ' '.join(srcs) + +build_cmd = "iverilog -o %s.vvp %s" % (testbench, src) + +def frame_checksum(frame): + data = frame[14:] + + csum = 0 + odd = False + + for b in data: + if odd: + csum += b + else: + csum += b << 8 + odd = not odd + + csum = (csum & 0xffff) + (csum >> 16) + csum = (csum & 0xffff) + (csum >> 16) + + return csum + +def bench(): + + # Parameters + + + # Inputs + clk = Signal(bool(0)) + rst = Signal(bool(0)) + current_test = Signal(intbv(0)[8:]) + + clk_156mhz = Signal(bool(0)) + rst_156mhz = Signal(bool(0)) + clk_250mhz = Signal(bool(0)) + rst_250mhz = Signal(bool(0)) + btnu = Signal(bool(0)) + btnl = Signal(bool(0)) + btnd = Signal(bool(0)) + btnr = Signal(bool(0)) + btnc = Signal(bool(0)) + sw = Signal(intbv(0)[4:]) + i2c_scl_i = Signal(bool(1)) + i2c_sda_i = Signal(bool(1)) + m_axis_rq_tready = Signal(bool(0)) + s_axis_rc_tdata = Signal(intbv(0)[256:]) + s_axis_rc_tkeep = Signal(intbv(0)[8:]) + s_axis_rc_tlast = Signal(bool(0)) + s_axis_rc_tuser = Signal(intbv(0)[75:]) + s_axis_rc_tvalid = Signal(bool(0)) + s_axis_cq_tdata = Signal(intbv(0)[256:]) + s_axis_cq_tkeep = Signal(intbv(0)[8:]) + s_axis_cq_tlast = Signal(bool(0)) + s_axis_cq_tuser = Signal(intbv(0)[85:]) + s_axis_cq_tvalid = Signal(bool(0)) + m_axis_cc_tready = Signal(bool(0)) + pcie_tfc_nph_av = Signal(intbv(0)[2:]) + pcie_tfc_npd_av = Signal(intbv(0)[2:]) + cfg_max_payload = Signal(intbv(0)[3:]) + cfg_max_read_req = Signal(intbv(0)[3:]) + cfg_mgmt_read_data = Signal(intbv(0)[32:]) + cfg_mgmt_read_write_done = Signal(bool(0)) + cfg_interrupt_msi_enable = Signal(intbv(0)[4:]) + cfg_interrupt_msi_vf_enable = Signal(intbv(0)[8:]) + cfg_interrupt_msi_mmenable = Signal(intbv(0)[12:]) + cfg_interrupt_msi_mask_update = Signal(bool(0)) + cfg_interrupt_msi_data = Signal(intbv(0)[32:]) + cfg_interrupt_msi_sent = Signal(bool(0)) + cfg_interrupt_msi_fail = Signal(bool(0)) + qsfp_tx_clk_1 = Signal(bool(0)) + qsfp_tx_rst_1 = Signal(bool(0)) + qsfp_rx_clk_1 = Signal(bool(0)) + qsfp_rx_rst_1 = Signal(bool(0)) + qsfp_rxd_1 = Signal(intbv(0)[64:]) + qsfp_rxc_1 = Signal(intbv(0)[8:]) + qsfp_tx_clk_2 = Signal(bool(0)) + qsfp_tx_rst_2 = Signal(bool(0)) + qsfp_rx_clk_2 = Signal(bool(0)) + qsfp_rx_rst_2 = Signal(bool(0)) + qsfp_rxd_2 = Signal(intbv(0)[64:]) + qsfp_rxc_2 = Signal(intbv(0)[8:]) + qsfp_tx_clk_3 = Signal(bool(0)) + qsfp_tx_rst_3 = Signal(bool(0)) + qsfp_rx_clk_3 = Signal(bool(0)) + qsfp_rx_rst_3 = Signal(bool(0)) + qsfp_rxd_3 = Signal(intbv(0)[64:]) + qsfp_rxc_3 = Signal(intbv(0)[8:]) + qsfp_tx_clk_4 = Signal(bool(0)) + qsfp_tx_rst_4 = Signal(bool(0)) + qsfp_rx_clk_4 = Signal(bool(0)) + qsfp_rx_rst_4 = Signal(bool(0)) + qsfp_rxd_4 = Signal(intbv(0)[64:]) + qsfp_rxc_4 = Signal(intbv(0)[8:]) + qsfp_modprsl = Signal(bool(1)) + qsfp_intl = Signal(bool(1)) + flash_dq_i = Signal(intbv(0)[16:]) + + # Outputs + led = Signal(intbv(0)[8:]) + i2c_scl_o = Signal(bool(1)) + i2c_scl_t = Signal(bool(1)) + i2c_sda_o = Signal(bool(1)) + i2c_sda_t = Signal(bool(1)) + m_axis_rq_tdata = Signal(intbv(0)[256:]) + m_axis_rq_tkeep = Signal(intbv(0)[8:]) + m_axis_rq_tlast = Signal(bool(0)) + m_axis_rq_tuser = Signal(intbv(0)[60:]) + m_axis_rq_tvalid = Signal(bool(0)) + s_axis_rc_tready = Signal(bool(0)) + s_axis_cq_tready = Signal(bool(0)) + m_axis_cc_tdata = Signal(intbv(0)[256:]) + m_axis_cc_tkeep = Signal(intbv(0)[8:]) + m_axis_cc_tlast = Signal(bool(0)) + m_axis_cc_tuser = Signal(intbv(0)[33:]) + m_axis_cc_tvalid = Signal(bool(0)) + status_error_cor = Signal(bool(0)) + status_error_uncor = Signal(bool(0)) + cfg_mgmt_addr = Signal(intbv(0)[19:]) + cfg_mgmt_write = Signal(bool(0)) + cfg_mgmt_write_data = Signal(intbv(0)[32:]) + cfg_mgmt_byte_enable = Signal(intbv(0)[4:]) + cfg_mgmt_read = Signal(bool(0)) + cfg_interrupt_msi_int = Signal(intbv(0)[32:]) + cfg_interrupt_msi_pending_status = Signal(intbv(0)[32:]) + cfg_interrupt_msi_select = Signal(intbv(0)[4:]) + cfg_interrupt_msi_pending_status_function_num = Signal(intbv(0)[4:]) + cfg_interrupt_msi_pending_status_data_enable = Signal(bool(0)) + cfg_interrupt_msi_attr = Signal(intbv(0)[3:]) + cfg_interrupt_msi_tph_present = Signal(bool(0)) + cfg_interrupt_msi_tph_type = Signal(intbv(0)[2:]) + cfg_interrupt_msi_tph_st_tag = Signal(intbv(0)[9:]) + cfg_interrupt_msi_function_number = Signal(intbv(0)[4:]) + qsfp_txd_1 = Signal(intbv(0)[64:]) + qsfp_txc_1 = Signal(intbv(0)[8:]) + qsfp_txd_2 = Signal(intbv(0)[64:]) + qsfp_txc_2 = Signal(intbv(0)[8:]) + qsfp_txd_3 = Signal(intbv(0)[64:]) + qsfp_txc_3 = Signal(intbv(0)[8:]) + qsfp_txd_4 = Signal(intbv(0)[64:]) + qsfp_txc_4 = Signal(intbv(0)[8:]) + qsfp_modsell = Signal(bool(0)) + qsfp_resetl = Signal(bool(1)) + qsfp_lpmode = Signal(bool(0)) + flash_dq_o = Signal(intbv(0)[16:]) + flash_dq_oe = Signal(bool(0)) + flash_addr = Signal(intbv(0)[23:]) + flash_region = Signal(bool(0)) + flash_region_oe = Signal(bool(0)) + flash_ce_n = Signal(bool(1)) + flash_oe_n = Signal(bool(1)) + flash_we_n = Signal(bool(1)) + flash_adv_n = Signal(bool(1)) + + # sources and sinks + qsfp_1_source = xgmii_ep.XGMIISource() + qsfp_1_source_logic = qsfp_1_source.create_logic(qsfp_rx_clk_1, qsfp_rx_rst_1, txd=qsfp_rxd_1, txc=qsfp_rxc_1, name='qsfp_1_source') + + qsfp_1_sink = xgmii_ep.XGMIISink() + qsfp_1_sink_logic = qsfp_1_sink.create_logic(qsfp_tx_clk_1, qsfp_tx_rst_1, rxd=qsfp_txd_1, rxc=qsfp_txc_1, name='qsfp_1_sink') + + qsfp_2_source = xgmii_ep.XGMIISource() + qsfp_2_source_logic = qsfp_2_source.create_logic(qsfp_rx_clk_2, qsfp_rx_rst_2, txd=qsfp_rxd_2, txc=qsfp_rxc_2, name='qsfp_2_source') + + qsfp_2_sink = xgmii_ep.XGMIISink() + qsfp_2_sink_logic = qsfp_2_sink.create_logic(qsfp_tx_clk_2, qsfp_tx_rst_2, rxd=qsfp_txd_2, rxc=qsfp_txc_2, name='qsfp_2_sink') + + qsfp_3_source = xgmii_ep.XGMIISource() + qsfp_3_source_logic = qsfp_3_source.create_logic(qsfp_rx_clk_3, qsfp_rx_rst_3, txd=qsfp_rxd_3, txc=qsfp_rxc_3, name='qsfp_3_source') + + qsfp_3_sink = xgmii_ep.XGMIISink() + qsfp_3_sink_logic = qsfp_3_sink.create_logic(qsfp_tx_clk_3, qsfp_tx_rst_3, rxd=qsfp_txd_3, rxc=qsfp_txc_3, name='qsfp_3_sink') + + qsfp_4_source = xgmii_ep.XGMIISource() + qsfp_4_source_logic = qsfp_4_source.create_logic(qsfp_rx_clk_4, qsfp_rx_rst_4, txd=qsfp_rxd_4, txc=qsfp_rxc_4, name='qsfp_4_source') + + qsfp_4_sink = xgmii_ep.XGMIISink() + qsfp_4_sink_logic = qsfp_4_sink.create_logic(qsfp_tx_clk_4, qsfp_tx_rst_4, rxd=qsfp_txd_4, rxc=qsfp_txc_4, name='qsfp_4_sink') + + # Clock and Reset Interface + user_clk=Signal(bool(0)) + user_reset=Signal(bool(0)) + sys_clk=Signal(bool(0)) + sys_reset=Signal(bool(0)) + + # PCIe devices + rc = pcie.RootComplex() + + rc.max_payload_size = 0x1 # 256 bytes + rc.max_read_request_size = 0x5 # 4096 bytes + + driver = mqnic.Driver(rc) + + dev = pcie_us.UltrascalePCIe() + + dev.pcie_generation = 3 + dev.pcie_link_width = 8 + dev.user_clock_frequency = 256e6 + + dev.functions[0].msi_multiple_message_capable = 5 + + dev.functions[0].configure_bar(0, 16*1024*1024) + dev.functions[0].configure_bar(1, 16*1024*1024) + + rc.make_port().connect(dev) + + pcie_logic = dev.create_logic( + # Completer reQuest Interface + m_axis_cq_tdata=s_axis_cq_tdata, + m_axis_cq_tuser=s_axis_cq_tuser, + m_axis_cq_tlast=s_axis_cq_tlast, + m_axis_cq_tkeep=s_axis_cq_tkeep, + m_axis_cq_tvalid=s_axis_cq_tvalid, + m_axis_cq_tready=s_axis_cq_tready, + #pcie_cq_np_req=pcie_cq_np_req, + pcie_cq_np_req=Signal(bool(1)), + #pcie_cq_np_req_count=pcie_cq_np_req_count, + + # Completer Completion Interface + s_axis_cc_tdata=m_axis_cc_tdata, + s_axis_cc_tuser=m_axis_cc_tuser, + s_axis_cc_tlast=m_axis_cc_tlast, + s_axis_cc_tkeep=m_axis_cc_tkeep, + s_axis_cc_tvalid=m_axis_cc_tvalid, + s_axis_cc_tready=m_axis_cc_tready, + + # Requester reQuest Interface + s_axis_rq_tdata=m_axis_rq_tdata, + s_axis_rq_tuser=m_axis_rq_tuser, + s_axis_rq_tlast=m_axis_rq_tlast, + s_axis_rq_tkeep=m_axis_rq_tkeep, + s_axis_rq_tvalid=m_axis_rq_tvalid, + s_axis_rq_tready=m_axis_rq_tready, + #pcie_rq_seq_num=pcie_rq_seq_num, + #pcie_rq_seq_num_vld=pcie_rq_seq_num_vld, + #pcie_rq_tag=pcie_rq_tag, + #pcie_rq_tag_vld=pcie_rq_tag_vld, + + # Requester Completion Interface + m_axis_rc_tdata=s_axis_rc_tdata, + m_axis_rc_tuser=s_axis_rc_tuser, + m_axis_rc_tlast=s_axis_rc_tlast, + m_axis_rc_tkeep=s_axis_rc_tkeep, + m_axis_rc_tvalid=s_axis_rc_tvalid, + m_axis_rc_tready=s_axis_rc_tready, + + # Transmit Flow Control Interface + pcie_tfc_nph_av=pcie_tfc_nph_av, + pcie_tfc_npd_av=pcie_tfc_npd_av, + + # Configuration Management Interface + cfg_mgmt_addr=cfg_mgmt_addr, + cfg_mgmt_write=cfg_mgmt_write, + cfg_mgmt_write_data=cfg_mgmt_write_data, + cfg_mgmt_byte_enable=cfg_mgmt_byte_enable, + cfg_mgmt_read=cfg_mgmt_read, + cfg_mgmt_read_data=cfg_mgmt_read_data, + cfg_mgmt_read_write_done=cfg_mgmt_read_write_done, + #cfg_mgmt_type1_cfg_reg_access=cfg_mgmt_type1_cfg_reg_access, + + # Configuration Status Interface + #cfg_phy_link_down=cfg_phy_link_down, + #cfg_phy_link_status=cfg_phy_link_status, + #cfg_negotiated_width=cfg_negotiated_width, + #cfg_current_speed=cfg_current_speed, + cfg_max_payload=cfg_max_payload, + cfg_max_read_req=cfg_max_read_req, + #cfg_function_status=cfg_function_status, + #cfg_vf_status=cfg_vf_status, + #cfg_function_power_state=cfg_function_power_state, + #cfg_vf_power_state=cfg_vf_power_state, + #cfg_link_power_state=cfg_link_power_state, + #cfg_err_cor_out=cfg_err_cor_out, + #cfg_err_nonfatal_out=cfg_err_nonfatal_out, + #cfg_err_fatal_out=cfg_err_fatal_out, + #cfg_ltr_enable=cfg_ltr_enable, + #cfg_ltssm_state=cfg_ltssm_state, + #cfg_rcb_status=cfg_rcb_status, + #cfg_dpa_substate_change=cfg_dpa_substate_change, + #cfg_obff_enable=cfg_obff_enable, + #cfg_pl_status_change=cfg_pl_status_change, + #cfg_tph_requester_enable=cfg_tph_requester_enable, + #cfg_tph_st_mode=cfg_tph_st_mode, + #cfg_vf_tph_requester_enable=cfg_vf_tph_requester_enable, + #cfg_vf_tph_st_mode=cfg_vf_tph_st_mode, + + # Configuration Received Message Interface + #cfg_msg_received=cfg_msg_received, + #cfg_msg_received_data=cfg_msg_received_data, + #cfg_msg_received_type=cfg_msg_received_type, + + # Configuration Transmit Message Interface + #cfg_msg_transmit=cfg_msg_transmit, + #cfg_msg_transmit_type=cfg_msg_transmit_type, + #cfg_msg_transmit_data=cfg_msg_transmit_data, + #cfg_msg_transmit_done=cfg_msg_transmit_done, + + # Configuration Flow Control Interface + #cfg_fc_ph=cfg_fc_ph, + #cfg_fc_pd=cfg_fc_pd, + #cfg_fc_nph=cfg_fc_nph, + #cfg_fc_npd=cfg_fc_npd, + #cfg_fc_cplh=cfg_fc_cplh, + #cfg_fc_cpld=cfg_fc_cpld, + #cfg_fc_sel=cfg_fc_sel, + + # Per-Function Status Interface + #cfg_per_func_status_control=cfg_per_func_status_control, + #cfg_per_func_status_data=cfg_per_func_status_data, + + # Configuration Control Interface + #cfg_hot_reset_in=cfg_hot_reset_in, + #cfg_hot_reset_out=cfg_hot_reset_out, + #cfg_config_space_enable=cfg_config_space_enable, + #cfg_per_function_update_done=cfg_per_function_update_done, + #cfg_per_function_number=cfg_per_function_number, + #cfg_per_function_output_request=cfg_per_function_output_request, + #cfg_dsn=cfg_dsn, + #cfg_ds_bus_number=cfg_ds_bus_number, + #cfg_ds_device_number=cfg_ds_device_number, + #cfg_ds_function_number=cfg_ds_function_number, + #cfg_power_state_change_ack=cfg_power_state_change_ack, + #cfg_power_state_change_interrupt=cfg_power_state_change_interrupt, + cfg_err_cor_in=status_error_cor, + cfg_err_uncor_in=status_error_uncor, + #cfg_flr_done=cfg_flr_done, + #cfg_vf_flr_done=cfg_vf_flr_done, + #cfg_flr_in_process=cfg_flr_in_process, + #cfg_vf_flr_in_process=cfg_vf_flr_in_process, + #cfg_req_pm_transition_l23_ready=cfg_req_pm_transition_l23_ready, + #cfg_link_training_enable=cfg_link_training_enable, + + # Configuration Interrupt Controller Interface + #cfg_interrupt_int=cfg_interrupt_int, + #cfg_interrupt_sent=cfg_interrupt_sent, + #cfg_interrupt_pending=cfg_interrupt_pending, + cfg_interrupt_msi_enable=cfg_interrupt_msi_enable, + cfg_interrupt_msi_vf_enable=cfg_interrupt_msi_vf_enable, + cfg_interrupt_msi_mmenable=cfg_interrupt_msi_mmenable, + cfg_interrupt_msi_mask_update=cfg_interrupt_msi_mask_update, + cfg_interrupt_msi_data=cfg_interrupt_msi_data, + cfg_interrupt_msi_select=cfg_interrupt_msi_select, + cfg_interrupt_msi_int=cfg_interrupt_msi_int, + cfg_interrupt_msi_pending_status=cfg_interrupt_msi_pending_status, + cfg_interrupt_msi_pending_status_data_enable=cfg_interrupt_msi_pending_status_data_enable, + cfg_interrupt_msi_pending_status_function_num=cfg_interrupt_msi_pending_status_function_num, + cfg_interrupt_msi_sent=cfg_interrupt_msi_sent, + cfg_interrupt_msi_fail=cfg_interrupt_msi_fail, + #cfg_interrupt_msix_enable=cfg_interrupt_msix_enable, + #cfg_interrupt_msix_mask=cfg_interrupt_msix_mask, + #cfg_interrupt_msix_vf_enable=cfg_interrupt_msix_vf_enable, + #cfg_interrupt_msix_vf_mask=cfg_interrupt_msix_vf_mask, + #cfg_interrupt_msix_address=cfg_interrupt_msix_address, + #cfg_interrupt_msix_data=cfg_interrupt_msix_data, + #cfg_interrupt_msix_int=cfg_interrupt_msix_int, + #cfg_interrupt_msix_sent=cfg_interrupt_msix_sent, + #cfg_interrupt_msix_fail=cfg_interrupt_msix_fail, + cfg_interrupt_msi_attr=cfg_interrupt_msi_attr, + cfg_interrupt_msi_tph_present=cfg_interrupt_msi_tph_present, + cfg_interrupt_msi_tph_type=cfg_interrupt_msi_tph_type, + cfg_interrupt_msi_tph_st_tag=cfg_interrupt_msi_tph_st_tag, + cfg_interrupt_msi_function_number=cfg_interrupt_msi_function_number, + + # Configuration Extend Interface + #cfg_ext_read_received=cfg_ext_read_received, + #cfg_ext_write_received=cfg_ext_write_received, + #cfg_ext_register_number=cfg_ext_register_number, + #cfg_ext_function_number=cfg_ext_function_number, + #cfg_ext_write_data=cfg_ext_write_data, + #cfg_ext_write_byte_enable=cfg_ext_write_byte_enable, + #cfg_ext_read_data=cfg_ext_read_data, + #cfg_ext_read_data_valid=cfg_ext_read_data_valid, + + # Clock and Reset Interface + user_clk=user_clk, + user_reset=user_reset, + sys_clk=sys_clk, + sys_clk_gt=sys_clk, + sys_reset=sys_reset, + #pcie_perstn0_out=pcie_perstn0_out, + #pcie_perstn1_in=pcie_perstn1_in, + #pcie_perstn1_out=pcie_perstn1_out + ) + + # DUT + if os.system(build_cmd): + raise Exception("Error running build command") + + dut = Cosimulation( + "vvp -m myhdl %s.vvp -lxt2" % testbench, + clk=clk, + rst=rst, + current_test=current_test, + clk_156mhz=clk_156mhz, + rst_156mhz=rst_156mhz, + clk_250mhz=user_clk, + rst_250mhz=user_reset, + btnu=btnu, + btnl=btnl, + btnd=btnd, + btnr=btnr, + btnc=btnc, + sw=sw, + led=led, + i2c_scl_i=i2c_scl_i, + i2c_scl_o=i2c_scl_o, + i2c_scl_t=i2c_scl_t, + i2c_sda_i=i2c_sda_i, + i2c_sda_o=i2c_sda_o, + i2c_sda_t=i2c_sda_t, + m_axis_rq_tdata=m_axis_rq_tdata, + m_axis_rq_tkeep=m_axis_rq_tkeep, + m_axis_rq_tlast=m_axis_rq_tlast, + m_axis_rq_tready=m_axis_rq_tready, + m_axis_rq_tuser=m_axis_rq_tuser, + m_axis_rq_tvalid=m_axis_rq_tvalid, + s_axis_rc_tdata=s_axis_rc_tdata, + s_axis_rc_tkeep=s_axis_rc_tkeep, + s_axis_rc_tlast=s_axis_rc_tlast, + s_axis_rc_tready=s_axis_rc_tready, + s_axis_rc_tuser=s_axis_rc_tuser, + s_axis_rc_tvalid=s_axis_rc_tvalid, + s_axis_cq_tdata=s_axis_cq_tdata, + s_axis_cq_tkeep=s_axis_cq_tkeep, + s_axis_cq_tlast=s_axis_cq_tlast, + s_axis_cq_tready=s_axis_cq_tready, + s_axis_cq_tuser=s_axis_cq_tuser, + s_axis_cq_tvalid=s_axis_cq_tvalid, + m_axis_cc_tdata=m_axis_cc_tdata, + m_axis_cc_tkeep=m_axis_cc_tkeep, + m_axis_cc_tlast=m_axis_cc_tlast, + m_axis_cc_tready=m_axis_cc_tready, + m_axis_cc_tuser=m_axis_cc_tuser, + m_axis_cc_tvalid=m_axis_cc_tvalid, + pcie_tfc_nph_av=pcie_tfc_nph_av, + pcie_tfc_npd_av=pcie_tfc_npd_av, + cfg_max_payload=cfg_max_payload, + cfg_max_read_req=cfg_max_read_req, + cfg_mgmt_addr=cfg_mgmt_addr, + cfg_mgmt_write=cfg_mgmt_write, + cfg_mgmt_write_data=cfg_mgmt_write_data, + cfg_mgmt_byte_enable=cfg_mgmt_byte_enable, + cfg_mgmt_read=cfg_mgmt_read, + cfg_mgmt_read_data=cfg_mgmt_read_data, + cfg_mgmt_read_write_done=cfg_mgmt_read_write_done, + cfg_interrupt_msi_enable=cfg_interrupt_msi_enable, + cfg_interrupt_msi_vf_enable=cfg_interrupt_msi_vf_enable, + cfg_interrupt_msi_int=cfg_interrupt_msi_int, + cfg_interrupt_msi_sent=cfg_interrupt_msi_sent, + cfg_interrupt_msi_fail=cfg_interrupt_msi_fail, + cfg_interrupt_msi_mmenable=cfg_interrupt_msi_mmenable, + cfg_interrupt_msi_pending_status=cfg_interrupt_msi_pending_status, + cfg_interrupt_msi_mask_update=cfg_interrupt_msi_mask_update, + cfg_interrupt_msi_select=cfg_interrupt_msi_select, + cfg_interrupt_msi_data=cfg_interrupt_msi_data, + cfg_interrupt_msi_pending_status_function_num=cfg_interrupt_msi_pending_status_function_num, + cfg_interrupt_msi_pending_status_data_enable=cfg_interrupt_msi_pending_status_data_enable, + cfg_interrupt_msi_attr=cfg_interrupt_msi_attr, + cfg_interrupt_msi_tph_present=cfg_interrupt_msi_tph_present, + cfg_interrupt_msi_tph_type=cfg_interrupt_msi_tph_type, + cfg_interrupt_msi_tph_st_tag=cfg_interrupt_msi_tph_st_tag, + cfg_interrupt_msi_function_number=cfg_interrupt_msi_function_number, + status_error_cor=status_error_cor, + status_error_uncor=status_error_uncor, + qsfp_tx_clk_1=qsfp_tx_clk_1, + qsfp_tx_rst_1=qsfp_tx_rst_1, + qsfp_txd_1=qsfp_txd_1, + qsfp_txc_1=qsfp_txc_1, + qsfp_rx_clk_1=qsfp_rx_clk_1, + qsfp_rx_rst_1=qsfp_rx_rst_1, + qsfp_rxd_1=qsfp_rxd_1, + qsfp_rxc_1=qsfp_rxc_1, + qsfp_tx_clk_2=qsfp_tx_clk_2, + qsfp_tx_rst_2=qsfp_tx_rst_2, + qsfp_txd_2=qsfp_txd_2, + qsfp_txc_2=qsfp_txc_2, + qsfp_rx_clk_2=qsfp_rx_clk_2, + qsfp_rx_rst_2=qsfp_rx_rst_2, + qsfp_rxd_2=qsfp_rxd_2, + qsfp_rxc_2=qsfp_rxc_2, + qsfp_tx_clk_3=qsfp_tx_clk_3, + qsfp_tx_rst_3=qsfp_tx_rst_3, + qsfp_txd_3=qsfp_txd_3, + qsfp_txc_3=qsfp_txc_3, + qsfp_rx_clk_3=qsfp_rx_clk_3, + qsfp_rx_rst_3=qsfp_rx_rst_3, + qsfp_rxd_3=qsfp_rxd_3, + qsfp_rxc_3=qsfp_rxc_3, + qsfp_tx_clk_4=qsfp_tx_clk_4, + qsfp_tx_rst_4=qsfp_tx_rst_4, + qsfp_txd_4=qsfp_txd_4, + qsfp_txc_4=qsfp_txc_4, + qsfp_rx_clk_4=qsfp_rx_clk_4, + qsfp_rx_rst_4=qsfp_rx_rst_4, + qsfp_rxd_4=qsfp_rxd_4, + qsfp_rxc_4=qsfp_rxc_4, + qsfp_modsell=qsfp_modsell, + qsfp_resetl=qsfp_resetl, + qsfp_modprsl=qsfp_modprsl, + qsfp_intl=qsfp_intl, + qsfp_lpmode=qsfp_lpmode, + flash_dq_i=flash_dq_i, + flash_dq_o=flash_dq_o, + flash_dq_oe=flash_dq_oe, + flash_addr=flash_addr, + flash_region=flash_region, + flash_region_oe=flash_region_oe, + flash_ce_n=flash_ce_n, + flash_oe_n=flash_oe_n, + flash_we_n=flash_we_n, + flash_adv_n=flash_adv_n + ) + + @always(delay(5)) + def clkgen(): + clk.next = not clk + + @always(delay(3)) + def clkgen2(): + qsfp_tx_clk_1.next = not qsfp_tx_clk_1 + qsfp_rx_clk_1.next = not qsfp_rx_clk_1 + qsfp_tx_clk_2.next = not qsfp_tx_clk_2 + qsfp_rx_clk_2.next = not qsfp_rx_clk_2 + qsfp_tx_clk_3.next = not qsfp_tx_clk_3 + qsfp_rx_clk_3.next = not qsfp_rx_clk_3 + qsfp_tx_clk_4.next = not qsfp_tx_clk_4 + qsfp_rx_clk_4.next = not qsfp_rx_clk_4 + + @always_comb + def clk_logic(): + sys_clk.next = clk + sys_reset.next = not rst + + loopback_enable = Signal(bool(0)) + + @instance + def loopback(): + while True: + + yield clk.posedge + + if loopback_enable: + if not qsfp_1_sink.empty(): + pkt = qsfp_1_sink.recv() + qsfp_1_source.send(pkt) + if not qsfp_2_sink.empty(): + pkt = qsfp_2_sink.recv() + qsfp_2_source.send(pkt) + if not qsfp_3_sink.empty(): + pkt = qsfp_3_sink.recv() + qsfp_3_source.send(pkt) + if not qsfp_4_sink.empty(): + pkt = qsfp_4_sink.recv() + qsfp_4_source.send(pkt) + + @instance + def check(): + yield delay(100) + yield clk.posedge + rst.next = 1 + qsfp_tx_rst_1.next = 1 + qsfp_rx_rst_1.next = 1 + qsfp_tx_rst_2.next = 1 + qsfp_rx_rst_2.next = 1 + qsfp_tx_rst_3.next = 1 + qsfp_rx_rst_3.next = 1 + qsfp_tx_rst_4.next = 1 + qsfp_rx_rst_4.next = 1 + yield clk.posedge + rst.next = 0 + qsfp_tx_rst_1.next = 0 + qsfp_rx_rst_1.next = 0 + qsfp_tx_rst_2.next = 0 + qsfp_rx_rst_2.next = 0 + qsfp_tx_rst_3.next = 0 + qsfp_rx_rst_3.next = 0 + qsfp_tx_rst_4.next = 0 + qsfp_rx_rst_4.next = 0 + yield clk.posedge + yield delay(100) + yield clk.posedge + + # testbench stimulus + + current_tag = 1 + + yield clk.posedge + print("test 1: enumeration") + current_test.next = 1 + + yield rc.enumerate(enable_bus_mastering=True, configure_msi=True) + + dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc + dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc + + yield from rc.mem_write_dword(dev_pf0_bar0+0x270, 0); + yield from rc.mem_write_dword(dev_pf0_bar0+0x274, 0); + yield from rc.mem_write_dword(dev_pf0_bar0+0x278, 0); + yield from rc.mem_write_dword(dev_pf0_bar0+0x27C, 0); + + yield from rc.mem_write_dword(dev_pf0_bar0+0x290, 0); + yield from rc.mem_write_dword(dev_pf0_bar0+0x294, 1000); + yield from rc.mem_write_dword(dev_pf0_bar0+0x298, 0); + yield from rc.mem_write_dword(dev_pf0_bar0+0x29C, 0); + + yield from rc.mem_write_dword(dev_pf0_bar0+0x280, 0); + yield from rc.mem_write_dword(dev_pf0_bar0+0x284, 2000); + yield from rc.mem_write_dword(dev_pf0_bar0+0x288, 0); + yield from rc.mem_write_dword(dev_pf0_bar0+0x28C, 0); + + yield delay(100) + + yield clk.posedge + print("test 2: init NIC") + current_test.next = 2 + + yield from driver.init_dev(dev.functions[0].get_id()) + yield from driver.interfaces[0].open() + + # enable queues + yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0200, 0xffffffff) + yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0300, 0xffffffff) + + yield from rc.mem_read(driver.hw_addr, 4) # wait for all writes to complete + + yield delay(100) + + yield clk.posedge + print("test 3: send and receive a packet") + current_test.next = 3 + + data = bytearray([x%256 for x in range(1024)]) + + yield from driver.interfaces[0].start_xmit(data, 0) + + yield qsfp_1_sink.wait() + + pkt = qsfp_1_sink.recv() + print(pkt) + + qsfp_1_source.send(pkt) + + yield driver.interfaces[0].wait() + + pkt = driver.interfaces[0].recv() + + print(pkt) + + yield delay(100) + + yield clk.posedge + print("test 4: multiple small packets") + current_test.next = 4 + + count = 64 + + pkts = [bytearray([(x+k)%256 for x in range(64)]) for k in range(count)] + + loopback_enable.next = True + + for p in pkts: + yield from driver.interfaces[0].start_xmit(p, 0) + + for k in range(count): + pkt = driver.interfaces[0].recv() + + if not pkt: + yield driver.interfaces[0].wait() + pkt = driver.interfaces[0].recv() + + print(pkt) + assert pkt.data == pkts[k] + assert frame_checksum(pkt.data) == pkt.rx_checksum + + loopback_enable.next = False + + yield delay(100) + + yield clk.posedge + print("test 5: multiple large packets") + current_test.next = 5 + + count = 64 + + pkts = [bytearray([(x+k)%256 for x in range(1514)]) for k in range(count)] + + loopback_enable.next = True + + for p in pkts: + yield from driver.interfaces[0].start_xmit(p, 0) + + for k in range(count): + pkt = driver.interfaces[0].recv() + + if not pkt: + yield driver.interfaces[0].wait() + pkt = driver.interfaces[0].recv() + + print(pkt) + assert pkt.data == pkts[k] + assert frame_checksum(pkt.data) == pkt.rx_checksum + + loopback_enable.next = False + + yield delay(1000) + + yield clk.posedge + print("test 6: TDMA") + current_test.next = 6 + + count = 16 + + pkts = [bytearray([(x+k)%256 for x in range(1514)]) for k in range(count)] + + loopback_enable.next = True + + # configure TDMA + + # configure TDMA scheduler + yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00120, 0) # schedule period fns + yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00124, 40000) # schedule period ns + yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00128, 0) # schedule period sec (low) + yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0012c, 0) # schedule period sec (high) + yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00130, 0) # timeslot period fns + yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00134, 10000) # timeslot period ns + yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00138, 0) # timeslot period sec (low) + yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0013c, 0) # timeslot period sec (high) + yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00140, 0) # active period fns + yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00144, 5000) # active period ns + yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00148, 0) # active period sec (low) + yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0014c, 0) # active period sec (high) + yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00110, 0) # schedule start fns + yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00114, 200000) # schedule start ns + yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00118, 0) # schedule start sec (low) + yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x0011c, 0) # schedule start sec (high) + yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00100, 0x00000001) + + # enable queues + yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00200, 0xffffffff) + # disable global enable + yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x00300, 0x00000000) + + # configure slots + yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x10000, 0x00000001) + yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x10100, 0x00000002) + yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x10200, 0x00000004) + yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+0x10300, 0x00000008) + + yield from rc.mem_read(driver.hw_addr, 4) # wait for all writes to complete + + # send packets + for k in range(count): + yield from driver.interfaces[0].start_xmit(pkts[k], k%4) + + for k in range(count): + pkt = driver.interfaces[0].recv() + + if not pkt: + yield driver.interfaces[0].wait() + pkt = driver.interfaces[0].recv() + + print(pkt) + #assert pkt.data == pkts[k] + #assert frame_checksum(pkt.data) == pkt.rx_checksum + + loopback_enable.next = False + + yield delay(100) + + raise StopSimulation + + return instances() + +def test_bench(): + sim = Simulation(bench()) + sim.run() + +if __name__ == '__main__': + print("Running test...") + test_bench() diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.v b/fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.v new file mode 100644 index 000000000..243befc13 --- /dev/null +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/tb/test_fpga_core.v @@ -0,0 +1,424 @@ +/* + +Copyright 2019, The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +The views and conclusions contained in the software and documentation are those +of the authors and should not be interpreted as representing official policies, +either expressed or implied, of The Regents of the University of California. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * Testbench for fpga_core + */ +module test_fpga_core; + +// Parameters + +// Inputs +reg clk = 0; +reg rst = 0; +reg [7:0] current_test = 0; + +reg clk_156mhz = 0; +reg rst_156mhz = 0; +reg clk_250mhz = 0; +reg rst_250mhz = 0; +reg btnu = 0; +reg btnl = 0; +reg btnd = 0; +reg btnr = 0; +reg btnc = 0; +reg [3:0] sw = 0; +reg i2c_scl_i = 1; +reg i2c_sda_i = 1; +reg m_axis_rq_tready = 0; +reg [255:0] s_axis_rc_tdata = 0; +reg [7:0] s_axis_rc_tkeep = 0; +reg s_axis_rc_tlast = 0; +reg [74:0] s_axis_rc_tuser = 0; +reg s_axis_rc_tvalid = 0; +reg [255:0] s_axis_cq_tdata = 0; +reg [7:0] s_axis_cq_tkeep = 0; +reg s_axis_cq_tlast = 0; +reg [84:0] s_axis_cq_tuser = 0; +reg s_axis_cq_tvalid = 0; +reg m_axis_cc_tready = 0; +reg [1:0] pcie_tfc_nph_av = 0; +reg [1:0] pcie_tfc_npd_av = 0; +reg [2:0] cfg_max_payload = 0; +reg [2:0] cfg_max_read_req = 0; +reg [31:0] cfg_mgmt_read_data = 0; +reg cfg_mgmt_read_write_done = 0; +reg [3:0] cfg_interrupt_msi_enable = 0; +reg [7:0] cfg_interrupt_msi_vf_enable = 0; +reg [11:0] cfg_interrupt_msi_mmenable = 0; +reg cfg_interrupt_msi_mask_update = 0; +reg [31:0] cfg_interrupt_msi_data = 0; +reg cfg_interrupt_msi_sent = 0; +reg cfg_interrupt_msi_fail = 0; +reg qsfp_tx_clk_1 = 0; +reg qsfp_tx_rst_1 = 0; +reg qsfp_rx_clk_1 = 0; +reg qsfp_rx_rst_1 = 0; +reg [63:0] qsfp_rxd_1 = 0; +reg [7:0] qsfp_rxc_1 = 0; +reg qsfp_tx_clk_2 = 0; +reg qsfp_tx_rst_2 = 0; +reg qsfp_rx_clk_2 = 0; +reg qsfp_rx_rst_2 = 0; +reg [63:0] qsfp_rxd_2 = 0; +reg [7:0] qsfp_rxc_2 = 0; +reg qsfp_tx_clk_3 = 0; +reg qsfp_tx_rst_3 = 0; +reg qsfp_rx_clk_3 = 0; +reg qsfp_rx_rst_3 = 0; +reg [63:0] qsfp_rxd_3 = 0; +reg [7:0] qsfp_rxc_3 = 0; +reg qsfp_tx_clk_4 = 0; +reg qsfp_tx_rst_4 = 0; +reg qsfp_rx_clk_4 = 0; +reg qsfp_rx_rst_4 = 0; +reg [63:0] qsfp_rxd_4 = 0; +reg [7:0] qsfp_rxc_4 = 0; +reg qsfp_modprsl = 1'b1; +reg qsfp_intl = 1'b1; +reg [15:0] flash_dq_i = 0; + +// Outputs +wire [7:0] led; +wire i2c_scl_o; +wire i2c_scl_t; +wire i2c_sda_o; +wire i2c_sda_t; +wire [255:0] m_axis_rq_tdata; +wire [7:0] m_axis_rq_tkeep; +wire m_axis_rq_tlast; +wire [59:0] m_axis_rq_tuser; +wire m_axis_rq_tvalid; +wire s_axis_rc_tready; +wire s_axis_cq_tready; +wire [255:0] m_axis_cc_tdata; +wire [7:0] m_axis_cc_tkeep; +wire m_axis_cc_tlast; +wire [32:0] m_axis_cc_tuser; +wire m_axis_cc_tvalid; +wire [18:0] cfg_mgmt_addr; +wire cfg_mgmt_write; +wire [31:0] cfg_mgmt_write_data; +wire [3:0] cfg_mgmt_byte_enable; +wire cfg_mgmt_read; +wire [3:0] cfg_interrupt_msi_select; +wire [31:0] cfg_interrupt_msi_int; +wire [31:0] cfg_interrupt_msi_pending_status; +wire cfg_interrupt_msi_pending_status_data_enable; +wire [3:0] cfg_interrupt_msi_pending_status_function_num; +wire [2:0] cfg_interrupt_msi_attr; +wire cfg_interrupt_msi_tph_present; +wire [1:0] cfg_interrupt_msi_tph_type; +wire [8:0] cfg_interrupt_msi_tph_st_tag; +wire [3:0] cfg_interrupt_msi_function_number; +wire status_error_cor; +wire status_error_uncor; +wire [63:0] qsfp_txd_1; +wire [7:0] qsfp_txc_1; +wire [63:0] qsfp_txd_2; +wire [7:0] qsfp_txc_2; +wire [63:0] qsfp_txd_3; +wire [7:0] qsfp_txc_3; +wire [63:0] qsfp_txd_4; +wire [7:0] qsfp_txc_4; +wire qsfp_modsell; +wire qsfp_resetl; +wire qsfp_lpmode; +wire [15:0] flash_dq_o; +wire flash_dq_oe; +wire [22:0] flash_addr; +wire flash_region; +wire flash_region_oe; +wire flash_ce_n; +wire flash_oe_n; +wire flash_we_n; +wire flash_adv_n; + +initial begin + // myhdl integration + $from_myhdl( + clk_156mhz, + rst_156mhz, + clk_250mhz, + rst_250mhz, + current_test, + btnu, + btnl, + btnd, + btnr, + btnc, + sw, + i2c_scl_i, + i2c_sda_i, + m_axis_rq_tready, + s_axis_rc_tdata, + s_axis_rc_tkeep, + s_axis_rc_tlast, + s_axis_rc_tuser, + s_axis_rc_tvalid, + s_axis_cq_tdata, + s_axis_cq_tkeep, + s_axis_cq_tlast, + s_axis_cq_tuser, + s_axis_cq_tvalid, + m_axis_cc_tready, + pcie_tfc_nph_av, + pcie_tfc_npd_av, + cfg_max_payload, + cfg_max_read_req, + cfg_mgmt_read_data, + cfg_mgmt_read_write_done, + cfg_interrupt_msi_enable, + cfg_interrupt_msi_vf_enable, + cfg_interrupt_msi_mmenable, + cfg_interrupt_msi_mask_update, + cfg_interrupt_msi_data, + cfg_interrupt_msi_sent, + cfg_interrupt_msi_fail, + qsfp_tx_clk_1, + qsfp_tx_rst_1, + qsfp_rx_clk_1, + qsfp_rx_rst_1, + qsfp_rxd_1, + qsfp_rxc_1, + qsfp_tx_clk_2, + qsfp_tx_rst_2, + qsfp_rx_clk_2, + qsfp_rx_rst_2, + qsfp_rxd_2, + qsfp_rxc_2, + qsfp_tx_clk_3, + qsfp_tx_rst_3, + qsfp_rx_clk_3, + qsfp_rx_rst_3, + qsfp_rxd_3, + qsfp_rxc_3, + qsfp_tx_clk_4, + qsfp_tx_rst_4, + qsfp_rx_clk_4, + qsfp_rx_rst_4, + qsfp_rxd_4, + qsfp_rxc_4, + qsfp_modprsl, + qsfp_intl, + flash_dq_i + ); + $to_myhdl( + led, + i2c_scl_o, + i2c_scl_t, + i2c_sda_o, + i2c_sda_t, + m_axis_rq_tdata, + m_axis_rq_tkeep, + m_axis_rq_tlast, + m_axis_rq_tuser, + m_axis_rq_tvalid, + s_axis_rc_tready, + s_axis_cq_tready, + m_axis_cc_tdata, + m_axis_cc_tkeep, + m_axis_cc_tlast, + m_axis_cc_tuser, + m_axis_cc_tvalid, + cfg_mgmt_addr, + cfg_mgmt_write, + cfg_mgmt_write_data, + cfg_mgmt_byte_enable, + cfg_mgmt_read, + cfg_interrupt_msi_select, + cfg_interrupt_msi_int, + cfg_interrupt_msi_pending_status, + cfg_interrupt_msi_pending_status_data_enable, + cfg_interrupt_msi_pending_status_function_num, + cfg_interrupt_msi_attr, + cfg_interrupt_msi_tph_present, + cfg_interrupt_msi_tph_type, + cfg_interrupt_msi_tph_st_tag, + cfg_interrupt_msi_function_number, + status_error_cor, + status_error_uncor, + qsfp_txd_1, + qsfp_txc_1, + qsfp_txd_2, + qsfp_txc_2, + qsfp_txd_3, + qsfp_txc_3, + qsfp_txd_4, + qsfp_txc_4, + qsfp_modsell, + qsfp_resetl, + qsfp_lpmode, + flash_dq_o, + flash_dq_oe, + flash_addr, + flash_region, + flash_region_oe, + flash_ce_n, + flash_oe_n, + flash_we_n, + flash_adv_n + ); + + // dump file + $dumpfile("test_fpga_core.lxt"); + $dumpvars(0, test_fpga_core); +end + +fpga_core +UUT ( + .clk_156mhz(clk_156mhz), + .rst_156mhz(rst_156mhz), + .clk_250mhz(clk_250mhz), + .rst_250mhz(rst_250mhz), + .btnu(btnu), + .btnl(btnl), + .btnd(btnd), + .btnr(btnr), + .btnc(btnc), + .sw(sw), + .led(led), + .i2c_scl_i(i2c_scl_i), + .i2c_scl_o(i2c_scl_o), + .i2c_scl_t(i2c_scl_t), + .i2c_sda_i(i2c_sda_i), + .i2c_sda_o(i2c_sda_o), + .i2c_sda_t(i2c_sda_t), + .m_axis_rq_tdata(m_axis_rq_tdata), + .m_axis_rq_tkeep(m_axis_rq_tkeep), + .m_axis_rq_tlast(m_axis_rq_tlast), + .m_axis_rq_tready(m_axis_rq_tready), + .m_axis_rq_tuser(m_axis_rq_tuser), + .m_axis_rq_tvalid(m_axis_rq_tvalid), + .s_axis_rc_tdata(s_axis_rc_tdata), + .s_axis_rc_tkeep(s_axis_rc_tkeep), + .s_axis_rc_tlast(s_axis_rc_tlast), + .s_axis_rc_tready(s_axis_rc_tready), + .s_axis_rc_tuser(s_axis_rc_tuser), + .s_axis_rc_tvalid(s_axis_rc_tvalid), + .s_axis_cq_tdata(s_axis_cq_tdata), + .s_axis_cq_tkeep(s_axis_cq_tkeep), + .s_axis_cq_tlast(s_axis_cq_tlast), + .s_axis_cq_tready(s_axis_cq_tready), + .s_axis_cq_tuser(s_axis_cq_tuser), + .s_axis_cq_tvalid(s_axis_cq_tvalid), + .m_axis_cc_tdata(m_axis_cc_tdata), + .m_axis_cc_tkeep(m_axis_cc_tkeep), + .m_axis_cc_tlast(m_axis_cc_tlast), + .m_axis_cc_tready(m_axis_cc_tready), + .m_axis_cc_tuser(m_axis_cc_tuser), + .m_axis_cc_tvalid(m_axis_cc_tvalid), + .pcie_tfc_nph_av(pcie_tfc_nph_av), + .pcie_tfc_npd_av(pcie_tfc_npd_av), + .cfg_max_payload(cfg_max_payload), + .cfg_max_read_req(cfg_max_read_req), + .cfg_mgmt_addr(cfg_mgmt_addr), + .cfg_mgmt_write(cfg_mgmt_write), + .cfg_mgmt_write_data(cfg_mgmt_write_data), + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), + .cfg_mgmt_read(cfg_mgmt_read), + .cfg_mgmt_read_data(cfg_mgmt_read_data), + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), + .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), + .cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable), + .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), + .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), + .cfg_interrupt_msi_data(cfg_interrupt_msi_data), + .cfg_interrupt_msi_select(cfg_interrupt_msi_select), + .cfg_interrupt_msi_int(cfg_interrupt_msi_int), + .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), + .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), + .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), + .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), + .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), + .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr), + .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present), + .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type), + .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag), + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + .status_error_cor(status_error_cor), + .status_error_uncor(status_error_uncor), + .qsfp_tx_clk_1(qsfp_tx_clk_1), + .qsfp_tx_rst_1(qsfp_tx_rst_1), + .qsfp_txd_1(qsfp_txd_1), + .qsfp_txc_1(qsfp_txc_1), + .qsfp_rx_clk_1(qsfp_rx_clk_1), + .qsfp_rx_rst_1(qsfp_rx_rst_1), + .qsfp_rxd_1(qsfp_rxd_1), + .qsfp_rxc_1(qsfp_rxc_1), + .qsfp_tx_clk_2(qsfp_tx_clk_2), + .qsfp_tx_rst_2(qsfp_tx_rst_2), + .qsfp_txd_2(qsfp_txd_2), + .qsfp_txc_2(qsfp_txc_2), + .qsfp_rx_clk_2(qsfp_rx_clk_2), + .qsfp_rx_rst_2(qsfp_rx_rst_2), + .qsfp_rxd_2(qsfp_rxd_2), + .qsfp_rxc_2(qsfp_rxc_2), + .qsfp_tx_clk_3(qsfp_tx_clk_3), + .qsfp_tx_rst_3(qsfp_tx_rst_3), + .qsfp_txd_3(qsfp_txd_3), + .qsfp_txc_3(qsfp_txc_3), + .qsfp_rx_clk_3(qsfp_rx_clk_3), + .qsfp_rx_rst_3(qsfp_rx_rst_3), + .qsfp_rxd_3(qsfp_rxd_3), + .qsfp_rxc_3(qsfp_rxc_3), + .qsfp_tx_clk_4(qsfp_tx_clk_4), + .qsfp_tx_rst_4(qsfp_tx_rst_4), + .qsfp_txd_4(qsfp_txd_4), + .qsfp_txc_4(qsfp_txc_4), + .qsfp_rx_clk_4(qsfp_rx_clk_4), + .qsfp_rx_rst_4(qsfp_rx_rst_4), + .qsfp_rxd_4(qsfp_rxd_4), + .qsfp_rxc_4(qsfp_rxc_4), + .qsfp_modprsl(qsfp_modprsl), + .qsfp_modsell(qsfp_modsell), + .qsfp_resetl(qsfp_resetl), + .qsfp_intl(qsfp_intl), + .qsfp_lpmode(qsfp_lpmode), + .flash_dq_i(flash_dq_i), + .flash_dq_o(flash_dq_o), + .flash_dq_oe(flash_dq_oe), + .flash_addr(flash_addr), + .flash_region(flash_region), + .flash_region_oe(flash_region_oe), + .flash_ce_n(flash_ce_n), + .flash_oe_n(flash_oe_n), + .flash_we_n(flash_we_n), + .flash_adv_n(flash_adv_n) +); + +endmodule diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/tb/xgmii_ep.py b/fpga/mqnic_tdma/VCU108/fpga_10g/tb/xgmii_ep.py new file mode 120000 index 000000000..63b6d3567 --- /dev/null +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/tb/xgmii_ep.py @@ -0,0 +1 @@ +../lib/eth/tb/xgmii_ep.py \ No newline at end of file