FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity

Update device lists

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-04-16 12:34:29 -07:00
parent 1ffbd2d8d3
commit 5bc569c469
3 changed files with 8 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
README.md
View File

@ -28,6 +28,7 @@ Corundum currently supports devices from both Xilinx and Intel, on boards from s
* Exablaze ExaNIC X25/Cisco Nexus K3P-S (Xilinx Kintex UltraScale+ XCKU3P)
* Silicom fb2CG@KU15P (Xilinx Kintex UltraScale+ XCKU15P)
* NetFPGA SUME (Xilinx Virtex 7 XC7V690T)
* BittWare XUP-P3R (Xilinx Virtex UltraScale+ XCVU9P)
* Intel Stratix 10 MX dev kit (Intel Stratix 10 MX 2100)
* Xilinx Alveo U50 (Xilinx Virtex UltraScale+ XCU50)
* Xilinx Alveo U200 (Xilinx Virtex UltraScale+ XCU200)

6
docs/source/devicelist.rst
View File

@ -22,6 +22,7 @@ This section details PCIe form-factor targets, which interface with a separate h
Exablaze ExaNIC X25 XCKU3P-2FFVB676E 0x1ce40009
Silicom fb2CG\@KU15P XCKU15P-2FFVE1760E 0x1c2ca00e
Digilent NetFPGA SUME XC7V690T-3FFG1761 0x10ee7028
BittWare XUP-P3R XCVU9P-2FLGB2104E 0x12ba9823
Intel DK-DEV-1SMX-H-A 1SM21BHU2F53E1VG 0x11720001
Intel DK-DEV-1SMC-H-A 1SM21CHU1F53E1VG 0x11720001
Xilinx Alveo U50 XCU50-2FSVH2104E 0x10ee9032
@ -45,6 +46,7 @@ This section details PCIe form-factor targets, which interface with a separate h
ExaNIC X25 Gen 3 x8 2x SFP28 \- \-
fb2CG\@KU15P Gen 3 x16 2x QSFP28 16 GB DDR4 2400 (4x 512M x72) \-
NetFPGA SUME Gen 3 x8 4x SFP+ 8 GB DDR3 1866 (2x 512M x64) \-
XUP-P3R Gen 3 x16 4x QSFP28 4x DDR4 2400 DIMM (4x x72) \-
DK-DEV-1SMX-H-A Gen 3 x8 2x QSFP28 8 GB DDR4 2666 (2x 512M x72) 8 GB
DK-DEV-1SMC-H-A Gen 3 x8 2x QSFP28 8 GB DDR4 2666 (2x 512M x72) 16 GB
Alveo U50 Gen 3 x16 1x QSFP28 \- 8 GB
@ -68,6 +70,7 @@ This section details PCIe form-factor targets, which interface with a separate h
ExaNIC X25 N :sup:`3` Y Y
fb2CG\@KU15P Y Y Y
NetFPGA SUME Y N :sup:`7` N :sup:`8`
XUP-P3R Y Y Y
DK-DEV-1SMX-H-A N N N
DK-DEV-1SMC-H-A N N N
Alveo U50 N :sup:`4` Y Y
@ -110,6 +113,9 @@ This section details PCIe form-factor targets, which interface with a separate h
fb2CG\@KU15P mqnic/fpga_100g/fpga 2x1 256/8K 100G RR
fb2CG\@KU15P mqnic/fpga_100g/fpga_tdma 2x1 256/256 100G TDMA
NetFPGA SUME mqnic/fpga/fpga 1x1 256/512 10G RR
XUP-P3R mqnic/fpga_25g/fpga 4x1 256/8K 25G RR
XUP-P3R mqnic/fpga_25g/fpga_10g 4x1 256/8K 10G RR
XUP-P3R mqnic/fpga_100g/fpga 4x1 256/8K 100G RR
DK-DEV-1SMX-H-A mqnic/fpga_10g/fpga_1sm21b 2x1 256/1K 10G RR
DK-DEV-1SMC-H-A mqnic/fpga_10g/fpga_1sm21c 2x1 256/1K 10G RR
Alveo U50 mqnic/fpga_25g/fpga 1x1 256/8K 25G RR

1
docs/source/index.rst
View File

@ -20,6 +20,7 @@ Corundum currently supports devices from both Xilinx and Intel, on boards from s
* Exablaze ExaNIC X25/Cisco Nexus K3P-S (Xilinx Kintex UltraScale+ XCKU3P)
* Silicom fb2CG\@KU15P (Xilinx Kintex UltraScale+ XCKU15P)
* NetFPGA SUME (Xilinx Virtex 7 XC7V690T)
* BittWare XUP-P3R (Xilinx Virtex UltraScale+ XCVU9P)
* Intel Stratix 10 MX dev kit (Intel Stratix 10 MX 2100)
* Xilinx Alveo U50 (Xilinx Virtex UltraScale+ XCU50)
* Xilinx Alveo U200 (Xilinx Virtex UltraScale+ XCU200)