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Add AXI stream demux and testbench

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This commit is contained in:
Alex Forencich 2014-11-12 19:21:28 -08:00
parent 73a580df95
commit 5c49ed6191
8 changed files with 2440 additions and 0 deletions
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290
rtl/axis_demux.py Executable file
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#!/usr/bin/env python
"""axis_mux
Generates an AXI Stream demux with the specified number of ports
Usage: axis_crosspoint [OPTION]...
-?, --help display this help and exit
-p, --ports specify number of ports
-n, --name specify module name
-o, --output specify output file name
"""
import io
import sys
import getopt
from math import *
from jinja2 import Template
class Usage(Exception):
def __init__(self, msg):
self.msg = msg
def main(argv=None):
if argv is None:
argv = sys.argv
try:
try:
opts, args = getopt.getopt(argv[1:], "?n:p:o:", ["help", "name=", "ports=", "output="])
except getopt.error as msg:
raise Usage(msg)
# more code, unchanged
except Usage as err:
print(err.msg, file=sys.stderr)
print("for help use --help", file=sys.stderr)
return 2
ports = 4
name = None
out_name = None
# process options
for o, a in opts:
if o in ('-?', '--help'):
print(__doc__)
sys.exit(0)
if o in ('-p', '--ports'):
ports = int(a)
if o in ('-n', '--name'):
name = a
if o in ('-o', '--output'):
out_name = a
if name is None:
name = "axis_demux_{0}".format(ports)
if out_name is None:
out_name = name + ".v"
print("Opening file '%s'..." % out_name)
try:
out_file = open(out_name, 'w')
except Exception as ex:
print("Error opening \"%s\": %s" %(out_name, ex.strerror), file=sys.stderr)
exit(1)
print("Generating {0} port AXI Stream demux {1}...".format(ports, name))
select_width = ceil(log2(ports))
t = Template(u"""/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream {{n}} port demultiplexer
*/
module {{name}} #
(
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI outputs
*/
{%- for p in ports %}
output wire [DATA_WIDTH-1:0] output_{{p}}_axis_tdata,
output wire output_{{p}}_axis_tvalid,
input wire output_{{p}}_axis_tready,
output wire output_{{p}}_axis_tlast,
output wire output_{{p}}_axis_tuser,
{% endfor %}
/*
* Control
*/
input wire [{{w-1}}:0] select
);
// // internal datapath
reg [DATA_WIDTH-1:0] output_axis_tdata_int;
reg output_axis_tvalid_int;
reg output_axis_tready_int = 0;
reg output_axis_tlast_int;
reg output_axis_tuser_int;
wire output_axis_tready_int_early;
reg [{{w-1}}:0] select_reg = 0, select_next;
reg frame_reg = 0, frame_next;
reg input_axis_tready_reg = 0, input_axis_tready_next;
assign input_axis_tready = input_axis_tready_reg;
// mux for output control signals
reg current_output_tready;
reg current_output_tvalid;
always @* begin
case (select_reg)
{%- for p in ports %}
{{w}}'d{{p}}: begin
current_output_tvalid = output_{{p}}_axis_tvalid;
current_output_tready = output_{{p}}_axis_tready;
end
{%- endfor %}
endcase
end
always @* begin
select_next = select_reg;
frame_next = frame_reg;
input_axis_tready_next = 0;
if (frame_reg) begin
if (input_axis_tvalid & input_axis_tready) begin
// end of frame detection
frame_next = ~input_axis_tlast;
end
end else if (input_axis_tvalid & ~current_output_tvalid) begin
// start of frame, grab select value
frame_next = 1;
select_next = select;
end
input_axis_tready_next = output_axis_tready_int_early & frame_next;
output_axis_tdata_int = input_axis_tdata;
output_axis_tvalid_int = input_axis_tvalid & input_axis_tready;
output_axis_tlast_int = input_axis_tlast;
output_axis_tuser_int = input_axis_tuser;
end
always @(posedge clk or posedge rst) begin
if (rst) begin
select_reg <= 0;
frame_reg <= 0;
input_axis_tready_reg <= 0;
end else begin
select_reg <= select_next;
frame_reg <= frame_next;
input_axis_tready_reg <= input_axis_tready_next;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = 0;
{%- for p in ports %}
reg output_{{p}}_axis_tvalid_reg = 0;
{%- endfor %}
reg output_axis_tlast_reg = 0;
reg output_axis_tuser_reg = 0;
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = 0;
reg temp_axis_tvalid_reg = 0;
reg temp_axis_tlast_reg = 0;
reg temp_axis_tuser_reg = 0;
{% for p in ports %}
assign output_{{p}}_axis_tdata = output_axis_tdata_reg;
assign output_{{p}}_axis_tvalid = output_{{p}}_axis_tvalid_reg;
assign output_{{p}}_axis_tlast = output_axis_tlast_reg;
assign output_{{p}}_axis_tuser = output_axis_tuser_reg;
{% endfor %}
// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
assign output_axis_tready_int_early = current_output_tready | (~temp_axis_tvalid_reg & ~current_output_tvalid) | (~temp_axis_tvalid_reg & ~output_axis_tvalid_int);
always @(posedge clk or posedge rst) begin
if (rst) begin
output_axis_tdata_reg <= 0;
{%- for p in ports %}
output_{{p}}_axis_tvalid_reg <= 0;
{%- endfor %}
output_axis_tlast_reg <= 0;
output_axis_tuser_reg <= 0;
output_axis_tready_int <= 0;
temp_axis_tdata_reg <= 0;
temp_axis_tvalid_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
end else begin
// transfer sink ready state to source
output_axis_tready_int <= output_axis_tready_int_early;
if (output_axis_tready_int) begin
// input is ready
if (current_output_tready | ~current_output_tvalid) begin
// output is ready or currently not valid, transfer data to output
output_axis_tdata_reg <= output_axis_tdata_int;
case (select_reg)
{%- for p in ports %}
{{w}}'d{{p}}: output_{{p}}_axis_tvalid_reg <= output_axis_tvalid_int;
{%- endfor %}
endcase
output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tuser_reg <= output_axis_tuser_int;
end else begin
// output is not ready, store input in temp
temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tvalid_reg <= output_axis_tvalid_int;
temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tuser_reg <= output_axis_tuser_int;
end
end else if (current_output_tready) begin
// input is not ready, but output is ready
output_axis_tdata_reg <= temp_axis_tdata_reg;
case (select_reg)
{%- for p in ports %}
{{w}}'d{{p}}: output_{{p}}_axis_tvalid_reg <= temp_axis_tvalid_reg;
{%- endfor %}
endcase
output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg;
temp_axis_tdata_reg <= 0;
temp_axis_tvalid_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
end
end
end
endmodule
""")
out_file.write(t.render(
n=ports,
w=select_width,
name=name,
ports=range(ports)
))
print("Done")
if __name__ == "__main__":
sys.exit(main())

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/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream 4 port demultiplexer
*/
module axis_demux_4 #
(
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI outputs
*/
output wire [DATA_WIDTH-1:0] output_0_axis_tdata,
output wire output_0_axis_tvalid,
input wire output_0_axis_tready,
output wire output_0_axis_tlast,
output wire output_0_axis_tuser,
output wire [DATA_WIDTH-1:0] output_1_axis_tdata,
output wire output_1_axis_tvalid,
input wire output_1_axis_tready,
output wire output_1_axis_tlast,
output wire output_1_axis_tuser,
output wire [DATA_WIDTH-1:0] output_2_axis_tdata,
output wire output_2_axis_tvalid,
input wire output_2_axis_tready,
output wire output_2_axis_tlast,
output wire output_2_axis_tuser,
output wire [DATA_WIDTH-1:0] output_3_axis_tdata,
output wire output_3_axis_tvalid,
input wire output_3_axis_tready,
output wire output_3_axis_tlast,
output wire output_3_axis_tuser,
/*
* Control
*/
input wire [1:0] select
);
// // internal datapath
reg [DATA_WIDTH-1:0] output_axis_tdata_int;
reg output_axis_tvalid_int;
reg output_axis_tready_int = 0;
reg output_axis_tlast_int;
reg output_axis_tuser_int;
wire output_axis_tready_int_early;
reg [1:0] select_reg = 0, select_next;
reg frame_reg = 0, frame_next;
reg input_axis_tready_reg = 0, input_axis_tready_next;
assign input_axis_tready = input_axis_tready_reg;
// mux for output control signals
reg current_output_tready;
reg current_output_tvalid;
always @* begin
case (select_reg)
2'd0: begin
current_output_tvalid = output_0_axis_tvalid;
current_output_tready = output_0_axis_tready;
end
2'd1: begin
current_output_tvalid = output_1_axis_tvalid;
current_output_tready = output_1_axis_tready;
end
2'd2: begin
current_output_tvalid = output_2_axis_tvalid;
current_output_tready = output_2_axis_tready;
end
2'd3: begin
current_output_tvalid = output_3_axis_tvalid;
current_output_tready = output_3_axis_tready;
end
endcase
end
always @* begin
select_next = select_reg;
frame_next = frame_reg;
input_axis_tready_next = 0;
if (frame_reg) begin
if (input_axis_tvalid & input_axis_tready) begin
// end of frame detection
frame_next = ~input_axis_tlast;
end
end else if (input_axis_tvalid & ~current_output_tvalid) begin
// start of frame, grab select value
frame_next = 1;
select_next = select;
end
input_axis_tready_next = output_axis_tready_int_early & frame_next;
output_axis_tdata_int = input_axis_tdata;
output_axis_tvalid_int = input_axis_tvalid & input_axis_tready;
output_axis_tlast_int = input_axis_tlast;
output_axis_tuser_int = input_axis_tuser;
end
always @(posedge clk or posedge rst) begin
if (rst) begin
select_reg <= 0;
frame_reg <= 0;
input_axis_tready_reg <= 0;
end else begin
select_reg <= select_next;
frame_reg <= frame_next;
input_axis_tready_reg <= input_axis_tready_next;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = 0;
reg output_0_axis_tvalid_reg = 0;
reg output_1_axis_tvalid_reg = 0;
reg output_2_axis_tvalid_reg = 0;
reg output_3_axis_tvalid_reg = 0;
reg output_axis_tlast_reg = 0;
reg output_axis_tuser_reg = 0;
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = 0;
reg temp_axis_tvalid_reg = 0;
reg temp_axis_tlast_reg = 0;
reg temp_axis_tuser_reg = 0;
assign output_0_axis_tdata = output_axis_tdata_reg;
assign output_0_axis_tvalid = output_0_axis_tvalid_reg;
assign output_0_axis_tlast = output_axis_tlast_reg;
assign output_0_axis_tuser = output_axis_tuser_reg;
assign output_1_axis_tdata = output_axis_tdata_reg;
assign output_1_axis_tvalid = output_1_axis_tvalid_reg;
assign output_1_axis_tlast = output_axis_tlast_reg;
assign output_1_axis_tuser = output_axis_tuser_reg;
assign output_2_axis_tdata = output_axis_tdata_reg;
assign output_2_axis_tvalid = output_2_axis_tvalid_reg;
assign output_2_axis_tlast = output_axis_tlast_reg;
assign output_2_axis_tuser = output_axis_tuser_reg;
assign output_3_axis_tdata = output_axis_tdata_reg;
assign output_3_axis_tvalid = output_3_axis_tvalid_reg;
assign output_3_axis_tlast = output_axis_tlast_reg;
assign output_3_axis_tuser = output_axis_tuser_reg;
// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
assign output_axis_tready_int_early = current_output_tready | (~temp_axis_tvalid_reg & ~current_output_tvalid) | (~temp_axis_tvalid_reg & ~output_axis_tvalid_int);
always @(posedge clk or posedge rst) begin
if (rst) begin
output_axis_tdata_reg <= 0;
output_0_axis_tvalid_reg <= 0;
output_1_axis_tvalid_reg <= 0;
output_2_axis_tvalid_reg <= 0;
output_3_axis_tvalid_reg <= 0;
output_axis_tlast_reg <= 0;
output_axis_tuser_reg <= 0;
output_axis_tready_int <= 0;
temp_axis_tdata_reg <= 0;
temp_axis_tvalid_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
end else begin
// transfer sink ready state to source
output_axis_tready_int <= output_axis_tready_int_early;
if (output_axis_tready_int) begin
// input is ready
if (current_output_tready | ~current_output_tvalid) begin
// output is ready or currently not valid, transfer data to output
output_axis_tdata_reg <= output_axis_tdata_int;
case (select_reg)
2'd0: output_0_axis_tvalid_reg <= output_axis_tvalid_int;
2'd1: output_1_axis_tvalid_reg <= output_axis_tvalid_int;
2'd2: output_2_axis_tvalid_reg <= output_axis_tvalid_int;
2'd3: output_3_axis_tvalid_reg <= output_axis_tvalid_int;
endcase
output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tuser_reg <= output_axis_tuser_int;
end else begin
// output is not ready, store input in temp
temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tvalid_reg <= output_axis_tvalid_int;
temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tuser_reg <= output_axis_tuser_int;
end
end else if (current_output_tready) begin
// input is not ready, but output is ready
output_axis_tdata_reg <= temp_axis_tdata_reg;
case (select_reg)
2'd0: output_0_axis_tvalid_reg <= temp_axis_tvalid_reg;
2'd1: output_1_axis_tvalid_reg <= temp_axis_tvalid_reg;
2'd2: output_2_axis_tvalid_reg <= temp_axis_tvalid_reg;
2'd3: output_3_axis_tvalid_reg <= temp_axis_tvalid_reg;
endcase
output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg;
temp_axis_tdata_reg <= 0;
temp_axis_tvalid_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
end
end
end
endmodule

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#!/usr/bin/env python
"""axis_mux
Generates an AXI Stream demux with the specified number of ports
Usage: axis_crosspoint [OPTION]...
-?, --help display this help and exit
-p, --ports specify number of ports
-n, --name specify module name
-o, --output specify output file name
"""
import io
import sys
import getopt
from math import *
from jinja2 import Template
class Usage(Exception):
def __init__(self, msg):
self.msg = msg
def main(argv=None):
if argv is None:
argv = sys.argv
try:
try:
opts, args = getopt.getopt(argv[1:], "?n:p:o:", ["help", "name=", "ports=", "output="])
except getopt.error as msg:
raise Usage(msg)
# more code, unchanged
except Usage as err:
print(err.msg, file=sys.stderr)
print("for help use --help", file=sys.stderr)
return 2
ports = 4
name = None
out_name = None
# process options
for o, a in opts:
if o in ('-?', '--help'):
print(__doc__)
sys.exit(0)
if o in ('-p', '--ports'):
ports = int(a)
if o in ('-n', '--name'):
name = a
if o in ('-o', '--output'):
out_name = a
if name is None:
name = "axis_demux_64_{0}".format(ports)
if out_name is None:
out_name = name + ".v"
print("Opening file '%s'..." % out_name)
try:
out_file = open(out_name, 'w')
except Exception as ex:
print("Error opening \"%s\": %s" %(out_name, ex.strerror), file=sys.stderr)
exit(1)
print("Generating {0} port AXI Stream demux {1}...".format(ports, name))
select_width = ceil(log2(ports))
t = Template(u"""/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream {{n}} port demultiplexer (64 bit datapath)
*/
module {{name}} #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI outputs
*/
{%- for p in ports %}
output wire [DATA_WIDTH-1:0] output_{{p}}_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_{{p}}_axis_tkeep,
output wire output_{{p}}_axis_tvalid,
input wire output_{{p}}_axis_tready,
output wire output_{{p}}_axis_tlast,
output wire output_{{p}}_axis_tuser,
{% endfor %}
/*
* Control
*/
input wire [{{w-1}}:0] select
);
// // internal datapath
reg [DATA_WIDTH-1:0] output_axis_tdata_int;
reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
reg output_axis_tvalid_int;
reg output_axis_tready_int = 0;
reg output_axis_tlast_int;
reg output_axis_tuser_int;
wire output_axis_tready_int_early;
reg [{{w-1}}:0] select_reg = 0, select_next;
reg frame_reg = 0, frame_next;
reg input_axis_tready_reg = 0, input_axis_tready_next;
assign input_axis_tready = input_axis_tready_reg;
// mux for output control signals
reg current_output_tready;
reg current_output_tvalid;
always @* begin
case (select_reg)
{%- for p in ports %}
{{w}}'d{{p}}: begin
current_output_tvalid = output_{{p}}_axis_tvalid;
current_output_tready = output_{{p}}_axis_tready;
end
{%- endfor %}
endcase
end
always @* begin
select_next = select_reg;
frame_next = frame_reg;
input_axis_tready_next = 0;
if (frame_reg) begin
if (input_axis_tvalid & input_axis_tready) begin
// end of frame detection
frame_next = ~input_axis_tlast;
end
end else if (input_axis_tvalid & ~current_output_tvalid) begin
// start of frame, grab select value
frame_next = 1;
select_next = select;
end
input_axis_tready_next = output_axis_tready_int_early & frame_next;
output_axis_tdata_int = input_axis_tdata;
output_axis_tkeep_int = input_axis_tkeep;
output_axis_tvalid_int = input_axis_tvalid & input_axis_tready;
output_axis_tlast_int = input_axis_tlast;
output_axis_tuser_int = input_axis_tuser;
end
always @(posedge clk or posedge rst) begin
if (rst) begin
select_reg <= 0;
frame_reg <= 0;
input_axis_tready_reg <= 0;
end else begin
select_reg <= select_next;
frame_reg <= frame_next;
input_axis_tready_reg <= input_axis_tready_next;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = 0;
reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = 0;
{%- for p in ports %}
reg output_{{p}}_axis_tvalid_reg = 0;
{%- endfor %}
reg output_axis_tlast_reg = 0;
reg output_axis_tuser_reg = 0;
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = 0;
reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = 0;
reg temp_axis_tvalid_reg = 0;
reg temp_axis_tlast_reg = 0;
reg temp_axis_tuser_reg = 0;
{% for p in ports %}
assign output_{{p}}_axis_tdata = output_axis_tdata_reg;
assign output_{{p}}_axis_tkeep = output_axis_tkeep_reg;
assign output_{{p}}_axis_tvalid = output_{{p}}_axis_tvalid_reg;
assign output_{{p}}_axis_tlast = output_axis_tlast_reg;
assign output_{{p}}_axis_tuser = output_axis_tuser_reg;
{% endfor %}
// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
assign output_axis_tready_int_early = current_output_tready | (~temp_axis_tvalid_reg & ~current_output_tvalid) | (~temp_axis_tvalid_reg & ~output_axis_tvalid_int);
always @(posedge clk or posedge rst) begin
if (rst) begin
output_axis_tdata_reg <= 0;
output_axis_tkeep_reg <= 0;
{%- for p in ports %}
output_{{p}}_axis_tvalid_reg <= 0;
{%- endfor %}
output_axis_tlast_reg <= 0;
output_axis_tuser_reg <= 0;
output_axis_tready_int <= 0;
temp_axis_tdata_reg <= 0;
temp_axis_tkeep_reg <= 0;
temp_axis_tvalid_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
end else begin
// transfer sink ready state to source
output_axis_tready_int <= output_axis_tready_int_early;
if (output_axis_tready_int) begin
// input is ready
if (current_output_tready | ~current_output_tvalid) begin
// output is ready or currently not valid, transfer data to output
output_axis_tdata_reg <= output_axis_tdata_int;
output_axis_tkeep_reg <= output_axis_tkeep_int;
case (select_reg)
{%- for p in ports %}
{{w}}'d{{p}}: output_{{p}}_axis_tvalid_reg <= output_axis_tvalid_int;
{%- endfor %}
endcase
output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tuser_reg <= output_axis_tuser_int;
end else begin
// output is not ready, store input in temp
temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tkeep_reg <= output_axis_tkeep_int;
temp_axis_tvalid_reg <= output_axis_tvalid_int;
temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tuser_reg <= output_axis_tuser_int;
end
end else if (current_output_tready) begin
// input is not ready, but output is ready
output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tkeep_reg <= temp_axis_tkeep_reg;
case (select_reg)
{%- for p in ports %}
{{w}}'d{{p}}: output_{{p}}_axis_tvalid_reg <= temp_axis_tvalid_reg;
{%- endfor %}
endcase
output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg;
temp_axis_tdata_reg <= 0;
temp_axis_tkeep_reg <= 0;
temp_axis_tvalid_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
end
end
end
endmodule
""")
out_file.write(t.render(
n=ports,
w=select_width,
name=name,
ports=range(ports)
))
print("Done")
if __name__ == "__main__":
sys.exit(main())

271
rtl/axis_demux_64_4.v Normal file
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/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream 4 port demultiplexer (64 bit datapath)
*/
module axis_demux_64_4 #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI outputs
*/
output wire [DATA_WIDTH-1:0] output_0_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_0_axis_tkeep,
output wire output_0_axis_tvalid,
input wire output_0_axis_tready,
output wire output_0_axis_tlast,
output wire output_0_axis_tuser,
output wire [DATA_WIDTH-1:0] output_1_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_1_axis_tkeep,
output wire output_1_axis_tvalid,
input wire output_1_axis_tready,
output wire output_1_axis_tlast,
output wire output_1_axis_tuser,
output wire [DATA_WIDTH-1:0] output_2_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_2_axis_tkeep,
output wire output_2_axis_tvalid,
input wire output_2_axis_tready,
output wire output_2_axis_tlast,
output wire output_2_axis_tuser,
output wire [DATA_WIDTH-1:0] output_3_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_3_axis_tkeep,
output wire output_3_axis_tvalid,
input wire output_3_axis_tready,
output wire output_3_axis_tlast,
output wire output_3_axis_tuser,
/*
* Control
*/
input wire [1:0] select
);
// // internal datapath
reg [DATA_WIDTH-1:0] output_axis_tdata_int;
reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
reg output_axis_tvalid_int;
reg output_axis_tready_int = 0;
reg output_axis_tlast_int;
reg output_axis_tuser_int;
wire output_axis_tready_int_early;
reg [1:0] select_reg = 0, select_next;
reg frame_reg = 0, frame_next;
reg input_axis_tready_reg = 0, input_axis_tready_next;
assign input_axis_tready = input_axis_tready_reg;
// mux for output control signals
reg current_output_tready;
reg current_output_tvalid;
always @* begin
case (select_reg)
2'd0: begin
current_output_tvalid = output_0_axis_tvalid;
current_output_tready = output_0_axis_tready;
end
2'd1: begin
current_output_tvalid = output_1_axis_tvalid;
current_output_tready = output_1_axis_tready;
end
2'd2: begin
current_output_tvalid = output_2_axis_tvalid;
current_output_tready = output_2_axis_tready;
end
2'd3: begin
current_output_tvalid = output_3_axis_tvalid;
current_output_tready = output_3_axis_tready;
end
endcase
end
always @* begin
select_next = select_reg;
frame_next = frame_reg;
input_axis_tready_next = 0;
if (frame_reg) begin
if (input_axis_tvalid & input_axis_tready) begin
// end of frame detection
frame_next = ~input_axis_tlast;
end
end else if (input_axis_tvalid & ~current_output_tvalid) begin
// start of frame, grab select value
frame_next = 1;
select_next = select;
end
input_axis_tready_next = output_axis_tready_int_early & frame_next;
output_axis_tdata_int = input_axis_tdata;
output_axis_tkeep_int = input_axis_tkeep;
output_axis_tvalid_int = input_axis_tvalid & input_axis_tready;
output_axis_tlast_int = input_axis_tlast;
output_axis_tuser_int = input_axis_tuser;
end
always @(posedge clk or posedge rst) begin
if (rst) begin
select_reg <= 0;
frame_reg <= 0;
input_axis_tready_reg <= 0;
end else begin
select_reg <= select_next;
frame_reg <= frame_next;
input_axis_tready_reg <= input_axis_tready_next;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = 0;
reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = 0;
reg output_0_axis_tvalid_reg = 0;
reg output_1_axis_tvalid_reg = 0;
reg output_2_axis_tvalid_reg = 0;
reg output_3_axis_tvalid_reg = 0;
reg output_axis_tlast_reg = 0;
reg output_axis_tuser_reg = 0;
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = 0;
reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = 0;
reg temp_axis_tvalid_reg = 0;
reg temp_axis_tlast_reg = 0;
reg temp_axis_tuser_reg = 0;
assign output_0_axis_tdata = output_axis_tdata_reg;
assign output_0_axis_tkeep = output_axis_tkeep_reg;
assign output_0_axis_tvalid = output_0_axis_tvalid_reg;
assign output_0_axis_tlast = output_axis_tlast_reg;
assign output_0_axis_tuser = output_axis_tuser_reg;
assign output_1_axis_tdata = output_axis_tdata_reg;
assign output_1_axis_tkeep = output_axis_tkeep_reg;
assign output_1_axis_tvalid = output_1_axis_tvalid_reg;
assign output_1_axis_tlast = output_axis_tlast_reg;
assign output_1_axis_tuser = output_axis_tuser_reg;
assign output_2_axis_tdata = output_axis_tdata_reg;
assign output_2_axis_tkeep = output_axis_tkeep_reg;
assign output_2_axis_tvalid = output_2_axis_tvalid_reg;
assign output_2_axis_tlast = output_axis_tlast_reg;
assign output_2_axis_tuser = output_axis_tuser_reg;
assign output_3_axis_tdata = output_axis_tdata_reg;
assign output_3_axis_tkeep = output_axis_tkeep_reg;
assign output_3_axis_tvalid = output_3_axis_tvalid_reg;
assign output_3_axis_tlast = output_axis_tlast_reg;
assign output_3_axis_tuser = output_axis_tuser_reg;
// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
assign output_axis_tready_int_early = current_output_tready | (~temp_axis_tvalid_reg & ~current_output_tvalid) | (~temp_axis_tvalid_reg & ~output_axis_tvalid_int);
always @(posedge clk or posedge rst) begin
if (rst) begin
output_axis_tdata_reg <= 0;
output_axis_tkeep_reg <= 0;
output_0_axis_tvalid_reg <= 0;
output_1_axis_tvalid_reg <= 0;
output_2_axis_tvalid_reg <= 0;
output_3_axis_tvalid_reg <= 0;
output_axis_tlast_reg <= 0;
output_axis_tuser_reg <= 0;
output_axis_tready_int <= 0;
temp_axis_tdata_reg <= 0;
temp_axis_tkeep_reg <= 0;
temp_axis_tvalid_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
end else begin
// transfer sink ready state to source
output_axis_tready_int <= output_axis_tready_int_early;
if (output_axis_tready_int) begin
// input is ready
if (current_output_tready | ~current_output_tvalid) begin
// output is ready or currently not valid, transfer data to output
output_axis_tdata_reg <= output_axis_tdata_int;
output_axis_tkeep_reg <= output_axis_tkeep_int;
case (select_reg)
2'd0: output_0_axis_tvalid_reg <= output_axis_tvalid_int;
2'd1: output_1_axis_tvalid_reg <= output_axis_tvalid_int;
2'd2: output_2_axis_tvalid_reg <= output_axis_tvalid_int;
2'd3: output_3_axis_tvalid_reg <= output_axis_tvalid_int;
endcase
output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tuser_reg <= output_axis_tuser_int;
end else begin
// output is not ready, store input in temp
temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tkeep_reg <= output_axis_tkeep_int;
temp_axis_tvalid_reg <= output_axis_tvalid_int;
temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tuser_reg <= output_axis_tuser_int;
end
end else if (current_output_tready) begin
// input is not ready, but output is ready
output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tkeep_reg <= temp_axis_tkeep_reg;
case (select_reg)
2'd0: output_0_axis_tvalid_reg <= temp_axis_tvalid_reg;
2'd1: output_1_axis_tvalid_reg <= temp_axis_tvalid_reg;
2'd2: output_2_axis_tvalid_reg <= temp_axis_tvalid_reg;
2'd3: output_3_axis_tvalid_reg <= temp_axis_tvalid_reg;
endcase
output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg;
temp_axis_tdata_reg <= 0;
temp_axis_tkeep_reg <= 0;
temp_axis_tvalid_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
end
end
end
endmodule

500
tb/test_axis_demux_4.py Executable file
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@ -0,0 +1,500 @@
#!/usr/bin/env python2
"""
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
"""
from myhdl import *
import os
from Queue import Queue
import axis_ep
module = 'axis_demux_4'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_demux_4(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_0_axis_tdata,
output_0_axis_tvalid,
output_0_axis_tready,
output_0_axis_tlast,
output_0_axis_tuser,
output_1_axis_tdata,
output_1_axis_tvalid,
output_1_axis_tready,
output_1_axis_tlast,
output_1_axis_tuser,
output_2_axis_tdata,
output_2_axis_tvalid,
output_2_axis_tready,
output_2_axis_tlast,
output_2_axis_tuser,
output_3_axis_tdata,
output_3_axis_tvalid,
output_3_axis_tready,
output_3_axis_tlast,
output_3_axis_tuser,
select):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_0_axis_tdata=output_0_axis_tdata,
output_0_axis_tvalid=output_0_axis_tvalid,
output_0_axis_tready=output_0_axis_tready,
output_0_axis_tlast=output_0_axis_tlast,
output_0_axis_tuser=output_0_axis_tuser,
output_1_axis_tdata=output_1_axis_tdata,
output_1_axis_tvalid=output_1_axis_tvalid,
output_1_axis_tready=output_1_axis_tready,
output_1_axis_tlast=output_1_axis_tlast,
output_1_axis_tuser=output_1_axis_tuser,
output_2_axis_tdata=output_2_axis_tdata,
output_2_axis_tvalid=output_2_axis_tvalid,
output_2_axis_tready=output_2_axis_tready,
output_2_axis_tlast=output_2_axis_tlast,
output_2_axis_tuser=output_2_axis_tuser,
output_3_axis_tdata=output_3_axis_tdata,
output_3_axis_tvalid=output_3_axis_tvalid,
output_3_axis_tready=output_3_axis_tready,
output_3_axis_tlast=output_3_axis_tlast,
output_3_axis_tuser=output_3_axis_tuser,
select=select)
def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[8:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
output_0_axis_tready = Signal(bool(0))
output_1_axis_tready = Signal(bool(0))
output_2_axis_tready = Signal(bool(0))
output_3_axis_tready = Signal(bool(0))
select = Signal(intbv(0)[2:])
# Outputs
input_axis_tready = Signal(bool(0))
output_0_axis_tdata = Signal(intbv(0)[8:])
output_0_axis_tvalid = Signal(bool(0))
output_0_axis_tlast = Signal(bool(0))
output_0_axis_tuser = Signal(bool(0))
output_1_axis_tdata = Signal(intbv(0)[8:])
output_1_axis_tvalid = Signal(bool(0))
output_1_axis_tlast = Signal(bool(0))
output_1_axis_tuser = Signal(bool(0))
output_2_axis_tdata = Signal(intbv(0)[8:])
output_2_axis_tvalid = Signal(bool(0))
output_2_axis_tlast = Signal(bool(0))
output_2_axis_tuser = Signal(bool(0))
output_3_axis_tdata = Signal(intbv(0)[8:])
output_3_axis_tvalid = Signal(bool(0))
output_3_axis_tlast = Signal(bool(0))
output_3_axis_tuser = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_0_queue = Queue()
sink_0_pause = Signal(bool(0))
sink_1_queue = Queue()
sink_1_pause = Signal(bool(0))
sink_2_queue = Queue()
sink_2_pause = Signal(bool(0))
sink_3_queue = Queue()
sink_3_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
sink_0 = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_0_axis_tdata,
tvalid=output_0_axis_tvalid,
tready=output_0_axis_tready,
tlast=output_0_axis_tlast,
tuser=output_0_axis_tuser,
fifo=sink_0_queue,
pause=sink_0_pause,
name='sink0')
sink_1 = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_1_axis_tdata,
tvalid=output_1_axis_tvalid,
tready=output_1_axis_tready,
tlast=output_1_axis_tlast,
tuser=output_1_axis_tuser,
fifo=sink_1_queue,
pause=sink_1_pause,
name='sink1')
sink_2 = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_2_axis_tdata,
tvalid=output_2_axis_tvalid,
tready=output_2_axis_tready,
tlast=output_2_axis_tlast,
tuser=output_2_axis_tuser,
fifo=sink_2_queue,
pause=sink_2_pause,
name='sink2')
sink_3 = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_3_axis_tdata,
tvalid=output_3_axis_tvalid,
tready=output_3_axis_tready,
tlast=output_3_axis_tlast,
tuser=output_3_axis_tuser,
fifo=sink_3_queue,
pause=sink_3_pause,
name='sink3')
# DUT
dut = dut_axis_demux_4(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_0_axis_tdata,
output_0_axis_tvalid,
output_0_axis_tready,
output_0_axis_tlast,
output_0_axis_tuser,
output_1_axis_tdata,
output_1_axis_tvalid,
output_1_axis_tready,
output_1_axis_tlast,
output_1_axis_tuser,
output_2_axis_tdata,
output_2_axis_tvalid,
output_2_axis_tready,
output_2_axis_tlast,
output_2_axis_tuser,
output_3_axis_tdata,
output_3_axis_tvalid,
output_3_axis_tready,
output_3_axis_tlast,
output_3_axis_tuser,
select)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
yield clk.posedge
print("test 1: select port 0")
current_test.next = 1
select.next = 0
test_frame = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
'\x5A\x51\x52\x53\x54\x55' +
'\x80\x00' +
'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
yield clk.posedge
while input_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_0_queue.empty():
rx_frame = sink_0_queue.get()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 2: select port 1")
current_test.next = 2
select.next = 1
test_frame = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
'\x5A\x51\x52\x53\x54\x55' +
'\x80\x00' +
'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
yield clk.posedge
while input_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_1_queue.empty():
rx_frame = sink_1_queue.get()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 3: back-to-back packets, same port")
current_test.next = 3
select.next = 0
test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
'\x5A\x51\x52\x53\x54\x55' +
'\x80\x00' +
'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
'\x5A\x51\x52\x53\x54\x55' +
'\x80\x00' +
'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
while input_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_0_queue.empty():
rx_frame = sink_0_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_0_queue.empty():
rx_frame = sink_0_queue.get()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 4: back-to-back packets, different ports")
current_test.next = 4
select.next = 1
test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
'\x5A\x51\x52\x53\x54\x55' +
'\x80\x00' +
'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
'\x5A\x51\x52\x53\x54\x55' +
'\x80\x00' +
'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
while input_axis_tvalid:
yield clk.posedge
select.next = 2
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_2_queue.empty():
rx_frame = sink_1_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_2_queue.empty():
rx_frame = sink_2_queue.get()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 5: alterate pause source")
current_test.next = 5
select.next = 1
test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
'\x5A\x51\x52\x53\x54\x55' +
'\x80\x00' +
'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
'\x5A\x51\x52\x53\x54\x55' +
'\x80\x00' +
'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
while input_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
select.next = 2
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_1_queue.empty():
rx_frame = sink_1_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_2_queue.empty():
rx_frame = sink_2_queue.get()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 6: alterate pause sink")
current_test.next = 6
select.next = 1
test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
'\x5A\x51\x52\x53\x54\x55' +
'\x80\x00' +
'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
'\x5A\x51\x52\x53\x54\x55' +
'\x80\x00' +
'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
while input_axis_tvalid:
sink_0_pause.next = True
sink_1_pause.next = True
sink_2_pause.next = True
sink_3_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_0_pause.next = False
sink_1_pause.next = False
sink_2_pause.next = False
sink_3_pause.next = False
yield clk.posedge
select.next = 2
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_1_queue.empty():
rx_frame = sink_1_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_2_queue.empty():
rx_frame = sink_2_queue.get()
assert rx_frame == test_frame2
yield delay(100)
raise StopSimulation
return dut, source, sink_0, sink_1, sink_2, sink_3, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))
sim = Simulation(bench())
sim.run()
if __name__ == '__main__':
print("Running test...")
test_bench()

142
tb/test_axis_demux_4.v Normal file
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/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_demux_4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_axis_tdata = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_0_axis_tready = 0;
reg output_1_axis_tready = 0;
reg output_2_axis_tready = 0;
reg output_3_axis_tready = 0;
reg [1:0] select = 0;
// Outputs
wire input_axis_tready;
wire [7:0] output_0_axis_tdata;
wire output_0_axis_tvalid;
wire output_0_axis_tlast;
wire output_0_axis_tuser;
wire [7:0] output_1_axis_tdata;
wire output_1_axis_tvalid;
wire output_1_axis_tlast;
wire output_1_axis_tuser;
wire [7:0] output_2_axis_tdata;
wire output_2_axis_tvalid;
wire output_2_axis_tlast;
wire output_2_axis_tuser;
wire [7:0] output_3_axis_tdata;
wire output_3_axis_tvalid;
wire output_3_axis_tlast;
wire output_3_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_0_axis_tready,
output_1_axis_tready,
output_2_axis_tready,
output_3_axis_tready,
select);
$to_myhdl(input_axis_tready,
output_0_axis_tdata,
output_0_axis_tvalid,
output_0_axis_tlast,
output_0_axis_tuser,
output_1_axis_tdata,
output_1_axis_tvalid,
output_1_axis_tlast,
output_1_axis_tuser,
output_2_axis_tdata,
output_2_axis_tvalid,
output_2_axis_tlast,
output_2_axis_tuser,
output_3_axis_tdata,
output_3_axis_tvalid,
output_3_axis_tlast,
output_3_axis_tuser);
// dump file
$dumpfile("test_axis_demux_4.lxt");
$dumpvars(0, test_axis_demux_4);
end
axis_demux_4 #(
.DATA_WIDTH(8)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(input_axis_tdata),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// AXI outputs
.output_0_axis_tdata(output_0_axis_tdata),
.output_0_axis_tvalid(output_0_axis_tvalid),
.output_0_axis_tready(output_0_axis_tready),
.output_0_axis_tlast(output_0_axis_tlast),
.output_0_axis_tuser(output_0_axis_tuser),
.output_1_axis_tdata(output_1_axis_tdata),
.output_1_axis_tvalid(output_1_axis_tvalid),
.output_1_axis_tready(output_1_axis_tready),
.output_1_axis_tlast(output_1_axis_tlast),
.output_1_axis_tuser(output_1_axis_tuser),
.output_2_axis_tdata(output_2_axis_tdata),
.output_2_axis_tvalid(output_2_axis_tvalid),
.output_2_axis_tready(output_2_axis_tready),
.output_2_axis_tlast(output_2_axis_tlast),
.output_2_axis_tuser(output_2_axis_tuser),
.output_3_axis_tdata(output_3_axis_tdata),
.output_3_axis_tvalid(output_3_axis_tvalid),
.output_3_axis_tready(output_3_axis_tready),
.output_3_axis_tlast(output_3_axis_tlast),
.output_3_axis_tuser(output_3_axis_tuser),
// Control
.select(select)
);
endmodule

525
tb/test_axis_demux_64_4.py Executable file
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@ -0,0 +1,525 @@
#!/usr/bin/env python2
"""
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
"""
from myhdl import *
import os
from Queue import Queue
import axis_ep
module = 'axis_demux_64_4'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("test_%s.v" % module)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_axis_demux_64_4(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_0_axis_tdata,
output_0_axis_tkeep,
output_0_axis_tvalid,
output_0_axis_tready,
output_0_axis_tlast,
output_0_axis_tuser,
output_1_axis_tdata,
output_1_axis_tkeep,
output_1_axis_tvalid,
output_1_axis_tready,
output_1_axis_tlast,
output_1_axis_tuser,
output_2_axis_tdata,
output_2_axis_tkeep,
output_2_axis_tvalid,
output_2_axis_tready,
output_2_axis_tlast,
output_2_axis_tuser,
output_3_axis_tdata,
output_3_axis_tkeep,
output_3_axis_tvalid,
output_3_axis_tready,
output_3_axis_tlast,
output_3_axis_tuser,
select):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tkeep=input_axis_tkeep,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
output_0_axis_tdata=output_0_axis_tdata,
output_0_axis_tkeep=output_0_axis_tkeep,
output_0_axis_tvalid=output_0_axis_tvalid,
output_0_axis_tready=output_0_axis_tready,
output_0_axis_tlast=output_0_axis_tlast,
output_0_axis_tuser=output_0_axis_tuser,
output_1_axis_tdata=output_1_axis_tdata,
output_1_axis_tkeep=output_1_axis_tkeep,
output_1_axis_tvalid=output_1_axis_tvalid,
output_1_axis_tready=output_1_axis_tready,
output_1_axis_tlast=output_1_axis_tlast,
output_1_axis_tuser=output_1_axis_tuser,
output_2_axis_tdata=output_2_axis_tdata,
output_2_axis_tkeep=output_2_axis_tkeep,
output_2_axis_tvalid=output_2_axis_tvalid,
output_2_axis_tready=output_2_axis_tready,
output_2_axis_tlast=output_2_axis_tlast,
output_2_axis_tuser=output_2_axis_tuser,
output_3_axis_tdata=output_3_axis_tdata,
output_3_axis_tkeep=output_3_axis_tkeep,
output_3_axis_tvalid=output_3_axis_tvalid,
output_3_axis_tready=output_3_axis_tready,
output_3_axis_tlast=output_3_axis_tlast,
output_3_axis_tuser=output_3_axis_tuser,
select=select)
def bench():
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[64:])
input_axis_tkeep = Signal(intbv(0)[8:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
output_0_axis_tready = Signal(bool(0))
output_1_axis_tready = Signal(bool(0))
output_2_axis_tready = Signal(bool(0))
output_3_axis_tready = Signal(bool(0))
select = Signal(intbv(0)[2:])
# Outputs
input_axis_tready = Signal(bool(0))
output_0_axis_tdata = Signal(intbv(0)[64:])
output_0_axis_tkeep = Signal(intbv(0)[8:])
output_0_axis_tvalid = Signal(bool(0))
output_0_axis_tlast = Signal(bool(0))
output_0_axis_tuser = Signal(bool(0))
output_1_axis_tdata = Signal(intbv(0)[64:])
output_1_axis_tkeep = Signal(intbv(0)[8:])
output_1_axis_tvalid = Signal(bool(0))
output_1_axis_tlast = Signal(bool(0))
output_1_axis_tuser = Signal(bool(0))
output_2_axis_tdata = Signal(intbv(0)[64:])
output_2_axis_tkeep = Signal(intbv(0)[8:])
output_2_axis_tvalid = Signal(bool(0))
output_2_axis_tlast = Signal(bool(0))
output_2_axis_tuser = Signal(bool(0))
output_3_axis_tdata = Signal(intbv(0)[64:])
output_3_axis_tkeep = Signal(intbv(0)[8:])
output_3_axis_tvalid = Signal(bool(0))
output_3_axis_tlast = Signal(bool(0))
output_3_axis_tuser = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_0_queue = Queue()
sink_0_pause = Signal(bool(0))
sink_1_queue = Queue()
sink_1_pause = Signal(bool(0))
sink_2_queue = Queue()
sink_2_pause = Signal(bool(0))
sink_3_queue = Queue()
sink_3_pause = Signal(bool(0))
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tkeep=input_axis_tkeep,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
sink_0 = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_0_axis_tdata,
tkeep=output_0_axis_tkeep,
tvalid=output_0_axis_tvalid,
tready=output_0_axis_tready,
tlast=output_0_axis_tlast,
tuser=output_0_axis_tuser,
fifo=sink_0_queue,
pause=sink_0_pause,
name='sink0')
sink_1 = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_1_axis_tdata,
tkeep=output_1_axis_tkeep,
tvalid=output_1_axis_tvalid,
tready=output_1_axis_tready,
tlast=output_1_axis_tlast,
tuser=output_1_axis_tuser,
fifo=sink_1_queue,
pause=sink_1_pause,
name='sink1')
sink_2 = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_2_axis_tdata,
tkeep=output_2_axis_tkeep,
tvalid=output_2_axis_tvalid,
tready=output_2_axis_tready,
tlast=output_2_axis_tlast,
tuser=output_2_axis_tuser,
fifo=sink_2_queue,
pause=sink_2_pause,
name='sink2')
sink_3 = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_3_axis_tdata,
tkeep=output_3_axis_tkeep,
tvalid=output_3_axis_tvalid,
tready=output_3_axis_tready,
tlast=output_3_axis_tlast,
tuser=output_3_axis_tuser,
fifo=sink_3_queue,
pause=sink_3_pause,
name='sink3')
# DUT
dut = dut_axis_demux_64_4(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
output_0_axis_tdata,
output_0_axis_tkeep,
output_0_axis_tvalid,
output_0_axis_tready,
output_0_axis_tlast,
output_0_axis_tuser,
output_1_axis_tdata,
output_1_axis_tkeep,
output_1_axis_tvalid,
output_1_axis_tready,
output_1_axis_tlast,
output_1_axis_tuser,
output_2_axis_tdata,
output_2_axis_tkeep,
output_2_axis_tvalid,
output_2_axis_tready,
output_2_axis_tlast,
output_2_axis_tuser,
output_3_axis_tdata,
output_3_axis_tkeep,
output_3_axis_tvalid,
output_3_axis_tready,
output_3_axis_tlast,
output_3_axis_tuser,
select)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
yield clk.posedge
yield clk.posedge
print("test 1: select port 0")
current_test.next = 1
select.next = 0
test_frame = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
'\x5A\x51\x52\x53\x54\x55' +
'\x80\x00' +
'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
yield clk.posedge
while input_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_0_queue.empty():
rx_frame = sink_0_queue.get()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 2: select port 1")
current_test.next = 2
select.next = 1
test_frame = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
'\x5A\x51\x52\x53\x54\x55' +
'\x80\x00' +
'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame)
yield clk.posedge
while input_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_1_queue.empty():
rx_frame = sink_1_queue.get()
assert rx_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 3: back-to-back packets, same port")
current_test.next = 3
select.next = 0
test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
'\x5A\x51\x52\x53\x54\x55' +
'\x80\x00' +
'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
'\x5A\x51\x52\x53\x54\x55' +
'\x80\x00' +
'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
while input_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_0_queue.empty():
rx_frame = sink_0_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_0_queue.empty():
rx_frame = sink_0_queue.get()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 4: back-to-back packets, different ports")
current_test.next = 4
select.next = 1
test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
'\x5A\x51\x52\x53\x54\x55' +
'\x80\x00' +
'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
'\x5A\x51\x52\x53\x54\x55' +
'\x80\x00' +
'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
while input_axis_tvalid:
yield clk.posedge
select.next = 2
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_2_queue.empty():
rx_frame = sink_1_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_2_queue.empty():
rx_frame = sink_2_queue.get()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 5: alterate pause source")
current_test.next = 5
select.next = 1
test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
'\x5A\x51\x52\x53\x54\x55' +
'\x80\x00' +
'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
'\x5A\x51\x52\x53\x54\x55' +
'\x80\x00' +
'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
while input_axis_tvalid:
source_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
source_pause.next = False
yield clk.posedge
select.next = 2
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_1_queue.empty():
rx_frame = sink_1_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_2_queue.empty():
rx_frame = sink_2_queue.get()
assert rx_frame == test_frame2
yield delay(100)
yield clk.posedge
print("test 6: alterate pause sink")
current_test.next = 6
select.next = 1
test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
'\x5A\x51\x52\x53\x54\x55' +
'\x80\x00' +
'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
'\x5A\x51\x52\x53\x54\x55' +
'\x80\x00' +
'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
source_queue.put(test_frame1)
source_queue.put(test_frame2)
yield clk.posedge
while input_axis_tvalid:
sink_0_pause.next = True
sink_1_pause.next = True
sink_2_pause.next = True
sink_3_pause.next = True
yield clk.posedge
yield clk.posedge
yield clk.posedge
sink_0_pause.next = False
sink_1_pause.next = False
sink_2_pause.next = False
sink_3_pause.next = False
yield clk.posedge
select.next = 2
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_1_queue.empty():
rx_frame = sink_1_queue.get()
assert rx_frame == test_frame1
rx_frame = None
if not sink_2_queue.empty():
rx_frame = sink_2_queue.get()
assert rx_frame == test_frame2
yield delay(100)
raise StopSimulation
return dut, source, sink_0, sink_1, sink_2, sink_3, clkgen, check
def test_bench():
os.chdir(os.path.dirname(os.path.abspath(__file__)))
sim = Simulation(bench())
sim.run()
if __name__ == '__main__':
print("Running test...")
test_bench()

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/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_demux_64_4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] input_axis_tdata = 0;
reg [7:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_0_axis_tready = 0;
reg output_1_axis_tready = 0;
reg output_2_axis_tready = 0;
reg output_3_axis_tready = 0;
reg [1:0] select = 0;
// Outputs
wire input_axis_tready;
wire [63:0] output_0_axis_tdata;
wire [7:0] output_0_axis_tkeep;
wire output_0_axis_tvalid;
wire output_0_axis_tlast;
wire output_0_axis_tuser;
wire [63:0] output_1_axis_tdata;
wire [7:0] output_1_axis_tkeep;
wire output_1_axis_tvalid;
wire output_1_axis_tlast;
wire output_1_axis_tuser;
wire [63:0] output_2_axis_tdata;
wire [7:0] output_2_axis_tkeep;
wire output_2_axis_tvalid;
wire output_2_axis_tlast;
wire output_2_axis_tuser;
wire [63:0] output_3_axis_tdata;
wire [7:0] output_3_axis_tkeep;
wire output_3_axis_tvalid;
wire output_3_axis_tlast;
wire output_3_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_0_axis_tready,
output_1_axis_tready,
output_2_axis_tready,
output_3_axis_tready,
select);
$to_myhdl(input_axis_tready,
output_0_axis_tdata,
output_0_axis_tkeep,
output_0_axis_tvalid,
output_0_axis_tlast,
output_0_axis_tuser,
output_1_axis_tdata,
output_1_axis_tkeep,
output_1_axis_tvalid,
output_1_axis_tlast,
output_1_axis_tuser,
output_2_axis_tdata,
output_2_axis_tkeep,
output_2_axis_tvalid,
output_2_axis_tlast,
output_2_axis_tuser,
output_3_axis_tdata,
output_3_axis_tkeep,
output_3_axis_tvalid,
output_3_axis_tlast,
output_3_axis_tuser);
// dump file
$dumpfile("test_axis_demux_64_4.lxt");
$dumpvars(0, test_axis_demux_64_4);
end
axis_demux_64_4 #(
.DATA_WIDTH(64)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// AXI outputs
.output_0_axis_tdata(output_0_axis_tdata),
.output_0_axis_tkeep(output_0_axis_tkeep),
.output_0_axis_tvalid(output_0_axis_tvalid),
.output_0_axis_tready(output_0_axis_tready),
.output_0_axis_tlast(output_0_axis_tlast),
.output_0_axis_tuser(output_0_axis_tuser),
.output_1_axis_tdata(output_1_axis_tdata),
.output_1_axis_tkeep(output_1_axis_tkeep),
.output_1_axis_tvalid(output_1_axis_tvalid),
.output_1_axis_tready(output_1_axis_tready),
.output_1_axis_tlast(output_1_axis_tlast),
.output_1_axis_tuser(output_1_axis_tuser),
.output_2_axis_tdata(output_2_axis_tdata),
.output_2_axis_tkeep(output_2_axis_tkeep),
.output_2_axis_tvalid(output_2_axis_tvalid),
.output_2_axis_tready(output_2_axis_tready),
.output_2_axis_tlast(output_2_axis_tlast),
.output_2_axis_tuser(output_2_axis_tuser),
.output_3_axis_tdata(output_3_axis_tdata),
.output_3_axis_tkeep(output_3_axis_tkeep),
.output_3_axis_tvalid(output_3_axis_tvalid),
.output_3_axis_tready(output_3_axis_tready),
.output_3_axis_tlast(output_3_axis_tlast),
.output_3_axis_tuser(output_3_axis_tuser),
// Control
.select(select)
);
endmodule