From 5d349c9cb26d010a0b6f1baf5c10172680f3271f Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 21 Jul 2023 18:17:12 -0700 Subject: [PATCH] Enable overtemp shutdown in constraints files Signed-off-by: Alex Forencich --- example/AU200/fpga_25g/fpga.xdc | 1 + example/AU250/fpga_25g/fpga.xdc | 1 + example/AU280/fpga_25g/fpga.xdc | 1 + example/AU50/fpga_25g/fpga.xdc | 1 + example/Arty/fpga/fpga.xdc | 11 ++++++----- example/ExaNIC_X10/fpga/fpga.xdc | 15 ++++++++------- example/HTG9200/fpga_25g/fpga.xdc | 1 + example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga.xdc | 1 + example/KC705/fpga_gmii/fpga.xdc | 7 ++++--- example/KC705/fpga_rgmii/fpga.xdc | 7 ++++--- example/KC705/fpga_sgmii/fpga.xdc | 7 ++++--- example/NetFPGA_SUME/fpga/fpga.xdc | 9 +++++---- example/NexysVideo/fpga/fpga.xdc | 7 ++++--- example/VCU108/fpga_10g/fpga.xdc | 1 + example/VCU108/fpga_1g/fpga.xdc | 1 + example/VCU118/fpga_1g/fpga.xdc | 1 + example/VCU118/fpga_25g/fpga.xdc | 1 + example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga.xdc | 1 + example/VCU1525/fpga_25g/fpga.xdc | 1 + 19 files changed, 47 insertions(+), 28 deletions(-) diff --git a/example/AU200/fpga_25g/fpga.xdc b/example/AU200/fpga_25g/fpga.xdc index 8be9b45b0..53665ef34 100644 --- a/example/AU200/fpga_25g/fpga.xdc +++ b/example/AU200/fpga_25g/fpga.xdc @@ -12,6 +12,7 @@ set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] set_operating_conditions -design_power_budget 160 diff --git a/example/AU250/fpga_25g/fpga.xdc b/example/AU250/fpga_25g/fpga.xdc index d7e188716..2d006125a 100644 --- a/example/AU250/fpga_25g/fpga.xdc +++ b/example/AU250/fpga_25g/fpga.xdc @@ -12,6 +12,7 @@ set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] set_operating_conditions -design_power_budget 160 diff --git a/example/AU280/fpga_25g/fpga.xdc b/example/AU280/fpga_25g/fpga.xdc index f9d723562..ff6be120e 100644 --- a/example/AU280/fpga_25g/fpga.xdc +++ b/example/AU280/fpga_25g/fpga.xdc @@ -13,6 +13,7 @@ set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design] set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] set_operating_conditions -design_power_budget 160 diff --git a/example/AU50/fpga_25g/fpga.xdc b/example/AU50/fpga_25g/fpga.xdc index e46f255f4..5d3515481 100644 --- a/example/AU50/fpga_25g/fpga.xdc +++ b/example/AU50/fpga_25g/fpga.xdc @@ -13,6 +13,7 @@ set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design] set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] set_operating_conditions -design_power_budget 63 diff --git a/example/Arty/fpga/fpga.xdc b/example/Arty/fpga/fpga.xdc index 6c23386f2..4bf23b38a 100644 --- a/example/Arty/fpga/fpga.xdc +++ b/example/Arty/fpga/fpga.xdc @@ -2,11 +2,12 @@ # part: xc7a35t-csg324-1 # General configuration -set_property CFGBVS VCCO [current_design] -set_property CONFIG_VOLTAGE 3.3 [current_design] -set_property BITSTREAM.GENERAL.COMPRESS true [current_design] -set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design] -set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] # 100 MHz clock set_property -dict {LOC E3 IOSTANDARD LVCMOS33} [get_ports clk] diff --git a/example/ExaNIC_X10/fpga/fpga.xdc b/example/ExaNIC_X10/fpga/fpga.xdc index f3c5ef2b0..59392e654 100644 --- a/example/ExaNIC_X10/fpga/fpga.xdc +++ b/example/ExaNIC_X10/fpga/fpga.xdc @@ -2,13 +2,14 @@ # part: xcku035-fbva676-2-e # General configuration -set_property CFGBVS GND [current_design] -set_property CONFIG_VOLTAGE 1.8 [current_design] -set_property BITSTREAM.GENERAL.COMPRESS true [current_design] -set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] -set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design] -set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type2 [current_design] -set_property CONFIG_MODE BPI16 [current_design] +set_property CFGBVS GND [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design] +set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type2 [current_design] +set_property CONFIG_MODE BPI16 [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] # 100 MHz system clock set_property -dict {LOC D18 IOSTANDARD LVDS} [get_ports clk_100mhz_p] diff --git a/example/HTG9200/fpga_25g/fpga.xdc b/example/HTG9200/fpga_25g/fpga.xdc index e1a7b4218..cca216957 100644 --- a/example/HTG9200/fpga_25g/fpga.xdc +++ b/example/HTG9200/fpga_25g/fpga.xdc @@ -9,6 +9,7 @@ set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design] set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] # System clocks # DDR4 clocks from U5 (200 MHz) diff --git a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga.xdc b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga.xdc index 119f122d1..e07da2558 100644 --- a/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga.xdc +++ b/example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga.xdc @@ -9,6 +9,7 @@ set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design] set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] # System clocks # DDR4 clocks from U5 (200 MHz) diff --git a/example/KC705/fpga_gmii/fpga.xdc b/example/KC705/fpga_gmii/fpga.xdc index 3b4484e67..225dee937 100644 --- a/example/KC705/fpga_gmii/fpga.xdc +++ b/example/KC705/fpga_gmii/fpga.xdc @@ -2,9 +2,10 @@ # part: xc7k325tffg900-2 # General configuration -set_property CFGBVS VCCO [current_design] -set_property CONFIG_VOLTAGE 2.5 [current_design] -set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 2.5 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] # System clocks # 200 MHz diff --git a/example/KC705/fpga_rgmii/fpga.xdc b/example/KC705/fpga_rgmii/fpga.xdc index 1f6408855..0fae76968 100644 --- a/example/KC705/fpga_rgmii/fpga.xdc +++ b/example/KC705/fpga_rgmii/fpga.xdc @@ -2,9 +2,10 @@ # part: xc7k325tffg900-2 # General configuration -set_property CFGBVS VCCO [current_design] -set_property CONFIG_VOLTAGE 2.5 [current_design] -set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 2.5 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] # System clocks # 200 MHz diff --git a/example/KC705/fpga_sgmii/fpga.xdc b/example/KC705/fpga_sgmii/fpga.xdc index f384048d6..0b4d2e08b 100644 --- a/example/KC705/fpga_sgmii/fpga.xdc +++ b/example/KC705/fpga_sgmii/fpga.xdc @@ -2,9 +2,10 @@ # part: xc7k325tffg900-2 # General configuration -set_property CFGBVS VCCO [current_design] -set_property CONFIG_VOLTAGE 2.5 [current_design] -set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 2.5 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] # System clocks # 200 MHz diff --git a/example/NetFPGA_SUME/fpga/fpga.xdc b/example/NetFPGA_SUME/fpga/fpga.xdc index d5188a5c0..28f6ae3f1 100644 --- a/example/NetFPGA_SUME/fpga/fpga.xdc +++ b/example/NetFPGA_SUME/fpga/fpga.xdc @@ -2,10 +2,11 @@ # part: xc7vx690tffg1761-3 # General configuration -set_property CFGBVS GND [current_design] -set_property CONFIG_VOLTAGE 1.8 [current_design] -set_property BITSTREAM.GENERAL.COMPRESS true [current_design] -set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] +set_property CFGBVS GND [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] # 200 MHz system clock set_property -dict {LOC H19 IOSTANDARD LVDS} [get_ports clk_200mhz_p] diff --git a/example/NexysVideo/fpga/fpga.xdc b/example/NexysVideo/fpga/fpga.xdc index 05cd5d125..b83cb2194 100644 --- a/example/NexysVideo/fpga/fpga.xdc +++ b/example/NexysVideo/fpga/fpga.xdc @@ -2,9 +2,10 @@ # part: xc7a200tsbg484-1 # General configuration -set_property CFGBVS VCCO [current_design] -set_property CONFIG_VOLTAGE 3.3 [current_design] -set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] # 100 MHz clock set_property -dict {LOC R4 IOSTANDARD LVCMOS33} [get_ports clk] diff --git a/example/VCU108/fpga_10g/fpga.xdc b/example/VCU108/fpga_10g/fpga.xdc index 037acab5b..1187f1bd4 100644 --- a/example/VCU108/fpga_10g/fpga.xdc +++ b/example/VCU108/fpga_10g/fpga.xdc @@ -8,6 +8,7 @@ set_property BITSTREAM.GENERAL.COMPRESS true [current_design] set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design] set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type1 [current_design] set_property CONFIG_MODE BPI16 [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] # System clocks # 300 MHz diff --git a/example/VCU108/fpga_1g/fpga.xdc b/example/VCU108/fpga_1g/fpga.xdc index 100e7d11a..275e1869c 100644 --- a/example/VCU108/fpga_1g/fpga.xdc +++ b/example/VCU108/fpga_1g/fpga.xdc @@ -8,6 +8,7 @@ set_property BITSTREAM.GENERAL.COMPRESS true [current_design] set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design] set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type1 [current_design] set_property CONFIG_MODE BPI16 [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] # System clocks # 300 MHz diff --git a/example/VCU118/fpga_1g/fpga.xdc b/example/VCU118/fpga_1g/fpga.xdc index 4e5166719..3b1fd2272 100644 --- a/example/VCU118/fpga_1g/fpga.xdc +++ b/example/VCU118/fpga_1g/fpga.xdc @@ -9,6 +9,7 @@ set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design] set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] # System clocks # 300 MHz diff --git a/example/VCU118/fpga_25g/fpga.xdc b/example/VCU118/fpga_25g/fpga.xdc index d87f30028..c2fda604f 100644 --- a/example/VCU118/fpga_25g/fpga.xdc +++ b/example/VCU118/fpga_25g/fpga.xdc @@ -9,6 +9,7 @@ set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design] set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] # System clocks # 300 MHz diff --git a/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga.xdc b/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga.xdc index 1f7765bc9..fb3596a51 100644 --- a/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga.xdc +++ b/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga.xdc @@ -9,6 +9,7 @@ set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design] set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] # System clocks # 300 MHz diff --git a/example/VCU1525/fpga_25g/fpga.xdc b/example/VCU1525/fpga_25g/fpga.xdc index 2042708b5..d78cb3ec2 100644 --- a/example/VCU1525/fpga_25g/fpga.xdc +++ b/example/VCU1525/fpga_25g/fpga.xdc @@ -12,6 +12,7 @@ set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] # System clocks # 300 MHz (DDR 0)