Enable overtemp shutdown in constraints files

Signed-off-by: Alex Forencich <alex@alexforencich.com>

example/AU200/fpga_25g/fpga.xdc

@@ -12,6 +12,7 @@ set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4           [current_design]
 set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
 set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP         [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 set_operating_conditions -design_power_budget 160
 

example/AU250/fpga_25g/fpga.xdc

@@ -12,6 +12,7 @@ set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4           [current_design]
 set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
 set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP         [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 set_operating_conditions -design_power_budget 160
 

example/AU280/fpga_25g/fpga.xdc

@@ -13,6 +13,7 @@ set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design]
 set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
 set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP         [current_design]
 set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 set_operating_conditions -design_power_budget 160
 

example/AU50/fpga_25g/fpga.xdc

@@ -13,6 +13,7 @@ set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design]
 set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
 set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP         [current_design]
 set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 set_operating_conditions -design_power_budget 63
 

example/Arty/fpga/fpga.xdc

@@ -7,6 +7,7 @@ set_property CONFIG_VOLTAGE 3.3              [current_design]
 set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
 set_property BITSTREAM.CONFIG.CONFIGRATE 50            [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4           [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # 100 MHz clock
 set_property -dict {LOC E3 IOSTANDARD LVCMOS33} [get_ports clk]

example/ExaNIC_X10/fpga/fpga.xdc

@@ -9,6 +9,7 @@ set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup    [current_design]
 set_property BITSTREAM.CONFIG.CONFIGRATE 50            [current_design]
 set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type2      [current_design]
 set_property CONFIG_MODE BPI16                         [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # 100 MHz system clock
 set_property -dict {LOC D18  IOSTANDARD LVDS} [get_ports clk_100mhz_p]

example/HTG9200/fpga_25g/fpga.xdc

@@ -9,6 +9,7 @@ set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
 set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8           [current_design]
 set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # System clocks
 # DDR4 clocks from U5 (200 MHz)

example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga.xdc

@@ -9,6 +9,7 @@ set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
 set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8           [current_design]
 set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # System clocks
 # DDR4 clocks from U5 (200 MHz)

example/KC705/fpga_gmii/fpga.xdc

@@ -5,6 +5,7 @@
 set_property CFGBVS VCCO                               [current_design]
 set_property CONFIG_VOLTAGE 2.5                        [current_design]
 set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # System clocks
 # 200 MHz

example/KC705/fpga_rgmii/fpga.xdc

@@ -5,6 +5,7 @@
 set_property CFGBVS VCCO                               [current_design]
 set_property CONFIG_VOLTAGE 2.5                        [current_design]
 set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # System clocks
 # 200 MHz

example/KC705/fpga_sgmii/fpga.xdc

@@ -5,6 +5,7 @@
 set_property CFGBVS VCCO                               [current_design]
 set_property CONFIG_VOLTAGE 2.5                        [current_design]
 set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # System clocks
 # 200 MHz

example/NetFPGA_SUME/fpga/fpga.xdc

@@ -6,6 +6,7 @@ set_property CFGBVS GND                           [current_design]
 set_property CONFIG_VOLTAGE 1.8                        [current_design]
 set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
 set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup         [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # 200 MHz system clock
 set_property -dict {LOC H19  IOSTANDARD LVDS} [get_ports clk_200mhz_p]

example/NexysVideo/fpga/fpga.xdc

@@ -5,6 +5,7 @@
 set_property CFGBVS VCCO                               [current_design]
 set_property CONFIG_VOLTAGE 3.3                        [current_design]
 set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # 100 MHz clock
 set_property -dict {LOC R4 IOSTANDARD LVCMOS33} [get_ports clk]

example/VCU108/fpga_10g/fpga.xdc

@@ -8,6 +8,7 @@ set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
 set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
 set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type1      [current_design]
 set_property CONFIG_MODE BPI16                         [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # System clocks
 # 300 MHz

example/VCU108/fpga_1g/fpga.xdc

@@ -8,6 +8,7 @@ set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
 set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
 set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type1      [current_design]
 set_property CONFIG_MODE BPI16                         [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # System clocks
 # 300 MHz

example/VCU118/fpga_1g/fpga.xdc

@@ -9,6 +9,7 @@ set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
 set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8           [current_design]
 set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # System clocks
 # 300 MHz

example/VCU118/fpga_25g/fpga.xdc

@@ -9,6 +9,7 @@ set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
 set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8           [current_design]
 set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # System clocks
 # 300 MHz

example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga.xdc

@@ -9,6 +9,7 @@ set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
 set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8           [current_design]
 set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # System clocks
 # 300 MHz

example/VCU1525/fpga_25g/fpga.xdc

@@ -12,6 +12,7 @@ set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4           [current_design]
 set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
 set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP         [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable  [current_design]
 
 # System clocks
 # 300 MHz (DDR 0)