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Use quad wrappers in ADM-PCIE-9V3 example design

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-08-26 00:36:39 -07:00
parent 1e88ed3d2e
commit 5d61059488
6 changed files with 614 additions and 443 deletions
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64
example/ADM_PCIE_9V3/fpga_25g/fpga.xdc
View File

@ -41,22 +41,22 @@ set_input_delay 0 [get_ports {user_sw[*]}]
#set_property -dict {LOC H31 IOSTANDARD LVCMOS18} [get_ports gpio_n[1]]
# QSFP28 Interfaces
set_property -dict {LOC G38 } [get_ports qsfp_0_rx_0_p] ;# MGTYRXP0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
set_property -dict {LOC G39 } [get_ports qsfp_0_rx_0_n] ;# MGTYRXN0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
set_property -dict {LOC F35 } [get_ports qsfp_0_tx_0_p] ;# MGTYTXP0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
set_property -dict {LOC F36 } [get_ports qsfp_0_tx_0_n] ;# MGTYTXN0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
set_property -dict {LOC E38 } [get_ports qsfp_0_rx_1_p] ;# MGTYRXP1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
set_property -dict {LOC E39 } [get_ports qsfp_0_rx_1_n] ;# MGTYRXN1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
set_property -dict {LOC D35 } [get_ports qsfp_0_tx_1_p] ;# MGTYTXP1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
set_property -dict {LOC D36 } [get_ports qsfp_0_tx_1_n] ;# MGTYTXN1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
set_property -dict {LOC C38 } [get_ports qsfp_0_rx_2_p] ;# MGTYRXP2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
set_property -dict {LOC C39 } [get_ports qsfp_0_rx_2_n] ;# MGTYRXN2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
set_property -dict {LOC C33 } [get_ports qsfp_0_tx_2_p] ;# MGTYTXP2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
set_property -dict {LOC C34 } [get_ports qsfp_0_tx_2_n] ;# MGTYTXN2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
set_property -dict {LOC B36 } [get_ports qsfp_0_rx_3_p] ;# MGTYRXP3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
set_property -dict {LOC B37 } [get_ports qsfp_0_rx_3_n] ;# MGTYRXN3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
set_property -dict {LOC A33 } [get_ports qsfp_0_tx_3_p] ;# MGTYTXP3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
set_property -dict {LOC A34 } [get_ports qsfp_0_tx_3_n] ;# MGTYTXN3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
set_property -dict {LOC G38 } [get_ports {qsfp_0_rx_p[0]}] ;# MGTYRXP0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
set_property -dict {LOC G39 } [get_ports {qsfp_0_rx_n[0]}] ;# MGTYRXN0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
set_property -dict {LOC F35 } [get_ports {qsfp_0_tx_p[0]}] ;# MGTYTXP0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
set_property -dict {LOC F36 } [get_ports {qsfp_0_tx_n[0]}] ;# MGTYTXN0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4
set_property -dict {LOC E38 } [get_ports {qsfp_0_rx_p[1]}] ;# MGTYRXP1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
set_property -dict {LOC E39 } [get_ports {qsfp_0_rx_n[1]}] ;# MGTYRXN1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
set_property -dict {LOC D35 } [get_ports {qsfp_0_tx_p[1]}] ;# MGTYTXP1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
set_property -dict {LOC D36 } [get_ports {qsfp_0_tx_n[1]}] ;# MGTYTXN1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4
set_property -dict {LOC C38 } [get_ports {qsfp_0_rx_p[2]}] ;# MGTYRXP2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
set_property -dict {LOC C39 } [get_ports {qsfp_0_rx_n[2]}] ;# MGTYRXN2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
set_property -dict {LOC C33 } [get_ports {qsfp_0_tx_p[2]}] ;# MGTYTXP2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
set_property -dict {LOC C34 } [get_ports {qsfp_0_tx_n[2]}] ;# MGTYTXN2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4
set_property -dict {LOC B36 } [get_ports {qsfp_0_rx_p[3]}] ;# MGTYRXP3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
set_property -dict {LOC B37 } [get_ports {qsfp_0_rx_n[3]}] ;# MGTYRXN3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
set_property -dict {LOC A33 } [get_ports {qsfp_0_tx_p[3]}] ;# MGTYTXP3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
set_property -dict {LOC A34 } [get_ports {qsfp_0_tx_n[3]}] ;# MGTYTXN3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4
set_property -dict {LOC N33 } [get_ports qsfp_0_mgt_refclk_p] ;# MGTREFCLK0P_128 from ?
set_property -dict {LOC N34 } [get_ports qsfp_0_mgt_refclk_n] ;# MGTREFCLK0N_128 from ?
set_property -dict {LOC F29 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_0_modprs_l]
@ -65,22 +65,22 @@ set_property -dict {LOC D31 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports
# 161.1328125 MHz MGT reference clock
create_clock -period 6.206 -name qsfp_0_mgt_refclk [get_ports qsfp_0_mgt_refclk_p]
set_property -dict {LOC R38 } [get_ports qsfp_1_rx_0_p] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
set_property -dict {LOC R39 } [get_ports qsfp_1_rx_0_n] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
set_property -dict {LOC P35 } [get_ports qsfp_1_tx_0_p] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
set_property -dict {LOC P36 } [get_ports qsfp_1_tx_0_n] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
set_property -dict {LOC N38 } [get_ports qsfp_1_rx_1_p] ;# MGTYRXP1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
set_property -dict {LOC N39 } [get_ports qsfp_1_rx_1_n] ;# MGTYRXN1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
set_property -dict {LOC M35 } [get_ports qsfp_1_tx_1_p] ;# MGTYTXP1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
set_property -dict {LOC M36 } [get_ports qsfp_1_tx_1_n] ;# MGTYTXN1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
set_property -dict {LOC L38 } [get_ports qsfp_1_rx_2_p] ;# MGTYRXP2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
set_property -dict {LOC L39 } [get_ports qsfp_1_rx_2_n] ;# MGTYRXN2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
set_property -dict {LOC K35 } [get_ports qsfp_1_tx_2_p] ;# MGTYTXP2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
set_property -dict {LOC K36 } [get_ports qsfp_1_tx_2_n] ;# MGTYTXN2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
set_property -dict {LOC J38 } [get_ports qsfp_1_rx_3_p] ;# MGTYRXP3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
set_property -dict {LOC J39 } [get_ports qsfp_1_rx_3_n] ;# MGTYRXN3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
set_property -dict {LOC H35 } [get_ports qsfp_1_tx_3_p] ;# MGTYTXP3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
set_property -dict {LOC H36 } [get_ports qsfp_1_tx_3_n] ;# MGTYTXN3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
set_property -dict {LOC R38 } [get_ports {qsfp_1_rx_p[0]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
set_property -dict {LOC R39 } [get_ports {qsfp_1_rx_n[0]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
set_property -dict {LOC P35 } [get_ports {qsfp_1_tx_p[0]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
set_property -dict {LOC P36 } [get_ports {qsfp_1_tx_n[0]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
set_property -dict {LOC N38 } [get_ports {qsfp_1_rx_p[1]}] ;# MGTYRXP1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
set_property -dict {LOC N39 } [get_ports {qsfp_1_rx_n[1]}] ;# MGTYRXN1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
set_property -dict {LOC M35 } [get_ports {qsfp_1_tx_p[1]}] ;# MGTYTXP1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
set_property -dict {LOC M36 } [get_ports {qsfp_1_tx_n[1]}] ;# MGTYTXN1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3
set_property -dict {LOC L38 } [get_ports {qsfp_1_rx_p[2]}] ;# MGTYRXP2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
set_property -dict {LOC L39 } [get_ports {qsfp_1_rx_n[2]}] ;# MGTYRXN2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
set_property -dict {LOC K35 } [get_ports {qsfp_1_tx_p[2]}] ;# MGTYTXP2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
set_property -dict {LOC K36 } [get_ports {qsfp_1_tx_n[2]}] ;# MGTYTXN2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3
set_property -dict {LOC J38 } [get_ports {qsfp_1_rx_p[3]}] ;# MGTYRXP3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
set_property -dict {LOC J39 } [get_ports {qsfp_1_rx_n[3]}] ;# MGTYRXN3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
set_property -dict {LOC H35 } [get_ports {qsfp_1_tx_p[3]}] ;# MGTYTXP3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
set_property -dict {LOC H36 } [get_ports {qsfp_1_tx_n[3]}] ;# MGTYTXN3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
set_property -dict {LOC U33 } [get_ports qsfp_1_mgt_refclk_p] ;# MGTREFCLK0P_127 from ?
set_property -dict {LOC U34 } [get_ports qsfp_1_mgt_refclk_n] ;# MGTREFCLK0N_127 from ?
set_property -dict {LOC F33 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_1_modprs_l]

1
example/ADM_PCIE_9V3/fpga_25g/fpga/Makefile
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@ -8,6 +8,7 @@ FPGA_ARCH = virtexuplus
SYN_FILES = rtl/fpga.v
SYN_FILES += rtl/fpga_core.v
SYN_FILES += rtl/eth_xcvr_phy_wrapper.v
SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v
SYN_FILES += rtl/debounce_switch.v
SYN_FILES += rtl/sync_signal.v
SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v

1
example/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile
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@ -8,6 +8,7 @@ FPGA_ARCH = virtexuplus
SYN_FILES = rtl/fpga.v
SYN_FILES += rtl/fpga_core.v
SYN_FILES += rtl/eth_xcvr_phy_wrapper.v
SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v
SYN_FILES += rtl/debounce_switch.v
SYN_FILES += rtl/sync_signal.v
SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v

395
example/ADM_PCIE_9V3/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v Normal file
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@ -0,0 +1,395 @@
/*
Copyright (c) 2023 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Transceiver and PHY quad wrapper
*/
module eth_xcvr_phy_quad_wrapper #
(
parameter COUNT = 4,
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = 2,
parameter PRBS31_ENABLE = 0,
parameter TX_SERDES_PIPELINE = 0,
parameter RX_SERDES_PIPELINE = 0,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8,
parameter COUNT_125US = 125000/6.4
)
(
input wire xcvr_ctrl_clk,
input wire xcvr_ctrl_rst,
/*
* Common
*/
output wire xcvr_gtpowergood_out,
/*
* PLL
*/
input wire xcvr_gtrefclk00_in,
/*
* Serial data
*/
output wire [COUNT-1:0] xcvr_txp,
output wire [COUNT-1:0] xcvr_txn,
input wire [COUNT-1:0] xcvr_rxp,
input wire [COUNT-1:0] xcvr_rxn,
/*
* PHY connections
*/
output wire phy_1_tx_clk,
output wire phy_1_tx_rst,
input wire [DATA_WIDTH-1:0] phy_1_xgmii_txd,
input wire [CTRL_WIDTH-1:0] phy_1_xgmii_txc,
output wire phy_1_rx_clk,
output wire phy_1_rx_rst,
output wire [DATA_WIDTH-1:0] phy_1_xgmii_rxd,
output wire [CTRL_WIDTH-1:0] phy_1_xgmii_rxc,
output wire phy_1_tx_bad_block,
output wire [6:0] phy_1_rx_error_count,
output wire phy_1_rx_bad_block,
output wire phy_1_rx_sequence_error,
output wire phy_1_rx_block_lock,
output wire phy_1_rx_high_ber,
output wire phy_1_rx_status,
input wire phy_1_cfg_tx_prbs31_enable,
input wire phy_1_cfg_rx_prbs31_enable,
output wire phy_2_tx_clk,
output wire phy_2_tx_rst,
input wire [DATA_WIDTH-1:0] phy_2_xgmii_txd,
input wire [CTRL_WIDTH-1:0] phy_2_xgmii_txc,
output wire phy_2_rx_clk,
output wire phy_2_rx_rst,
output wire [DATA_WIDTH-1:0] phy_2_xgmii_rxd,
output wire [CTRL_WIDTH-1:0] phy_2_xgmii_rxc,
output wire phy_2_tx_bad_block,
output wire [6:0] phy_2_rx_error_count,
output wire phy_2_rx_bad_block,
output wire phy_2_rx_sequence_error,
output wire phy_2_rx_block_lock,
output wire phy_2_rx_high_ber,
output wire phy_2_rx_status,
input wire phy_2_cfg_tx_prbs31_enable,
input wire phy_2_cfg_rx_prbs31_enable,
output wire phy_3_tx_clk,
output wire phy_3_tx_rst,
input wire [DATA_WIDTH-1:0] phy_3_xgmii_txd,
input wire [CTRL_WIDTH-1:0] phy_3_xgmii_txc,
output wire phy_3_rx_clk,
output wire phy_3_rx_rst,
output wire [DATA_WIDTH-1:0] phy_3_xgmii_rxd,
output wire [CTRL_WIDTH-1:0] phy_3_xgmii_rxc,
output wire phy_3_tx_bad_block,
output wire [6:0] phy_3_rx_error_count,
output wire phy_3_rx_bad_block,
output wire phy_3_rx_sequence_error,
output wire phy_3_rx_block_lock,
output wire phy_3_rx_high_ber,
output wire phy_3_rx_status,
input wire phy_3_cfg_tx_prbs31_enable,
input wire phy_3_cfg_rx_prbs31_enable,
output wire phy_4_tx_clk,
output wire phy_4_tx_rst,
input wire [DATA_WIDTH-1:0] phy_4_xgmii_txd,
input wire [CTRL_WIDTH-1:0] phy_4_xgmii_txc,
output wire phy_4_rx_clk,
output wire phy_4_rx_rst,
output wire [DATA_WIDTH-1:0] phy_4_xgmii_rxd,
output wire [CTRL_WIDTH-1:0] phy_4_xgmii_rxc,
output wire phy_4_tx_bad_block,
output wire [6:0] phy_4_rx_error_count,
output wire phy_4_rx_bad_block,
output wire phy_4_rx_sequence_error,
output wire phy_4_rx_block_lock,
output wire phy_4_rx_high_ber,
output wire phy_4_rx_status,
input wire phy_4_cfg_tx_prbs31_enable,
input wire phy_4_cfg_rx_prbs31_enable
);
generate
wire xcvr_qpll0lock;
wire xcvr_qpll0clk;
wire xcvr_qpll0refclk;
if (COUNT > 0) begin : phy1
eth_xcvr_phy_wrapper #(
.HAS_COMMON(1),
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.PRBS31_ENABLE(PRBS31_ENABLE),
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_xcvr_phy_1 (
.xcvr_ctrl_clk(xcvr_ctrl_clk),
.xcvr_ctrl_rst(xcvr_ctrl_rst),
// Common
.xcvr_gtpowergood_out(xcvr_gtpowergood_out),
// PLL out
.xcvr_gtrefclk00_in(xcvr_gtrefclk00_in),
.xcvr_qpll0lock_out(xcvr_qpll0lock),
.xcvr_qpll0clk_out(xcvr_qpll0clk),
.xcvr_qpll0refclk_out(xcvr_qpll0refclk),
// PLL in
.xcvr_qpll0lock_in(1'b0),
.xcvr_qpll0clk_in(1'b0),
.xcvr_qpll0refclk_in(1'b0),
// Serial data
.xcvr_txp(xcvr_txp[0]),
.xcvr_txn(xcvr_txn[0]),
.xcvr_rxp(xcvr_rxp[0]),
.xcvr_rxn(xcvr_rxn[0]),
// PHY connections
.phy_tx_clk(phy_1_tx_clk),
.phy_tx_rst(phy_1_tx_rst),
.phy_xgmii_txd(phy_1_xgmii_txd),
.phy_xgmii_txc(phy_1_xgmii_txc),
.phy_rx_clk(phy_1_rx_clk),
.phy_rx_rst(phy_1_rx_rst),
.phy_xgmii_rxd(phy_1_xgmii_rxd),
.phy_xgmii_rxc(phy_1_xgmii_rxc),
.phy_tx_bad_block(phy_1_tx_bad_block),
.phy_rx_error_count(phy_1_rx_error_count),
.phy_rx_bad_block(phy_1_rx_bad_block),
.phy_rx_sequence_error(phy_1_rx_sequence_error),
.phy_rx_block_lock(phy_1_rx_block_lock),
.phy_rx_high_ber(phy_1_rx_high_ber),
.phy_rx_status(phy_1_rx_status),
.phy_cfg_tx_prbs31_enable(phy_1_cfg_tx_prbs31_enable),
.phy_cfg_rx_prbs31_enable(phy_1_cfg_rx_prbs31_enable)
);
end
if (COUNT > 1) begin : phy2
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0),
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.PRBS31_ENABLE(PRBS31_ENABLE),
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_xcvr_phy_2 (
.xcvr_ctrl_clk(xcvr_ctrl_clk),
.xcvr_ctrl_rst(xcvr_ctrl_rst),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
// PLL in
.xcvr_qpll0lock_in(xcvr_qpll0lock),
.xcvr_qpll0clk_in(xcvr_qpll0clk),
.xcvr_qpll0refclk_in(xcvr_qpll0refclk),
// Serial data
.xcvr_txp(xcvr_txp[1]),
.xcvr_txn(xcvr_txn[1]),
.xcvr_rxp(xcvr_rxp[1]),
.xcvr_rxn(xcvr_rxn[1]),
// PHY connections
.phy_tx_clk(phy_2_tx_clk),
.phy_tx_rst(phy_2_tx_rst),
.phy_xgmii_txd(phy_2_xgmii_txd),
.phy_xgmii_txc(phy_2_xgmii_txc),
.phy_rx_clk(phy_2_rx_clk),
.phy_rx_rst(phy_2_rx_rst),
.phy_xgmii_rxd(phy_2_xgmii_rxd),
.phy_xgmii_rxc(phy_2_xgmii_rxc),
.phy_tx_bad_block(phy_2_tx_bad_block),
.phy_rx_error_count(phy_2_rx_error_count),
.phy_rx_bad_block(phy_2_rx_bad_block),
.phy_rx_sequence_error(phy_2_rx_sequence_error),
.phy_rx_block_lock(phy_2_rx_block_lock),
.phy_rx_high_ber(phy_2_rx_high_ber),
.phy_rx_status(phy_2_rx_status),
.phy_cfg_tx_prbs31_enable(phy_2_cfg_tx_prbs31_enable),
.phy_cfg_rx_prbs31_enable(phy_2_cfg_rx_prbs31_enable)
);
end
if (COUNT > 2) begin : phy3
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0),
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.PRBS31_ENABLE(PRBS31_ENABLE),
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_xcvr_phy_3 (
.xcvr_ctrl_clk(xcvr_ctrl_clk),
.xcvr_ctrl_rst(xcvr_ctrl_rst),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
// PLL in
.xcvr_qpll0lock_in(xcvr_qpll0lock),
.xcvr_qpll0clk_in(xcvr_qpll0clk),
.xcvr_qpll0refclk_in(xcvr_qpll0refclk),
// Serial data
.xcvr_txp(xcvr_txp[2]),
.xcvr_txn(xcvr_txn[2]),
.xcvr_rxp(xcvr_rxp[2]),
.xcvr_rxn(xcvr_rxn[2]),
// PHY connections
.phy_tx_clk(phy_3_tx_clk),
.phy_tx_rst(phy_3_tx_rst),
.phy_xgmii_txd(phy_3_xgmii_txd),
.phy_xgmii_txc(phy_3_xgmii_txc),
.phy_rx_clk(phy_3_rx_clk),
.phy_rx_rst(phy_3_rx_rst),
.phy_xgmii_rxd(phy_3_xgmii_rxd),
.phy_xgmii_rxc(phy_3_xgmii_rxc),
.phy_tx_bad_block(phy_3_tx_bad_block),
.phy_rx_error_count(phy_3_rx_error_count),
.phy_rx_bad_block(phy_3_rx_bad_block),
.phy_rx_sequence_error(phy_3_rx_sequence_error),
.phy_rx_block_lock(phy_3_rx_block_lock),
.phy_rx_high_ber(phy_3_rx_high_ber),
.phy_rx_status(phy_3_rx_status),
.phy_cfg_tx_prbs31_enable(phy_3_cfg_tx_prbs31_enable),
.phy_cfg_rx_prbs31_enable(phy_3_cfg_rx_prbs31_enable)
);
end
if (COUNT > 3) begin : phy4
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0),
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.PRBS31_ENABLE(PRBS31_ENABLE),
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_xcvr_phy_4 (
.xcvr_ctrl_clk(xcvr_ctrl_clk),
.xcvr_ctrl_rst(xcvr_ctrl_rst),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0clk_out(),
.xcvr_qpll0refclk_out(),
// PLL in
.xcvr_qpll0lock_in(xcvr_qpll0lock),
.xcvr_qpll0clk_in(xcvr_qpll0clk),
.xcvr_qpll0refclk_in(xcvr_qpll0refclk),
// Serial data
.xcvr_txp(xcvr_txp[3]),
.xcvr_txn(xcvr_txn[3]),
.xcvr_rxp(xcvr_rxp[3]),
.xcvr_rxn(xcvr_rxn[3]),
// PHY connections
.phy_tx_clk(phy_4_tx_clk),
.phy_tx_rst(phy_4_tx_rst),
.phy_xgmii_txd(phy_4_xgmii_txd),
.phy_xgmii_txc(phy_4_xgmii_txc),
.phy_rx_clk(phy_4_rx_clk),
.phy_rx_rst(phy_4_rx_rst),
.phy_xgmii_rxd(phy_4_xgmii_rxd),
.phy_xgmii_rxc(phy_4_xgmii_rxc),
.phy_tx_bad_block(phy_4_tx_bad_block),
.phy_rx_error_count(phy_4_rx_error_count),
.phy_rx_bad_block(phy_4_rx_bad_block),
.phy_rx_sequence_error(phy_4_rx_sequence_error),
.phy_rx_block_lock(phy_4_rx_block_lock),
.phy_rx_high_ber(phy_4_rx_high_ber),
.phy_rx_status(phy_4_rx_status),
.phy_cfg_tx_prbs31_enable(phy_4_cfg_tx_prbs31_enable),
.phy_cfg_rx_prbs31_enable(phy_4_cfg_rx_prbs31_enable)
);
end
endgenerate
endmodule
`resetall

18
example/ADM_PCIE_9V3/fpga_25g/rtl/eth_xcvr_phy_wrapper.v
View File

@ -1,6 +1,6 @@
/*
Copyright (c) 2021 Alex Forencich
Copyright (c) 2021-2023 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
@ -58,8 +58,8 @@ module eth_xcvr_phy_wrapper #
*/
input wire xcvr_gtrefclk00_in,
output wire xcvr_qpll0lock_out,
output wire xcvr_qpll0outclk_out,
output wire xcvr_qpll0outrefclk_out,
output wire xcvr_qpll0clk_out,
output wire xcvr_qpll0refclk_out,
/*
* PLL in
@ -94,6 +94,7 @@ module eth_xcvr_phy_wrapper #
output wire phy_rx_sequence_error,
output wire phy_rx_block_lock,
output wire phy_rx_high_ber,
output wire phy_rx_status,
input wire phy_cfg_tx_prbs31_enable,
input wire phy_cfg_rx_prbs31_enable
);
@ -128,8 +129,8 @@ if (HAS_COMMON) begin : xcvr
// PLL
.gtrefclk00_in(xcvr_gtrefclk00_in),
.qpll0lock_out(xcvr_qpll0lock_out),
.qpll0outclk_out(xcvr_qpll0outclk_out),
.qpll0outrefclk_out(xcvr_qpll0outrefclk_out),
.qpll0outclk_out(xcvr_qpll0clk_out),
.qpll0outrefclk_out(xcvr_qpll0refclk_out),
// Serial data
.gtytxp_out(xcvr_txp),
@ -174,6 +175,8 @@ if (HAS_COMMON) begin : xcvr
.rxstartofseq_out()
);
assign xcvr_qpll0reset_out = 1'b0;
end else begin : xcvr
eth_xcvr_gt_channel
@ -234,6 +237,10 @@ end else begin : xcvr
.rxstartofseq_out()
);
assign xcvr_qpll0lock_out = 1'b0;
assign xcvr_qpll0clk_out = 1'b0;
assign xcvr_qpll0refclk_out = 1'b0;
end
endgenerate
@ -290,6 +297,7 @@ phy_inst (
.rx_sequence_error(phy_rx_sequence_error),
.rx_block_lock(phy_rx_block_lock),
.rx_high_ber(phy_rx_high_ber),
.rx_status(phy_rx_status),
.cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable),
.cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable)
);

578
example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
View File

@ -49,43 +49,19 @@ module fpga (
/*
* Ethernet: QSFP28
*/
output wire qsfp_0_tx_0_p,
output wire qsfp_0_tx_0_n,
input wire qsfp_0_rx_0_p,
input wire qsfp_0_rx_0_n,
output wire qsfp_0_tx_1_p,
output wire qsfp_0_tx_1_n,
input wire qsfp_0_rx_1_p,
input wire qsfp_0_rx_1_n,
output wire qsfp_0_tx_2_p,
output wire qsfp_0_tx_2_n,
input wire qsfp_0_rx_2_p,
input wire qsfp_0_rx_2_n,
output wire qsfp_0_tx_3_p,
output wire qsfp_0_tx_3_n,
input wire qsfp_0_rx_3_p,
input wire qsfp_0_rx_3_n,
output wire [3:0] qsfp_0_tx_p,
output wire [3:0] qsfp_0_tx_n,
input wire [3:0] qsfp_0_rx_p,
input wire [3:0] qsfp_0_rx_n,
input wire qsfp_0_mgt_refclk_p,
input wire qsfp_0_mgt_refclk_n,
input wire qsfp_0_modprs_l,
output wire qsfp_0_sel_l,
output wire qsfp_1_tx_0_p,
output wire qsfp_1_tx_0_n,
input wire qsfp_1_rx_0_p,
input wire qsfp_1_rx_0_n,
output wire qsfp_1_tx_1_p,
output wire qsfp_1_tx_1_n,
input wire qsfp_1_rx_1_p,
input wire qsfp_1_rx_1_n,
output wire qsfp_1_tx_2_p,
output wire qsfp_1_tx_2_n,
input wire qsfp_1_rx_2_p,
input wire qsfp_1_rx_2_n,
output wire qsfp_1_tx_3_p,
output wire qsfp_1_tx_3_n,
input wire qsfp_1_rx_3_p,
input wire qsfp_1_rx_3_n,
output wire [3:0] qsfp_1_tx_p,
output wire [3:0] qsfp_1_tx_n,
input wire [3:0] qsfp_1_rx_p,
input wire [3:0] qsfp_1_rx_n,
input wire qsfp_1_mgt_refclk_p,
input wire qsfp_1_mgt_refclk_n,
input wire qsfp_1_modprs_l,
@ -268,208 +244,103 @@ IBUFDS_GTE4 ibufds_gte4_qsfp_0_mgt_refclk_inst (
.ODIV2 ()
);
wire qsfp_0_qpll0lock;
wire qsfp_0_qpll0outclk;
wire qsfp_0_qpll0outrefclk;
eth_xcvr_phy_wrapper #(
.HAS_COMMON(1),
eth_xcvr_phy_quad_wrapper #(
.TX_SERDES_PIPELINE(2),
.RX_SERDES_PIPELINE(2),
.COUNT_125US(125000/2.56)
)
qsfp_0_phy_0_inst (
qsfp_0_phy_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
/*
* Common
*/
.xcvr_gtpowergood_out(),
// PLL out
/*
* PLL
*/
.xcvr_gtrefclk00_in(qsfp_0_mgt_refclk),
.xcvr_qpll0lock_out(qsfp_0_qpll0lock),
.xcvr_qpll0outclk_out(qsfp_0_qpll0outclk),
.xcvr_qpll0outrefclk_out(qsfp_0_qpll0outrefclk),
// PLL in
.xcvr_qpll0lock_in(1'b0),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(1'b0),
.xcvr_qpll0refclk_in(1'b0),
/*
* Serial data
*/
.xcvr_txp(qsfp_0_tx_p),
.xcvr_txn(qsfp_0_tx_n),
.xcvr_rxp(qsfp_0_rx_p),
.xcvr_rxn(qsfp_0_rx_n),
// Serial data
.xcvr_txp(qsfp_0_tx_0_p),
.xcvr_txn(qsfp_0_tx_0_n),
.xcvr_rxp(qsfp_0_rx_0_p),
.xcvr_rxn(qsfp_0_rx_0_n),
/*
* PHY connections
*/
.phy_1_tx_clk(qsfp_0_tx_clk_0_int),
.phy_1_tx_rst(qsfp_0_tx_rst_0_int),
.phy_1_xgmii_txd(qsfp_0_txd_0_int),
.phy_1_xgmii_txc(qsfp_0_txc_0_int),
.phy_1_rx_clk(qsfp_0_rx_clk_0_int),
.phy_1_rx_rst(qsfp_0_rx_rst_0_int),
.phy_1_xgmii_rxd(qsfp_0_rxd_0_int),
.phy_1_xgmii_rxc(qsfp_0_rxc_0_int),
.phy_1_tx_bad_block(),
.phy_1_rx_error_count(),
.phy_1_rx_bad_block(),
.phy_1_rx_sequence_error(),
.phy_1_rx_block_lock(qsfp_0_rx_block_lock_0),
.phy_1_rx_status(),
.phy_1_cfg_tx_prbs31_enable(1'b0),
.phy_1_cfg_rx_prbs31_enable(1'b0),
// PHY connections
.phy_tx_clk(qsfp_0_tx_clk_0_int),
.phy_tx_rst(qsfp_0_tx_rst_0_int),
.phy_xgmii_txd(qsfp_0_txd_0_int),
.phy_xgmii_txc(qsfp_0_txc_0_int),
.phy_rx_clk(qsfp_0_rx_clk_0_int),
.phy_rx_rst(qsfp_0_rx_rst_0_int),
.phy_xgmii_rxd(qsfp_0_rxd_0_int),
.phy_xgmii_rxc(qsfp_0_rxc_0_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_0_rx_block_lock_0),
.phy_rx_high_ber(),
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
.phy_2_tx_clk(qsfp_0_tx_clk_1_int),
.phy_2_tx_rst(qsfp_0_tx_rst_1_int),
.phy_2_xgmii_txd(qsfp_0_txd_1_int),
.phy_2_xgmii_txc(qsfp_0_txc_1_int),
.phy_2_rx_clk(qsfp_0_rx_clk_1_int),
.phy_2_rx_rst(qsfp_0_rx_rst_1_int),
.phy_2_xgmii_rxd(qsfp_0_rxd_1_int),
.phy_2_xgmii_rxc(qsfp_0_rxc_1_int),
.phy_2_tx_bad_block(),
.phy_2_rx_error_count(),
.phy_2_rx_bad_block(),
.phy_2_rx_sequence_error(),
.phy_2_rx_block_lock(qsfp_0_rx_block_lock_1),
.phy_2_rx_status(),
.phy_2_cfg_tx_prbs31_enable(1'b0),
.phy_2_cfg_rx_prbs31_enable(1'b0),
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0),
.TX_SERDES_PIPELINE(2),
.RX_SERDES_PIPELINE(2),
.COUNT_125US(125000/2.56)
)
qsfp_0_phy_1_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
.phy_3_tx_clk(qsfp_0_tx_clk_2_int),
.phy_3_tx_rst(qsfp_0_tx_rst_2_int),
.phy_3_xgmii_txd(qsfp_0_txd_2_int),
.phy_3_xgmii_txc(qsfp_0_txc_2_int),
.phy_3_rx_clk(qsfp_0_rx_clk_2_int),
.phy_3_rx_rst(qsfp_0_rx_rst_2_int),
.phy_3_xgmii_rxd(qsfp_0_rxd_2_int),
.phy_3_xgmii_rxc(qsfp_0_rxc_2_int),
.phy_3_tx_bad_block(),
.phy_3_rx_error_count(),
.phy_3_rx_bad_block(),
.phy_3_rx_sequence_error(),
.phy_3_rx_block_lock(qsfp_0_rx_block_lock_2),
.phy_3_rx_status(),
.phy_3_cfg_tx_prbs31_enable(1'b0),
.phy_3_cfg_rx_prbs31_enable(1'b0),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp_0_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp_0_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp_0_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp_0_tx_1_p),
.xcvr_txn(qsfp_0_tx_1_n),
.xcvr_rxp(qsfp_0_rx_1_p),
.xcvr_rxn(qsfp_0_rx_1_n),
// PHY connections
.phy_tx_clk(qsfp_0_tx_clk_1_int),
.phy_tx_rst(qsfp_0_tx_rst_1_int),
.phy_xgmii_txd(qsfp_0_txd_1_int),
.phy_xgmii_txc(qsfp_0_txc_1_int),
.phy_rx_clk(qsfp_0_rx_clk_1_int),
.phy_rx_rst(qsfp_0_rx_rst_1_int),
.phy_xgmii_rxd(qsfp_0_rxd_1_int),
.phy_xgmii_rxc(qsfp_0_rxc_1_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_0_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0),
.TX_SERDES_PIPELINE(2),
.RX_SERDES_PIPELINE(2),
.COUNT_125US(125000/2.56)
)
qsfp_0_phy_2_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp_0_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp_0_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp_0_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp_0_tx_2_p),
.xcvr_txn(qsfp_0_tx_2_n),
.xcvr_rxp(qsfp_0_rx_2_p),
.xcvr_rxn(qsfp_0_rx_2_n),
// PHY connections
.phy_tx_clk(qsfp_0_tx_clk_2_int),
.phy_tx_rst(qsfp_0_tx_rst_2_int),
.phy_xgmii_txd(qsfp_0_txd_2_int),
.phy_xgmii_txc(qsfp_0_txc_2_int),
.phy_rx_clk(qsfp_0_rx_clk_2_int),
.phy_rx_rst(qsfp_0_rx_rst_2_int),
.phy_xgmii_rxd(qsfp_0_rxd_2_int),
.phy_xgmii_rxc(qsfp_0_rxc_2_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_0_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0),
.TX_SERDES_PIPELINE(2),
.RX_SERDES_PIPELINE(2),
.COUNT_125US(125000/2.56)
)
qsfp_0_phy_3_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp_0_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp_0_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp_0_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp_0_tx_3_p),
.xcvr_txn(qsfp_0_tx_3_n),
.xcvr_rxp(qsfp_0_rx_3_p),
.xcvr_rxn(qsfp_0_rx_3_n),
// PHY connections
.phy_tx_clk(qsfp_0_tx_clk_3_int),
.phy_tx_rst(qsfp_0_tx_rst_3_int),
.phy_xgmii_txd(qsfp_0_txd_3_int),
.phy_xgmii_txc(qsfp_0_txc_3_int),
.phy_rx_clk(qsfp_0_rx_clk_3_int),
.phy_rx_rst(qsfp_0_rx_rst_3_int),
.phy_xgmii_rxd(qsfp_0_rxd_3_int),
.phy_xgmii_rxc(qsfp_0_rxc_3_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_0_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
.phy_4_tx_clk(qsfp_0_tx_clk_3_int),
.phy_4_tx_rst(qsfp_0_tx_rst_3_int),
.phy_4_xgmii_txd(qsfp_0_txd_3_int),
.phy_4_xgmii_txc(qsfp_0_txc_3_int),
.phy_4_rx_clk(qsfp_0_rx_clk_3_int),
.phy_4_rx_rst(qsfp_0_rx_rst_3_int),
.phy_4_xgmii_rxd(qsfp_0_rxd_3_int),
.phy_4_xgmii_rxc(qsfp_0_rxc_3_int),
.phy_4_tx_bad_block(),
.phy_4_rx_error_count(),
.phy_4_rx_bad_block(),
.phy_4_rx_sequence_error(),
.phy_4_rx_block_lock(qsfp_0_rx_block_lock_3),
.phy_4_rx_status(),
.phy_4_cfg_tx_prbs31_enable(1'b0),
.phy_4_cfg_rx_prbs31_enable(1'b0)
);
// QSFP 1
@ -523,208 +394,103 @@ IBUFDS_GTE4 ibufds_gte4_qsfp_1_mgt_refclk_inst (
.ODIV2 ()
);
wire qsfp_1_qpll0lock;
wire qsfp_1_qpll0outclk;
wire qsfp_1_qpll0outrefclk;
eth_xcvr_phy_wrapper #(
.HAS_COMMON(1),
eth_xcvr_phy_quad_wrapper #(
.TX_SERDES_PIPELINE(2),
.RX_SERDES_PIPELINE(2),
.COUNT_125US(125000/2.56)
)
qsfp_1_phy_0_inst (
qsfp_1_phy_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
/*
* Common
*/
.xcvr_gtpowergood_out(),
// PLL out
/*
* PLL
*/
.xcvr_gtrefclk00_in(qsfp_1_mgt_refclk),
.xcvr_qpll0lock_out(qsfp_1_qpll0lock),
.xcvr_qpll0outclk_out(qsfp_1_qpll0outclk),
.xcvr_qpll0outrefclk_out(qsfp_1_qpll0outrefclk),
// PLL in
.xcvr_qpll0lock_in(1'b0),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(1'b0),
.xcvr_qpll0refclk_in(1'b0),
/*
* Serial data
*/
.xcvr_txp(qsfp_1_tx_p),
.xcvr_txn(qsfp_1_tx_n),
.xcvr_rxp(qsfp_1_rx_p),
.xcvr_rxn(qsfp_1_rx_n),
// Serial data
.xcvr_txp(qsfp_1_tx_0_p),
.xcvr_txn(qsfp_1_tx_0_n),
.xcvr_rxp(qsfp_1_rx_0_p),
.xcvr_rxn(qsfp_1_rx_0_n),
/*
* PHY connections
*/
.phy_1_tx_clk(qsfp_1_tx_clk_0_int),
.phy_1_tx_rst(qsfp_1_tx_rst_0_int),
.phy_1_xgmii_txd(qsfp_1_txd_0_int),
.phy_1_xgmii_txc(qsfp_1_txc_0_int),
.phy_1_rx_clk(qsfp_1_rx_clk_0_int),
.phy_1_rx_rst(qsfp_1_rx_rst_0_int),
.phy_1_xgmii_rxd(qsfp_1_rxd_0_int),
.phy_1_xgmii_rxc(qsfp_1_rxc_0_int),
.phy_1_tx_bad_block(),
.phy_1_rx_error_count(),
.phy_1_rx_bad_block(),
.phy_1_rx_sequence_error(),
.phy_1_rx_block_lock(qsfp_1_rx_block_lock_0),
.phy_1_rx_status(),
.phy_1_cfg_tx_prbs31_enable(1'b0),
.phy_1_cfg_rx_prbs31_enable(1'b0),
// PHY connections
.phy_tx_clk(qsfp_1_tx_clk_0_int),
.phy_tx_rst(qsfp_1_tx_rst_0_int),
.phy_xgmii_txd(qsfp_1_txd_0_int),
.phy_xgmii_txc(qsfp_1_txc_0_int),
.phy_rx_clk(qsfp_1_rx_clk_0_int),
.phy_rx_rst(qsfp_1_rx_rst_0_int),
.phy_xgmii_rxd(qsfp_1_rxd_0_int),
.phy_xgmii_rxc(qsfp_1_rxc_0_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_1_rx_block_lock_0),
.phy_rx_high_ber(),
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
.phy_2_tx_clk(qsfp_1_tx_clk_1_int),
.phy_2_tx_rst(qsfp_1_tx_rst_1_int),
.phy_2_xgmii_txd(qsfp_1_txd_1_int),
.phy_2_xgmii_txc(qsfp_1_txc_1_int),
.phy_2_rx_clk(qsfp_1_rx_clk_1_int),
.phy_2_rx_rst(qsfp_1_rx_rst_1_int),
.phy_2_xgmii_rxd(qsfp_1_rxd_1_int),
.phy_2_xgmii_rxc(qsfp_1_rxc_1_int),
.phy_2_tx_bad_block(),
.phy_2_rx_error_count(),
.phy_2_rx_bad_block(),
.phy_2_rx_sequence_error(),
.phy_2_rx_block_lock(qsfp_1_rx_block_lock_1),
.phy_2_rx_status(),
.phy_2_cfg_tx_prbs31_enable(1'b0),
.phy_2_cfg_rx_prbs31_enable(1'b0),
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0),
.TX_SERDES_PIPELINE(2),
.RX_SERDES_PIPELINE(2),
.COUNT_125US(125000/2.56)
)
qsfp_1_phy_1_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
.phy_3_tx_clk(qsfp_1_tx_clk_2_int),
.phy_3_tx_rst(qsfp_1_tx_rst_2_int),
.phy_3_xgmii_txd(qsfp_1_txd_2_int),
.phy_3_xgmii_txc(qsfp_1_txc_2_int),
.phy_3_rx_clk(qsfp_1_rx_clk_2_int),
.phy_3_rx_rst(qsfp_1_rx_rst_2_int),
.phy_3_xgmii_rxd(qsfp_1_rxd_2_int),
.phy_3_xgmii_rxc(qsfp_1_rxc_2_int),
.phy_3_tx_bad_block(),
.phy_3_rx_error_count(),
.phy_3_rx_bad_block(),
.phy_3_rx_sequence_error(),
.phy_3_rx_block_lock(qsfp_1_rx_block_lock_2),
.phy_3_rx_status(),
.phy_3_cfg_tx_prbs31_enable(1'b0),
.phy_3_cfg_rx_prbs31_enable(1'b0),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp_1_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp_1_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp_1_tx_1_p),
.xcvr_txn(qsfp_1_tx_1_n),
.xcvr_rxp(qsfp_1_rx_1_p),
.xcvr_rxn(qsfp_1_rx_1_n),
// PHY connections
.phy_tx_clk(qsfp_1_tx_clk_1_int),
.phy_tx_rst(qsfp_1_tx_rst_1_int),
.phy_xgmii_txd(qsfp_1_txd_1_int),
.phy_xgmii_txc(qsfp_1_txc_1_int),
.phy_rx_clk(qsfp_1_rx_clk_1_int),
.phy_rx_rst(qsfp_1_rx_rst_1_int),
.phy_xgmii_rxd(qsfp_1_rxd_1_int),
.phy_xgmii_rxc(qsfp_1_rxc_1_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_1_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0),
.TX_SERDES_PIPELINE(2),
.RX_SERDES_PIPELINE(2),
.COUNT_125US(125000/2.56)
)
qsfp_1_phy_2_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp_1_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp_1_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp_1_tx_2_p),
.xcvr_txn(qsfp_1_tx_2_n),
.xcvr_rxp(qsfp_1_rx_2_p),
.xcvr_rxn(qsfp_1_rx_2_n),
// PHY connections
.phy_tx_clk(qsfp_1_tx_clk_2_int),
.phy_tx_rst(qsfp_1_tx_rst_2_int),
.phy_xgmii_txd(qsfp_1_txd_2_int),
.phy_xgmii_txc(qsfp_1_txc_2_int),
.phy_rx_clk(qsfp_1_rx_clk_2_int),
.phy_rx_rst(qsfp_1_rx_rst_2_int),
.phy_xgmii_rxd(qsfp_1_rxd_2_int),
.phy_xgmii_rxc(qsfp_1_rxc_2_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_1_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0),
.TX_SERDES_PIPELINE(2),
.RX_SERDES_PIPELINE(2),
.COUNT_125US(125000/2.56)
)
qsfp_1_phy_3_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp_1_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp_1_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp_1_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp_1_tx_3_p),
.xcvr_txn(qsfp_1_tx_3_n),
.xcvr_rxp(qsfp_1_rx_3_p),
.xcvr_rxn(qsfp_1_rx_3_n),
// PHY connections
.phy_tx_clk(qsfp_1_tx_clk_3_int),
.phy_tx_rst(qsfp_1_tx_rst_3_int),
.phy_xgmii_txd(qsfp_1_txd_3_int),
.phy_xgmii_txc(qsfp_1_txc_3_int),
.phy_rx_clk(qsfp_1_rx_clk_3_int),
.phy_rx_rst(qsfp_1_rx_rst_3_int),
.phy_xgmii_rxd(qsfp_1_rxd_3_int),
.phy_xgmii_rxc(qsfp_1_rxc_3_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp_1_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_cfg_tx_prbs31_enable(1'b0),
.phy_cfg_rx_prbs31_enable(1'b0)
.phy_4_tx_clk(qsfp_1_tx_clk_3_int),
.phy_4_tx_rst(qsfp_1_tx_rst_3_int),
.phy_4_xgmii_txd(qsfp_1_txd_3_int),
.phy_4_xgmii_txc(qsfp_1_txc_3_int),
.phy_4_rx_clk(qsfp_1_rx_clk_3_int),
.phy_4_rx_rst(qsfp_1_rx_rst_3_int),
.phy_4_xgmii_rxd(qsfp_1_rxd_3_int),
.phy_4_xgmii_rxc(qsfp_1_rxc_3_int),
.phy_4_tx_bad_block(),
.phy_4_rx_error_count(),
.phy_4_rx_bad_block(),
.phy_4_rx_sequence_error(),
.phy_4_rx_block_lock(qsfp_1_rx_block_lock_3),
.phy_4_rx_status(),
.phy_4_cfg_tx_prbs31_enable(1'b0),
.phy_4_cfg_rx_prbs31_enable(1'b0)
);
assign front_led[0] = qsfp_0_rx_block_lock_0;