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Add switch testbenches
This commit is contained in:
Alex Forencich
parent
34d5a4fed5
commit
5d9c982cd4
134
tb/axis_ram_switch/Makefile
Normal file
134
tb/axis_ram_switch/Makefile
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@ -0,0 +1,134 @@
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# Copyright (c) 2021 Alex Forencich
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
# copies of the Software, and to permit persons to whom the Software is
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||||
# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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# THE SOFTWARE.
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TOPLEVEL_LANG = verilog
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SIM ?= icarus
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WAVES ?= 0
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COCOTB_HDL_TIMEUNIT = 1ns
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COCOTB_HDL_TIMEPRECISION = 1ps
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export PARAM_S_COUNT ?= 4
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export PARAM_M_COUNT ?= 4
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DUT = axis_ram_switch
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WRAPPER = $(DUT)_wrap_$(PARAM_S_COUNT)x$(PARAM_M_COUNT)
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TOPLEVEL = $(WRAPPER)
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MODULE = test_$(DUT)
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VERILOG_SOURCES += $(WRAPPER).v
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VERILOG_SOURCES += ../../rtl/$(DUT).v
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VERILOG_SOURCES += ../../rtl/axis_adapter.v
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VERILOG_SOURCES += ../../rtl/arbiter.v
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VERILOG_SOURCES += ../../rtl/priority_encoder.v
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# module parameters
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export PARAM_FIFO_DEPTH ?= 4096
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export PARAM_CMD_FIFO_DEPTH ?= 32
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export PARAM_SPEEDUP ?= 0
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export PARAM_S_DATA_WIDTH ?= 8
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export PARAM_S_KEEP_ENABLE ?= $(shell expr $(PARAM_S_DATA_WIDTH) \> 8 )
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export PARAM_S_KEEP_WIDTH ?= $(shell expr $(PARAM_S_DATA_WIDTH) / 8 )
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export PARAM_M_DATA_WIDTH ?= 8
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export PARAM_M_KEEP_ENABLE ?= $(shell expr $(PARAM_M_DATA_WIDTH) \> 8 )
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export PARAM_M_KEEP_WIDTH ?= $(shell expr $(PARAM_M_DATA_WIDTH) / 8 )
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export PARAM_ID_ENABLE ?= 1
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export PARAM_ID_WIDTH ?= 16
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export PARAM_DEST_WIDTH ?= 8
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export PARAM_USER_ENABLE ?= 1
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export PARAM_USER_WIDTH ?= 1
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export PARAM_USER_BAD_FRAME_VALUE ?= 1
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export PARAM_USER_BAD_FRAME_MASK ?= 1
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export PARAM_DROP_BAD_FRAME ?= 0
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export PARAM_DROP_WHEN_FULL ?= 0
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export PARAM_RAM_PIPELINE ?= 2
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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COMPILE_ARGS += -P $(TOPLEVEL).FIFO_DEPTH=$(PARAM_FIFO_DEPTH)
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COMPILE_ARGS += -P $(TOPLEVEL).CMD_FIFO_DEPTH=$(PARAM_CMD_FIFO_DEPTH)
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COMPILE_ARGS += -P $(TOPLEVEL).SPEEDUP=$(PARAM_SPEEDUP)
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COMPILE_ARGS += -P $(TOPLEVEL).S_DATA_WIDTH=$(PARAM_S_DATA_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).S_KEEP_ENABLE=$(PARAM_S_KEEP_ENABLE)
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COMPILE_ARGS += -P $(TOPLEVEL).S_KEEP_WIDTH=$(PARAM_S_KEEP_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).M_DATA_WIDTH=$(PARAM_M_DATA_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).M_KEEP_ENABLE=$(PARAM_M_KEEP_ENABLE)
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COMPILE_ARGS += -P $(TOPLEVEL).M_KEEP_WIDTH=$(PARAM_M_KEEP_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).ID_ENABLE=$(PARAM_ID_ENABLE)
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COMPILE_ARGS += -P $(TOPLEVEL).ID_WIDTH=$(PARAM_ID_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).DEST_WIDTH=$(PARAM_DEST_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE)
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COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH)
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COMPILE_ARGS += -P $(TOPLEVEL).USER_BAD_FRAME_VALUE=$(PARAM_USER_BAD_FRAME_VALUE)
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COMPILE_ARGS += -P $(TOPLEVEL).USER_BAD_FRAME_MASK=$(PARAM_USER_BAD_FRAME_MASK)
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COMPILE_ARGS += -P $(TOPLEVEL).DROP_BAD_FRAME=$(PARAM_DROP_BAD_FRAME)
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COMPILE_ARGS += -P $(TOPLEVEL).DROP_WHEN_FULL=$(PARAM_DROP_WHEN_FULL)
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COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE)
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ifeq ($(WAVES), 1)
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VERILOG_SOURCES += iverilog_dump.v
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COMPILE_ARGS += -s iverilog_dump
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endif
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else ifeq ($(SIM), verilator)
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COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
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COMPILE_ARGS += -GFIFO_DEPTH=$(PARAM_FIFO_DEPTH)
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COMPILE_ARGS += -GCMD_FIFO_DEPTH=$(PARAM_CMD_FIFO_DEPTH)
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COMPILE_ARGS += -GSPEEDUP=$(PARAM_SPEEDUP)
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COMPILE_ARGS += -GS_DATA_WIDTH=$(PARAM_S_DATA_WIDTH)
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COMPILE_ARGS += -GS_KEEP_ENABLE=$(PARAM_S_KEEP_ENABLE)
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COMPILE_ARGS += -GS_KEEP_WIDTH=$(PARAM_S_KEEP_WIDTH)
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COMPILE_ARGS += -GM_DATA_WIDTH=$(PARAM_M_DATA_WIDTH)
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COMPILE_ARGS += -GM_KEEP_ENABLE=$(PARAM_M_KEEP_ENABLE)
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COMPILE_ARGS += -GM_KEEP_WIDTH=$(PARAM_M_KEEP_WIDTH)
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COMPILE_ARGS += -GID_ENABLE=$(PARAM_ID_ENABLE)
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COMPILE_ARGS += -GID_WIDTH=$(PARAM_ID_WIDTH)
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COMPILE_ARGS += -GDEST_WIDTH=$(PARAM_DEST_WIDTH)
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COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE)
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COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH)
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COMPILE_ARGS += -GUSER_BAD_FRAME_VALUE=$(PARAM_USER_BAD_FRAME_VALUE)
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COMPILE_ARGS += -GUSER_BAD_FRAME_MASK=$(PARAM_USER_BAD_FRAME_MASK)
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COMPILE_ARGS += -GDROP_BAD_FRAME=$(PARAM_DROP_BAD_FRAME)
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COMPILE_ARGS += -GDROP_WHEN_FULL=$(PARAM_DROP_WHEN_FULL)
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COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE)
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ifeq ($(WAVES), 1)
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COMPILE_ARGS += --trace-fst
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endif
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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$(WRAPPER).v: ../../rtl/$(DUT)_wrap.py
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$< -p $(PARAM_S_COUNT) $(PARAM_M_COUNT)
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iverilog_dump.v:
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echo 'module iverilog_dump();' > $@
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echo 'initial begin' >> $@
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echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@
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echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@
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echo 'end' >> $@
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echo 'endmodule' >> $@
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clean::
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@rm -rf iverilog_dump.v
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@rm -rf dump.fst $(TOPLEVEL).fst
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@rm -rf *_wrap_*.v
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361
tb/axis_ram_switch/test_axis_ram_switch.py
Normal file
361
tb/axis_ram_switch/test_axis_ram_switch.py
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@ -0,0 +1,361 @@
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#!/usr/bin/env python
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"""
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Copyright (c) 2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
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all copies or substantial portions of the Software.
|
||||
|
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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import itertools
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import logging
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import os
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import random
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import subprocess
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import cocotb_test.simulator
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import pytest
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge, Event
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from cocotb.regression import TestFactory
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from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
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class TB(object):
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def __init__(self, dut):
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self.dut = dut
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s_count = len(dut.axis_ram_switch_inst.s_axis_tvalid)
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m_count = len(dut.axis_ram_switch_inst.m_axis_tvalid)
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self.log = logging.getLogger("cocotb.tb")
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self.log.setLevel(logging.DEBUG)
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cocotb.fork(Clock(dut.clk, 10, units="ns").start())
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self.source = [AxiStreamSource(AxiStreamBus.from_prefix(dut, f"s{k:02d}_axis"), dut.clk, dut.rst) for k in range(s_count)]
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self.sink = [AxiStreamSink(AxiStreamBus.from_prefix(dut, f"m{k:02d}_axis"), dut.clk, dut.rst) for k in range(m_count)]
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def set_idle_generator(self, generator=None):
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if generator:
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for source in self.source:
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source.set_pause_generator(generator())
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def set_backpressure_generator(self, generator=None):
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if generator:
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for sink in self.sink:
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sink.set_pause_generator(generator())
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async def reset(self):
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self.dut.rst.setimmediatevalue(0)
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst <= 1
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst <= 0
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None, s=0, m=0):
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tb = TB(dut)
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id_count = 2**len(tb.source[s].bus.tid)
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cur_id = 1
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await tb.reset()
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tb.set_idle_generator(idle_inserter)
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tb.set_backpressure_generator(backpressure_inserter)
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test_frames = []
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for test_data in [payload_data(x) for x in payload_lengths()]:
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test_frame = AxiStreamFrame(test_data)
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test_frame.tid = cur_id
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test_frame.tdest = m
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test_frames.append(test_frame)
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await tb.source[s].send(test_frame)
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cur_id = (cur_id + 1) % id_count
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for test_frame in test_frames:
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rx_frame = await tb.sink[m].recv()
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assert rx_frame.tdata == test_frame.tdata
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assert rx_frame.tid == test_frame.tid
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assert rx_frame.tdest == test_frame.tdest
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assert not rx_frame.tuser
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assert all(s.empty() for s in tb.sink)
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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async def run_test_tuser_assert(dut, s=0, m=0):
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tb = TB(dut)
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await tb.reset()
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test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
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test_frame = AxiStreamFrame(test_data, tuser=1, tdest=m)
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await tb.source[s].send(test_frame)
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rx_frame = await tb.sink[m].recv()
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assert rx_frame.tdata == test_data
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assert rx_frame.tuser
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assert all(s.empty() for s in tb.sink)
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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async def run_arb_test(dut):
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tb = TB(dut)
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byte_lanes = max(tb.source[0].byte_lanes, tb.sink[0].byte_lanes)
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id_count = 2**len(tb.source[0].bus.tid)
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cur_id = 1
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await tb.reset()
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test_frames = []
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length = byte_lanes*16
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test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
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for k in range(5):
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test_frame = AxiStreamFrame(test_data, tx_complete=Event())
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test_frame.tid = cur_id
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test_frame.tdest = 0
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src_ind = 0
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if k == 0:
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src_ind = 0
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elif k == 4:
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await test_frames[1].tx_complete.wait()
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for j in range(8):
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await RisingEdge(dut.clk)
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src_ind = 0
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else:
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src_ind = 1
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test_frames.append(test_frame)
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await tb.source[src_ind].send(test_frame)
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cur_id = (cur_id + 1) % id_count
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for k in [0, 1, 2, 4, 3]:
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test_frame = test_frames[k]
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rx_frame = await tb.sink[0].recv()
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assert rx_frame.tdata == test_frame.tdata
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assert rx_frame.tid == test_frame.tid
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assert rx_frame.tdest == test_frame.tdest
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assert not rx_frame.tuser
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assert all(s.empty() for s in tb.sink)
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
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tb = TB(dut)
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byte_lanes = max(tb.source[0].byte_lanes, tb.sink[0].byte_lanes)
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id_count = 2**len(tb.source[0].bus.tid)
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cur_id = 1
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await tb.reset()
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tb.set_idle_generator(idle_inserter)
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tb.set_backpressure_generator(backpressure_inserter)
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test_frames = [[list() for y in tb.sink] for x in tb.source]
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for p in range(len(tb.source)):
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for k in range(128):
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length = random.randint(1, byte_lanes*16)
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test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
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test_frame = AxiStreamFrame(test_data)
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test_frame.tid = cur_id
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test_frame.tdest = random.randrange(len(tb.sink))
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test_frames[p][test_frame.tdest].append(test_frame)
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await tb.source[p].send(test_frame)
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cur_id = (cur_id + 1) % id_count
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for lst in test_frames:
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while any(lst):
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rx_frame = await tb.sink[[x for x in lst if x][0][0].tdest].recv()
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test_frame = None
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for lst_a in test_frames:
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for lst_b in lst_a:
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if lst_b and lst_b[0].tid == rx_frame.tid:
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test_frame = lst_b.pop(0)
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break
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assert test_frame is not None
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assert rx_frame.tdata == test_frame.tdata
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assert rx_frame.tid == test_frame.tid
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assert rx_frame.tdest == test_frame.tdest
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assert not rx_frame.tuser
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assert all(s.empty() for s in tb.sink)
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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def cycle_pause():
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return itertools.cycle([1, 1, 1, 0])
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def size_list():
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data_width = max(len(cocotb.top.s00_axis_tdata), len(cocotb.top.m00_axis_tdata))
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byte_width = data_width // 8
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return list(range(1, byte_width*4+1))+[512]+[1]*64
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def incrementing_payload(length):
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return bytearray(itertools.islice(itertools.cycle(range(256)), length))
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if cocotb.SIM_NAME:
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s_count = len(cocotb.top.axis_ram_switch_inst.s_axis_tvalid)
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m_count = len(cocotb.top.axis_ram_switch_inst.m_axis_tvalid)
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factory = TestFactory(run_test)
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factory.add_option("payload_lengths", [size_list])
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factory.add_option("payload_data", [incrementing_payload])
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factory.add_option("idle_inserter", [None, cycle_pause])
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factory.add_option("backpressure_inserter", [None, cycle_pause])
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factory.add_option("s", range(min(s_count, 2)))
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factory.add_option("m", range(min(m_count, 2)))
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factory.generate_tests()
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for test in [run_test_tuser_assert]:
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factory = TestFactory(test)
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factory.add_option("s", range(min(s_count, 2)))
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factory.add_option("m", range(min(m_count, 2)))
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factory.generate_tests()
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if s_count > 1:
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factory = TestFactory(run_arb_test)
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factory.generate_tests()
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factory = TestFactory(run_stress_test)
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factory.add_option("idle_inserter", [None, cycle_pause])
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factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
|
||||
|
||||
@pytest.mark.parametrize("m_data_width", [8, 32])
|
||||
@pytest.mark.parametrize("s_data_width", [8, 32])
|
||||
@pytest.mark.parametrize("m_count", [1, 4])
|
||||
@pytest.mark.parametrize("s_count", [1, 4])
|
||||
def test_axis_ram_switch(request, s_count, m_count, s_data_width, m_data_width):
|
||||
dut = "axis_ram_switch"
|
||||
wrapper = f"{dut}_wrap_{s_count}x{m_count}"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = wrapper
|
||||
|
||||
# generate wrapper
|
||||
wrapper_file = os.path.join(tests_dir, f"{wrapper}.v")
|
||||
if not os.path.exists(wrapper_file):
|
||||
subprocess.Popen(
|
||||
[os.path.join(rtl_dir, f"{dut}_wrap.py"), "-p", f"{s_count}", f"{m_count}"],
|
||||
cwd=tests_dir
|
||||
).wait()
|
||||
|
||||
verilog_sources = [
|
||||
wrapper_file,
|
||||
os.path.join(rtl_dir, f"{dut}.v"),
|
||||
os.path.join(rtl_dir, "axis_adapter.v"),
|
||||
os.path.join(rtl_dir, "arbiter.v"),
|
||||
os.path.join(rtl_dir, "priority_encoder.v"),
|
||||
]
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['S_COUNT'] = s_count
|
||||
parameters['M_COUNT'] = m_count
|
||||
|
||||
parameters['FIFO_DEPTH'] = 4096
|
||||
parameters['CMD_FIFO_DEPTH'] = 32
|
||||
parameters['SPEEDUP'] = 0
|
||||
parameters['S_DATA_WIDTH'] = s_data_width
|
||||
parameters['S_KEEP_ENABLE'] = int(parameters['S_DATA_WIDTH'] > 8)
|
||||
parameters['S_KEEP_WIDTH'] = parameters['S_DATA_WIDTH'] // 8
|
||||
parameters['M_DATA_WIDTH'] = m_data_width
|
||||
parameters['M_KEEP_ENABLE'] = int(parameters['M_DATA_WIDTH'] > 8)
|
||||
parameters['M_KEEP_WIDTH'] = parameters['M_DATA_WIDTH'] // 8
|
||||
parameters['ID_ENABLE'] = 1
|
||||
parameters['ID_WIDTH'] = 16
|
||||
parameters['DEST_WIDTH'] = 8
|
||||
parameters['USER_ENABLE'] = 1
|
||||
parameters['USER_WIDTH'] = 1
|
||||
parameters['USER_BAD_FRAME_VALUE'] = 1
|
||||
parameters['USER_BAD_FRAME_MASK'] = 1
|
||||
parameters['DROP_BAD_FRAME'] = 0
|
||||
parameters['DROP_WHEN_FULL'] = 0
|
||||
parameters['RAM_PIPELINE'] = 2
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
107
tb/axis_switch/Makefile
Normal file
107
tb/axis_switch/Makefile
Normal file
@ -0,0 +1,107 @@
|
||||
# Copyright (c) 2021 Alex Forencich
|
||||
#
|
||||
# Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
# of this software and associated documentation files (the "Software"), to deal
|
||||
# in the Software without restriction, including without limitation the rights
|
||||
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
# copies of the Software, and to permit persons to whom the Software is
|
||||
# furnished to do so, subject to the following conditions:
|
||||
#
|
||||
# The above copyright notice and this permission notice shall be included in
|
||||
# all copies or substantial portions of the Software.
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
# THE SOFTWARE.
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= icarus
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
export PARAM_S_COUNT ?= 4
|
||||
export PARAM_M_COUNT ?= 4
|
||||
|
||||
DUT = axis_switch
|
||||
WRAPPER = $(DUT)_wrap_$(PARAM_S_COUNT)x$(PARAM_M_COUNT)
|
||||
TOPLEVEL = $(WRAPPER)
|
||||
MODULE = test_$(DUT)
|
||||
VERILOG_SOURCES += $(WRAPPER).v
|
||||
VERILOG_SOURCES += ../../rtl/$(DUT).v
|
||||
VERILOG_SOURCES += ../../rtl/axis_register.v
|
||||
VERILOG_SOURCES += ../../rtl/arbiter.v
|
||||
VERILOG_SOURCES += ../../rtl/priority_encoder.v
|
||||
|
||||
# module parameters
|
||||
export PARAM_DATA_WIDTH ?= 8
|
||||
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
|
||||
export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
|
||||
export PARAM_ID_ENABLE ?= 1
|
||||
export PARAM_ID_WIDTH ?= 16
|
||||
export PARAM_DEST_WIDTH ?= 8
|
||||
export PARAM_USER_ENABLE ?= 1
|
||||
export PARAM_USER_WIDTH ?= 1
|
||||
export PARAM_S_REG_TYPE ?= 0
|
||||
export PARAM_M_REG_TYPE ?= 2
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).DATA_WIDTH=$(PARAM_DATA_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).KEEP_ENABLE=$(PARAM_KEEP_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).KEEP_WIDTH=$(PARAM_KEEP_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).ID_ENABLE=$(PARAM_ID_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).ID_WIDTH=$(PARAM_ID_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).DEST_WIDTH=$(PARAM_DEST_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).USER_ENABLE=$(PARAM_USER_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).USER_WIDTH=$(PARAM_USER_WIDTH)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).S_REG_TYPE=$(PARAM_S_REG_TYPE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).M_REG_TYPE=$(PARAM_M_REG_TYPE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
VERILOG_SOURCES += iverilog_dump.v
|
||||
COMPILE_ARGS += -s iverilog_dump
|
||||
endif
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
|
||||
|
||||
COMPILE_ARGS += -GDATA_WIDTH=$(PARAM_DATA_WIDTH)
|
||||
COMPILE_ARGS += -GKEEP_ENABLE=$(PARAM_KEEP_ENABLE)
|
||||
COMPILE_ARGS += -GKEEP_WIDTH=$(PARAM_KEEP_WIDTH)
|
||||
COMPILE_ARGS += -GID_ENABLE=$(PARAM_ID_ENABLE)
|
||||
COMPILE_ARGS += -GID_WIDTH=$(PARAM_ID_WIDTH)
|
||||
COMPILE_ARGS += -GDEST_WIDTH=$(PARAM_DEST_WIDTH)
|
||||
COMPILE_ARGS += -GUSER_ENABLE=$(PARAM_USER_ENABLE)
|
||||
COMPILE_ARGS += -GUSER_WIDTH=$(PARAM_USER_WIDTH)
|
||||
COMPILE_ARGS += -GS_REG_TYPE=$(PARAM_S_REG_TYPE)
|
||||
COMPILE_ARGS += -GM_REG_TYPE=$(PARAM_M_REG_TYPE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
|
||||
$(WRAPPER).v: ../../rtl/$(DUT)_wrap.py
|
||||
$< -p $(PARAM_S_COUNT) $(PARAM_M_COUNT)
|
||||
|
||||
iverilog_dump.v:
|
||||
echo 'module iverilog_dump();' > $@
|
||||
echo 'initial begin' >> $@
|
||||
echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@
|
||||
echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@
|
||||
echo 'end' >> $@
|
||||
echo 'endmodule' >> $@
|
||||
|
||||
clean::
|
||||
@rm -rf iverilog_dump.v
|
||||
@rm -rf dump.fst $(TOPLEVEL).fst
|
||||
@rm -rf *_wrap_*.v
|
||||
351
tb/axis_switch/test_axis_switch.py
Normal file
351
tb/axis_switch/test_axis_switch.py
Normal file
@ -0,0 +1,351 @@
|
||||
#!/usr/bin/env python
|
||||
"""
|
||||
|
||||
Copyright (c) 2021 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
"""
|
||||
|
||||
import itertools
|
||||
import logging
|
||||
import os
|
||||
import random
|
||||
import subprocess
|
||||
|
||||
import cocotb_test.simulator
|
||||
import pytest
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge, Event
|
||||
from cocotb.regression import TestFactory
|
||||
|
||||
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
|
||||
|
||||
|
||||
class TB(object):
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
s_count = len(dut.axis_switch_inst.s_axis_tvalid)
|
||||
m_count = len(dut.axis_switch_inst.m_axis_tvalid)
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.fork(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
self.source = [AxiStreamSource(AxiStreamBus.from_prefix(dut, f"s{k:02d}_axis"), dut.clk, dut.rst) for k in range(s_count)]
|
||||
self.sink = [AxiStreamSink(AxiStreamBus.from_prefix(dut, f"m{k:02d}_axis"), dut.clk, dut.rst) for k in range(m_count)]
|
||||
|
||||
def set_idle_generator(self, generator=None):
|
||||
if generator:
|
||||
for source in self.source:
|
||||
source.set_pause_generator(generator())
|
||||
|
||||
def set_backpressure_generator(self, generator=None):
|
||||
if generator:
|
||||
for sink in self.sink:
|
||||
sink.set_pause_generator(generator())
|
||||
|
||||
async def reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst <= 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst <= 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
|
||||
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None, s=0, m=0):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
id_count = 2**len(tb.source[s].bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = []
|
||||
|
||||
for test_data in [payload_data(x) for x in payload_lengths()]:
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = m
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source[s].send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
for test_frame in test_frames:
|
||||
rx_frame = await tb.sink[m].recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert all(s.empty() for s in tb.sink)
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_test_tuser_assert(dut, s=0, m=0):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
|
||||
test_frame = AxiStreamFrame(test_data, tuser=1, tdest=m)
|
||||
await tb.source[s].send(test_frame)
|
||||
|
||||
rx_frame = await tb.sink[m].recv()
|
||||
|
||||
assert rx_frame.tdata == test_data
|
||||
assert rx_frame.tuser
|
||||
|
||||
assert all(s.empty() for s in tb.sink)
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_arb_test(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.source[0].byte_lanes
|
||||
id_count = 2**len(tb.source[0].bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
test_frames = []
|
||||
|
||||
length = byte_lanes*16
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
for k in range(5):
|
||||
test_frame = AxiStreamFrame(test_data, tx_complete=Event())
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = 0
|
||||
|
||||
src_ind = 0
|
||||
|
||||
if k == 0:
|
||||
src_ind = 0
|
||||
elif k == 4:
|
||||
await test_frames[1].tx_complete.wait()
|
||||
for j in range(8):
|
||||
await RisingEdge(dut.clk)
|
||||
src_ind = 0
|
||||
else:
|
||||
src_ind = 1
|
||||
|
||||
test_frames.append(test_frame)
|
||||
await tb.source[src_ind].send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
for k in [0, 1, 2, 4, 3]:
|
||||
test_frame = test_frames[k]
|
||||
rx_frame = await tb.sink[0].recv()
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert all(s.empty() for s in tb.sink)
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
byte_lanes = tb.source[0].byte_lanes
|
||||
id_count = 2**len(tb.source[0].bus.tid)
|
||||
|
||||
cur_id = 1
|
||||
|
||||
await tb.reset()
|
||||
|
||||
tb.set_idle_generator(idle_inserter)
|
||||
tb.set_backpressure_generator(backpressure_inserter)
|
||||
|
||||
test_frames = [[list() for y in tb.sink] for x in tb.source]
|
||||
|
||||
for p in range(len(tb.source)):
|
||||
for k in range(128):
|
||||
length = random.randint(1, byte_lanes*16)
|
||||
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
test_frame = AxiStreamFrame(test_data)
|
||||
test_frame.tid = cur_id
|
||||
test_frame.tdest = random.randrange(len(tb.sink))
|
||||
|
||||
test_frames[p][test_frame.tdest].append(test_frame)
|
||||
await tb.source[p].send(test_frame)
|
||||
|
||||
cur_id = (cur_id + 1) % id_count
|
||||
|
||||
for lst in test_frames:
|
||||
while any(lst):
|
||||
rx_frame = await tb.sink[[x for x in lst if x][0][0].tdest].recv()
|
||||
|
||||
test_frame = None
|
||||
|
||||
for lst_a in test_frames:
|
||||
for lst_b in lst_a:
|
||||
if lst_b and lst_b[0].tid == rx_frame.tid:
|
||||
test_frame = lst_b.pop(0)
|
||||
break
|
||||
|
||||
assert test_frame is not None
|
||||
|
||||
assert rx_frame.tdata == test_frame.tdata
|
||||
assert rx_frame.tid == test_frame.tid
|
||||
assert rx_frame.tdest == test_frame.tdest
|
||||
assert not rx_frame.tuser
|
||||
|
||||
assert all(s.empty() for s in tb.sink)
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
def size_list():
|
||||
data_width = len(cocotb.top.s00_axis_tdata)
|
||||
byte_width = data_width // 8
|
||||
return list(range(1, byte_width*4+1))+[512]+[1]*64
|
||||
|
||||
|
||||
def incrementing_payload(length):
|
||||
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
s_count = len(cocotb.top.axis_switch_inst.s_axis_tvalid)
|
||||
m_count = len(cocotb.top.axis_switch_inst.m_axis_tvalid)
|
||||
|
||||
factory = TestFactory(run_test)
|
||||
factory.add_option("payload_lengths", [size_list])
|
||||
factory.add_option("payload_data", [incrementing_payload])
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.add_option("s", range(min(s_count, 2)))
|
||||
factory.add_option("m", range(min(m_count, 2)))
|
||||
factory.generate_tests()
|
||||
|
||||
for test in [run_test_tuser_assert]:
|
||||
factory = TestFactory(test)
|
||||
factory.add_option("s", range(min(s_count, 2)))
|
||||
factory.add_option("m", range(min(m_count, 2)))
|
||||
factory.generate_tests()
|
||||
|
||||
if s_count > 1:
|
||||
factory = TestFactory(run_arb_test)
|
||||
factory.generate_tests()
|
||||
|
||||
factory = TestFactory(run_stress_test)
|
||||
factory.add_option("idle_inserter", [None, cycle_pause])
|
||||
factory.add_option("backpressure_inserter", [None, cycle_pause])
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.dirname(__file__)
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
|
||||
|
||||
@pytest.mark.parametrize("data_width", [8, 16, 32])
|
||||
@pytest.mark.parametrize("m_count", [1, 4])
|
||||
@pytest.mark.parametrize("s_count", [1, 4])
|
||||
def test_axis_switch(request, s_count, m_count, data_width):
|
||||
dut = "axis_switch"
|
||||
wrapper = f"{dut}_wrap_{s_count}x{m_count}"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = wrapper
|
||||
|
||||
# generate wrapper
|
||||
wrapper_file = os.path.join(tests_dir, f"{wrapper}.v")
|
||||
if not os.path.exists(wrapper_file):
|
||||
subprocess.Popen(
|
||||
[os.path.join(rtl_dir, f"{dut}_wrap.py"), "-p", f"{s_count}", f"{m_count}"],
|
||||
cwd=tests_dir
|
||||
).wait()
|
||||
|
||||
verilog_sources = [
|
||||
wrapper_file,
|
||||
os.path.join(rtl_dir, f"{dut}.v"),
|
||||
os.path.join(rtl_dir, "axis_register.v"),
|
||||
os.path.join(rtl_dir, "arbiter.v"),
|
||||
os.path.join(rtl_dir, "priority_encoder.v"),
|
||||
]
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['S_COUNT'] = s_count
|
||||
parameters['M_COUNT'] = m_count
|
||||
|
||||
parameters['DATA_WIDTH'] = data_width
|
||||
parameters['KEEP_ENABLE'] = int(parameters['DATA_WIDTH'] > 8)
|
||||
parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
|
||||
parameters['ID_ENABLE'] = 1
|
||||
parameters['ID_WIDTH'] = 16
|
||||
parameters['DEST_WIDTH'] = 8
|
||||
parameters['USER_ENABLE'] = 1
|
||||
parameters['USER_WIDTH'] = 1
|
||||
parameters['S_REG_TYPE'] = 0
|
||||
parameters['M_REG_TYPE'] = 2
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
Loading…
x
Reference in New Issue
Block a user